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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / pci / host / pcie-rockchip.c
blobf2dca7bb0b39f8d02537ba985f958a19d1bfcf14
1 /*
2 * Rockchip AXI PCIe host controller driver
3 *
4 * Copyright (c) 2016 Rockchip, Inc.
5 *
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
8 *
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
11 *
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
39
40 /*
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
43 */
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
46
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
48
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
57 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
58 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
59 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
60 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
61 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
62 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
63 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
64 #define PCIE_CLIENT_INTR_SHIFT 5
65 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
66 #define PCIE_CLIENT_INT_MSG BIT(14)
67 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
68 #define PCIE_CLIENT_INT_DPA BIT(12)
69 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
70 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
71 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
72 #define PCIE_CLIENT_INT_INTD BIT(8)
73 #define PCIE_CLIENT_INT_INTC BIT(7)
74 #define PCIE_CLIENT_INT_INTB BIT(6)
75 #define PCIE_CLIENT_INT_INTA BIT(5)
76 #define PCIE_CLIENT_INT_LOCAL BIT(4)
77 #define PCIE_CLIENT_INT_UDMA BIT(3)
78 #define PCIE_CLIENT_INT_PHY BIT(2)
79 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
80 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
81
82 #define PCIE_CLIENT_INT_LEGACY \
83 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
84 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
85
86 #define PCIE_CLIENT_INT_CLI \
87 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
88 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
89 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
90 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
91 PCIE_CLIENT_INT_PHY)
92
93 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
94 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
95 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
96 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
97 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
98 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
99 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
100 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
101 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
102 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
103 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
106 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
107 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
108 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
109 #define PCIE_CORE_INT_PRFPE BIT(0)
110 #define PCIE_CORE_INT_CRFPE BIT(1)
111 #define PCIE_CORE_INT_RRPE BIT(2)
112 #define PCIE_CORE_INT_PRFO BIT(3)
113 #define PCIE_CORE_INT_CRFO BIT(4)
114 #define PCIE_CORE_INT_RT BIT(5)
115 #define PCIE_CORE_INT_RTR BIT(6)
116 #define PCIE_CORE_INT_PE BIT(7)
117 #define PCIE_CORE_INT_MTR BIT(8)
118 #define PCIE_CORE_INT_UCR BIT(9)
119 #define PCIE_CORE_INT_FCE BIT(10)
120 #define PCIE_CORE_INT_CT BIT(11)
121 #define PCIE_CORE_INT_UTC BIT(18)
122 #define PCIE_CORE_INT_MMVC BIT(19)
123 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
124 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
125
126 #define PCIE_CORE_INT \
127 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
128 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
129 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
130 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
131 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
132 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
133 PCIE_CORE_INT_MMVC)
134
135 #define PCIE_RC_CONFIG_BASE 0xa00000
136 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
137 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
138 #define PCIE_RC_CONFIG_SCC_SHIFT 16
139 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
140 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
141 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
142 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
143 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
144 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
145 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
146 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
147
148 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
149 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
150 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
151 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
152 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
153 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
154 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
155
156 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
157 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
158 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
159 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
160 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
161
162 /* Size of one AXI Region (not Region 0) */
163 #define AXI_REGION_SIZE BIT(20)
164 /* Size of Region 0, equal to sum of sizes of other regions */
165 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
166 #define OB_REG_SIZE_SHIFT 5
167 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
168 #define AXI_WRAPPER_IO_WRITE 0x6
169 #define AXI_WRAPPER_MEM_WRITE 0x2
170
171 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
172 #define MIN_AXI_ADDR_BITS_PASSED 8
173 #define ROCKCHIP_VENDOR_ID 0x1d87
174 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
175 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
176 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
177 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
178 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
179 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
180 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
181
182 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
183 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
184 #define RC_REGION_0_PASS_BITS (25 - 1)
185 #define MAX_AXI_WRAPPER_REGION_NUM 33
186
187 struct rockchip_pcie {
188 void __iomem *reg_base; /* DT axi-base */
189 void __iomem *apb_base; /* DT apb-base */
190 struct phy *phy;
191 struct reset_control *core_rst;
192 struct reset_control *mgmt_rst;
193 struct reset_control *mgmt_sticky_rst;
194 struct reset_control *pipe_rst;
195 struct reset_control *pm_rst;
196 struct reset_control *aclk_rst;
197 struct reset_control *pclk_rst;
198 struct clk *aclk_pcie;
199 struct clk *aclk_perf_pcie;
200 struct clk *hclk_pcie;
201 struct clk *clk_pcie_pm;
202 struct regulator *vpcie3v3; /* 3.3V power supply */
203 struct regulator *vpcie1v8; /* 1.8V power supply */
204 struct regulator *vpcie0v9; /* 0.9V power supply */
205 struct gpio_desc *ep_gpio;
206 u32 lanes;
207 u8 root_bus_nr;
208 int link_gen;
209 struct device *dev;
210 struct irq_domain *irq_domain;
211 u32 io_size;
212 int offset;
213 phys_addr_t io_bus_addr;
214 u32 mem_size;
215 phys_addr_t mem_bus_addr;
216 };
217
218 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
219 {
220 return readl(rockchip->apb_base + reg);
221 }
222
223 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
224 u32 reg)
225 {
226 writel(val, rockchip->apb_base + reg);
227 }
228
229 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
230 {
231 u32 status;
232
233 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
234 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
235 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
236 }
237
238 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
239 {
240 u32 status;
241
242 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
243 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
244 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
245 }
246
247 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
248 {
249 u32 val;
250
251 /* Update Tx credit maximum update interval */
252 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
253 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
254 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
255 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
256 }
257
258 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
259 struct pci_bus *bus, int dev)
260 {
261 /* access only one slot on each root port */
262 if (bus->number == rockchip->root_bus_nr && dev > 0)
263 return 0;
264
265 /*
266 * do not read more than one device on the bus directly attached
267 * to RC's downstream side.
268 */
269 if (bus->primary == rockchip->root_bus_nr && dev > 0)
270 return 0;
271
272 return 1;
273 }
274
275 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
276 int where, int size, u32 *val)
277 {
278 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
279
280 if (!IS_ALIGNED((uintptr_t)addr, size)) {
281 *val = 0;
282 return PCIBIOS_BAD_REGISTER_NUMBER;
283 }
284
285 if (size == 4) {
286 *val = readl(addr);
287 } else if (size == 2) {
288 *val = readw(addr);
289 } else if (size == 1) {
290 *val = readb(addr);
291 } else {
292 *val = 0;
293 return PCIBIOS_BAD_REGISTER_NUMBER;
294 }
295 return PCIBIOS_SUCCESSFUL;
296 }
297
298 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
299 int where, int size, u32 val)
300 {
301 u32 mask, tmp, offset;
302
303 offset = where & ~0x3;
304
305 if (size == 4) {
306 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
307 return PCIBIOS_SUCCESSFUL;
308 }
309
310 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
311
312 /*
313 * N.B. This read/modify/write isn't safe in general because it can
314 * corrupt RW1C bits in adjacent registers. But the hardware
315 * doesn't support smaller writes.
316 */
317 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
318 tmp |= val << ((where & 0x3) * 8);
319 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
320
321 return PCIBIOS_SUCCESSFUL;
322 }
323
324 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
325 struct pci_bus *bus, u32 devfn,
326 int where, int size, u32 *val)
327 {
328 u32 busdev;
329
330 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
331 PCI_FUNC(devfn), where);
332
333 if (!IS_ALIGNED(busdev, size)) {
334 *val = 0;
335 return PCIBIOS_BAD_REGISTER_NUMBER;
336 }
337
338 if (size == 4) {
339 *val = readl(rockchip->reg_base + busdev);
340 } else if (size == 2) {
341 *val = readw(rockchip->reg_base + busdev);
342 } else if (size == 1) {
343 *val = readb(rockchip->reg_base + busdev);
344 } else {
345 *val = 0;
346 return PCIBIOS_BAD_REGISTER_NUMBER;
347 }
348 return PCIBIOS_SUCCESSFUL;
349 }
350
351 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
352 struct pci_bus *bus, u32 devfn,
353 int where, int size, u32 val)
354 {
355 u32 busdev;
356
357 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
358 PCI_FUNC(devfn), where);
359 if (!IS_ALIGNED(busdev, size))
360 return PCIBIOS_BAD_REGISTER_NUMBER;
361
362 if (size == 4)
363 writel(val, rockchip->reg_base + busdev);
364 else if (size == 2)
365 writew(val, rockchip->reg_base + busdev);
366 else if (size == 1)
367 writeb(val, rockchip->reg_base + busdev);
368 else
369 return PCIBIOS_BAD_REGISTER_NUMBER;
370
371 return PCIBIOS_SUCCESSFUL;
372 }
373
374 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
375 int size, u32 *val)
376 {
377 struct rockchip_pcie *rockchip = bus->sysdata;
378
379 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
380 *val = 0xffffffff;
381 return PCIBIOS_DEVICE_NOT_FOUND;
382 }
383
384 if (bus->number == rockchip->root_bus_nr)
385 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
386
387 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
388 }
389
390 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
391 int where, int size, u32 val)
392 {
393 struct rockchip_pcie *rockchip = bus->sysdata;
394
395 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
396 return PCIBIOS_DEVICE_NOT_FOUND;
397
398 if (bus->number == rockchip->root_bus_nr)
399 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
400
401 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
402 }
403
404 static struct pci_ops rockchip_pcie_ops = {
405 .read = rockchip_pcie_rd_conf,
406 .write = rockchip_pcie_wr_conf,
407 };
408
409 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
410 {
411 u32 status, curr, scale, power;
412
413 if (IS_ERR(rockchip->vpcie3v3))
414 return;
415
416 /*
417 * Set RC's captured slot power limit and scale if
418 * vpcie3v3 available. The default values are both zero
419 * which means the software should set these two according
420 * to the actual power supply.
421 */
422 curr = regulator_get_current_limit(rockchip->vpcie3v3);
423 if (curr > 0) {
424 scale = 3; /* 0.001x */
425 curr = curr / 1000; /* convert to mA */
426 power = (curr * 3300) / 1000; /* milliwatt */
427 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
428 if (!scale) {
429 dev_warn(rockchip->dev, "invalid power supply\n");
430 return;
431 }
432 scale--;
433 power = power / 10;
434 }
435
436 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
437 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
438 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
439 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
440 }
441 }
442
443 /**
444 * rockchip_pcie_init_port - Initialize hardware
445 * @rockchip: PCIe port information
446 */
447 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
448 {
449 struct device *dev = rockchip->dev;
450 int err;
451 u32 status;
452 unsigned long timeout;
453
454 gpiod_set_value(rockchip->ep_gpio, 0);
455
456 err = reset_control_assert(rockchip->aclk_rst);
457 if (err) {
458 dev_err(dev, "assert aclk_rst err %d\n", err);
459 return err;
460 }
461
462 err = reset_control_assert(rockchip->pclk_rst);
463 if (err) {
464 dev_err(dev, "assert pclk_rst err %d\n", err);
465 return err;
466 }
467
468 err = reset_control_assert(rockchip->pm_rst);
469 if (err) {
470 dev_err(dev, "assert pm_rst err %d\n", err);
471 return err;
472 }
473
474 err = phy_init(rockchip->phy);
475 if (err < 0) {
476 dev_err(dev, "fail to init phy, err %d\n", err);
477 return err;
478 }
479
480 err = reset_control_assert(rockchip->core_rst);
481 if (err) {
482 dev_err(dev, "assert core_rst err %d\n", err);
483 return err;
484 }
485
486 err = reset_control_assert(rockchip->mgmt_rst);
487 if (err) {
488 dev_err(dev, "assert mgmt_rst err %d\n", err);
489 return err;
490 }
491
492 err = reset_control_assert(rockchip->mgmt_sticky_rst);
493 if (err) {
494 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
495 return err;
496 }
497
498 err = reset_control_assert(rockchip->pipe_rst);
499 if (err) {
500 dev_err(dev, "assert pipe_rst err %d\n", err);
501 return err;
502 }
503
504 udelay(10);
505
506 err = reset_control_deassert(rockchip->pm_rst);
507 if (err) {
508 dev_err(dev, "deassert pm_rst err %d\n", err);
509 return err;
510 }
511
512 err = reset_control_deassert(rockchip->aclk_rst);
513 if (err) {
514 dev_err(dev, "deassert aclk_rst err %d\n", err);
515 return err;
516 }
517
518 err = reset_control_deassert(rockchip->pclk_rst);
519 if (err) {
520 dev_err(dev, "deassert pclk_rst err %d\n", err);
521 return err;
522 }
523
524 if (rockchip->link_gen == 2)
525 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
526 PCIE_CLIENT_CONFIG);
527 else
528 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
529 PCIE_CLIENT_CONFIG);
530
531 rockchip_pcie_write(rockchip,
532 PCIE_CLIENT_CONF_ENABLE |
533 PCIE_CLIENT_LINK_TRAIN_ENABLE |
534 PCIE_CLIENT_ARI_ENABLE |
535 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
536 PCIE_CLIENT_MODE_RC,
537 PCIE_CLIENT_CONFIG);
538
539 err = phy_power_on(rockchip->phy);
540 if (err) {
541 dev_err(dev, "fail to power on phy, err %d\n", err);
542 return err;
543 }
544
545 /*
546 * Please don't reorder the deassert sequence of the following
547 * four reset pins.
548 */
549 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
550 if (err) {
551 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
552 return err;
553 }
554
555 err = reset_control_deassert(rockchip->core_rst);
556 if (err) {
557 dev_err(dev, "deassert core_rst err %d\n", err);
558 return err;
559 }
560
561 err = reset_control_deassert(rockchip->mgmt_rst);
562 if (err) {
563 dev_err(dev, "deassert mgmt_rst err %d\n", err);
564 return err;
565 }
566
567 err = reset_control_deassert(rockchip->pipe_rst);
568 if (err) {
569 dev_err(dev, "deassert pipe_rst err %d\n", err);
570 return err;
571 }
572
573 /* Fix the transmitted FTS count desired to exit from L0s. */
574 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
575 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
576 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
577 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
578
579 rockchip_pcie_set_power_limit(rockchip);
580
581 /* Set RC's clock architecture as common clock */
582 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
583 status |= PCI_EXP_LNKCTL_CCC;
584 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
585
586 /* Enable Gen1 training */
587 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
588 PCIE_CLIENT_CONFIG);
589
590 gpiod_set_value(rockchip->ep_gpio, 1);
591
592 /* 500ms timeout value should be enough for Gen1/2 training */
593 timeout = jiffies + msecs_to_jiffies(500);
594
595 for (;;) {
596 status = rockchip_pcie_read(rockchip,
597 PCIE_CLIENT_BASIC_STATUS1);
598 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
599 PCIE_CLIENT_LINK_STATUS_UP) {
600 dev_dbg(dev, "PCIe link training gen1 pass!\n");
601 break;
602 }
603
604 if (time_after(jiffies, timeout)) {
605 dev_err(dev, "PCIe link training gen1 timeout!\n");
606 return -ETIMEDOUT;
607 }
608
609 msleep(20);
610 }
611
612 if (rockchip->link_gen == 2) {
613 /*
614 * Enable retrain for gen2. This should be configured only after
615 * gen1 finished.
616 */
617 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
618 status |= PCI_EXP_LNKCTL_RL;
619 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
620
621 timeout = jiffies + msecs_to_jiffies(500);
622 for (;;) {
623 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
624 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
625 PCIE_CORE_PL_CONF_SPEED_5G) {
626 dev_dbg(dev, "PCIe link training gen2 pass!\n");
627 break;
628 }
629
630 if (time_after(jiffies, timeout)) {
631 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
632 break;
633 }
634
635 msleep(20);
636 }
637 }
638
639 /* Check the final link width from negotiated lane counter from MGMT */
640 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
641 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
642 PCIE_CORE_PL_CONF_LANE_SHIFT);
643 dev_dbg(dev, "current link width is x%d\n", status);
644
645 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
646 PCIE_RC_CONFIG_VENDOR);
647 rockchip_pcie_write(rockchip,
648 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
649 PCIE_RC_CONFIG_RID_CCR);
650
651 /* Clear THP cap's next cap pointer to remove L1 substate cap */
652 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
653 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
654 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
655
656 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
657
658 rockchip_pcie_write(rockchip,
659 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
660 PCIE_CORE_OB_REGION_ADDR0);
661 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
662 PCIE_CORE_OB_REGION_ADDR1);
663 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
664 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
665
666 return 0;
667 }
668
669 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
670 {
671 struct rockchip_pcie *rockchip = arg;
672 struct device *dev = rockchip->dev;
673 u32 reg;
674 u32 sub_reg;
675
676 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
677 if (reg & PCIE_CLIENT_INT_LOCAL) {
678 dev_dbg(dev, "local interrupt received\n");
679 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
680 if (sub_reg & PCIE_CORE_INT_PRFPE)
681 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
682
683 if (sub_reg & PCIE_CORE_INT_CRFPE)
684 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
685
686 if (sub_reg & PCIE_CORE_INT_RRPE)
687 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
688
689 if (sub_reg & PCIE_CORE_INT_PRFO)
690 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
691
692 if (sub_reg & PCIE_CORE_INT_CRFO)
693 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
694
695 if (sub_reg & PCIE_CORE_INT_RT)
696 dev_dbg(dev, "replay timer timed out\n");
697
698 if (sub_reg & PCIE_CORE_INT_RTR)
699 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
700
701 if (sub_reg & PCIE_CORE_INT_PE)
702 dev_dbg(dev, "phy error detected on receive side\n");
703
704 if (sub_reg & PCIE_CORE_INT_MTR)
705 dev_dbg(dev, "malformed TLP received from the link\n");
706
707 if (sub_reg & PCIE_CORE_INT_UCR)
708 dev_dbg(dev, "malformed TLP received from the link\n");
709
710 if (sub_reg & PCIE_CORE_INT_FCE)
711 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
712
713 if (sub_reg & PCIE_CORE_INT_CT)
714 dev_dbg(dev, "a request timed out waiting for completion\n");
715
716 if (sub_reg & PCIE_CORE_INT_UTC)
717 dev_dbg(dev, "unmapped TC error\n");
718
719 if (sub_reg & PCIE_CORE_INT_MMVC)
720 dev_dbg(dev, "MSI mask register changes\n");
721
722 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
723 } else if (reg & PCIE_CLIENT_INT_PHY) {
724 dev_dbg(dev, "phy link changes\n");
725 rockchip_pcie_update_txcredit_mui(rockchip);
726 rockchip_pcie_clr_bw_int(rockchip);
727 }
728
729 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
730 PCIE_CLIENT_INT_STATUS);
731
732 return IRQ_HANDLED;
733 }
734
735 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
736 {
737 struct rockchip_pcie *rockchip = arg;
738 struct device *dev = rockchip->dev;
739 u32 reg;
740
741 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
742 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
743 dev_dbg(dev, "legacy done interrupt received\n");
744
745 if (reg & PCIE_CLIENT_INT_MSG)
746 dev_dbg(dev, "message done interrupt received\n");
747
748 if (reg & PCIE_CLIENT_INT_HOT_RST)
749 dev_dbg(dev, "hot reset interrupt received\n");
750
751 if (reg & PCIE_CLIENT_INT_DPA)
752 dev_dbg(dev, "dpa interrupt received\n");
753
754 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
755 dev_dbg(dev, "fatal error interrupt received\n");
756
757 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
758 dev_dbg(dev, "no fatal error interrupt received\n");
759
760 if (reg & PCIE_CLIENT_INT_CORR_ERR)
761 dev_dbg(dev, "correctable error interrupt received\n");
762
763 if (reg & PCIE_CLIENT_INT_PHY)
764 dev_dbg(dev, "phy interrupt received\n");
765
766 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
767 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
768 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
769 PCIE_CLIENT_INT_NFATAL_ERR |
770 PCIE_CLIENT_INT_CORR_ERR |
771 PCIE_CLIENT_INT_PHY),
772 PCIE_CLIENT_INT_STATUS);
773
774 return IRQ_HANDLED;
775 }
776
777 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
778 {
779 struct irq_chip *chip = irq_desc_get_chip(desc);
780 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
781 struct device *dev = rockchip->dev;
782 u32 reg;
783 u32 hwirq;
784 u32 virq;
785
786 chained_irq_enter(chip, desc);
787
788 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
789 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
790
791 while (reg) {
792 hwirq = ffs(reg) - 1;
793 reg &= ~BIT(hwirq);
794
795 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
796 if (virq)
797 generic_handle_irq(virq);
798 else
799 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
800 }
801
802 chained_irq_exit(chip, desc);
803 }
804
805
806 /**
807 * rockchip_pcie_parse_dt - Parse Device Tree
808 * @rockchip: PCIe port information
809 *
810 * Return: '0' on success and error value on failure
811 */
812 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
813 {
814 struct device *dev = rockchip->dev;
815 struct platform_device *pdev = to_platform_device(dev);
816 struct device_node *node = dev->of_node;
817 struct resource *regs;
818 int irq;
819 int err;
820
821 regs = platform_get_resource_byname(pdev,
822 IORESOURCE_MEM,
823 "axi-base");
824 rockchip->reg_base = devm_ioremap_resource(dev, regs);
825 if (IS_ERR(rockchip->reg_base))
826 return PTR_ERR(rockchip->reg_base);
827
828 regs = platform_get_resource_byname(pdev,
829 IORESOURCE_MEM,
830 "apb-base");
831 rockchip->apb_base = devm_ioremap_resource(dev, regs);
832 if (IS_ERR(rockchip->apb_base))
833 return PTR_ERR(rockchip->apb_base);
834
835 rockchip->phy = devm_phy_get(dev, "pcie-phy");
836 if (IS_ERR(rockchip->phy)) {
837 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
838 dev_err(dev, "missing phy\n");
839 return PTR_ERR(rockchip->phy);
840 }
841
842 rockchip->lanes = 1;
843 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
844 if (!err && (rockchip->lanes == 0 ||
845 rockchip->lanes == 3 ||
846 rockchip->lanes > 4)) {
847 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
848 rockchip->lanes = 1;
849 }
850
851 rockchip->link_gen = of_pci_get_max_link_speed(node);
852 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
853 rockchip->link_gen = 2;
854
855 rockchip->core_rst = devm_reset_control_get(dev, "core");
856 if (IS_ERR(rockchip->core_rst)) {
857 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
858 dev_err(dev, "missing core reset property in node\n");
859 return PTR_ERR(rockchip->core_rst);
860 }
861
862 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
863 if (IS_ERR(rockchip->mgmt_rst)) {
864 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
865 dev_err(dev, "missing mgmt reset property in node\n");
866 return PTR_ERR(rockchip->mgmt_rst);
867 }
868
869 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
870 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
871 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
872 dev_err(dev, "missing mgmt-sticky reset property in node\n");
873 return PTR_ERR(rockchip->mgmt_sticky_rst);
874 }
875
876 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
877 if (IS_ERR(rockchip->pipe_rst)) {
878 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
879 dev_err(dev, "missing pipe reset property in node\n");
880 return PTR_ERR(rockchip->pipe_rst);
881 }
882
883 rockchip->pm_rst = devm_reset_control_get(dev, "pm");
884 if (IS_ERR(rockchip->pm_rst)) {
885 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
886 dev_err(dev, "missing pm reset property in node\n");
887 return PTR_ERR(rockchip->pm_rst);
888 }
889
890 rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
891 if (IS_ERR(rockchip->pclk_rst)) {
892 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
893 dev_err(dev, "missing pclk reset property in node\n");
894 return PTR_ERR(rockchip->pclk_rst);
895 }
896
897 rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
898 if (IS_ERR(rockchip->aclk_rst)) {
899 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
900 dev_err(dev, "missing aclk reset property in node\n");
901 return PTR_ERR(rockchip->aclk_rst);
902 }
903
904 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
905 if (IS_ERR(rockchip->ep_gpio)) {
906 dev_err(dev, "missing ep-gpios property in node\n");
907 return PTR_ERR(rockchip->ep_gpio);
908 }
909
910 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
911 if (IS_ERR(rockchip->aclk_pcie)) {
912 dev_err(dev, "aclk clock not found\n");
913 return PTR_ERR(rockchip->aclk_pcie);
914 }
915
916 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
917 if (IS_ERR(rockchip->aclk_perf_pcie)) {
918 dev_err(dev, "aclk_perf clock not found\n");
919 return PTR_ERR(rockchip->aclk_perf_pcie);
920 }
921
922 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
923 if (IS_ERR(rockchip->hclk_pcie)) {
924 dev_err(dev, "hclk clock not found\n");
925 return PTR_ERR(rockchip->hclk_pcie);
926 }
927
928 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
929 if (IS_ERR(rockchip->clk_pcie_pm)) {
930 dev_err(dev, "pm clock not found\n");
931 return PTR_ERR(rockchip->clk_pcie_pm);
932 }
933
934 irq = platform_get_irq_byname(pdev, "sys");
935 if (irq < 0) {
936 dev_err(dev, "missing sys IRQ resource\n");
937 return -EINVAL;
938 }
939
940 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
941 IRQF_SHARED, "pcie-sys", rockchip);
942 if (err) {
943 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
944 return err;
945 }
946
947 irq = platform_get_irq_byname(pdev, "legacy");
948 if (irq < 0) {
949 dev_err(dev, "missing legacy IRQ resource\n");
950 return -EINVAL;
951 }
952
953 irq_set_chained_handler_and_data(irq,
954 rockchip_pcie_legacy_int_handler,
955 rockchip);
956
957 irq = platform_get_irq_byname(pdev, "client");
958 if (irq < 0) {
959 dev_err(dev, "missing client IRQ resource\n");
960 return -EINVAL;
961 }
962
963 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
964 IRQF_SHARED, "pcie-client", rockchip);
965 if (err) {
966 dev_err(dev, "failed to request PCIe client IRQ\n");
967 return err;
968 }
969
970 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
971 if (IS_ERR(rockchip->vpcie3v3)) {
972 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
973 return -EPROBE_DEFER;
974 dev_info(dev, "no vpcie3v3 regulator found\n");
975 }
976
977 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
978 if (IS_ERR(rockchip->vpcie1v8)) {
979 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
980 return -EPROBE_DEFER;
981 dev_info(dev, "no vpcie1v8 regulator found\n");
982 }
983
984 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
985 if (IS_ERR(rockchip->vpcie0v9)) {
986 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
987 return -EPROBE_DEFER;
988 dev_info(dev, "no vpcie0v9 regulator found\n");
989 }
990
991 return 0;
992 }
993
994 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
995 {
996 struct device *dev = rockchip->dev;
997 int err;
998
999 if (!IS_ERR(rockchip->vpcie3v3)) {
1000 err = regulator_enable(rockchip->vpcie3v3);
1001 if (err) {
1002 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
1003 goto err_out;
1004 }
1005 }
1006
1007 if (!IS_ERR(rockchip->vpcie1v8)) {
1008 err = regulator_enable(rockchip->vpcie1v8);
1009 if (err) {
1010 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
1011 goto err_disable_3v3;
1012 }
1013 }
1014
1015 if (!IS_ERR(rockchip->vpcie0v9)) {
1016 err = regulator_enable(rockchip->vpcie0v9);
1017 if (err) {
1018 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1019 goto err_disable_1v8;
1020 }
1021 }
1022
1023 return 0;
1024
1025 err_disable_1v8:
1026 if (!IS_ERR(rockchip->vpcie1v8))
1027 regulator_disable(rockchip->vpcie1v8);
1028 err_disable_3v3:
1029 if (!IS_ERR(rockchip->vpcie3v3))
1030 regulator_disable(rockchip->vpcie3v3);
1031 err_out:
1032 return err;
1033 }
1034
1035 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
1036 {
1037 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
1038 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
1039 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
1040 PCIE_CORE_INT_MASK);
1041
1042 rockchip_pcie_enable_bw_int(rockchip);
1043 }
1044
1045 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
1046 irq_hw_number_t hwirq)
1047 {
1048 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
1049 irq_set_chip_data(irq, domain->host_data);
1050
1051 return 0;
1052 }
1053
1054 static const struct irq_domain_ops intx_domain_ops = {
1055 .map = rockchip_pcie_intx_map,
1056 };
1057
1058 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1059 {
1060 struct device *dev = rockchip->dev;
1061 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1062
1063 if (!intc) {
1064 dev_err(dev, "missing child interrupt-controller node\n");
1065 return -EINVAL;
1066 }
1067
1068 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
1069 &intx_domain_ops, rockchip);
1070 if (!rockchip->irq_domain) {
1071 dev_err(dev, "failed to get a INTx IRQ domain\n");
1072 return -EINVAL;
1073 }
1074
1075 return 0;
1076 }
1077
1078 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1079 int region_no, int type, u8 num_pass_bits,
1080 u32 lower_addr, u32 upper_addr)
1081 {
1082 u32 ob_addr_0;
1083 u32 ob_addr_1;
1084 u32 ob_desc_0;
1085 u32 aw_offset;
1086
1087 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1088 return -EINVAL;
1089 if (num_pass_bits + 1 < 8)
1090 return -EINVAL;
1091 if (num_pass_bits > 63)
1092 return -EINVAL;
1093 if (region_no == 0) {
1094 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1095 return -EINVAL;
1096 }
1097 if (region_no != 0) {
1098 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1099 return -EINVAL;
1100 }
1101
1102 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1103
1104 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1105 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1106 ob_addr_1 = upper_addr;
1107 ob_desc_0 = (1 << 23 | type);
1108
1109 rockchip_pcie_write(rockchip, ob_addr_0,
1110 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1111 rockchip_pcie_write(rockchip, ob_addr_1,
1112 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1113 rockchip_pcie_write(rockchip, ob_desc_0,
1114 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1115 rockchip_pcie_write(rockchip, 0,
1116 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1117
1118 return 0;
1119 }
1120
1121 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1122 int region_no, u8 num_pass_bits,
1123 u32 lower_addr, u32 upper_addr)
1124 {
1125 u32 ib_addr_0;
1126 u32 ib_addr_1;
1127 u32 aw_offset;
1128
1129 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1130 return -EINVAL;
1131 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1132 return -EINVAL;
1133 if (num_pass_bits > 63)
1134 return -EINVAL;
1135
1136 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1137
1138 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1139 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1140 ib_addr_1 = upper_addr;
1141
1142 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1143 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1144
1145 return 0;
1146 }
1147
1148 static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
1149 {
1150 struct device *dev = rockchip->dev;
1151 int offset;
1152 int err;
1153 int reg_no;
1154
1155 for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {
1156 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1157 AXI_WRAPPER_MEM_WRITE,
1158 20 - 1,
1159 rockchip->mem_bus_addr +
1160 (reg_no << 20),
1161 0);
1162 if (err) {
1163 dev_err(dev, "program RC mem outbound ATU failed\n");
1164 return err;
1165 }
1166 }
1167
1168 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1169 if (err) {
1170 dev_err(dev, "program RC mem inbound ATU failed\n");
1171 return err;
1172 }
1173
1174 offset = rockchip->mem_size >> 20;
1175 for (reg_no = 0; reg_no < (rockchip->io_size >> 20); reg_no++) {
1176 err = rockchip_pcie_prog_ob_atu(rockchip,
1177 reg_no + 1 + offset,
1178 AXI_WRAPPER_IO_WRITE,
1179 20 - 1,
1180 rockchip->io_bus_addr +
1181 (reg_no << 20),
1182 0);
1183 if (err) {
1184 dev_err(dev, "program RC io outbound ATU failed\n");
1185 return err;
1186 }
1187 }
1188
1189 return 0;
1190 }
1191
1192 static int rockchip_pcie_probe(struct platform_device *pdev)
1193 {
1194 struct rockchip_pcie *rockchip;
1195 struct device *dev = &pdev->dev;
1196 struct pci_bus *bus, *child;
1197 struct resource_entry *win;
1198 resource_size_t io_base;
1199 struct resource *mem;
1200 struct resource *io;
1201 int err;
1202
1203 LIST_HEAD(res);
1204
1205 if (!dev->of_node)
1206 return -ENODEV;
1207
1208 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1209 if (!rockchip)
1210 return -ENOMEM;
1211
1212 rockchip->dev = dev;
1213
1214 err = rockchip_pcie_parse_dt(rockchip);
1215 if (err)
1216 return err;
1217
1218 err = clk_prepare_enable(rockchip->aclk_pcie);
1219 if (err) {
1220 dev_err(dev, "unable to enable aclk_pcie clock\n");
1221 goto err_aclk_pcie;
1222 }
1223
1224 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1225 if (err) {
1226 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1227 goto err_aclk_perf_pcie;
1228 }
1229
1230 err = clk_prepare_enable(rockchip->hclk_pcie);
1231 if (err) {
1232 dev_err(dev, "unable to enable hclk_pcie clock\n");
1233 goto err_hclk_pcie;
1234 }
1235
1236 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1237 if (err) {
1238 dev_err(dev, "unable to enable hclk_pcie clock\n");
1239 goto err_pcie_pm;
1240 }
1241
1242 err = rockchip_pcie_set_vpcie(rockchip);
1243 if (err) {
1244 dev_err(dev, "failed to set vpcie regulator\n");
1245 goto err_set_vpcie;
1246 }
1247
1248 err = rockchip_pcie_init_port(rockchip);
1249 if (err)
1250 goto err_vpcie;
1251
1252 rockchip_pcie_enable_interrupts(rockchip);
1253
1254 err = rockchip_pcie_init_irq_domain(rockchip);
1255 if (err < 0)
1256 goto err_vpcie;
1257
1258 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1259 &res, &io_base);
1260 if (err)
1261 goto err_vpcie;
1262
1263 err = devm_request_pci_bus_resources(dev, &res);
1264 if (err)
1265 goto err_vpcie;
1266
1267 /* Get the I/O and memory ranges from DT */
1268 resource_list_for_each_entry(win, &res) {
1269 switch (resource_type(win->res)) {
1270 case IORESOURCE_IO:
1271 io = win->res;
1272 io->name = "I/O";
1273 rockchip->io_size = resource_size(io);
1274 rockchip->io_bus_addr = io->start - win->offset;
1275 err = pci_remap_iospace(io, io_base);
1276 if (err) {
1277 dev_warn(dev, "error %d: failed to map resource %pR\n",
1278 err, io);
1279 continue;
1280 }
1281 break;
1282 case IORESOURCE_MEM:
1283 mem = win->res;
1284 mem->name = "MEM";
1285 rockchip->mem_size = resource_size(mem);
1286 rockchip->mem_bus_addr = mem->start - win->offset;
1287 break;
1288 case IORESOURCE_BUS:
1289 rockchip->root_bus_nr = win->res->start;
1290 break;
1291 default:
1292 continue;
1293 }
1294 }
1295
1296 err = rockchip_cfg_atu(rockchip);
1297 if (err)
1298 goto err_vpcie;
1299 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1300 if (!bus) {
1301 err = -ENOMEM;
1302 goto err_vpcie;
1303 }
1304
1305 pci_bus_size_bridges(bus);
1306 pci_bus_assign_resources(bus);
1307 list_for_each_entry(child, &bus->children, node)
1308 pcie_bus_configure_settings(child);
1309
1310 pci_bus_add_devices(bus);
1311 return err;
1312
1313 err_vpcie:
1314 if (!IS_ERR(rockchip->vpcie3v3))
1315 regulator_disable(rockchip->vpcie3v3);
1316 if (!IS_ERR(rockchip->vpcie1v8))
1317 regulator_disable(rockchip->vpcie1v8);
1318 if (!IS_ERR(rockchip->vpcie0v9))
1319 regulator_disable(rockchip->vpcie0v9);
1320 err_set_vpcie:
1321 clk_disable_unprepare(rockchip->clk_pcie_pm);
1322 err_pcie_pm:
1323 clk_disable_unprepare(rockchip->hclk_pcie);
1324 err_hclk_pcie:
1325 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1326 err_aclk_perf_pcie:
1327 clk_disable_unprepare(rockchip->aclk_pcie);
1328 err_aclk_pcie:
1329 return err;
1330 }
1331
1332 static const struct of_device_id rockchip_pcie_of_match[] = {
1333 { .compatible = "rockchip,rk3399-pcie", },
1334 {}
1335 };
1336
1337 static struct platform_driver rockchip_pcie_driver = {
1338 .driver = {
1339 .name = "rockchip-pcie",
1340 .of_match_table = rockchip_pcie_of_match,
1341 },
1342 .probe = rockchip_pcie_probe,
1343
1344 };
1345 builtin_platform_driver(rockchip_pcie_driver);
Linux with added FPC-III support