2 * PCIe host controller driver for NWL PCIe Bridge
3 * Based on pcie-xilinx.c, pci-tegra.c
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/msi.h>
20 #include <linux/of_address.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_irq.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/irqchip/chained_irq.h>
28 /* Bridge core config registers */
29 #define BRCFG_PCIE_RX0 0x00000000
30 #define BRCFG_INTERRUPT 0x00000010
31 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
33 /* Egress - Bridge translation registers */
34 #define E_BREG_CAPABILITIES 0x00000200
35 #define E_BREG_CONTROL 0x00000208
36 #define E_BREG_BASE_LO 0x00000210
37 #define E_BREG_BASE_HI 0x00000214
38 #define E_ECAM_CAPABILITIES 0x00000220
39 #define E_ECAM_CONTROL 0x00000228
40 #define E_ECAM_BASE_LO 0x00000230
41 #define E_ECAM_BASE_HI 0x00000234
43 /* Ingress - address translations */
44 #define I_MSII_CAPABILITIES 0x00000300
45 #define I_MSII_CONTROL 0x00000308
46 #define I_MSII_BASE_LO 0x00000310
47 #define I_MSII_BASE_HI 0x00000314
49 #define I_ISUB_CONTROL 0x000003E8
50 #define SET_ISUB_CONTROL BIT(0)
51 /* Rxed msg fifo - Interrupt status registers */
52 #define MSGF_MISC_STATUS 0x00000400
53 #define MSGF_MISC_MASK 0x00000404
54 #define MSGF_LEG_STATUS 0x00000420
55 #define MSGF_LEG_MASK 0x00000424
56 #define MSGF_MSI_STATUS_LO 0x00000440
57 #define MSGF_MSI_STATUS_HI 0x00000444
58 #define MSGF_MSI_MASK_LO 0x00000448
59 #define MSGF_MSI_MASK_HI 0x0000044C
61 /* Msg filter mask bits */
62 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
63 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
64 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65 #define CFG_ENABLE_SLT_MSG_FWD BIT(5)
66 #define CFG_ENABLE_VEN_MSG_FWD BIT(7)
67 #define CFG_ENABLE_OTH_MSG_FWD BIT(13)
68 #define CFG_ENABLE_VEN_MSG_EN BIT(14)
69 #define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15)
70 #define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16)
71 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
72 CFG_ENABLE_INT_MSG_FWD | \
73 CFG_ENABLE_ERR_MSG_FWD | \
74 CFG_ENABLE_SLT_MSG_FWD | \
75 CFG_ENABLE_VEN_MSG_FWD | \
76 CFG_ENABLE_OTH_MSG_FWD | \
77 CFG_ENABLE_VEN_MSG_EN | \
78 CFG_ENABLE_VEN_MSG_VEN_INV | \
79 CFG_ENABLE_VEN_MSG_VEN_ID)
81 /* Misc interrupt status mask bits */
82 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
83 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
84 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
85 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
86 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
87 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
88 #define MSGF_MISC_SR_FATAL_AER BIT(16)
89 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
90 #define MSGF_MISC_SR_CORR_AER BIT(18)
91 #define MSGF_MISC_SR_UR_DETECT BIT(20)
92 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
93 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
94 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
95 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
96 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
98 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
99 MSGF_MISC_SR_RXMSG_OVER | \
100 MSGF_MISC_SR_SLAVE_ERR | \
101 MSGF_MISC_SR_MASTER_ERR | \
102 MSGF_MISC_SR_I_ADDR_ERR | \
103 MSGF_MISC_SR_E_ADDR_ERR | \
104 MSGF_MISC_SR_FATAL_AER | \
105 MSGF_MISC_SR_NON_FATAL_AER | \
106 MSGF_MISC_SR_CORR_AER | \
107 MSGF_MISC_SR_UR_DETECT | \
108 MSGF_MISC_SR_NON_FATAL_DEV | \
109 MSGF_MISC_SR_FATAL_DEV | \
110 MSGF_MISC_SR_LINK_DOWN | \
111 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
112 MSGF_MSIC_SR_LINK_BWIDTH)
114 /* Legacy interrupt status mask bits */
115 #define MSGF_LEG_SR_INTA BIT(0)
116 #define MSGF_LEG_SR_INTB BIT(1)
117 #define MSGF_LEG_SR_INTC BIT(2)
118 #define MSGF_LEG_SR_INTD BIT(3)
119 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
120 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
122 /* MSI interrupt status mask bits */
123 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
124 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
126 #define MSII_PRESENT BIT(0)
127 #define MSII_ENABLE BIT(0)
128 #define MSII_STATUS_ENABLE BIT(15)
130 /* Bridge config interrupt mask */
131 #define BRCFG_INTERRUPT_MASK BIT(0)
132 #define BREG_PRESENT BIT(0)
133 #define BREG_ENABLE BIT(0)
134 #define BREG_ENABLE_FORCE BIT(1)
136 /* E_ECAM status mask bits */
137 #define E_ECAM_PRESENT BIT(0)
138 #define E_ECAM_CR_ENABLE BIT(0)
139 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
140 #define E_ECAM_SIZE_SHIFT 16
141 #define ECAM_BUS_LOC_SHIFT 20
142 #define ECAM_DEV_LOC_SHIFT 12
143 #define NWL_ECAM_VALUE_DEFAULT 12
145 #define CFG_DMA_REG_BAR GENMASK(2, 0)
147 #define INT_PCI_MSI_NR (2 * 32)
150 /* Readin the PS_LINKUP */
151 #define PS_LINKUP_OFFSET 0x00000238
152 #define PCIE_PHY_LINKUP_BIT BIT(0)
153 #define PHY_RDY_LINKUP_BIT BIT(1)
155 /* Parameters for the waiting for link up routine */
156 #define LINK_WAIT_MAX_RETRIES 10
157 #define LINK_WAIT_USLEEP_MIN 90000
158 #define LINK_WAIT_USLEEP_MAX 100000
160 struct nwl_msi
{ /* MSI information */
161 struct irq_domain
*msi_domain
;
162 unsigned long *bitmap
;
163 struct irq_domain
*dev_domain
;
164 struct mutex lock
; /* protect bitmap variable */
171 void __iomem
*breg_base
;
172 void __iomem
*pcireg_base
;
173 void __iomem
*ecam_base
;
174 phys_addr_t phys_breg_base
; /* Physical Bridge Register Base */
175 phys_addr_t phys_pcie_reg_base
; /* Physical PCIe Controller Base */
176 phys_addr_t phys_ecam_base
; /* Physical Configuration Base */
186 struct irq_domain
*legacy_irq_domain
;
189 static inline u32
nwl_bridge_readl(struct nwl_pcie
*pcie
, u32 off
)
191 return readl(pcie
->breg_base
+ off
);
194 static inline void nwl_bridge_writel(struct nwl_pcie
*pcie
, u32 val
, u32 off
)
196 writel(val
, pcie
->breg_base
+ off
);
199 static bool nwl_pcie_link_up(struct nwl_pcie
*pcie
)
201 if (readl(pcie
->pcireg_base
+ PS_LINKUP_OFFSET
) & PCIE_PHY_LINKUP_BIT
)
206 static bool nwl_phy_link_up(struct nwl_pcie
*pcie
)
208 if (readl(pcie
->pcireg_base
+ PS_LINKUP_OFFSET
) & PHY_RDY_LINKUP_BIT
)
213 static int nwl_wait_for_link(struct nwl_pcie
*pcie
)
215 struct device
*dev
= pcie
->dev
;
218 /* check if the link is up or not */
219 for (retries
= 0; retries
< LINK_WAIT_MAX_RETRIES
; retries
++) {
220 if (nwl_phy_link_up(pcie
))
222 usleep_range(LINK_WAIT_USLEEP_MIN
, LINK_WAIT_USLEEP_MAX
);
225 dev_err(dev
, "PHY link never came up\n");
229 static bool nwl_pcie_valid_device(struct pci_bus
*bus
, unsigned int devfn
)
231 struct nwl_pcie
*pcie
= bus
->sysdata
;
233 /* Check link before accessing downstream ports */
234 if (bus
->number
!= pcie
->root_busno
) {
235 if (!nwl_pcie_link_up(pcie
))
239 /* Only one device down on each root port */
240 if (bus
->number
== pcie
->root_busno
&& devfn
> 0)
247 * nwl_pcie_map_bus - Get configuration base
249 * @bus: Bus structure of current bus
250 * @devfn: Device/function
251 * @where: Offset from base
253 * Return: Base address of the configuration space needed to be
256 static void __iomem
*nwl_pcie_map_bus(struct pci_bus
*bus
, unsigned int devfn
,
259 struct nwl_pcie
*pcie
= bus
->sysdata
;
262 if (!nwl_pcie_valid_device(bus
, devfn
))
265 relbus
= (bus
->number
<< ECAM_BUS_LOC_SHIFT
) |
266 (devfn
<< ECAM_DEV_LOC_SHIFT
);
268 return pcie
->ecam_base
+ relbus
+ where
;
271 /* PCIe operations */
272 static struct pci_ops nwl_pcie_ops
= {
273 .map_bus
= nwl_pcie_map_bus
,
274 .read
= pci_generic_config_read
,
275 .write
= pci_generic_config_write
,
278 static irqreturn_t
nwl_pcie_misc_handler(int irq
, void *data
)
280 struct nwl_pcie
*pcie
= data
;
281 struct device
*dev
= pcie
->dev
;
284 /* Checking for misc interrupts */
285 misc_stat
= nwl_bridge_readl(pcie
, MSGF_MISC_STATUS
) &
286 MSGF_MISC_SR_MASKALL
;
290 if (misc_stat
& MSGF_MISC_SR_RXMSG_OVER
)
291 dev_err(dev
, "Received Message FIFO Overflow\n");
293 if (misc_stat
& MSGF_MISC_SR_SLAVE_ERR
)
294 dev_err(dev
, "Slave error\n");
296 if (misc_stat
& MSGF_MISC_SR_MASTER_ERR
)
297 dev_err(dev
, "Master error\n");
299 if (misc_stat
& MSGF_MISC_SR_I_ADDR_ERR
)
300 dev_err(dev
, "In Misc Ingress address translation error\n");
302 if (misc_stat
& MSGF_MISC_SR_E_ADDR_ERR
)
303 dev_err(dev
, "In Misc Egress address translation error\n");
305 if (misc_stat
& MSGF_MISC_SR_FATAL_AER
)
306 dev_err(dev
, "Fatal Error in AER Capability\n");
308 if (misc_stat
& MSGF_MISC_SR_NON_FATAL_AER
)
309 dev_err(dev
, "Non-Fatal Error in AER Capability\n");
311 if (misc_stat
& MSGF_MISC_SR_CORR_AER
)
312 dev_err(dev
, "Correctable Error in AER Capability\n");
314 if (misc_stat
& MSGF_MISC_SR_UR_DETECT
)
315 dev_err(dev
, "Unsupported request Detected\n");
317 if (misc_stat
& MSGF_MISC_SR_NON_FATAL_DEV
)
318 dev_err(dev
, "Non-Fatal Error Detected\n");
320 if (misc_stat
& MSGF_MISC_SR_FATAL_DEV
)
321 dev_err(dev
, "Fatal Error Detected\n");
323 if (misc_stat
& MSGF_MSIC_SR_LINK_AUTO_BWIDTH
)
324 dev_info(dev
, "Link Autonomous Bandwidth Management Status bit set\n");
326 if (misc_stat
& MSGF_MSIC_SR_LINK_BWIDTH
)
327 dev_info(dev
, "Link Bandwidth Management Status bit set\n");
329 /* Clear misc interrupt status */
330 nwl_bridge_writel(pcie
, misc_stat
, MSGF_MISC_STATUS
);
335 static void nwl_pcie_leg_handler(struct irq_desc
*desc
)
337 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
338 struct nwl_pcie
*pcie
;
339 unsigned long status
;
343 chained_irq_enter(chip
, desc
);
344 pcie
= irq_desc_get_handler_data(desc
);
346 while ((status
= nwl_bridge_readl(pcie
, MSGF_LEG_STATUS
) &
347 MSGF_LEG_SR_MASKALL
) != 0) {
348 for_each_set_bit(bit
, &status
, INTX_NUM
) {
349 virq
= irq_find_mapping(pcie
->legacy_irq_domain
,
352 generic_handle_irq(virq
);
356 chained_irq_exit(chip
, desc
);
359 static void nwl_pcie_handle_msi_irq(struct nwl_pcie
*pcie
, u32 status_reg
)
362 unsigned long status
;
368 while ((status
= nwl_bridge_readl(pcie
, status_reg
)) != 0) {
369 for_each_set_bit(bit
, &status
, 32) {
370 nwl_bridge_writel(pcie
, 1 << bit
, status_reg
);
371 virq
= irq_find_mapping(msi
->dev_domain
, bit
);
373 generic_handle_irq(virq
);
378 static void nwl_pcie_msi_handler_high(struct irq_desc
*desc
)
380 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
381 struct nwl_pcie
*pcie
= irq_desc_get_handler_data(desc
);
383 chained_irq_enter(chip
, desc
);
384 nwl_pcie_handle_msi_irq(pcie
, MSGF_MSI_STATUS_HI
);
385 chained_irq_exit(chip
, desc
);
388 static void nwl_pcie_msi_handler_low(struct irq_desc
*desc
)
390 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
391 struct nwl_pcie
*pcie
= irq_desc_get_handler_data(desc
);
393 chained_irq_enter(chip
, desc
);
394 nwl_pcie_handle_msi_irq(pcie
, MSGF_MSI_STATUS_LO
);
395 chained_irq_exit(chip
, desc
);
398 static int nwl_legacy_map(struct irq_domain
*domain
, unsigned int irq
,
399 irq_hw_number_t hwirq
)
401 irq_set_chip_and_handler(irq
, &dummy_irq_chip
, handle_simple_irq
);
402 irq_set_chip_data(irq
, domain
->host_data
);
407 static const struct irq_domain_ops legacy_domain_ops
= {
408 .map
= nwl_legacy_map
,
411 #ifdef CONFIG_PCI_MSI
412 static struct irq_chip nwl_msi_irq_chip
= {
413 .name
= "nwl_pcie:msi",
414 .irq_enable
= unmask_msi_irq
,
415 .irq_disable
= mask_msi_irq
,
416 .irq_mask
= mask_msi_irq
,
417 .irq_unmask
= unmask_msi_irq
,
421 static struct msi_domain_info nwl_msi_domain_info
= {
422 .flags
= (MSI_FLAG_USE_DEF_DOM_OPS
| MSI_FLAG_USE_DEF_CHIP_OPS
|
423 MSI_FLAG_MULTI_PCI_MSI
),
424 .chip
= &nwl_msi_irq_chip
,
428 static void nwl_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
)
430 struct nwl_pcie
*pcie
= irq_data_get_irq_chip_data(data
);
431 phys_addr_t msi_addr
= pcie
->phys_pcie_reg_base
;
433 msg
->address_lo
= lower_32_bits(msi_addr
);
434 msg
->address_hi
= upper_32_bits(msi_addr
);
435 msg
->data
= data
->hwirq
;
438 static int nwl_msi_set_affinity(struct irq_data
*irq_data
,
439 const struct cpumask
*mask
, bool force
)
444 static struct irq_chip nwl_irq_chip
= {
445 .name
= "Xilinx MSI",
446 .irq_compose_msi_msg
= nwl_compose_msi_msg
,
447 .irq_set_affinity
= nwl_msi_set_affinity
,
450 static int nwl_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
451 unsigned int nr_irqs
, void *args
)
453 struct nwl_pcie
*pcie
= domain
->host_data
;
454 struct nwl_msi
*msi
= &pcie
->msi
;
458 mutex_lock(&msi
->lock
);
459 bit
= bitmap_find_next_zero_area(msi
->bitmap
, INT_PCI_MSI_NR
, 0,
461 if (bit
>= INT_PCI_MSI_NR
) {
462 mutex_unlock(&msi
->lock
);
466 bitmap_set(msi
->bitmap
, bit
, nr_irqs
);
468 for (i
= 0; i
< nr_irqs
; i
++) {
469 irq_domain_set_info(domain
, virq
+ i
, bit
+ i
, &nwl_irq_chip
,
470 domain
->host_data
, handle_simple_irq
,
473 mutex_unlock(&msi
->lock
);
477 static void nwl_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
478 unsigned int nr_irqs
)
480 struct irq_data
*data
= irq_domain_get_irq_data(domain
, virq
);
481 struct nwl_pcie
*pcie
= irq_data_get_irq_chip_data(data
);
482 struct nwl_msi
*msi
= &pcie
->msi
;
484 mutex_lock(&msi
->lock
);
485 bitmap_clear(msi
->bitmap
, data
->hwirq
, nr_irqs
);
486 mutex_unlock(&msi
->lock
);
489 static const struct irq_domain_ops dev_msi_domain_ops
= {
490 .alloc
= nwl_irq_domain_alloc
,
491 .free
= nwl_irq_domain_free
,
494 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie
*pcie
)
496 #ifdef CONFIG_PCI_MSI
497 struct device
*dev
= pcie
->dev
;
498 struct fwnode_handle
*fwnode
= of_node_to_fwnode(dev
->of_node
);
499 struct nwl_msi
*msi
= &pcie
->msi
;
501 msi
->dev_domain
= irq_domain_add_linear(NULL
, INT_PCI_MSI_NR
,
502 &dev_msi_domain_ops
, pcie
);
503 if (!msi
->dev_domain
) {
504 dev_err(dev
, "failed to create dev IRQ domain\n");
507 msi
->msi_domain
= pci_msi_create_irq_domain(fwnode
,
508 &nwl_msi_domain_info
,
510 if (!msi
->msi_domain
) {
511 dev_err(dev
, "failed to create msi IRQ domain\n");
512 irq_domain_remove(msi
->dev_domain
);
519 static int nwl_pcie_init_irq_domain(struct nwl_pcie
*pcie
)
521 struct device
*dev
= pcie
->dev
;
522 struct device_node
*node
= dev
->of_node
;
523 struct device_node
*legacy_intc_node
;
525 legacy_intc_node
= of_get_next_child(node
, NULL
);
526 if (!legacy_intc_node
) {
527 dev_err(dev
, "No legacy intc node found\n");
531 pcie
->legacy_irq_domain
= irq_domain_add_linear(legacy_intc_node
,
536 if (!pcie
->legacy_irq_domain
) {
537 dev_err(dev
, "failed to create IRQ domain\n");
541 nwl_pcie_init_msi_irq_domain(pcie
);
545 static int nwl_pcie_enable_msi(struct nwl_pcie
*pcie
, struct pci_bus
*bus
)
547 struct device
*dev
= pcie
->dev
;
548 struct platform_device
*pdev
= to_platform_device(dev
);
549 struct nwl_msi
*msi
= &pcie
->msi
;
552 int size
= BITS_TO_LONGS(INT_PCI_MSI_NR
) * sizeof(long);
554 mutex_init(&msi
->lock
);
556 msi
->bitmap
= kzalloc(size
, GFP_KERNEL
);
560 /* Get msi_1 IRQ number */
561 msi
->irq_msi1
= platform_get_irq_byname(pdev
, "msi1");
562 if (msi
->irq_msi1
< 0) {
563 dev_err(dev
, "failed to get IRQ#%d\n", msi
->irq_msi1
);
568 irq_set_chained_handler_and_data(msi
->irq_msi1
,
569 nwl_pcie_msi_handler_high
, pcie
);
571 /* Get msi_0 IRQ number */
572 msi
->irq_msi0
= platform_get_irq_byname(pdev
, "msi0");
573 if (msi
->irq_msi0
< 0) {
574 dev_err(dev
, "failed to get IRQ#%d\n", msi
->irq_msi0
);
579 irq_set_chained_handler_and_data(msi
->irq_msi0
,
580 nwl_pcie_msi_handler_low
, pcie
);
582 /* Check for msii_present bit */
583 ret
= nwl_bridge_readl(pcie
, I_MSII_CAPABILITIES
) & MSII_PRESENT
;
585 dev_err(dev
, "MSI not present\n");
591 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, I_MSII_CONTROL
) |
592 MSII_ENABLE
, I_MSII_CONTROL
);
594 /* Enable MSII status */
595 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, I_MSII_CONTROL
) |
596 MSII_STATUS_ENABLE
, I_MSII_CONTROL
);
598 /* setup AFI/FPCI range */
599 base
= pcie
->phys_pcie_reg_base
;
600 nwl_bridge_writel(pcie
, lower_32_bits(base
), I_MSII_BASE_LO
);
601 nwl_bridge_writel(pcie
, upper_32_bits(base
), I_MSII_BASE_HI
);
604 * For high range MSI interrupts: disable, clear any pending,
607 nwl_bridge_writel(pcie
, (u32
)~MSGF_MSI_SR_HI_MASK
, MSGF_MSI_MASK_HI
);
609 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, MSGF_MSI_STATUS_HI
) &
610 MSGF_MSI_SR_HI_MASK
, MSGF_MSI_STATUS_HI
);
612 nwl_bridge_writel(pcie
, MSGF_MSI_SR_HI_MASK
, MSGF_MSI_MASK_HI
);
615 * For low range MSI interrupts: disable, clear any pending,
618 nwl_bridge_writel(pcie
, (u32
)~MSGF_MSI_SR_LO_MASK
, MSGF_MSI_MASK_LO
);
620 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, MSGF_MSI_STATUS_LO
) &
621 MSGF_MSI_SR_LO_MASK
, MSGF_MSI_STATUS_LO
);
623 nwl_bridge_writel(pcie
, MSGF_MSI_SR_LO_MASK
, MSGF_MSI_MASK_LO
);
632 static int nwl_pcie_bridge_init(struct nwl_pcie
*pcie
)
634 struct device
*dev
= pcie
->dev
;
635 struct platform_device
*pdev
= to_platform_device(dev
);
636 u32 breg_val
, ecam_val
, first_busno
= 0;
639 breg_val
= nwl_bridge_readl(pcie
, E_BREG_CAPABILITIES
) & BREG_PRESENT
;
641 dev_err(dev
, "BREG is not present\n");
645 /* Write bridge_off to breg base */
646 nwl_bridge_writel(pcie
, lower_32_bits(pcie
->phys_breg_base
),
648 nwl_bridge_writel(pcie
, upper_32_bits(pcie
->phys_breg_base
),
652 nwl_bridge_writel(pcie
, ~BREG_ENABLE_FORCE
& BREG_ENABLE
,
655 /* Disable DMA channel registers */
656 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, BRCFG_PCIE_RX0
) |
657 CFG_DMA_REG_BAR
, BRCFG_PCIE_RX0
);
659 /* Enable Ingress subtractive decode translation */
660 nwl_bridge_writel(pcie
, SET_ISUB_CONTROL
, I_ISUB_CONTROL
);
662 /* Enable msg filtering details */
663 nwl_bridge_writel(pcie
, CFG_ENABLE_MSG_FILTER_MASK
,
664 BRCFG_PCIE_RX_MSG_FILTER
);
666 err
= nwl_wait_for_link(pcie
);
670 ecam_val
= nwl_bridge_readl(pcie
, E_ECAM_CAPABILITIES
) & E_ECAM_PRESENT
;
672 dev_err(dev
, "ECAM is not present\n");
677 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, E_ECAM_CONTROL
) |
678 E_ECAM_CR_ENABLE
, E_ECAM_CONTROL
);
680 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, E_ECAM_CONTROL
) |
681 (pcie
->ecam_value
<< E_ECAM_SIZE_SHIFT
),
684 nwl_bridge_writel(pcie
, lower_32_bits(pcie
->phys_ecam_base
),
686 nwl_bridge_writel(pcie
, upper_32_bits(pcie
->phys_ecam_base
),
690 ecam_val
= nwl_bridge_readl(pcie
, E_ECAM_CONTROL
);
691 pcie
->last_busno
= (ecam_val
& E_ECAM_SIZE_LOC
) >> E_ECAM_SIZE_SHIFT
;
692 /* Write primary, secondary and subordinate bus numbers */
693 ecam_val
= first_busno
;
694 ecam_val
|= (first_busno
+ 1) << 8;
695 ecam_val
|= (pcie
->last_busno
<< E_ECAM_SIZE_SHIFT
);
696 writel(ecam_val
, (pcie
->ecam_base
+ PCI_PRIMARY_BUS
));
698 if (nwl_pcie_link_up(pcie
))
699 dev_info(dev
, "Link is UP\n");
701 dev_info(dev
, "Link is DOWN\n");
703 /* Get misc IRQ number */
704 pcie
->irq_misc
= platform_get_irq_byname(pdev
, "misc");
705 if (pcie
->irq_misc
< 0) {
706 dev_err(dev
, "failed to get misc IRQ %d\n",
711 err
= devm_request_irq(dev
, pcie
->irq_misc
,
712 nwl_pcie_misc_handler
, IRQF_SHARED
,
713 "nwl_pcie:misc", pcie
);
715 dev_err(dev
, "fail to register misc IRQ#%d\n",
720 /* Disable all misc interrupts */
721 nwl_bridge_writel(pcie
, (u32
)~MSGF_MISC_SR_MASKALL
, MSGF_MISC_MASK
);
723 /* Clear pending misc interrupts */
724 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, MSGF_MISC_STATUS
) &
725 MSGF_MISC_SR_MASKALL
, MSGF_MISC_STATUS
);
727 /* Enable all misc interrupts */
728 nwl_bridge_writel(pcie
, MSGF_MISC_SR_MASKALL
, MSGF_MISC_MASK
);
731 /* Disable all legacy interrupts */
732 nwl_bridge_writel(pcie
, (u32
)~MSGF_LEG_SR_MASKALL
, MSGF_LEG_MASK
);
734 /* Clear pending legacy interrupts */
735 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, MSGF_LEG_STATUS
) &
736 MSGF_LEG_SR_MASKALL
, MSGF_LEG_STATUS
);
738 /* Enable all legacy interrupts */
739 nwl_bridge_writel(pcie
, MSGF_LEG_SR_MASKALL
, MSGF_LEG_MASK
);
741 /* Enable the bridge config interrupt */
742 nwl_bridge_writel(pcie
, nwl_bridge_readl(pcie
, BRCFG_INTERRUPT
) |
743 BRCFG_INTERRUPT_MASK
, BRCFG_INTERRUPT
);
748 static int nwl_pcie_parse_dt(struct nwl_pcie
*pcie
,
749 struct platform_device
*pdev
)
751 struct device
*dev
= pcie
->dev
;
752 struct device_node
*node
= dev
->of_node
;
753 struct resource
*res
;
756 /* Check for device type */
757 type
= of_get_property(node
, "device_type", NULL
);
758 if (!type
|| strcmp(type
, "pci")) {
759 dev_err(dev
, "invalid \"device_type\" %s\n", type
);
763 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "breg");
764 pcie
->breg_base
= devm_ioremap_resource(dev
, res
);
765 if (IS_ERR(pcie
->breg_base
))
766 return PTR_ERR(pcie
->breg_base
);
767 pcie
->phys_breg_base
= res
->start
;
769 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "pcireg");
770 pcie
->pcireg_base
= devm_ioremap_resource(dev
, res
);
771 if (IS_ERR(pcie
->pcireg_base
))
772 return PTR_ERR(pcie
->pcireg_base
);
773 pcie
->phys_pcie_reg_base
= res
->start
;
775 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "cfg");
776 pcie
->ecam_base
= devm_ioremap_resource(dev
, res
);
777 if (IS_ERR(pcie
->ecam_base
))
778 return PTR_ERR(pcie
->ecam_base
);
779 pcie
->phys_ecam_base
= res
->start
;
781 /* Get intx IRQ number */
782 pcie
->irq_intx
= platform_get_irq_byname(pdev
, "intx");
783 if (pcie
->irq_intx
< 0) {
784 dev_err(dev
, "failed to get intx IRQ %d\n", pcie
->irq_intx
);
788 irq_set_chained_handler_and_data(pcie
->irq_intx
,
789 nwl_pcie_leg_handler
, pcie
);
794 static const struct of_device_id nwl_pcie_of_match
[] = {
795 { .compatible
= "xlnx,nwl-pcie-2.11", },
799 static int nwl_pcie_probe(struct platform_device
*pdev
)
801 struct device
*dev
= &pdev
->dev
;
802 struct device_node
*node
= dev
->of_node
;
803 struct nwl_pcie
*pcie
;
805 struct pci_bus
*child
;
807 resource_size_t iobase
= 0;
810 pcie
= devm_kzalloc(dev
, sizeof(*pcie
), GFP_KERNEL
);
815 pcie
->ecam_value
= NWL_ECAM_VALUE_DEFAULT
;
817 err
= nwl_pcie_parse_dt(pcie
, pdev
);
819 dev_err(dev
, "Parsing DT failed\n");
823 err
= nwl_pcie_bridge_init(pcie
);
825 dev_err(dev
, "HW Initialization failed\n");
829 err
= of_pci_get_host_bridge_resources(node
, 0, 0xff, &res
, &iobase
);
831 dev_err(dev
, "Getting bridge resources failed\n");
835 err
= devm_request_pci_bus_resources(dev
, &res
);
839 err
= nwl_pcie_init_irq_domain(pcie
);
841 dev_err(dev
, "Failed creating IRQ Domain\n");
845 bus
= pci_create_root_bus(dev
, pcie
->root_busno
,
846 &nwl_pcie_ops
, pcie
, &res
);
852 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
853 err
= nwl_pcie_enable_msi(pcie
, bus
);
855 dev_err(dev
, "failed to enable MSI support: %d\n", err
);
859 pci_scan_child_bus(bus
);
860 pci_assign_unassigned_bus_resources(bus
);
861 list_for_each_entry(child
, &bus
->children
, node
)
862 pcie_bus_configure_settings(child
);
863 pci_bus_add_devices(bus
);
867 pci_free_resource_list(&res
);
871 static struct platform_driver nwl_pcie_driver
= {
874 .suppress_bind_attrs
= true,
875 .of_match_table
= nwl_pcie_of_match
,
877 .probe
= nwl_pcie_probe
,
879 builtin_platform_driver(nwl_pcie_driver
);