sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / pci / proc.c
blobf82710a8694ddd48925a8ba92ef196e033e06dc8
1 /*
2 * Procfs interface for the PCI bus.
4 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
5 */
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <linux/uaccess.h>
15 #include <asm/byteorder.h>
16 #include "pci.h"
18 static int proc_initialized; /* = 0 */
20 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
22 struct pci_dev *dev = PDE_DATA(file_inode(file));
23 return fixed_size_llseek(file, off, whence, dev->cfg_size);
26 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
27 size_t nbytes, loff_t *ppos)
29 struct pci_dev *dev = PDE_DATA(file_inode(file));
30 unsigned int pos = *ppos;
31 unsigned int cnt, size;
34 * Normal users can read only the standardized portion of the
35 * configuration space as several chips lock up when trying to read
36 * undefined locations (think of Intel PIIX4 as a typical example).
39 if (capable(CAP_SYS_ADMIN))
40 size = dev->cfg_size;
41 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
42 size = 128;
43 else
44 size = 64;
46 if (pos >= size)
47 return 0;
48 if (nbytes >= size)
49 nbytes = size;
50 if (pos + nbytes > size)
51 nbytes = size - pos;
52 cnt = nbytes;
54 if (!access_ok(VERIFY_WRITE, buf, cnt))
55 return -EINVAL;
57 pci_config_pm_runtime_get(dev);
59 if ((pos & 1) && cnt) {
60 unsigned char val;
61 pci_user_read_config_byte(dev, pos, &val);
62 __put_user(val, buf);
63 buf++;
64 pos++;
65 cnt--;
68 if ((pos & 3) && cnt > 2) {
69 unsigned short val;
70 pci_user_read_config_word(dev, pos, &val);
71 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
72 buf += 2;
73 pos += 2;
74 cnt -= 2;
77 while (cnt >= 4) {
78 unsigned int val;
79 pci_user_read_config_dword(dev, pos, &val);
80 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
81 buf += 4;
82 pos += 4;
83 cnt -= 4;
86 if (cnt >= 2) {
87 unsigned short val;
88 pci_user_read_config_word(dev, pos, &val);
89 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
90 buf += 2;
91 pos += 2;
92 cnt -= 2;
95 if (cnt) {
96 unsigned char val;
97 pci_user_read_config_byte(dev, pos, &val);
98 __put_user(val, buf);
99 buf++;
100 pos++;
101 cnt--;
104 pci_config_pm_runtime_put(dev);
106 *ppos = pos;
107 return nbytes;
110 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
111 size_t nbytes, loff_t *ppos)
113 struct inode *ino = file_inode(file);
114 struct pci_dev *dev = PDE_DATA(ino);
115 int pos = *ppos;
116 int size = dev->cfg_size;
117 int cnt;
119 if (pos >= size)
120 return 0;
121 if (nbytes >= size)
122 nbytes = size;
123 if (pos + nbytes > size)
124 nbytes = size - pos;
125 cnt = nbytes;
127 if (!access_ok(VERIFY_READ, buf, cnt))
128 return -EINVAL;
130 pci_config_pm_runtime_get(dev);
132 if ((pos & 1) && cnt) {
133 unsigned char val;
134 __get_user(val, buf);
135 pci_user_write_config_byte(dev, pos, val);
136 buf++;
137 pos++;
138 cnt--;
141 if ((pos & 3) && cnt > 2) {
142 __le16 val;
143 __get_user(val, (__le16 __user *) buf);
144 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
145 buf += 2;
146 pos += 2;
147 cnt -= 2;
150 while (cnt >= 4) {
151 __le32 val;
152 __get_user(val, (__le32 __user *) buf);
153 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
154 buf += 4;
155 pos += 4;
156 cnt -= 4;
159 if (cnt >= 2) {
160 __le16 val;
161 __get_user(val, (__le16 __user *) buf);
162 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
163 buf += 2;
164 pos += 2;
165 cnt -= 2;
168 if (cnt) {
169 unsigned char val;
170 __get_user(val, buf);
171 pci_user_write_config_byte(dev, pos, val);
172 buf++;
173 pos++;
174 cnt--;
177 pci_config_pm_runtime_put(dev);
179 *ppos = pos;
180 i_size_write(ino, dev->cfg_size);
181 return nbytes;
184 struct pci_filp_private {
185 enum pci_mmap_state mmap_state;
186 int write_combine;
189 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
190 unsigned long arg)
192 struct pci_dev *dev = PDE_DATA(file_inode(file));
193 #ifdef HAVE_PCI_MMAP
194 struct pci_filp_private *fpriv = file->private_data;
195 #endif /* HAVE_PCI_MMAP */
196 int ret = 0;
198 switch (cmd) {
199 case PCIIOC_CONTROLLER:
200 ret = pci_domain_nr(dev->bus);
201 break;
203 #ifdef HAVE_PCI_MMAP
204 case PCIIOC_MMAP_IS_IO:
205 fpriv->mmap_state = pci_mmap_io;
206 break;
208 case PCIIOC_MMAP_IS_MEM:
209 fpriv->mmap_state = pci_mmap_mem;
210 break;
212 case PCIIOC_WRITE_COMBINE:
213 if (arg)
214 fpriv->write_combine = 1;
215 else
216 fpriv->write_combine = 0;
217 break;
219 #endif /* HAVE_PCI_MMAP */
221 default:
222 ret = -EINVAL;
223 break;
226 return ret;
229 #ifdef HAVE_PCI_MMAP
230 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
232 struct pci_dev *dev = PDE_DATA(file_inode(file));
233 struct pci_filp_private *fpriv = file->private_data;
234 int i, ret, write_combine;
236 if (!capable(CAP_SYS_RAWIO))
237 return -EPERM;
239 /* Make sure the caller is mapping a real resource for this device */
240 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
241 if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
242 break;
245 if (i >= PCI_ROM_RESOURCE)
246 return -ENODEV;
248 if (fpriv->mmap_state == pci_mmap_mem)
249 write_combine = fpriv->write_combine;
250 else
251 write_combine = 0;
252 ret = pci_mmap_page_range(dev, vma,
253 fpriv->mmap_state, write_combine);
254 if (ret < 0)
255 return ret;
257 return 0;
260 static int proc_bus_pci_open(struct inode *inode, struct file *file)
262 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
264 if (!fpriv)
265 return -ENOMEM;
267 fpriv->mmap_state = pci_mmap_io;
268 fpriv->write_combine = 0;
270 file->private_data = fpriv;
272 return 0;
275 static int proc_bus_pci_release(struct inode *inode, struct file *file)
277 kfree(file->private_data);
278 file->private_data = NULL;
280 return 0;
282 #endif /* HAVE_PCI_MMAP */
284 static const struct file_operations proc_bus_pci_operations = {
285 .owner = THIS_MODULE,
286 .llseek = proc_bus_pci_lseek,
287 .read = proc_bus_pci_read,
288 .write = proc_bus_pci_write,
289 .unlocked_ioctl = proc_bus_pci_ioctl,
290 .compat_ioctl = proc_bus_pci_ioctl,
291 #ifdef HAVE_PCI_MMAP
292 .open = proc_bus_pci_open,
293 .release = proc_bus_pci_release,
294 .mmap = proc_bus_pci_mmap,
295 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
296 .get_unmapped_area = get_pci_unmapped_area,
297 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
298 #endif /* HAVE_PCI_MMAP */
301 /* iterator */
302 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
304 struct pci_dev *dev = NULL;
305 loff_t n = *pos;
307 for_each_pci_dev(dev) {
308 if (!n--)
309 break;
311 return dev;
314 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
316 struct pci_dev *dev = v;
318 (*pos)++;
319 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
320 return dev;
323 static void pci_seq_stop(struct seq_file *m, void *v)
325 if (v) {
326 struct pci_dev *dev = v;
327 pci_dev_put(dev);
331 static int show_device(struct seq_file *m, void *v)
333 const struct pci_dev *dev = v;
334 const struct pci_driver *drv;
335 int i;
337 if (dev == NULL)
338 return 0;
340 drv = pci_dev_driver(dev);
341 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
342 dev->bus->number,
343 dev->devfn,
344 dev->vendor,
345 dev->device,
346 dev->irq);
348 /* only print standard and ROM resources to preserve compatibility */
349 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
350 resource_size_t start, end;
351 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
352 seq_printf(m, "\t%16llx",
353 (unsigned long long)(start |
354 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
356 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
357 resource_size_t start, end;
358 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
359 seq_printf(m, "\t%16llx",
360 dev->resource[i].start < dev->resource[i].end ?
361 (unsigned long long)(end - start) + 1 : 0);
363 seq_putc(m, '\t');
364 if (drv)
365 seq_printf(m, "%s", drv->name);
366 seq_putc(m, '\n');
367 return 0;
370 static const struct seq_operations proc_bus_pci_devices_op = {
371 .start = pci_seq_start,
372 .next = pci_seq_next,
373 .stop = pci_seq_stop,
374 .show = show_device
377 static struct proc_dir_entry *proc_bus_pci_dir;
379 int pci_proc_attach_device(struct pci_dev *dev)
381 struct pci_bus *bus = dev->bus;
382 struct proc_dir_entry *e;
383 char name[16];
385 if (!proc_initialized)
386 return -EACCES;
388 if (!bus->procdir) {
389 if (pci_proc_domain(bus)) {
390 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
391 bus->number);
392 } else {
393 sprintf(name, "%02x", bus->number);
395 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
396 if (!bus->procdir)
397 return -ENOMEM;
400 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
401 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
402 &proc_bus_pci_operations, dev);
403 if (!e)
404 return -ENOMEM;
405 proc_set_size(e, dev->cfg_size);
406 dev->procent = e;
408 return 0;
411 int pci_proc_detach_device(struct pci_dev *dev)
413 proc_remove(dev->procent);
414 dev->procent = NULL;
415 return 0;
418 int pci_proc_detach_bus(struct pci_bus *bus)
420 proc_remove(bus->procdir);
421 return 0;
424 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
426 return seq_open(file, &proc_bus_pci_devices_op);
429 static const struct file_operations proc_bus_pci_dev_operations = {
430 .owner = THIS_MODULE,
431 .open = proc_bus_pci_dev_open,
432 .read = seq_read,
433 .llseek = seq_lseek,
434 .release = seq_release,
437 static int __init pci_proc_init(void)
439 struct pci_dev *dev = NULL;
440 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
441 proc_create("devices", 0, proc_bus_pci_dir,
442 &proc_bus_pci_dev_operations);
443 proc_initialized = 1;
444 for_each_pci_dev(dev)
445 pci_proc_attach_device(dev);
447 return 0;
449 device_initcall(pci_proc_init);