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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / rtc / rtc-r7301.c
blob28d540885f3db055ebbf238983cbb64371894d79
1 /*
2 * EPSON TOYOCOM RTC-7301SF/DG Driver
3 *
4 * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
5 *
6 * Based on rtc-rp5c01.c
7 *
8 * Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
9 */
10
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/regmap.h>
16 #include <linux/platform_device.h>
17 #include <linux/rtc.h>
18
19 #define DRV_NAME "rtc-r7301"
20
21 #define RTC7301_1_SEC 0x0 /* Bank 0 and Band 1 */
22 #define RTC7301_10_SEC 0x1 /* Bank 0 and Band 1 */
23 #define RTC7301_AE BIT(3)
24 #define RTC7301_1_MIN 0x2 /* Bank 0 and Band 1 */
25 #define RTC7301_10_MIN 0x3 /* Bank 0 and Band 1 */
26 #define RTC7301_1_HOUR 0x4 /* Bank 0 and Band 1 */
27 #define RTC7301_10_HOUR 0x5 /* Bank 0 and Band 1 */
28 #define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
29 #define RTC7301_1_DAY 0x7 /* Bank 0 and Band 1 */
30 #define RTC7301_10_DAY 0x8 /* Bank 0 and Band 1 */
31 #define RTC7301_1_MONTH 0x9 /* Bank 0 */
32 #define RTC7301_10_MONTH 0xa /* Bank 0 */
33 #define RTC7301_1_YEAR 0xb /* Bank 0 */
34 #define RTC7301_10_YEAR 0xc /* Bank 0 */
35 #define RTC7301_100_YEAR 0xd /* Bank 0 */
36 #define RTC7301_1000_YEAR 0xe /* Bank 0 */
37 #define RTC7301_ALARM_CONTROL 0xe /* Bank 1 */
38 #define RTC7301_ALARM_CONTROL_AIE BIT(0)
39 #define RTC7301_ALARM_CONTROL_AF BIT(1)
40 #define RTC7301_TIMER_CONTROL 0xe /* Bank 2 */
41 #define RTC7301_TIMER_CONTROL_TIE BIT(0)
42 #define RTC7301_TIMER_CONTROL_TF BIT(1)
43 #define RTC7301_CONTROL 0xf /* All banks */
44 #define RTC7301_CONTROL_BUSY BIT(0)
45 #define RTC7301_CONTROL_STOP BIT(1)
46 #define RTC7301_CONTROL_BANK_SEL_0 BIT(2)
47 #define RTC7301_CONTROL_BANK_SEL_1 BIT(3)
48
49 struct rtc7301_priv {
50 struct regmap *regmap;
51 int irq;
52 spinlock_t lock;
53 u8 bank;
54 };
55
56 static const struct regmap_config rtc7301_regmap_config = {
57 .reg_bits = 32,
58 .val_bits = 8,
59 .reg_stride = 4,
60 };
61
62 static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
63 {
64 int reg_stride = regmap_get_reg_stride(priv->regmap);
65 unsigned int val;
66
67 regmap_read(priv->regmap, reg_stride * reg, &val);
68
69 return val & 0xf;
70 }
71
72 static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
73 {
74 int reg_stride = regmap_get_reg_stride(priv->regmap);
75
76 regmap_write(priv->regmap, reg_stride * reg, val);
77 }
78
79 static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
80 u8 mask, u8 val)
81 {
82 int reg_stride = regmap_get_reg_stride(priv->regmap);
83
84 regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
85 }
86
87 static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
88 {
89 int retries = 100;
90
91 while (retries-- > 0) {
92 u8 val;
93
94 val = rtc7301_read(priv, RTC7301_CONTROL);
95 if (!(val & RTC7301_CONTROL_BUSY))
96 return 0;
97
98 usleep_range(200, 300);
99 }
100
101 return -ETIMEDOUT;
102 }
103
104 static void rtc7301_stop(struct rtc7301_priv *priv)
105 {
106 rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
107 RTC7301_CONTROL_STOP);
108 }
109
110 static void rtc7301_start(struct rtc7301_priv *priv)
111 {
112 rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
113 }
114
115 static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
116 {
117 u8 val = 0;
118
119 if (bank == priv->bank)
120 return;
121
122 if (bank & BIT(0))
123 val |= RTC7301_CONTROL_BANK_SEL_0;
124 if (bank & BIT(1))
125 val |= RTC7301_CONTROL_BANK_SEL_1;
126
127 rtc7301_update_bits(priv, RTC7301_CONTROL,
128 RTC7301_CONTROL_BANK_SEL_0 |
129 RTC7301_CONTROL_BANK_SEL_1, val);
130
131 priv->bank = bank;
132 }
133
134 static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
135 bool alarm)
136 {
137 int year;
138
139 tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
140 tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
141 tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
142 tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
143 tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
144 tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
145 tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
146 tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
147
148 if (alarm) {
149 tm->tm_wday = -1;
150 tm->tm_mon = -1;
151 tm->tm_year = -1;
152 tm->tm_yday = -1;
153 tm->tm_isdst = -1;
154 return;
155 }
156
157 tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
158 tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
159 rtc7301_read(priv, RTC7301_1_MONTH) - 1;
160 year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
161 rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
162 rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
163 rtc7301_read(priv, RTC7301_1_YEAR);
164
165 tm->tm_year = year - 1900;
166 }
167
168 static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
169 bool alarm)
170 {
171 int year;
172
173 rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
174 rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
175
176 rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
177 rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
178
179 rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
180 rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
181
182 rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
183 rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
184
185 /* Don't care for alarm register */
186 rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
187 RTC7301_DAY_OF_WEEK);
188
189 if (alarm)
190 return;
191
192 rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
193 rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
194
195 year = tm->tm_year + 1900;
196
197 rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
198 rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
199 rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
200 rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
201 }
202
203 static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
204 {
205 rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
206 RTC7301_ALARM_CONTROL_AF |
207 RTC7301_ALARM_CONTROL_AIE,
208 enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
209 }
210
211 static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
212 {
213 struct rtc7301_priv *priv = dev_get_drvdata(dev);
214 unsigned long flags;
215 int err;
216
217 spin_lock_irqsave(&priv->lock, flags);
218
219 rtc7301_select_bank(priv, 0);
220
221 err = rtc7301_wait_while_busy(priv);
222 if (!err)
223 rtc7301_get_time(priv, tm, false);
224
225 spin_unlock_irqrestore(&priv->lock, flags);
226
227 return err ? err : rtc_valid_tm(tm);
228 }
229
230 static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
231 {
232 struct rtc7301_priv *priv = dev_get_drvdata(dev);
233 unsigned long flags;
234
235 spin_lock_irqsave(&priv->lock, flags);
236
237 rtc7301_stop(priv);
238 usleep_range(200, 300);
239 rtc7301_select_bank(priv, 0);
240 rtc7301_write_time(priv, tm, false);
241 rtc7301_start(priv);
242
243 spin_unlock_irqrestore(&priv->lock, flags);
244
245 return 0;
246 }
247
248 static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
249 {
250 struct rtc7301_priv *priv = dev_get_drvdata(dev);
251 unsigned long flags;
252 u8 alrm_ctrl;
253
254 if (priv->irq <= 0)
255 return -EINVAL;
256
257 spin_lock_irqsave(&priv->lock, flags);
258
259 rtc7301_select_bank(priv, 1);
260 rtc7301_get_time(priv, &alarm->time, true);
261
262 alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
263
264 alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
265 alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
266
267 spin_unlock_irqrestore(&priv->lock, flags);
268
269 return 0;
270 }
271
272 static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
273 {
274 struct rtc7301_priv *priv = dev_get_drvdata(dev);
275 unsigned long flags;
276
277 if (priv->irq <= 0)
278 return -EINVAL;
279
280 spin_lock_irqsave(&priv->lock, flags);
281
282 rtc7301_select_bank(priv, 1);
283 rtc7301_write_time(priv, &alarm->time, true);
284 rtc7301_alarm_irq(priv, alarm->enabled);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 return 0;
289 }
290
291 static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
292 {
293 struct rtc7301_priv *priv = dev_get_drvdata(dev);
294 unsigned long flags;
295
296 if (priv->irq <= 0)
297 return -EINVAL;
298
299 spin_lock_irqsave(&priv->lock, flags);
300
301 rtc7301_select_bank(priv, 1);
302 rtc7301_alarm_irq(priv, enabled);
303
304 spin_unlock_irqrestore(&priv->lock, flags);
305
306 return 0;
307 }
308
309 static const struct rtc_class_ops rtc7301_rtc_ops = {
310 .read_time = rtc7301_read_time,
311 .set_time = rtc7301_set_time,
312 .read_alarm = rtc7301_read_alarm,
313 .set_alarm = rtc7301_set_alarm,
314 .alarm_irq_enable = rtc7301_alarm_irq_enable,
315 };
316
317 static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
318 {
319 struct rtc_device *rtc = dev_id;
320 struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
321 unsigned long flags;
322 irqreturn_t ret = IRQ_NONE;
323 u8 alrm_ctrl;
324
325 spin_lock_irqsave(&priv->lock, flags);
326
327 rtc7301_select_bank(priv, 1);
328
329 alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
330 if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
331 ret = IRQ_HANDLED;
332 rtc7301_alarm_irq(priv, false);
333 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
334 }
335
336 spin_unlock_irqrestore(&priv->lock, flags);
337
338 return ret;
339 }
340
341 static void rtc7301_init(struct rtc7301_priv *priv)
342 {
343 unsigned long flags;
344
345 spin_lock_irqsave(&priv->lock, flags);
346
347 rtc7301_select_bank(priv, 2);
348 rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
349
350 spin_unlock_irqrestore(&priv->lock, flags);
351 }
352
353 static int __init rtc7301_rtc_probe(struct platform_device *dev)
354 {
355 struct resource *res;
356 void __iomem *regs;
357 struct rtc7301_priv *priv;
358 struct rtc_device *rtc;
359 int ret;
360
361 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
362 if (!res)
363 return -ENODEV;
364
365 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
366 if (!priv)
367 return -ENOMEM;
368
369 regs = devm_ioremap_resource(&dev->dev, res);
370 if (IS_ERR(regs))
371 return PTR_ERR(regs);
372
373 priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
374 &rtc7301_regmap_config);
375 if (IS_ERR(priv->regmap))
376 return PTR_ERR(priv->regmap);
377
378 priv->irq = platform_get_irq(dev, 0);
379
380 spin_lock_init(&priv->lock);
381 priv->bank = -1;
382
383 rtc7301_init(priv);
384
385 platform_set_drvdata(dev, priv);
386
387 rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
388 THIS_MODULE);
389 if (IS_ERR(rtc))
390 return PTR_ERR(rtc);
391
392 if (priv->irq > 0) {
393 ret = devm_request_irq(&dev->dev, priv->irq,
394 rtc7301_irq_handler, IRQF_SHARED,
395 dev_name(&dev->dev), rtc);
396 if (ret) {
397 priv->irq = 0;
398 dev_err(&dev->dev, "unable to request IRQ\n");
399 } else {
400 device_set_wakeup_capable(&dev->dev, true);
401 }
402 }
403
404 return 0;
405 }
406
407 #ifdef CONFIG_PM_SLEEP
408
409 static int rtc7301_suspend(struct device *dev)
410 {
411 struct rtc7301_priv *priv = dev_get_drvdata(dev);
412
413 if (device_may_wakeup(dev))
414 enable_irq_wake(priv->irq);
415
416 return 0;
417 }
418
419 static int rtc7301_resume(struct device *dev)
420 {
421 struct rtc7301_priv *priv = dev_get_drvdata(dev);
422
423 if (device_may_wakeup(dev))
424 disable_irq_wake(priv->irq);
425
426 return 0;
427 }
428
429 #endif
430
431 static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
432
433 static const struct of_device_id rtc7301_dt_match[] = {
434 { .compatible = "epson,rtc7301sf" },
435 { .compatible = "epson,rtc7301dg" },
436 {}
437 };
438 MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
439
440 static struct platform_driver rtc7301_rtc_driver = {
441 .driver = {
442 .name = DRV_NAME,
443 .of_match_table = rtc7301_dt_match,
444 .pm = &rtc7301_pm_ops,
445 },
446 };
447
448 module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
449
450 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
451 MODULE_LICENSE("GPL");
452 MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
453 MODULE_ALIAS("platform:rtc-r7301");
Linux with added FPC-III support