drivers/rtc/rtc-snvs.c

   1 /*
   2  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/rtc.h>
  20 #include <linux/clk.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/regmap.h>
  23
  24 #define SNVS_LPREGISTER_OFFSET  0x34
  25
  26 /* These register offsets are relative to LP (Low Power) range */
  27 #define SNVS_LPCR               0x04
  28 #define SNVS_LPSR               0x18
  29 #define SNVS_LPSRTCMR           0x1c
  30 #define SNVS_LPSRTCLR           0x20
  31 #define SNVS_LPTAR              0x24
  32 #define SNVS_LPPGDR             0x30
  33
  34 #define SNVS_LPCR_SRTC_ENV      (1 << 0)
  35 #define SNVS_LPCR_LPTA_EN       (1 << 1)
  36 #define SNVS_LPCR_LPWUI_EN      (1 << 3)
  37 #define SNVS_LPSR_LPTA          (1 << 0)
  38
  39 #define SNVS_LPPGDR_INIT        0x41736166
  40 #define CNTR_TO_SECS_SH         15
  41
  42 struct snvs_rtc_data {
  43         struct rtc_device *rtc;
  44         struct regmap *regmap;
  45         int offset;
  46         int irq;
  47         struct clk *clk;
  48 };
  49
  50 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
  51 {
  52         u64 read1, read2;
  53         u32 val;
  54
  55         do {
  56                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
  57                 read1 = val;
  58                 read1 <<= 32;
  59                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
  60                 read1 |= val;
  61
  62                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val);
  63                 read2 = val;
  64                 read2 <<= 32;
  65                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val);
  66                 read2 |= val;
  67         } while (read1 != read2);
  68
  69         /* Convert 47-bit counter to 32-bit raw second count */
  70         return (u32) (read1 >> CNTR_TO_SECS_SH);
  71 }
  72
  73 static void rtc_write_sync_lp(struct snvs_rtc_data *data)
  74 {
  75         u32 count1, count2, count3;
  76         int i;
  77
  78         /* Wait for 3 CKIL cycles */
  79         for (i = 0; i < 3; i++) {
  80                 do {
  81                         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
  82                         regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
  83                 } while (count1 != count2);
  84
  85                 /* Now wait until counter value changes */
  86                 do {
  87                         do {
  88                                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2);
  89                                 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3);
  90                         } while (count2 != count3);
  91                 } while (count3 == count1);
  92         }
  93 }
  94
  95 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
  96 {
  97         int timeout = 1000;
  98         u32 lpcr;
  99
 100         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
 101                            enable ? SNVS_LPCR_SRTC_ENV : 0);
 102
 103         while (--timeout) {
 104                 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
 105
 106                 if (enable) {
 107                         if (lpcr & SNVS_LPCR_SRTC_ENV)
 108                                 break;
 109                 } else {
 110                         if (!(lpcr & SNVS_LPCR_SRTC_ENV))
 111                                 break;
 112                 }
 113         }
 114
 115         if (!timeout)
 116                 return -ETIMEDOUT;
 117
 118         return 0;
 119 }
 120
 121 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
 122 {
 123         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 124         unsigned long time = rtc_read_lp_counter(data);
 125
 126         rtc_time_to_tm(time, tm);
 127
 128         return 0;
 129 }
 130
 131 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
 132 {
 133         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 134         unsigned long time;
 135
 136         rtc_tm_to_time(tm, &time);
 137
 138         /* Disable RTC first */
 139         snvs_rtc_enable(data, false);
 140
 141         /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
 142         regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
 143         regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
 144
 145         /* Enable RTC again */
 146         snvs_rtc_enable(data, true);
 147
 148         return 0;
 149 }
 150
 151 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 152 {
 153         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 154         u32 lptar, lpsr;
 155
 156         regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
 157         rtc_time_to_tm(lptar, &alrm->time);
 158
 159         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 160         alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
 161
 162         return 0;
 163 }
 164
 165 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 166 {
 167         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 168
 169         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
 170                            (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
 171                            enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
 172
 173         rtc_write_sync_lp(data);
 174
 175         return 0;
 176 }
 177
 178 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 179 {
 180         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 181         struct rtc_time *alrm_tm = &alrm->time;
 182         unsigned long time;
 183
 184         rtc_tm_to_time(alrm_tm, &time);
 185
 186         regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
 187         regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
 188
 189         /* Clear alarm interrupt status bit */
 190         regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
 191
 192         return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
 193 }
 194
 195 static const struct rtc_class_ops snvs_rtc_ops = {
 196         .read_time = snvs_rtc_read_time,
 197         .set_time = snvs_rtc_set_time,
 198         .read_alarm = snvs_rtc_read_alarm,
 199         .set_alarm = snvs_rtc_set_alarm,
 200         .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
 201 };
 202
 203 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
 204 {
 205         struct device *dev = dev_id;
 206         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 207         u32 lpsr;
 208         u32 events = 0;
 209
 210         regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
 211
 212         if (lpsr & SNVS_LPSR_LPTA) {
 213                 events |= (RTC_AF | RTC_IRQF);
 214
 215                 /* RTC alarm should be one-shot */
 216                 snvs_rtc_alarm_irq_enable(dev, 0);
 217
 218                 rtc_update_irq(data->rtc, 1, events);
 219         }
 220
 221         /* clear interrupt status */
 222         regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
 223
 224         return events ? IRQ_HANDLED : IRQ_NONE;
 225 }
 226
 227 static const struct regmap_config snvs_rtc_config = {
 228         .reg_bits = 32,
 229         .val_bits = 32,
 230         .reg_stride = 4,
 231 };
 232
 233 static int snvs_rtc_probe(struct platform_device *pdev)
 234 {
 235         struct snvs_rtc_data *data;
 236         struct resource *res;
 237         int ret;
 238         void __iomem *mmio;
 239
 240         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 241         if (!data)
 242                 return -ENOMEM;
 243
 244         data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
 245
 246         if (IS_ERR(data->regmap)) {
 247                 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
 248                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 249
 250                 mmio = devm_ioremap_resource(&pdev->dev, res);
 251                 if (IS_ERR(mmio))
 252                         return PTR_ERR(mmio);
 253
 254                 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
 255         } else {
 256                 data->offset = SNVS_LPREGISTER_OFFSET;
 257                 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
 258         }
 259
 260         if (!data->regmap) {
 261                 dev_err(&pdev->dev, "Can't find snvs syscon\n");
 262                 return -ENODEV;
 263         }
 264
 265         data->irq = platform_get_irq(pdev, 0);
 266         if (data->irq < 0)
 267                 return data->irq;
 268
 269         data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
 270         if (IS_ERR(data->clk)) {
 271                 data->clk = NULL;
 272         } else {
 273                 ret = clk_prepare_enable(data->clk);
 274                 if (ret) {
 275                         dev_err(&pdev->dev,
 276                                 "Could not prepare or enable the snvs clock\n");
 277                         return ret;
 278                 }
 279         }
 280
 281         platform_set_drvdata(pdev, data);
 282
 283         /* Initialize glitch detect */
 284         regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
 285
 286         /* Clear interrupt status */
 287         regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
 288
 289         /* Enable RTC */
 290         snvs_rtc_enable(data, true);
 291
 292         device_init_wakeup(&pdev->dev, true);
 293
 294         ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
 295                                IRQF_SHARED, "rtc alarm", &pdev->dev);
 296         if (ret) {
 297                 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
 298                         data->irq, ret);
 299                 goto error_rtc_device_register;
 300         }
 301
 302         data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 303                                         &snvs_rtc_ops, THIS_MODULE);
 304         if (IS_ERR(data->rtc)) {
 305                 ret = PTR_ERR(data->rtc);
 306                 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
 307                 goto error_rtc_device_register;
 308         }
 309
 310         return 0;
 311
 312 error_rtc_device_register:
 313         if (data->clk)
 314                 clk_disable_unprepare(data->clk);
 315
 316         return ret;
 317 }
 318
 319 #ifdef CONFIG_PM_SLEEP
 320 static int snvs_rtc_suspend(struct device *dev)
 321 {
 322         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 323
 324         if (device_may_wakeup(dev))
 325                 return enable_irq_wake(data->irq);
 326
 327         return 0;
 328 }
 329
 330 static int snvs_rtc_suspend_noirq(struct device *dev)
 331 {
 332         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 333
 334         if (data->clk)
 335                 clk_disable_unprepare(data->clk);
 336
 337         return 0;
 338 }
 339
 340 static int snvs_rtc_resume(struct device *dev)
 341 {
 342         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 343
 344         if (device_may_wakeup(dev))
 345                 return disable_irq_wake(data->irq);
 346
 347         return 0;
 348 }
 349
 350 static int snvs_rtc_resume_noirq(struct device *dev)
 351 {
 352         struct snvs_rtc_data *data = dev_get_drvdata(dev);
 353
 354         if (data->clk)
 355                 return clk_prepare_enable(data->clk);
 356
 357         return 0;
 358 }
 359
 360 static const struct dev_pm_ops snvs_rtc_pm_ops = {
 361         .suspend = snvs_rtc_suspend,
 362         .suspend_noirq = snvs_rtc_suspend_noirq,
 363         .resume = snvs_rtc_resume,
 364         .resume_noirq = snvs_rtc_resume_noirq,
 365 };
 366
 367 #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
 368
 369 #else
 370
 371 #define SNVS_RTC_PM_OPS NULL
 372
 373 #endif
 374
 375 static const struct of_device_id snvs_dt_ids[] = {
 376         { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
 377         { /* sentinel */ }
 378 };
 379 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
 380
 381 static struct platform_driver snvs_rtc_driver = {
 382         .driver = {
 383                 .name   = "snvs_rtc",
 384                 .pm     = SNVS_RTC_PM_OPS,
 385                 .of_match_table = snvs_dt_ids,
 386         },
 387         .probe          = snvs_rtc_probe,
 388 };
 389 module_platform_driver(snvs_rtc_driver);
 390
 391 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 392 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
 393 MODULE_LICENSE("GPL");