sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / sh / intc / internals.h
blob6ce7f0d26dcf0ec914b433cec73cf0c2337fb1e8
1 #include <linux/sh_intc.h>
2 #include <linux/irq.h>
3 #include <linux/irqdomain.h>
4 #include <linux/list.h>
5 #include <linux/kernel.h>
6 #include <linux/types.h>
7 #include <linux/radix-tree.h>
8 #include <linux/device.h>
10 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
11 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
12 ((addr_e) << 16) | ((addr_d << 24)))
14 #define _INTC_SHIFT(h) (h & 0x1f)
15 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
16 #define _INTC_FN(h) ((h >> 9) & 0xf)
17 #define _INTC_MODE(h) ((h >> 13) & 0x7)
18 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
19 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
21 #ifdef CONFIG_SMP
22 #define IS_SMP(x) (x.smp)
23 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
24 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
25 #else
26 #define IS_SMP(x) 0
27 #define INTC_REG(d, x, c) (d->reg[(x)])
28 #define SMP_NR(d, x) 1
29 #endif
31 struct intc_handle_int {
32 unsigned int irq;
33 unsigned long handle;
36 struct intc_window {
37 phys_addr_t phys;
38 void __iomem *virt;
39 unsigned long size;
42 struct intc_map_entry {
43 intc_enum enum_id;
44 struct intc_desc_int *desc;
47 struct intc_subgroup_entry {
48 unsigned int pirq;
49 intc_enum enum_id;
50 unsigned long handle;
53 struct intc_desc_int {
54 struct list_head list;
55 struct device dev;
56 struct radix_tree_root tree;
57 raw_spinlock_t lock;
58 unsigned int index;
59 unsigned long *reg;
60 #ifdef CONFIG_SMP
61 unsigned long *smp;
62 #endif
63 unsigned int nr_reg;
64 struct intc_handle_int *prio;
65 unsigned int nr_prio;
66 struct intc_handle_int *sense;
67 unsigned int nr_sense;
68 struct intc_window *window;
69 unsigned int nr_windows;
70 struct irq_domain *domain;
71 struct irq_chip chip;
72 bool skip_suspend;
76 enum {
77 REG_FN_ERR = 0,
78 REG_FN_TEST_BASE = 1,
79 REG_FN_WRITE_BASE = 5,
80 REG_FN_MODIFY_BASE = 9
83 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
84 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
85 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
86 MODE_PRIO_REG, /* Priority value written to enable interrupt */
87 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
90 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
92 struct irq_chip *chip = irq_get_chip(irq);
94 return container_of(chip, struct intc_desc_int, chip);
98 * Grumble.
100 static inline void activate_irq(int irq)
102 irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
105 static inline int intc_handle_int_cmp(const void *a, const void *b)
107 const struct intc_handle_int *_a = a;
108 const struct intc_handle_int *_b = b;
110 return _a->irq - _b->irq;
113 /* access.c */
114 extern unsigned long
115 (*intc_reg_fns[])(unsigned long addr, unsigned long h, unsigned long data);
117 extern unsigned long
118 (*intc_enable_fns[])(unsigned long addr, unsigned long handle,
119 unsigned long (*fn)(unsigned long,
120 unsigned long, unsigned long),
121 unsigned int irq);
122 extern unsigned long
123 (*intc_disable_fns[])(unsigned long addr, unsigned long handle,
124 unsigned long (*fn)(unsigned long,
125 unsigned long, unsigned long),
126 unsigned int irq);
127 extern unsigned long
128 (*intc_enable_noprio_fns[])(unsigned long addr, unsigned long handle,
129 unsigned long (*fn)(unsigned long,
130 unsigned long, unsigned long),
131 unsigned int irq);
133 unsigned long intc_phys_to_virt(struct intc_desc_int *d, unsigned long address);
134 unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address);
135 unsigned int intc_set_field_from_handle(unsigned int value,
136 unsigned int field_value,
137 unsigned int handle);
138 unsigned long intc_get_field_from_handle(unsigned int value,
139 unsigned int handle);
141 /* balancing.c */
142 #ifdef CONFIG_INTC_BALANCING
143 void intc_balancing_enable(unsigned int irq);
144 void intc_balancing_disable(unsigned int irq);
145 void intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
146 struct intc_desc_int *d, intc_enum id);
147 #else
148 static inline void intc_balancing_enable(unsigned int irq) { }
149 static inline void intc_balancing_disable(unsigned int irq) { }
150 static inline void
151 intc_set_dist_handle(unsigned int irq, struct intc_desc *desc,
152 struct intc_desc_int *d, intc_enum id) { }
153 #endif
155 /* chip.c */
156 extern struct irq_chip intc_irq_chip;
157 void _intc_enable(struct irq_data *data, unsigned long handle);
159 /* core.c */
160 extern struct list_head intc_list;
161 extern raw_spinlock_t intc_big_lock;
162 extern struct bus_type intc_subsys;
164 unsigned int intc_get_dfl_prio_level(void);
165 unsigned int intc_get_prio_level(unsigned int irq);
166 void intc_set_prio_level(unsigned int irq, unsigned int level);
168 /* handle.c */
169 unsigned int intc_get_mask_handle(struct intc_desc *desc,
170 struct intc_desc_int *d,
171 intc_enum enum_id, int do_grps);
172 unsigned int intc_get_prio_handle(struct intc_desc *desc,
173 struct intc_desc_int *d,
174 intc_enum enum_id, int do_grps);
175 unsigned int intc_get_sense_handle(struct intc_desc *desc,
176 struct intc_desc_int *d,
177 intc_enum enum_id);
178 void intc_set_ack_handle(unsigned int irq, struct intc_desc *desc,
179 struct intc_desc_int *d, intc_enum id);
180 unsigned long intc_get_ack_handle(unsigned int irq);
181 void intc_enable_disable_enum(struct intc_desc *desc, struct intc_desc_int *d,
182 intc_enum enum_id, int enable);
184 /* irqdomain.c */
185 void intc_irq_domain_init(struct intc_desc_int *d, struct intc_hw_desc *hw);
187 /* virq.c */
188 void intc_subgroup_init(struct intc_desc *desc, struct intc_desc_int *d);
189 void intc_irq_xlate_set(unsigned int irq, intc_enum id, struct intc_desc_int *d);
190 struct intc_map_entry *intc_irq_xlate_get(unsigned int irq);