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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / ssb / main.c
blobd1a750760cf30b270b44929ac91eb22971d15b22
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
24
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
27
28
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
31
32
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue);
35 /* List if running buses */
36 static LIST_HEAD(buses);
37 /* Software ID counter */
38 static unsigned int next_busnumber;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex);
42
43 /* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49 static bool ssb_is_early_boot = 1;
50
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
53
54
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
57 {
58 struct ssb_bus *bus;
59
60 ssb_buses_lock();
61 list_for_each_entry(bus, &buses, list) {
62 if (bus->bustype == SSB_BUSTYPE_PCI &&
63 bus->host_pci == pdev)
64 goto found;
65 }
66 bus = NULL;
67 found:
68 ssb_buses_unlock();
69
70 return bus;
71 }
72 #endif /* CONFIG_SSB_PCIHOST */
73
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
76 {
77 struct ssb_bus *bus;
78
79 ssb_buses_lock();
80 list_for_each_entry(bus, &buses, list) {
81 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 bus->host_pcmcia == pdev)
83 goto found;
84 }
85 bus = NULL;
86 found:
87 ssb_buses_unlock();
88
89 return bus;
90 }
91 #endif /* CONFIG_SSB_PCMCIAHOST */
92
93 int ssb_for_each_bus_call(unsigned long data,
94 int (*func)(struct ssb_bus *bus, unsigned long data))
95 {
96 struct ssb_bus *bus;
97 int res;
98
99 ssb_buses_lock();
100 list_for_each_entry(bus, &buses, list) {
101 res = func(bus, data);
102 if (res >= 0) {
103 ssb_buses_unlock();
104 return res;
105 }
106 }
107 ssb_buses_unlock();
108
109 return -ENODEV;
110 }
111
112 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
113 {
114 if (dev)
115 get_device(dev->dev);
116 return dev;
117 }
118
119 static void ssb_device_put(struct ssb_device *dev)
120 {
121 if (dev)
122 put_device(dev->dev);
123 }
124
125 static int ssb_device_resume(struct device *dev)
126 {
127 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
128 struct ssb_driver *ssb_drv;
129 int err = 0;
130
131 if (dev->driver) {
132 ssb_drv = drv_to_ssb_drv(dev->driver);
133 if (ssb_drv && ssb_drv->resume)
134 err = ssb_drv->resume(ssb_dev);
135 if (err)
136 goto out;
137 }
138 out:
139 return err;
140 }
141
142 static int ssb_device_suspend(struct device *dev, pm_message_t state)
143 {
144 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
145 struct ssb_driver *ssb_drv;
146 int err = 0;
147
148 if (dev->driver) {
149 ssb_drv = drv_to_ssb_drv(dev->driver);
150 if (ssb_drv && ssb_drv->suspend)
151 err = ssb_drv->suspend(ssb_dev, state);
152 if (err)
153 goto out;
154 }
155 out:
156 return err;
157 }
158
159 int ssb_bus_resume(struct ssb_bus *bus)
160 {
161 int err;
162
163 /* Reset HW state information in memory, so that HW is
164 * completely reinitialized. */
165 bus->mapped_device = NULL;
166 #ifdef CONFIG_SSB_DRIVER_PCICORE
167 bus->pcicore.setup_done = 0;
168 #endif
169
170 err = ssb_bus_powerup(bus, 0);
171 if (err)
172 return err;
173 err = ssb_pcmcia_hardware_setup(bus);
174 if (err) {
175 ssb_bus_may_powerdown(bus);
176 return err;
177 }
178 ssb_chipco_resume(&bus->chipco);
179 ssb_bus_may_powerdown(bus);
180
181 return 0;
182 }
183 EXPORT_SYMBOL(ssb_bus_resume);
184
185 int ssb_bus_suspend(struct ssb_bus *bus)
186 {
187 ssb_chipco_suspend(&bus->chipco);
188 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
189
190 return 0;
191 }
192 EXPORT_SYMBOL(ssb_bus_suspend);
193
194 #ifdef CONFIG_SSB_SPROM
195 /** ssb_devices_freeze - Freeze all devices on the bus.
196 *
197 * After freezing no device driver will be handling a device
198 * on this bus anymore. ssb_devices_thaw() must be called after
199 * a successful freeze to reactivate the devices.
200 *
201 * @bus: The bus.
202 * @ctx: Context structure. Pass this to ssb_devices_thaw().
203 */
204 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
205 {
206 struct ssb_device *sdev;
207 struct ssb_driver *sdrv;
208 unsigned int i;
209
210 memset(ctx, 0, sizeof(*ctx));
211 ctx->bus = bus;
212 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
213
214 for (i = 0; i < bus->nr_devices; i++) {
215 sdev = ssb_device_get(&bus->devices[i]);
216
217 if (!sdev->dev || !sdev->dev->driver ||
218 !device_is_registered(sdev->dev)) {
219 ssb_device_put(sdev);
220 continue;
221 }
222 sdrv = drv_to_ssb_drv(sdev->dev->driver);
223 if (SSB_WARN_ON(!sdrv->remove))
224 continue;
225 sdrv->remove(sdev);
226 ctx->device_frozen[i] = 1;
227 }
228
229 return 0;
230 }
231
232 /** ssb_devices_thaw - Unfreeze all devices on the bus.
233 *
234 * This will re-attach the device drivers and re-init the devices.
235 *
236 * @ctx: The context structure from ssb_devices_freeze()
237 */
238 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
239 {
240 struct ssb_bus *bus = ctx->bus;
241 struct ssb_device *sdev;
242 struct ssb_driver *sdrv;
243 unsigned int i;
244 int err, result = 0;
245
246 for (i = 0; i < bus->nr_devices; i++) {
247 if (!ctx->device_frozen[i])
248 continue;
249 sdev = &bus->devices[i];
250
251 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
252 continue;
253 sdrv = drv_to_ssb_drv(sdev->dev->driver);
254 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
255 continue;
256
257 err = sdrv->probe(sdev, &sdev->id);
258 if (err) {
259 ssb_err("Failed to thaw device %s\n",
260 dev_name(sdev->dev));
261 result = err;
262 }
263 ssb_device_put(sdev);
264 }
265
266 return result;
267 }
268 #endif /* CONFIG_SSB_SPROM */
269
270 static void ssb_device_shutdown(struct device *dev)
271 {
272 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
273 struct ssb_driver *ssb_drv;
274
275 if (!dev->driver)
276 return;
277 ssb_drv = drv_to_ssb_drv(dev->driver);
278 if (ssb_drv && ssb_drv->shutdown)
279 ssb_drv->shutdown(ssb_dev);
280 }
281
282 static int ssb_device_remove(struct device *dev)
283 {
284 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
285 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
286
287 if (ssb_drv && ssb_drv->remove)
288 ssb_drv->remove(ssb_dev);
289 ssb_device_put(ssb_dev);
290
291 return 0;
292 }
293
294 static int ssb_device_probe(struct device *dev)
295 {
296 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
297 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
298 int err = 0;
299
300 ssb_device_get(ssb_dev);
301 if (ssb_drv && ssb_drv->probe)
302 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
303 if (err)
304 ssb_device_put(ssb_dev);
305
306 return err;
307 }
308
309 static int ssb_match_devid(const struct ssb_device_id *tabid,
310 const struct ssb_device_id *devid)
311 {
312 if ((tabid->vendor != devid->vendor) &&
313 tabid->vendor != SSB_ANY_VENDOR)
314 return 0;
315 if ((tabid->coreid != devid->coreid) &&
316 tabid->coreid != SSB_ANY_ID)
317 return 0;
318 if ((tabid->revision != devid->revision) &&
319 tabid->revision != SSB_ANY_REV)
320 return 0;
321 return 1;
322 }
323
324 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
325 {
326 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
327 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
328 const struct ssb_device_id *id;
329
330 for (id = ssb_drv->id_table;
331 id->vendor || id->coreid || id->revision;
332 id++) {
333 if (ssb_match_devid(id, &ssb_dev->id))
334 return 1; /* found */
335 }
336
337 return 0;
338 }
339
340 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
341 {
342 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
343
344 if (!dev)
345 return -ENODEV;
346
347 return add_uevent_var(env,
348 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
349 ssb_dev->id.vendor, ssb_dev->id.coreid,
350 ssb_dev->id.revision);
351 }
352
353 #define ssb_config_attr(attrib, field, format_string) \
354 static ssize_t \
355 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
356 { \
357 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
358 } \
359 static DEVICE_ATTR_RO(attrib);
360
361 ssb_config_attr(core_num, core_index, "%u\n")
362 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
363 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
364 ssb_config_attr(revision, id.revision, "%u\n")
365 ssb_config_attr(irq, irq, "%u\n")
366 static ssize_t
367 name_show(struct device *dev, struct device_attribute *attr, char *buf)
368 {
369 return sprintf(buf, "%s\n",
370 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
371 }
372 static DEVICE_ATTR_RO(name);
373
374 static struct attribute *ssb_device_attrs[] = {
375 &dev_attr_name.attr,
376 &dev_attr_core_num.attr,
377 &dev_attr_coreid.attr,
378 &dev_attr_vendor.attr,
379 &dev_attr_revision.attr,
380 &dev_attr_irq.attr,
381 NULL,
382 };
383 ATTRIBUTE_GROUPS(ssb_device);
384
385 static struct bus_type ssb_bustype = {
386 .name = "ssb",
387 .match = ssb_bus_match,
388 .probe = ssb_device_probe,
389 .remove = ssb_device_remove,
390 .shutdown = ssb_device_shutdown,
391 .suspend = ssb_device_suspend,
392 .resume = ssb_device_resume,
393 .uevent = ssb_device_uevent,
394 .dev_groups = ssb_device_groups,
395 };
396
397 static void ssb_buses_lock(void)
398 {
399 /* See the comment at the ssb_is_early_boot definition */
400 if (!ssb_is_early_boot)
401 mutex_lock(&buses_mutex);
402 }
403
404 static void ssb_buses_unlock(void)
405 {
406 /* See the comment at the ssb_is_early_boot definition */
407 if (!ssb_is_early_boot)
408 mutex_unlock(&buses_mutex);
409 }
410
411 static void ssb_devices_unregister(struct ssb_bus *bus)
412 {
413 struct ssb_device *sdev;
414 int i;
415
416 for (i = bus->nr_devices - 1; i >= 0; i--) {
417 sdev = &(bus->devices[i]);
418 if (sdev->dev)
419 device_unregister(sdev->dev);
420 }
421
422 #ifdef CONFIG_SSB_EMBEDDED
423 if (bus->bustype == SSB_BUSTYPE_SSB)
424 platform_device_unregister(bus->watchdog);
425 #endif
426 }
427
428 void ssb_bus_unregister(struct ssb_bus *bus)
429 {
430 int err;
431
432 err = ssb_gpio_unregister(bus);
433 if (err == -EBUSY)
434 ssb_dbg("Some GPIOs are still in use\n");
435 else if (err)
436 ssb_dbg("Can not unregister GPIO driver: %i\n", err);
437
438 ssb_buses_lock();
439 ssb_devices_unregister(bus);
440 list_del(&bus->list);
441 ssb_buses_unlock();
442
443 ssb_pcmcia_exit(bus);
444 ssb_pci_exit(bus);
445 ssb_iounmap(bus);
446 }
447 EXPORT_SYMBOL(ssb_bus_unregister);
448
449 static void ssb_release_dev(struct device *dev)
450 {
451 struct __ssb_dev_wrapper *devwrap;
452
453 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
454 kfree(devwrap);
455 }
456
457 static int ssb_devices_register(struct ssb_bus *bus)
458 {
459 struct ssb_device *sdev;
460 struct device *dev;
461 struct __ssb_dev_wrapper *devwrap;
462 int i, err = 0;
463 int dev_idx = 0;
464
465 for (i = 0; i < bus->nr_devices; i++) {
466 sdev = &(bus->devices[i]);
467
468 /* We don't register SSB-system devices to the kernel,
469 * as the drivers for them are built into SSB. */
470 switch (sdev->id.coreid) {
471 case SSB_DEV_CHIPCOMMON:
472 case SSB_DEV_PCI:
473 case SSB_DEV_PCIE:
474 case SSB_DEV_PCMCIA:
475 case SSB_DEV_MIPS:
476 case SSB_DEV_MIPS_3302:
477 case SSB_DEV_EXTIF:
478 continue;
479 }
480
481 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
482 if (!devwrap) {
483 ssb_err("Could not allocate device\n");
484 err = -ENOMEM;
485 goto error;
486 }
487 dev = &devwrap->dev;
488 devwrap->sdev = sdev;
489
490 dev->release = ssb_release_dev;
491 dev->bus = &ssb_bustype;
492 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
493
494 switch (bus->bustype) {
495 case SSB_BUSTYPE_PCI:
496 #ifdef CONFIG_SSB_PCIHOST
497 sdev->irq = bus->host_pci->irq;
498 dev->parent = &bus->host_pci->dev;
499 sdev->dma_dev = dev->parent;
500 #endif
501 break;
502 case SSB_BUSTYPE_PCMCIA:
503 #ifdef CONFIG_SSB_PCMCIAHOST
504 sdev->irq = bus->host_pcmcia->irq;
505 dev->parent = &bus->host_pcmcia->dev;
506 #endif
507 break;
508 case SSB_BUSTYPE_SDIO:
509 #ifdef CONFIG_SSB_SDIOHOST
510 dev->parent = &bus->host_sdio->dev;
511 #endif
512 break;
513 case SSB_BUSTYPE_SSB:
514 dev->dma_mask = &dev->coherent_dma_mask;
515 sdev->dma_dev = dev;
516 break;
517 }
518
519 sdev->dev = dev;
520 err = device_register(dev);
521 if (err) {
522 ssb_err("Could not register %s\n", dev_name(dev));
523 /* Set dev to NULL to not unregister
524 * dev on error unwinding. */
525 sdev->dev = NULL;
526 kfree(devwrap);
527 goto error;
528 }
529 dev_idx++;
530 }
531
532 #ifdef CONFIG_SSB_DRIVER_MIPS
533 if (bus->mipscore.pflash.present) {
534 err = platform_device_register(&ssb_pflash_dev);
535 if (err)
536 pr_err("Error registering parallel flash\n");
537 }
538 #endif
539
540 #ifdef CONFIG_SSB_SFLASH
541 if (bus->mipscore.sflash.present) {
542 err = platform_device_register(&ssb_sflash_dev);
543 if (err)
544 pr_err("Error registering serial flash\n");
545 }
546 #endif
547
548 return 0;
549 error:
550 /* Unwind the already registered devices. */
551 ssb_devices_unregister(bus);
552 return err;
553 }
554
555 /* Needs ssb_buses_lock() */
556 static int ssb_attach_queued_buses(void)
557 {
558 struct ssb_bus *bus, *n;
559 int err = 0;
560 int drop_them_all = 0;
561
562 list_for_each_entry_safe(bus, n, &attach_queue, list) {
563 if (drop_them_all) {
564 list_del(&bus->list);
565 continue;
566 }
567 /* Can't init the PCIcore in ssb_bus_register(), as that
568 * is too early in boot for embedded systems
569 * (no udelay() available). So do it here in attach stage.
570 */
571 err = ssb_bus_powerup(bus, 0);
572 if (err)
573 goto error;
574 ssb_pcicore_init(&bus->pcicore);
575 if (bus->bustype == SSB_BUSTYPE_SSB)
576 ssb_watchdog_register(bus);
577
578 err = ssb_gpio_init(bus);
579 if (err == -ENOTSUPP)
580 ssb_dbg("GPIO driver not activated\n");
581 else if (err)
582 ssb_dbg("Error registering GPIO driver: %i\n", err);
583
584 ssb_bus_may_powerdown(bus);
585
586 err = ssb_devices_register(bus);
587 error:
588 if (err) {
589 drop_them_all = 1;
590 list_del(&bus->list);
591 continue;
592 }
593 list_move_tail(&bus->list, &buses);
594 }
595
596 return err;
597 }
598
599 static int ssb_fetch_invariants(struct ssb_bus *bus,
600 ssb_invariants_func_t get_invariants)
601 {
602 struct ssb_init_invariants iv;
603 int err;
604
605 memset(&iv, 0, sizeof(iv));
606 err = get_invariants(bus, &iv);
607 if (err)
608 goto out;
609 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
610 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
611 bus->has_cardbus_slot = iv.has_cardbus_slot;
612 out:
613 return err;
614 }
615
616 static int __maybe_unused
617 ssb_bus_register(struct ssb_bus *bus,
618 ssb_invariants_func_t get_invariants,
619 unsigned long baseaddr)
620 {
621 int err;
622
623 spin_lock_init(&bus->bar_lock);
624 INIT_LIST_HEAD(&bus->list);
625 #ifdef CONFIG_SSB_EMBEDDED
626 spin_lock_init(&bus->gpio_lock);
627 #endif
628
629 /* Powerup the bus */
630 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
631 if (err)
632 goto out;
633
634 /* Init SDIO-host device (if any), before the scan */
635 err = ssb_sdio_init(bus);
636 if (err)
637 goto err_disable_xtal;
638
639 ssb_buses_lock();
640 bus->busnumber = next_busnumber;
641 /* Scan for devices (cores) */
642 err = ssb_bus_scan(bus, baseaddr);
643 if (err)
644 goto err_sdio_exit;
645
646 /* Init PCI-host device (if any) */
647 err = ssb_pci_init(bus);
648 if (err)
649 goto err_unmap;
650 /* Init PCMCIA-host device (if any) */
651 err = ssb_pcmcia_init(bus);
652 if (err)
653 goto err_pci_exit;
654
655 /* Initialize basic system devices (if available) */
656 err = ssb_bus_powerup(bus, 0);
657 if (err)
658 goto err_pcmcia_exit;
659 ssb_chipcommon_init(&bus->chipco);
660 ssb_extif_init(&bus->extif);
661 ssb_mipscore_init(&bus->mipscore);
662 err = ssb_fetch_invariants(bus, get_invariants);
663 if (err) {
664 ssb_bus_may_powerdown(bus);
665 goto err_pcmcia_exit;
666 }
667 ssb_bus_may_powerdown(bus);
668
669 /* Queue it for attach.
670 * See the comment at the ssb_is_early_boot definition. */
671 list_add_tail(&bus->list, &attach_queue);
672 if (!ssb_is_early_boot) {
673 /* This is not early boot, so we must attach the bus now */
674 err = ssb_attach_queued_buses();
675 if (err)
676 goto err_dequeue;
677 }
678 next_busnumber++;
679 ssb_buses_unlock();
680
681 out:
682 return err;
683
684 err_dequeue:
685 list_del(&bus->list);
686 err_pcmcia_exit:
687 ssb_pcmcia_exit(bus);
688 err_pci_exit:
689 ssb_pci_exit(bus);
690 err_unmap:
691 ssb_iounmap(bus);
692 err_sdio_exit:
693 ssb_sdio_exit(bus);
694 err_disable_xtal:
695 ssb_buses_unlock();
696 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
697 return err;
698 }
699
700 #ifdef CONFIG_SSB_PCIHOST
701 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
702 {
703 int err;
704
705 bus->bustype = SSB_BUSTYPE_PCI;
706 bus->host_pci = host_pci;
707 bus->ops = &ssb_pci_ops;
708
709 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
710 if (!err) {
711 ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
712 dev_name(&host_pci->dev));
713 } else {
714 ssb_err("Failed to register PCI version of SSB with error %d\n",
715 err);
716 }
717
718 return err;
719 }
720 #endif /* CONFIG_SSB_PCIHOST */
721
722 #ifdef CONFIG_SSB_PCMCIAHOST
723 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
724 struct pcmcia_device *pcmcia_dev,
725 unsigned long baseaddr)
726 {
727 int err;
728
729 bus->bustype = SSB_BUSTYPE_PCMCIA;
730 bus->host_pcmcia = pcmcia_dev;
731 bus->ops = &ssb_pcmcia_ops;
732
733 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
734 if (!err) {
735 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
736 pcmcia_dev->devname);
737 }
738
739 return err;
740 }
741 #endif /* CONFIG_SSB_PCMCIAHOST */
742
743 #ifdef CONFIG_SSB_SDIOHOST
744 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
745 unsigned int quirks)
746 {
747 int err;
748
749 bus->bustype = SSB_BUSTYPE_SDIO;
750 bus->host_sdio = func;
751 bus->ops = &ssb_sdio_ops;
752 bus->quirks = quirks;
753
754 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
755 if (!err) {
756 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
757 sdio_func_id(func));
758 }
759
760 return err;
761 }
762 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
763 #endif /* CONFIG_SSB_PCMCIAHOST */
764
765 #ifdef CONFIG_SSB_HOST_SOC
766 int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
767 {
768 int err;
769
770 bus->bustype = SSB_BUSTYPE_SSB;
771 bus->ops = &ssb_host_soc_ops;
772
773 err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
774 if (!err) {
775 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
776 baseaddr);
777 }
778
779 return err;
780 }
781 #endif
782
783 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
784 {
785 drv->drv.name = drv->name;
786 drv->drv.bus = &ssb_bustype;
787 drv->drv.owner = owner;
788
789 return driver_register(&drv->drv);
790 }
791 EXPORT_SYMBOL(__ssb_driver_register);
792
793 void ssb_driver_unregister(struct ssb_driver *drv)
794 {
795 driver_unregister(&drv->drv);
796 }
797 EXPORT_SYMBOL(ssb_driver_unregister);
798
799 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
800 {
801 struct ssb_bus *bus = dev->bus;
802 struct ssb_device *ent;
803 int i;
804
805 for (i = 0; i < bus->nr_devices; i++) {
806 ent = &(bus->devices[i]);
807 if (ent->id.vendor != dev->id.vendor)
808 continue;
809 if (ent->id.coreid != dev->id.coreid)
810 continue;
811
812 ent->devtypedata = data;
813 }
814 }
815 EXPORT_SYMBOL(ssb_set_devtypedata);
816
817 static u32 clkfactor_f6_resolve(u32 v)
818 {
819 /* map the magic values */
820 switch (v) {
821 case SSB_CHIPCO_CLK_F6_2:
822 return 2;
823 case SSB_CHIPCO_CLK_F6_3:
824 return 3;
825 case SSB_CHIPCO_CLK_F6_4:
826 return 4;
827 case SSB_CHIPCO_CLK_F6_5:
828 return 5;
829 case SSB_CHIPCO_CLK_F6_6:
830 return 6;
831 case SSB_CHIPCO_CLK_F6_7:
832 return 7;
833 }
834 return 0;
835 }
836
837 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
838 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
839 {
840 u32 n1, n2, clock, m1, m2, m3, mc;
841
842 n1 = (n & SSB_CHIPCO_CLK_N1);
843 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
844
845 switch (plltype) {
846 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
847 if (m & SSB_CHIPCO_CLK_T6_MMASK)
848 return SSB_CHIPCO_CLK_T6_M1;
849 return SSB_CHIPCO_CLK_T6_M0;
850 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
851 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
852 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
853 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
854 n1 = clkfactor_f6_resolve(n1);
855 n2 += SSB_CHIPCO_CLK_F5_BIAS;
856 break;
857 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
858 n1 += SSB_CHIPCO_CLK_T2_BIAS;
859 n2 += SSB_CHIPCO_CLK_T2_BIAS;
860 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
861 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
862 break;
863 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
864 return 100000000;
865 default:
866 SSB_WARN_ON(1);
867 }
868
869 switch (plltype) {
870 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
871 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
872 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
873 break;
874 default:
875 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
876 }
877 if (!clock)
878 return 0;
879
880 m1 = (m & SSB_CHIPCO_CLK_M1);
881 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
882 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
883 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
884
885 switch (plltype) {
886 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
887 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
888 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
889 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
890 m1 = clkfactor_f6_resolve(m1);
891 if ((plltype == SSB_PLLTYPE_1) ||
892 (plltype == SSB_PLLTYPE_3))
893 m2 += SSB_CHIPCO_CLK_F5_BIAS;
894 else
895 m2 = clkfactor_f6_resolve(m2);
896 m3 = clkfactor_f6_resolve(m3);
897
898 switch (mc) {
899 case SSB_CHIPCO_CLK_MC_BYPASS:
900 return clock;
901 case SSB_CHIPCO_CLK_MC_M1:
902 return (clock / m1);
903 case SSB_CHIPCO_CLK_MC_M1M2:
904 return (clock / (m1 * m2));
905 case SSB_CHIPCO_CLK_MC_M1M2M3:
906 return (clock / (m1 * m2 * m3));
907 case SSB_CHIPCO_CLK_MC_M1M3:
908 return (clock / (m1 * m3));
909 }
910 return 0;
911 case SSB_PLLTYPE_2:
912 m1 += SSB_CHIPCO_CLK_T2_BIAS;
913 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
914 m3 += SSB_CHIPCO_CLK_T2_BIAS;
915 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
916 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
917 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
918
919 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
920 clock /= m1;
921 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
922 clock /= m2;
923 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
924 clock /= m3;
925 return clock;
926 default:
927 SSB_WARN_ON(1);
928 }
929 return 0;
930 }
931
932 /* Get the current speed the backplane is running at */
933 u32 ssb_clockspeed(struct ssb_bus *bus)
934 {
935 u32 rate;
936 u32 plltype;
937 u32 clkctl_n, clkctl_m;
938
939 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
940 return ssb_pmu_get_controlclock(&bus->chipco);
941
942 if (ssb_extif_available(&bus->extif))
943 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
944 &clkctl_n, &clkctl_m);
945 else if (bus->chipco.dev)
946 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
947 &clkctl_n, &clkctl_m);
948 else
949 return 0;
950
951 if (bus->chip_id == 0x5365) {
952 rate = 100000000;
953 } else {
954 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
955 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
956 rate /= 2;
957 }
958
959 return rate;
960 }
961 EXPORT_SYMBOL(ssb_clockspeed);
962
963 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
964 {
965 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
966
967 /* The REJECT bit seems to be different for Backplane rev 2.3 */
968 switch (rev) {
969 case SSB_IDLOW_SSBREV_22:
970 case SSB_IDLOW_SSBREV_24:
971 case SSB_IDLOW_SSBREV_26:
972 return SSB_TMSLOW_REJECT;
973 case SSB_IDLOW_SSBREV_23:
974 return SSB_TMSLOW_REJECT_23;
975 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
976 case SSB_IDLOW_SSBREV_27: /* same here */
977 return SSB_TMSLOW_REJECT; /* this is a guess */
978 case SSB_IDLOW_SSBREV:
979 break;
980 default:
981 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
982 }
983 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
984 }
985
986 int ssb_device_is_enabled(struct ssb_device *dev)
987 {
988 u32 val;
989 u32 reject;
990
991 reject = ssb_tmslow_reject_bitmask(dev);
992 val = ssb_read32(dev, SSB_TMSLOW);
993 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
994
995 return (val == SSB_TMSLOW_CLOCK);
996 }
997 EXPORT_SYMBOL(ssb_device_is_enabled);
998
999 static void ssb_flush_tmslow(struct ssb_device *dev)
1000 {
1001 /* Make _really_ sure the device has finished the TMSLOW
1002 * register write transaction, as we risk running into
1003 * a machine check exception otherwise.
1004 * Do this by reading the register back to commit the
1005 * PCI write and delay an additional usec for the device
1006 * to react to the change. */
1007 ssb_read32(dev, SSB_TMSLOW);
1008 udelay(1);
1009 }
1010
1011 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1012 {
1013 u32 val;
1014
1015 ssb_device_disable(dev, core_specific_flags);
1016 ssb_write32(dev, SSB_TMSLOW,
1017 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1018 SSB_TMSLOW_FGC | core_specific_flags);
1019 ssb_flush_tmslow(dev);
1020
1021 /* Clear SERR if set. This is a hw bug workaround. */
1022 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1023 ssb_write32(dev, SSB_TMSHIGH, 0);
1024
1025 val = ssb_read32(dev, SSB_IMSTATE);
1026 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1027 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1028 ssb_write32(dev, SSB_IMSTATE, val);
1029 }
1030
1031 ssb_write32(dev, SSB_TMSLOW,
1032 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1033 core_specific_flags);
1034 ssb_flush_tmslow(dev);
1035
1036 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1037 core_specific_flags);
1038 ssb_flush_tmslow(dev);
1039 }
1040 EXPORT_SYMBOL(ssb_device_enable);
1041
1042 /* Wait for bitmask in a register to get set or cleared.
1043 * timeout is in units of ten-microseconds */
1044 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1045 int timeout, int set)
1046 {
1047 int i;
1048 u32 val;
1049
1050 for (i = 0; i < timeout; i++) {
1051 val = ssb_read32(dev, reg);
1052 if (set) {
1053 if ((val & bitmask) == bitmask)
1054 return 0;
1055 } else {
1056 if (!(val & bitmask))
1057 return 0;
1058 }
1059 udelay(10);
1060 }
1061 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1062 "register %04X to %s.\n",
1063 bitmask, reg, (set ? "set" : "clear"));
1064
1065 return -ETIMEDOUT;
1066 }
1067
1068 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1069 {
1070 u32 reject, val;
1071
1072 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1073 return;
1074
1075 reject = ssb_tmslow_reject_bitmask(dev);
1076
1077 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1078 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1079 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1080 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1081
1082 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1083 val = ssb_read32(dev, SSB_IMSTATE);
1084 val |= SSB_IMSTATE_REJECT;
1085 ssb_write32(dev, SSB_IMSTATE, val);
1086 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1087 0);
1088 }
1089
1090 ssb_write32(dev, SSB_TMSLOW,
1091 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1092 reject | SSB_TMSLOW_RESET |
1093 core_specific_flags);
1094 ssb_flush_tmslow(dev);
1095
1096 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1097 val = ssb_read32(dev, SSB_IMSTATE);
1098 val &= ~SSB_IMSTATE_REJECT;
1099 ssb_write32(dev, SSB_IMSTATE, val);
1100 }
1101 }
1102
1103 ssb_write32(dev, SSB_TMSLOW,
1104 reject | SSB_TMSLOW_RESET |
1105 core_specific_flags);
1106 ssb_flush_tmslow(dev);
1107 }
1108 EXPORT_SYMBOL(ssb_device_disable);
1109
1110 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1111 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1112 {
1113 u16 chip_id = dev->bus->chip_id;
1114
1115 if (dev->id.coreid == SSB_DEV_80211) {
1116 return (chip_id == 0x4322 || chip_id == 43221 ||
1117 chip_id == 43231 || chip_id == 43222);
1118 }
1119
1120 return 0;
1121 }
1122
1123 u32 ssb_dma_translation(struct ssb_device *dev)
1124 {
1125 switch (dev->bus->bustype) {
1126 case SSB_BUSTYPE_SSB:
1127 return 0;
1128 case SSB_BUSTYPE_PCI:
1129 if (pci_is_pcie(dev->bus->host_pci) &&
1130 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1131 return SSB_PCIE_DMA_H32;
1132 } else {
1133 if (ssb_dma_translation_special_bit(dev))
1134 return SSB_PCIE_DMA_H32;
1135 else
1136 return SSB_PCI_DMA;
1137 }
1138 default:
1139 __ssb_dma_not_implemented(dev);
1140 }
1141 return 0;
1142 }
1143 EXPORT_SYMBOL(ssb_dma_translation);
1144
1145 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1146 {
1147 struct ssb_chipcommon *cc;
1148 int err = 0;
1149
1150 /* On buses where more than one core may be working
1151 * at a time, we must not powerdown stuff if there are
1152 * still cores that may want to run. */
1153 if (bus->bustype == SSB_BUSTYPE_SSB)
1154 goto out;
1155
1156 cc = &bus->chipco;
1157
1158 if (!cc->dev)
1159 goto out;
1160 if (cc->dev->id.revision < 5)
1161 goto out;
1162
1163 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1164 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1165 if (err)
1166 goto error;
1167 out:
1168 #ifdef CONFIG_SSB_DEBUG
1169 bus->powered_up = 0;
1170 #endif
1171 return err;
1172 error:
1173 ssb_err("Bus powerdown failed\n");
1174 goto out;
1175 }
1176 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1177
1178 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1179 {
1180 int err;
1181 enum ssb_clkmode mode;
1182
1183 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1184 if (err)
1185 goto error;
1186
1187 #ifdef CONFIG_SSB_DEBUG
1188 bus->powered_up = 1;
1189 #endif
1190
1191 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1192 ssb_chipco_set_clockmode(&bus->chipco, mode);
1193
1194 return 0;
1195 error:
1196 ssb_err("Bus powerup failed\n");
1197 return err;
1198 }
1199 EXPORT_SYMBOL(ssb_bus_powerup);
1200
1201 static void ssb_broadcast_value(struct ssb_device *dev,
1202 u32 address, u32 data)
1203 {
1204 #ifdef CONFIG_SSB_DRIVER_PCICORE
1205 /* This is used for both, PCI and ChipCommon core, so be careful. */
1206 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1207 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1208 #endif
1209
1210 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1211 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1212 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1213 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1214 }
1215
1216 void ssb_commit_settings(struct ssb_bus *bus)
1217 {
1218 struct ssb_device *dev;
1219
1220 #ifdef CONFIG_SSB_DRIVER_PCICORE
1221 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1222 #else
1223 dev = bus->chipco.dev;
1224 #endif
1225 if (WARN_ON(!dev))
1226 return;
1227 /* This forces an update of the cached registers. */
1228 ssb_broadcast_value(dev, 0xFD8, 0);
1229 }
1230 EXPORT_SYMBOL(ssb_commit_settings);
1231
1232 u32 ssb_admatch_base(u32 adm)
1233 {
1234 u32 base = 0;
1235
1236 switch (adm & SSB_ADM_TYPE) {
1237 case SSB_ADM_TYPE0:
1238 base = (adm & SSB_ADM_BASE0);
1239 break;
1240 case SSB_ADM_TYPE1:
1241 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1242 base = (adm & SSB_ADM_BASE1);
1243 break;
1244 case SSB_ADM_TYPE2:
1245 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1246 base = (adm & SSB_ADM_BASE2);
1247 break;
1248 default:
1249 SSB_WARN_ON(1);
1250 }
1251
1252 return base;
1253 }
1254 EXPORT_SYMBOL(ssb_admatch_base);
1255
1256 u32 ssb_admatch_size(u32 adm)
1257 {
1258 u32 size = 0;
1259
1260 switch (adm & SSB_ADM_TYPE) {
1261 case SSB_ADM_TYPE0:
1262 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1263 break;
1264 case SSB_ADM_TYPE1:
1265 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1266 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1267 break;
1268 case SSB_ADM_TYPE2:
1269 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1270 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1271 break;
1272 default:
1273 SSB_WARN_ON(1);
1274 }
1275 size = (1 << (size + 1));
1276
1277 return size;
1278 }
1279 EXPORT_SYMBOL(ssb_admatch_size);
1280
1281 static int __init ssb_modinit(void)
1282 {
1283 int err;
1284
1285 /* See the comment at the ssb_is_early_boot definition */
1286 ssb_is_early_boot = 0;
1287 err = bus_register(&ssb_bustype);
1288 if (err)
1289 return err;
1290
1291 /* Maybe we already registered some buses at early boot.
1292 * Check for this and attach them
1293 */
1294 ssb_buses_lock();
1295 err = ssb_attach_queued_buses();
1296 ssb_buses_unlock();
1297 if (err) {
1298 bus_unregister(&ssb_bustype);
1299 goto out;
1300 }
1301
1302 err = b43_pci_ssb_bridge_init();
1303 if (err) {
1304 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1305 /* don't fail SSB init because of this */
1306 err = 0;
1307 }
1308 err = ssb_host_pcmcia_init();
1309 if (err) {
1310 ssb_err("PCMCIA host initialization failed\n");
1311 /* don't fail SSB init because of this */
1312 err = 0;
1313 }
1314 err = ssb_gige_init();
1315 if (err) {
1316 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1317 /* don't fail SSB init because of this */
1318 err = 0;
1319 }
1320 out:
1321 return err;
1322 }
1323 /* ssb must be initialized after PCI but before the ssb drivers.
1324 * That means we must use some initcall between subsys_initcall
1325 * and device_initcall. */
1326 fs_initcall(ssb_modinit);
1327
1328 static void __exit ssb_modexit(void)
1329 {
1330 ssb_gige_exit();
1331 ssb_host_pcmcia_exit();
1332 b43_pci_ssb_bridge_exit();
1333 bus_unregister(&ssb_bustype);
1334 }
1335 module_exit(ssb_modexit)
Linux with added FPC-III support