sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / 8250 / 8250_of.c
blobd25ab1cd42958cb8f24c00af1d0def1fd0711278
1 /*
2 * Serial Port driver for Open Firmware platform devices
4 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/console.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/clk.h>
23 #include "8250.h"
25 struct of_serial_info {
26 struct clk *clk;
27 int type;
28 int line;
31 #ifdef CONFIG_ARCH_TEGRA
32 static void tegra_serial_handle_break(struct uart_port *p)
34 unsigned int status, tmout = 10000;
36 do {
37 status = p->serial_in(p, UART_LSR);
38 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
39 status = p->serial_in(p, UART_RX);
40 else
41 break;
42 if (--tmout == 0)
43 break;
44 udelay(1);
45 } while (1);
47 #else
48 static inline void tegra_serial_handle_break(struct uart_port *port)
51 #endif
54 * Fill a struct uart_port for a given device node
56 static int of_platform_serial_setup(struct platform_device *ofdev,
57 int type, struct uart_port *port,
58 struct of_serial_info *info)
60 struct resource resource;
61 struct device_node *np = ofdev->dev.of_node;
62 u32 clk, spd, prop;
63 int ret;
65 memset(port, 0, sizeof *port);
66 if (of_property_read_u32(np, "clock-frequency", &clk)) {
68 /* Get clk rate through clk driver if present */
69 info->clk = devm_clk_get(&ofdev->dev, NULL);
70 if (IS_ERR(info->clk)) {
71 dev_warn(&ofdev->dev,
72 "clk or clock-frequency not defined\n");
73 return PTR_ERR(info->clk);
76 ret = clk_prepare_enable(info->clk);
77 if (ret < 0)
78 return ret;
80 clk = clk_get_rate(info->clk);
82 /* If current-speed was set, then try not to change it. */
83 if (of_property_read_u32(np, "current-speed", &spd) == 0)
84 port->custom_divisor = clk / (16 * spd);
86 ret = of_address_to_resource(np, 0, &resource);
87 if (ret) {
88 dev_warn(&ofdev->dev, "invalid address\n");
89 goto out;
92 spin_lock_init(&port->lock);
93 port->mapbase = resource.start;
94 port->mapsize = resource_size(&resource);
96 /* Check for shifted address mapping */
97 if (of_property_read_u32(np, "reg-offset", &prop) == 0)
98 port->mapbase += prop;
100 /* Check for registers offset within the devices address range */
101 if (of_property_read_u32(np, "reg-shift", &prop) == 0)
102 port->regshift = prop;
104 /* Check for fifo size */
105 if (of_property_read_u32(np, "fifo-size", &prop) == 0)
106 port->fifosize = prop;
108 /* Check for a fixed line number */
109 ret = of_alias_get_id(np, "serial");
110 if (ret >= 0)
111 port->line = ret;
113 port->irq = irq_of_parse_and_map(np, 0);
114 port->iotype = UPIO_MEM;
115 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
116 switch (prop) {
117 case 1:
118 port->iotype = UPIO_MEM;
119 break;
120 case 2:
121 port->iotype = UPIO_MEM16;
122 break;
123 case 4:
124 port->iotype = of_device_is_big_endian(np) ?
125 UPIO_MEM32BE : UPIO_MEM32;
126 break;
127 default:
128 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
129 prop);
130 ret = -EINVAL;
131 goto out;
135 port->type = type;
136 port->uartclk = clk;
137 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
138 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
140 if (of_find_property(np, "no-loopback-test", NULL))
141 port->flags |= UPF_SKIP_TEST;
143 port->dev = &ofdev->dev;
145 switch (type) {
146 case PORT_TEGRA:
147 port->handle_break = tegra_serial_handle_break;
148 break;
150 case PORT_RT2880:
151 port->iotype = UPIO_AU;
152 break;
155 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
156 (of_device_is_compatible(np, "fsl,ns16550") ||
157 of_device_is_compatible(np, "fsl,16550-FIFO64")))
158 port->handle_irq = fsl8250_handle_irq;
160 return 0;
161 out:
162 if (info->clk)
163 clk_disable_unprepare(info->clk);
164 return ret;
168 * Try to register a serial port
170 static const struct of_device_id of_platform_serial_table[];
171 static int of_platform_serial_probe(struct platform_device *ofdev)
173 const struct of_device_id *match;
174 struct of_serial_info *info;
175 struct uart_port port;
176 int port_type;
177 int ret;
179 match = of_match_device(of_platform_serial_table, &ofdev->dev);
180 if (!match)
181 return -EINVAL;
183 if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
184 return -EBUSY;
186 info = kzalloc(sizeof(*info), GFP_KERNEL);
187 if (info == NULL)
188 return -ENOMEM;
190 port_type = (unsigned long)match->data;
191 ret = of_platform_serial_setup(ofdev, port_type, &port, info);
192 if (ret)
193 goto out;
195 switch (port_type) {
196 case PORT_8250 ... PORT_MAX_8250:
198 u32 tx_threshold;
199 struct uart_8250_port port8250;
200 memset(&port8250, 0, sizeof(port8250));
201 port8250.port = port;
203 if (port.fifosize)
204 port8250.capabilities = UART_CAP_FIFO;
206 /* Check for TX FIFO threshold & set tx_loadsz */
207 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
208 &tx_threshold) == 0) &&
209 (tx_threshold < port.fifosize))
210 port8250.tx_loadsz = port.fifosize - tx_threshold;
212 if (of_property_read_bool(ofdev->dev.of_node,
213 "auto-flow-control"))
214 port8250.capabilities |= UART_CAP_AFE;
216 ret = serial8250_register_8250_port(&port8250);
217 break;
219 default:
220 /* need to add code for these */
221 case PORT_UNKNOWN:
222 dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
223 ret = -ENODEV;
224 break;
226 if (ret < 0)
227 goto out;
229 info->type = port_type;
230 info->line = ret;
231 platform_set_drvdata(ofdev, info);
232 return 0;
233 out:
234 kfree(info);
235 irq_dispose_mapping(port.irq);
236 return ret;
240 * Release a line
242 static int of_platform_serial_remove(struct platform_device *ofdev)
244 struct of_serial_info *info = platform_get_drvdata(ofdev);
245 switch (info->type) {
246 case PORT_8250 ... PORT_MAX_8250:
247 serial8250_unregister_port(info->line);
248 break;
249 default:
250 /* need to add code for these */
251 break;
254 if (info->clk)
255 clk_disable_unprepare(info->clk);
256 kfree(info);
257 return 0;
260 #ifdef CONFIG_PM_SLEEP
261 static void of_serial_suspend_8250(struct of_serial_info *info)
263 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
264 struct uart_port *port = &port8250->port;
266 serial8250_suspend_port(info->line);
267 if (info->clk && (!uart_console(port) || console_suspend_enabled))
268 clk_disable_unprepare(info->clk);
271 static void of_serial_resume_8250(struct of_serial_info *info)
273 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
274 struct uart_port *port = &port8250->port;
276 if (info->clk && (!uart_console(port) || console_suspend_enabled))
277 clk_prepare_enable(info->clk);
279 serial8250_resume_port(info->line);
282 static int of_serial_suspend(struct device *dev)
284 struct of_serial_info *info = dev_get_drvdata(dev);
286 switch (info->type) {
287 case PORT_8250 ... PORT_MAX_8250:
288 of_serial_suspend_8250(info);
289 break;
290 default:
291 break;
294 return 0;
297 static int of_serial_resume(struct device *dev)
299 struct of_serial_info *info = dev_get_drvdata(dev);
301 switch (info->type) {
302 case PORT_8250 ... PORT_MAX_8250:
303 of_serial_resume_8250(info);
304 break;
305 default:
306 break;
309 return 0;
311 #endif
312 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
315 * A few common types, add more as needed.
317 static const struct of_device_id of_platform_serial_table[] = {
318 { .compatible = "ns8250", .data = (void *)PORT_8250, },
319 { .compatible = "ns16450", .data = (void *)PORT_16450, },
320 { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
321 { .compatible = "ns16550", .data = (void *)PORT_16550, },
322 { .compatible = "ns16750", .data = (void *)PORT_16750, },
323 { .compatible = "ns16850", .data = (void *)PORT_16850, },
324 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
325 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
326 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
327 { .compatible = "altr,16550-FIFO32",
328 .data = (void *)PORT_ALTR_16550_F32, },
329 { .compatible = "altr,16550-FIFO64",
330 .data = (void *)PORT_ALTR_16550_F64, },
331 { .compatible = "altr,16550-FIFO128",
332 .data = (void *)PORT_ALTR_16550_F128, },
333 { .compatible = "mrvl,mmp-uart",
334 .data = (void *)PORT_XSCALE, },
335 { /* end of list */ },
337 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
339 static struct platform_driver of_platform_serial_driver = {
340 .driver = {
341 .name = "of_serial",
342 .of_match_table = of_platform_serial_table,
343 .pm = &of_serial_pm_ops,
345 .probe = of_platform_serial_probe,
346 .remove = of_platform_serial_remove,
349 module_platform_driver(of_platform_serial_driver);
351 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
352 MODULE_LICENSE("GPL");
353 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");