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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / crisv10.c
blobe92c23470e519f839693ca2d486e3aaf2d368854
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/string.h>
22 #include <linux/fcntl.h>
23 #include <linux/mm.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/mutex.h>
28 #include <linux/bitops.h>
29 #include <linux/seq_file.h>
30 #include <linux/delay.h>
31 #include <linux/uaccess.h>
32 #include <linux/io.h>
33
34 #include <asm/irq.h>
35 #include <asm/dma.h>
36
37 #include <arch/svinto.h>
38 #include <arch/system.h>
39
40 /* non-arch dependent serial structures are in linux/serial.h */
41 #include <linux/serial.h>
42 /* while we keep our own stuff (struct e100_serial) in a local .h file */
43 #include "crisv10.h"
44 #include <asm/fasttimer.h>
45 #include <arch/io_interface_mux.h>
46
47 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
48 #ifndef CONFIG_ETRAX_FAST_TIMER
49 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
50 #endif
51 #endif
52
53 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
54 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
55 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
56 #endif
57
58 /*
59 * All of the compatibilty code so we can compile serial.c against
60 * older kernels is hidden in serial_compat.h
61 */
62 #if defined(LOCAL_HEADERS)
63 #include "serial_compat.h"
64 #endif
65
66 struct tty_driver *serial_driver;
67
68 /* number of characters left in xmit buffer before we ask for more */
69 #define WAKEUP_CHARS 256
70
71 //#define SERIAL_DEBUG_INTR
72 //#define SERIAL_DEBUG_OPEN
73 //#define SERIAL_DEBUG_FLOW
74 //#define SERIAL_DEBUG_DATA
75 //#define SERIAL_DEBUG_THROTTLE
76 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
77 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
78
79 /* Enable this to use serial interrupts to handle when you
80 expect the first received event on the serial port to
81 be an error, break or similar. Used to be able to flash IRMA
82 from eLinux */
83 #define SERIAL_HANDLE_EARLY_ERRORS
84
85 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
86 #define SERIAL_DESCR_BUF_SIZE 256
87
88 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
89 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
90
91 /* We don't want to load the system with massive fast timer interrupt
92 * on high baudrates so limit it to 250 us (4kHz) */
93 #define MIN_FLUSH_TIME_USEC 250
94
95 /* Add an x here to log a lot of timer stuff */
96 #define TIMERD(x)
97 /* Debug details of interrupt handling */
98 #define DINTR1(x) /* irq on/off, errors */
99 #define DINTR2(x) /* tx and rx */
100 /* Debug flip buffer stuff */
101 #define DFLIP(x)
102 /* Debug flow control and overview of data flow */
103 #define DFLOW(x)
104 #define DBAUD(x)
105 #define DLOG_INT_TRIG(x)
106
107 //#define DEBUG_LOG_INCLUDED
108 #ifndef DEBUG_LOG_INCLUDED
109 #define DEBUG_LOG(line, string, value)
110 #else
111 struct debug_log_info
112 {
113 unsigned long time;
114 unsigned long timer_data;
115 // int line;
116 const char *string;
117 int value;
118 };
119 #define DEBUG_LOG_SIZE 4096
120
121 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
122 int debug_log_pos = 0;
123
124 #define DEBUG_LOG(_line, _string, _value) do { \
125 if ((_line) == SERIAL_DEBUG_LINE) {\
126 debug_log_func(_line, _string, _value); \
127 }\
128 }while(0)
129
130 void debug_log_func(int line, const char *string, int value)
131 {
132 if (debug_log_pos < DEBUG_LOG_SIZE) {
133 debug_log[debug_log_pos].time = jiffies;
134 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
135 // debug_log[debug_log_pos].line = line;
136 debug_log[debug_log_pos].string = string;
137 debug_log[debug_log_pos].value = value;
138 debug_log_pos++;
139 }
140 /*printk(string, value);*/
141 }
142 #endif
143
144 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
145 /* Default number of timer ticks before flushing rx fifo
146 * When using "little data, low latency applications: use 0
147 * When using "much data applications (PPP)" use ~5
148 */
149 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
150 #endif
151
152 unsigned long timer_data_to_ns(unsigned long timer_data);
153
154 static void change_speed(struct e100_serial *info);
155 static void rs_throttle(struct tty_struct * tty);
156 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
157 static int rs_write(struct tty_struct *tty,
158 const unsigned char *buf, int count);
159 #ifdef CONFIG_ETRAX_RS485
160 static int e100_write_rs485(struct tty_struct *tty,
161 const unsigned char *buf, int count);
162 #endif
163 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
164
165
166 #define DEF_BAUD 115200 /* 115.2 kbit/s */
167 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
168 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
169 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
170
171 /* offsets from R_SERIALx_CTRL */
172
173 #define REG_DATA 0
174 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
175 #define REG_TR_DATA 0
176 #define REG_STATUS 1
177 #define REG_TR_CTRL 1
178 #define REG_REC_CTRL 2
179 #define REG_BAUD 3
180 #define REG_XOFF 4 /* this is a 32 bit register */
181
182 /* The bitfields are the same for all serial ports */
183 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
184 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
185 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
186 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
187 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
188
189 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
190
191 /* Values for info->errorcode */
192 #define ERRCODE_SET_BREAK (TTY_BREAK)
193 #define ERRCODE_INSERT 0x100
194 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
195
196 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
197
198 /*
199 * General note regarding the use of IO_* macros in this file:
200 *
201 * We will use the bits defined for DMA channel 6 when using various
202 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
203 * the same for all channels (which of course they are).
204 *
205 * We will also use the bits defined for serial port 0 when writing commands
206 * to the different ports, as these bits too are the same for all ports.
207 */
208
209
210 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
211 static const unsigned long e100_ser_int_mask = 0
212 #ifdef CONFIG_ETRAX_SERIAL_PORT0
213 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
214 #endif
215 #ifdef CONFIG_ETRAX_SERIAL_PORT1
216 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
217 #endif
218 #ifdef CONFIG_ETRAX_SERIAL_PORT2
219 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
220 #endif
221 #ifdef CONFIG_ETRAX_SERIAL_PORT3
222 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
223 #endif
224 ;
225 unsigned long r_alt_ser_baudrate_shadow = 0;
226
227 /* this is the data for the four serial ports in the etrax100 */
228 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
229 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
230
231 static struct e100_serial rs_table[] = {
232 { .baud = DEF_BAUD,
233 .ioport = (unsigned char *)R_SERIAL0_CTRL,
234 .irq = 1U << 12, /* uses DMA 6 and 7 */
235 .oclrintradr = R_DMA_CH6_CLR_INTR,
236 .ofirstadr = R_DMA_CH6_FIRST,
237 .ocmdadr = R_DMA_CH6_CMD,
238 .ostatusadr = R_DMA_CH6_STATUS,
239 .iclrintradr = R_DMA_CH7_CLR_INTR,
240 .ifirstadr = R_DMA_CH7_FIRST,
241 .icmdadr = R_DMA_CH7_CMD,
242 .idescradr = R_DMA_CH7_DESCR,
243 .rx_ctrl = DEF_RX,
244 .tx_ctrl = DEF_TX,
245 .iseteop = 2,
246 .dma_owner = dma_ser0,
247 .io_if = if_serial_0,
248 #ifdef CONFIG_ETRAX_SERIAL_PORT0
249 .enabled = 1,
250 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
251 .dma_out_enabled = 1,
252 .dma_out_nbr = SER0_TX_DMA_NBR,
253 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
254 .dma_out_irq_flags = 0,
255 .dma_out_irq_description = "serial 0 dma tr",
256 #else
257 .dma_out_enabled = 0,
258 .dma_out_nbr = UINT_MAX,
259 .dma_out_irq_nbr = 0,
260 .dma_out_irq_flags = 0,
261 .dma_out_irq_description = NULL,
262 #endif
263 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
264 .dma_in_enabled = 1,
265 .dma_in_nbr = SER0_RX_DMA_NBR,
266 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
267 .dma_in_irq_flags = 0,
268 .dma_in_irq_description = "serial 0 dma rec",
269 #else
270 .dma_in_enabled = 0,
271 .dma_in_nbr = UINT_MAX,
272 .dma_in_irq_nbr = 0,
273 .dma_in_irq_flags = 0,
274 .dma_in_irq_description = NULL,
275 #endif
276 #else
277 .enabled = 0,
278 .io_if_description = NULL,
279 .dma_out_enabled = 0,
280 .dma_in_enabled = 0
281 #endif
282
283 }, /* ttyS0 */
284 { .baud = DEF_BAUD,
285 .ioport = (unsigned char *)R_SERIAL1_CTRL,
286 .irq = 1U << 16, /* uses DMA 8 and 9 */
287 .oclrintradr = R_DMA_CH8_CLR_INTR,
288 .ofirstadr = R_DMA_CH8_FIRST,
289 .ocmdadr = R_DMA_CH8_CMD,
290 .ostatusadr = R_DMA_CH8_STATUS,
291 .iclrintradr = R_DMA_CH9_CLR_INTR,
292 .ifirstadr = R_DMA_CH9_FIRST,
293 .icmdadr = R_DMA_CH9_CMD,
294 .idescradr = R_DMA_CH9_DESCR,
295 .rx_ctrl = DEF_RX,
296 .tx_ctrl = DEF_TX,
297 .iseteop = 3,
298 .dma_owner = dma_ser1,
299 .io_if = if_serial_1,
300 #ifdef CONFIG_ETRAX_SERIAL_PORT1
301 .enabled = 1,
302 .io_if_description = "ser1",
303 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
304 .dma_out_enabled = 1,
305 .dma_out_nbr = SER1_TX_DMA_NBR,
306 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
307 .dma_out_irq_flags = 0,
308 .dma_out_irq_description = "serial 1 dma tr",
309 #else
310 .dma_out_enabled = 0,
311 .dma_out_nbr = UINT_MAX,
312 .dma_out_irq_nbr = 0,
313 .dma_out_irq_flags = 0,
314 .dma_out_irq_description = NULL,
315 #endif
316 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
317 .dma_in_enabled = 1,
318 .dma_in_nbr = SER1_RX_DMA_NBR,
319 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
320 .dma_in_irq_flags = 0,
321 .dma_in_irq_description = "serial 1 dma rec",
322 #else
323 .dma_in_enabled = 0,
324 .dma_in_enabled = 0,
325 .dma_in_nbr = UINT_MAX,
326 .dma_in_irq_nbr = 0,
327 .dma_in_irq_flags = 0,
328 .dma_in_irq_description = NULL,
329 #endif
330 #else
331 .enabled = 0,
332 .io_if_description = NULL,
333 .dma_in_irq_nbr = 0,
334 .dma_out_enabled = 0,
335 .dma_in_enabled = 0
336 #endif
337 }, /* ttyS1 */
338
339 { .baud = DEF_BAUD,
340 .ioport = (unsigned char *)R_SERIAL2_CTRL,
341 .irq = 1U << 4, /* uses DMA 2 and 3 */
342 .oclrintradr = R_DMA_CH2_CLR_INTR,
343 .ofirstadr = R_DMA_CH2_FIRST,
344 .ocmdadr = R_DMA_CH2_CMD,
345 .ostatusadr = R_DMA_CH2_STATUS,
346 .iclrintradr = R_DMA_CH3_CLR_INTR,
347 .ifirstadr = R_DMA_CH3_FIRST,
348 .icmdadr = R_DMA_CH3_CMD,
349 .idescradr = R_DMA_CH3_DESCR,
350 .rx_ctrl = DEF_RX,
351 .tx_ctrl = DEF_TX,
352 .iseteop = 0,
353 .dma_owner = dma_ser2,
354 .io_if = if_serial_2,
355 #ifdef CONFIG_ETRAX_SERIAL_PORT2
356 .enabled = 1,
357 .io_if_description = "ser2",
358 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
359 .dma_out_enabled = 1,
360 .dma_out_nbr = SER2_TX_DMA_NBR,
361 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
362 .dma_out_irq_flags = 0,
363 .dma_out_irq_description = "serial 2 dma tr",
364 #else
365 .dma_out_enabled = 0,
366 .dma_out_nbr = UINT_MAX,
367 .dma_out_irq_nbr = 0,
368 .dma_out_irq_flags = 0,
369 .dma_out_irq_description = NULL,
370 #endif
371 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
372 .dma_in_enabled = 1,
373 .dma_in_nbr = SER2_RX_DMA_NBR,
374 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
375 .dma_in_irq_flags = 0,
376 .dma_in_irq_description = "serial 2 dma rec",
377 #else
378 .dma_in_enabled = 0,
379 .dma_in_nbr = UINT_MAX,
380 .dma_in_irq_nbr = 0,
381 .dma_in_irq_flags = 0,
382 .dma_in_irq_description = NULL,
383 #endif
384 #else
385 .enabled = 0,
386 .io_if_description = NULL,
387 .dma_out_enabled = 0,
388 .dma_in_enabled = 0
389 #endif
390 }, /* ttyS2 */
391
392 { .baud = DEF_BAUD,
393 .ioport = (unsigned char *)R_SERIAL3_CTRL,
394 .irq = 1U << 8, /* uses DMA 4 and 5 */
395 .oclrintradr = R_DMA_CH4_CLR_INTR,
396 .ofirstadr = R_DMA_CH4_FIRST,
397 .ocmdadr = R_DMA_CH4_CMD,
398 .ostatusadr = R_DMA_CH4_STATUS,
399 .iclrintradr = R_DMA_CH5_CLR_INTR,
400 .ifirstadr = R_DMA_CH5_FIRST,
401 .icmdadr = R_DMA_CH5_CMD,
402 .idescradr = R_DMA_CH5_DESCR,
403 .rx_ctrl = DEF_RX,
404 .tx_ctrl = DEF_TX,
405 .iseteop = 1,
406 .dma_owner = dma_ser3,
407 .io_if = if_serial_3,
408 #ifdef CONFIG_ETRAX_SERIAL_PORT3
409 .enabled = 1,
410 .io_if_description = "ser3",
411 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
412 .dma_out_enabled = 1,
413 .dma_out_nbr = SER3_TX_DMA_NBR,
414 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
415 .dma_out_irq_flags = 0,
416 .dma_out_irq_description = "serial 3 dma tr",
417 #else
418 .dma_out_enabled = 0,
419 .dma_out_nbr = UINT_MAX,
420 .dma_out_irq_nbr = 0,
421 .dma_out_irq_flags = 0,
422 .dma_out_irq_description = NULL,
423 #endif
424 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
425 .dma_in_enabled = 1,
426 .dma_in_nbr = SER3_RX_DMA_NBR,
427 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
428 .dma_in_irq_flags = 0,
429 .dma_in_irq_description = "serial 3 dma rec",
430 #else
431 .dma_in_enabled = 0,
432 .dma_in_nbr = UINT_MAX,
433 .dma_in_irq_nbr = 0,
434 .dma_in_irq_flags = 0,
435 .dma_in_irq_description = NULL
436 #endif
437 #else
438 .enabled = 0,
439 .io_if_description = NULL,
440 .dma_out_enabled = 0,
441 .dma_in_enabled = 0
442 #endif
443 } /* ttyS3 */
444 };
445
446
447 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
448
449 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
450 static struct fast_timer fast_timers[NR_PORTS];
451 #endif
452
453 /* RS-485 */
454 #if defined(CONFIG_ETRAX_RS485)
455 #ifdef CONFIG_ETRAX_FAST_TIMER
456 static struct fast_timer fast_timers_rs485[NR_PORTS];
457 #endif
458 #if defined(CONFIG_ETRAX_RS485_ON_PA)
459 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
460 #endif
461 #endif
462
463 /* Info and macros needed for each ports extra control/status signals. */
464 #define E100_STRUCT_PORT(line, pinname) \
465 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
466 (R_PORT_PA_DATA): ( \
467 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
468 (R_PORT_PB_DATA):&dummy_ser[line]))
469
470 #define E100_STRUCT_SHADOW(line, pinname) \
471 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
472 (&port_pa_data_shadow): ( \
473 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
474 (&port_pb_data_shadow):&dummy_ser[line]))
475 #define E100_STRUCT_MASK(line, pinname) \
476 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
477 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
478 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
479 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
480
481 #define DUMMY_DTR_MASK 1
482 #define DUMMY_RI_MASK 2
483 #define DUMMY_DSR_MASK 4
484 #define DUMMY_CD_MASK 8
485 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
486
487 /* If not all status pins are used or disabled, use mixed mode */
488 #ifdef CONFIG_ETRAX_SERIAL_PORT0
489
490 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
491
492 #if SER0_PA_BITSUM != -4
493 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
494 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
495 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
496 # endif
497 # endif
498 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
499 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
500 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
501 # endif
502 # endif
503 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
504 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
505 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
506 # endif
507 # endif
508 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
509 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
510 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
511 # endif
512 # endif
513 #endif
514
515 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
516
517 #if SER0_PB_BITSUM != -4
518 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
519 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
520 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
521 # endif
522 # endif
523 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
524 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
525 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
526 # endif
527 # endif
528 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
529 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
530 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
531 # endif
532 # endif
533 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
534 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536 # endif
537 # endif
538 #endif
539
540 #endif /* PORT0 */
541
542
543 #ifdef CONFIG_ETRAX_SERIAL_PORT1
544
545 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
546
547 #if SER1_PA_BITSUM != -4
548 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
549 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
550 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
551 # endif
552 # endif
553 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
554 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
555 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
556 # endif
557 # endif
558 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
559 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
560 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
561 # endif
562 # endif
563 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
564 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
565 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
566 # endif
567 # endif
568 #endif
569
570 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
571
572 #if SER1_PB_BITSUM != -4
573 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
574 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
575 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
576 # endif
577 # endif
578 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
579 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
580 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
581 # endif
582 # endif
583 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
584 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
585 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
586 # endif
587 # endif
588 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
589 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591 # endif
592 # endif
593 #endif
594
595 #endif /* PORT1 */
596
597 #ifdef CONFIG_ETRAX_SERIAL_PORT2
598
599 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
600
601 #if SER2_PA_BITSUM != -4
602 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
603 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
604 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
605 # endif
606 # endif
607 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
608 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
609 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
610 # endif
611 # endif
612 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
613 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
614 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
615 # endif
616 # endif
617 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
618 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
619 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
620 # endif
621 # endif
622 #endif
623
624 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
625
626 #if SER2_PB_BITSUM != -4
627 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
628 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
629 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
630 # endif
631 # endif
632 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
633 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
634 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
635 # endif
636 # endif
637 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
638 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
639 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
640 # endif
641 # endif
642 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
643 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645 # endif
646 # endif
647 #endif
648
649 #endif /* PORT2 */
650
651 #ifdef CONFIG_ETRAX_SERIAL_PORT3
652
653 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
654
655 #if SER3_PA_BITSUM != -4
656 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
657 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
658 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
659 # endif
660 # endif
661 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
662 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
663 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
664 # endif
665 # endif
666 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
667 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
668 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
669 # endif
670 # endif
671 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
672 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
673 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
674 # endif
675 # endif
676 #endif
677
678 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
679
680 #if SER3_PB_BITSUM != -4
681 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
682 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
683 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
684 # endif
685 # endif
686 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
687 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
688 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
689 # endif
690 # endif
691 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
692 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
693 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
694 # endif
695 # endif
696 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
697 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699 # endif
700 # endif
701 #endif
702
703 #endif /* PORT3 */
704
705
706 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
707 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
708 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
709 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
710 #define ETRAX_SERX_DTR_RI_DSR_CD_MIXED
711 #endif
712
713 #ifdef ETRAX_SERX_DTR_RI_DSR_CD_MIXED
714 /* The pins can be mixed on PA and PB */
715 #define CONTROL_PINS_PORT_NOT_USED(line) \
716 &dummy_ser[line], &dummy_ser[line], \
717 &dummy_ser[line], &dummy_ser[line], \
718 &dummy_ser[line], &dummy_ser[line], \
719 &dummy_ser[line], &dummy_ser[line], \
720 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
721
722
723 struct control_pins
724 {
725 volatile unsigned char *dtr_port;
726 unsigned char *dtr_shadow;
727 volatile unsigned char *ri_port;
728 unsigned char *ri_shadow;
729 volatile unsigned char *dsr_port;
730 unsigned char *dsr_shadow;
731 volatile unsigned char *cd_port;
732 unsigned char *cd_shadow;
733
734 unsigned char dtr_mask;
735 unsigned char ri_mask;
736 unsigned char dsr_mask;
737 unsigned char cd_mask;
738 };
739
740 static const struct control_pins e100_modem_pins[NR_PORTS] =
741 {
742 /* Ser 0 */
743 {
744 #ifdef CONFIG_ETRAX_SERIAL_PORT0
745 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
746 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
747 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
748 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
749 E100_STRUCT_MASK(0,DTR),
750 E100_STRUCT_MASK(0,RI),
751 E100_STRUCT_MASK(0,DSR),
752 E100_STRUCT_MASK(0,CD)
753 #else
754 CONTROL_PINS_PORT_NOT_USED(0)
755 #endif
756 },
757
758 /* Ser 1 */
759 {
760 #ifdef CONFIG_ETRAX_SERIAL_PORT1
761 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
762 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
763 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
764 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
765 E100_STRUCT_MASK(1,DTR),
766 E100_STRUCT_MASK(1,RI),
767 E100_STRUCT_MASK(1,DSR),
768 E100_STRUCT_MASK(1,CD)
769 #else
770 CONTROL_PINS_PORT_NOT_USED(1)
771 #endif
772 },
773
774 /* Ser 2 */
775 {
776 #ifdef CONFIG_ETRAX_SERIAL_PORT2
777 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
778 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
779 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
780 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
781 E100_STRUCT_MASK(2,DTR),
782 E100_STRUCT_MASK(2,RI),
783 E100_STRUCT_MASK(2,DSR),
784 E100_STRUCT_MASK(2,CD)
785 #else
786 CONTROL_PINS_PORT_NOT_USED(2)
787 #endif
788 },
789
790 /* Ser 3 */
791 {
792 #ifdef CONFIG_ETRAX_SERIAL_PORT3
793 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
794 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
795 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
796 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
797 E100_STRUCT_MASK(3,DTR),
798 E100_STRUCT_MASK(3,RI),
799 E100_STRUCT_MASK(3,DSR),
800 E100_STRUCT_MASK(3,CD)
801 #else
802 CONTROL_PINS_PORT_NOT_USED(3)
803 #endif
804 }
805 };
806 #else /* ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
807
808 /* All pins are on either PA or PB for each serial port */
809 #define CONTROL_PINS_PORT_NOT_USED(line) \
810 &dummy_ser[line], &dummy_ser[line], \
811 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
812
813
814 struct control_pins
815 {
816 volatile unsigned char *port;
817 unsigned char *shadow;
818
819 unsigned char dtr_mask;
820 unsigned char ri_mask;
821 unsigned char dsr_mask;
822 unsigned char cd_mask;
823 };
824
825 #define dtr_port port
826 #define dtr_shadow shadow
827 #define ri_port port
828 #define ri_shadow shadow
829 #define dsr_port port
830 #define dsr_shadow shadow
831 #define cd_port port
832 #define cd_shadow shadow
833
834 static const struct control_pins e100_modem_pins[NR_PORTS] =
835 {
836 /* Ser 0 */
837 {
838 #ifdef CONFIG_ETRAX_SERIAL_PORT0
839 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
840 E100_STRUCT_MASK(0,DTR),
841 E100_STRUCT_MASK(0,RI),
842 E100_STRUCT_MASK(0,DSR),
843 E100_STRUCT_MASK(0,CD)
844 #else
845 CONTROL_PINS_PORT_NOT_USED(0)
846 #endif
847 },
848
849 /* Ser 1 */
850 {
851 #ifdef CONFIG_ETRAX_SERIAL_PORT1
852 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
853 E100_STRUCT_MASK(1,DTR),
854 E100_STRUCT_MASK(1,RI),
855 E100_STRUCT_MASK(1,DSR),
856 E100_STRUCT_MASK(1,CD)
857 #else
858 CONTROL_PINS_PORT_NOT_USED(1)
859 #endif
860 },
861
862 /* Ser 2 */
863 {
864 #ifdef CONFIG_ETRAX_SERIAL_PORT2
865 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
866 E100_STRUCT_MASK(2,DTR),
867 E100_STRUCT_MASK(2,RI),
868 E100_STRUCT_MASK(2,DSR),
869 E100_STRUCT_MASK(2,CD)
870 #else
871 CONTROL_PINS_PORT_NOT_USED(2)
872 #endif
873 },
874
875 /* Ser 3 */
876 {
877 #ifdef CONFIG_ETRAX_SERIAL_PORT3
878 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
879 E100_STRUCT_MASK(3,DTR),
880 E100_STRUCT_MASK(3,RI),
881 E100_STRUCT_MASK(3,DSR),
882 E100_STRUCT_MASK(3,CD)
883 #else
884 CONTROL_PINS_PORT_NOT_USED(3)
885 #endif
886 }
887 };
888 #endif /* !ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
889
890 #define E100_RTS_MASK 0x20
891 #define E100_CTS_MASK 0x40
892
893 /* All serial port signals are active low:
894 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
895 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
896 *
897 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
898 */
899
900 /* Output */
901 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
902 /* Input */
903 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
904
905 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
906 /* Is an output */
907 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
908
909 /* Normally inputs */
910 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
911 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
912
913 /* Input */
914 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
915
916 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
917 static void update_char_time(struct e100_serial * info)
918 {
919 tcflag_t cflags = info->port.tty->termios.c_cflag;
920 int bits;
921
922 /* calc. number of bits / data byte */
923 /* databits + startbit and 1 stopbit */
924 if ((cflags & CSIZE) == CS7)
925 bits = 9;
926 else
927 bits = 10;
928
929 if (cflags & CSTOPB) /* 2 stopbits ? */
930 bits++;
931
932 if (cflags & PARENB) /* parity bit ? */
933 bits++;
934
935 /* calc timeout */
936 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
937 info->flush_time_usec = 4*info->char_time_usec;
938 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
939 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
940
941 }
942
943 /*
944 * This function maps from the Bxxxx defines in asm/termbits.h into real
945 * baud rates.
946 */
947
948 static int
949 cflag_to_baud(unsigned int cflag)
950 {
951 static int baud_table[] = {
952 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
953 4800, 9600, 19200, 38400 };
954
955 static int ext_baud_table[] = {
956 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
957 0, 0, 0, 0, 0, 0, 0, 0 };
958
959 if (cflag & CBAUDEX)
960 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
961 else
962 return baud_table[cflag & CBAUD];
963 }
964
965 /* and this maps to an etrax100 hardware baud constant */
966
967 static unsigned char
968 cflag_to_etrax_baud(unsigned int cflag)
969 {
970 char retval;
971
972 static char baud_table[] = {
973 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
974
975 static char ext_baud_table[] = {
976 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
977
978 if (cflag & CBAUDEX)
979 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
980 else
981 retval = baud_table[cflag & CBAUD];
982
983 if (retval < 0) {
984 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
985 retval = 5; /* choose default 9600 instead */
986 }
987
988 return retval | (retval << 4); /* choose same for both TX and RX */
989 }
990
991
992 /* Various static support functions */
993
994 /* Functions to set or clear DTR/RTS on the requested line */
995 /* It is complicated by the fact that RTS is a serial port register, while
996 * DTR might not be implemented in the HW at all, and if it is, it can be on
997 * any general port.
998 */
999
1000
1001 static inline void
1002 e100_dtr(struct e100_serial *info, int set)
1003 {
1004 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1005
1006 #ifdef SERIAL_DEBUG_IO
1007 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1008 printk("ser%i shadow before 0x%02X get: %i\n",
1009 info->line, *e100_modem_pins[info->line].dtr_shadow,
1010 E100_DTR_GET(info));
1011 #endif
1012 /* DTR is active low */
1013 {
1014 unsigned long flags;
1015
1016 local_irq_save(flags);
1017 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1018 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1019 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1020 local_irq_restore(flags);
1021 }
1022
1023 #ifdef SERIAL_DEBUG_IO
1024 printk("ser%i shadow after 0x%02X get: %i\n",
1025 info->line, *e100_modem_pins[info->line].dtr_shadow,
1026 E100_DTR_GET(info));
1027 #endif
1028 }
1029
1030 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1031 * 0=0V , 1=3.3V
1032 */
1033 static inline void
1034 e100_rts(struct e100_serial *info, int set)
1035 {
1036 unsigned long flags;
1037 local_irq_save(flags);
1038 info->rx_ctrl &= ~E100_RTS_MASK;
1039 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1040 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1041 local_irq_restore(flags);
1042 #ifdef SERIAL_DEBUG_IO
1043 printk("ser%i rts %i\n", info->line, set);
1044 #endif
1045 }
1046
1047
1048 /* If this behaves as a modem, RI and CD is an output */
1049 static inline void
1050 e100_ri_out(struct e100_serial *info, int set)
1051 {
1052 /* RI is active low */
1053 {
1054 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1055 unsigned long flags;
1056
1057 local_irq_save(flags);
1058 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1059 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1060 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1061 local_irq_restore(flags);
1062 }
1063 }
1064 static inline void
1065 e100_cd_out(struct e100_serial *info, int set)
1066 {
1067 /* CD is active low */
1068 {
1069 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1070 unsigned long flags;
1071
1072 local_irq_save(flags);
1073 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1074 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1075 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1076 local_irq_restore(flags);
1077 }
1078 }
1079
1080 static inline void
1081 e100_disable_rx(struct e100_serial *info)
1082 {
1083 /* disable the receiver */
1084 info->ioport[REG_REC_CTRL] =
1085 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1086 }
1087
1088 static inline void
1089 e100_enable_rx(struct e100_serial *info)
1090 {
1091 /* enable the receiver */
1092 info->ioport[REG_REC_CTRL] =
1093 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1094 }
1095
1096 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1097
1098 static inline void
1099 e100_disable_rxdma_irq(struct e100_serial *info)
1100 {
1101 #ifdef SERIAL_DEBUG_INTR
1102 printk("rxdma_irq(%d): 0\n",info->line);
1103 #endif
1104 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1105 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1106 }
1107
1108 static inline void
1109 e100_enable_rxdma_irq(struct e100_serial *info)
1110 {
1111 #ifdef SERIAL_DEBUG_INTR
1112 printk("rxdma_irq(%d): 1\n",info->line);
1113 #endif
1114 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1115 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1116 }
1117
1118 /* the tx DMA uses only dma_descr interrupt */
1119
1120 static void e100_disable_txdma_irq(struct e100_serial *info)
1121 {
1122 #ifdef SERIAL_DEBUG_INTR
1123 printk("txdma_irq(%d): 0\n",info->line);
1124 #endif
1125 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1126 *R_IRQ_MASK2_CLR = info->irq;
1127 }
1128
1129 static void e100_enable_txdma_irq(struct e100_serial *info)
1130 {
1131 #ifdef SERIAL_DEBUG_INTR
1132 printk("txdma_irq(%d): 1\n",info->line);
1133 #endif
1134 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1135 *R_IRQ_MASK2_SET = info->irq;
1136 }
1137
1138 static void e100_disable_txdma_channel(struct e100_serial *info)
1139 {
1140 unsigned long flags;
1141
1142 /* Disable output DMA channel for the serial port in question
1143 * ( set to something other than serialX)
1144 */
1145 local_irq_save(flags);
1146 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1147 if (info->line == 0) {
1148 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1149 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1150 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1151 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1152 }
1153 } else if (info->line == 1) {
1154 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1155 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1156 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1157 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1158 }
1159 } else if (info->line == 2) {
1160 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1161 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1162 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1163 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1164 }
1165 } else if (info->line == 3) {
1166 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1167 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1168 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1169 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1170 }
1171 }
1172 *R_GEN_CONFIG = genconfig_shadow;
1173 local_irq_restore(flags);
1174 }
1175
1176
1177 static void e100_enable_txdma_channel(struct e100_serial *info)
1178 {
1179 unsigned long flags;
1180
1181 local_irq_save(flags);
1182 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1183 /* Enable output DMA channel for the serial port in question */
1184 if (info->line == 0) {
1185 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1186 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1187 } else if (info->line == 1) {
1188 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1189 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1190 } else if (info->line == 2) {
1191 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1192 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1193 } else if (info->line == 3) {
1194 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1195 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1196 }
1197 *R_GEN_CONFIG = genconfig_shadow;
1198 local_irq_restore(flags);
1199 }
1200
1201 static void e100_disable_rxdma_channel(struct e100_serial *info)
1202 {
1203 unsigned long flags;
1204
1205 /* Disable input DMA channel for the serial port in question
1206 * ( set to something other than serialX)
1207 */
1208 local_irq_save(flags);
1209 if (info->line == 0) {
1210 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1211 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1212 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1213 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1214 }
1215 } else if (info->line == 1) {
1216 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1217 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1218 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1219 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1220 }
1221 } else if (info->line == 2) {
1222 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1223 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1224 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1225 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1226 }
1227 } else if (info->line == 3) {
1228 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1229 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1230 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1231 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1232 }
1233 }
1234 *R_GEN_CONFIG = genconfig_shadow;
1235 local_irq_restore(flags);
1236 }
1237
1238
1239 static void e100_enable_rxdma_channel(struct e100_serial *info)
1240 {
1241 unsigned long flags;
1242
1243 local_irq_save(flags);
1244 /* Enable input DMA channel for the serial port in question */
1245 if (info->line == 0) {
1246 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1247 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1248 } else if (info->line == 1) {
1249 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1250 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1251 } else if (info->line == 2) {
1252 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1253 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1254 } else if (info->line == 3) {
1255 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1256 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1257 }
1258 *R_GEN_CONFIG = genconfig_shadow;
1259 local_irq_restore(flags);
1260 }
1261
1262 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1263 /* in order to detect and fix errors on the first byte
1264 we have to use the serial interrupts as well. */
1265
1266 static inline void
1267 e100_disable_serial_data_irq(struct e100_serial *info)
1268 {
1269 #ifdef SERIAL_DEBUG_INTR
1270 printk("ser_irq(%d): 0\n",info->line);
1271 #endif
1272 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1273 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1274 }
1275
1276 static inline void
1277 e100_enable_serial_data_irq(struct e100_serial *info)
1278 {
1279 #ifdef SERIAL_DEBUG_INTR
1280 printk("ser_irq(%d): 1\n",info->line);
1281 printk("**** %d = %d\n",
1282 (8+2*info->line),
1283 (1U << (8+2*info->line)));
1284 #endif
1285 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1286 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1287 }
1288 #endif
1289
1290 static inline void
1291 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1292 {
1293 #ifdef SERIAL_DEBUG_INTR
1294 printk("ser_tx_irq(%d): 0\n",info->line);
1295 #endif
1296 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1297 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1298 }
1299
1300 static inline void
1301 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1302 {
1303 #ifdef SERIAL_DEBUG_INTR
1304 printk("ser_tx_irq(%d): 1\n",info->line);
1305 printk("**** %d = %d\n",
1306 (8+1+2*info->line),
1307 (1U << (8+1+2*info->line)));
1308 #endif
1309 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1310 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1311 }
1312
1313 static inline void e100_enable_rx_irq(struct e100_serial *info)
1314 {
1315 if (info->uses_dma_in)
1316 e100_enable_rxdma_irq(info);
1317 else
1318 e100_enable_serial_data_irq(info);
1319 }
1320 static inline void e100_disable_rx_irq(struct e100_serial *info)
1321 {
1322 if (info->uses_dma_in)
1323 e100_disable_rxdma_irq(info);
1324 else
1325 e100_disable_serial_data_irq(info);
1326 }
1327
1328 #if defined(CONFIG_ETRAX_RS485)
1329 /* Enable RS-485 mode on selected port. This is UGLY. */
1330 static int
1331 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1332 {
1333 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1334
1335 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1336 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1337 #endif
1338
1339 info->rs485 = *r;
1340
1341 /* Maximum delay before RTS equal to 1000 */
1342 if (info->rs485.delay_rts_before_send >= 1000)
1343 info->rs485.delay_rts_before_send = 1000;
1344
1345 /* printk("rts: on send = %i, after = %i, enabled = %i",
1346 info->rs485.rts_on_send,
1347 info->rs485.rts_after_sent,
1348 info->rs485.enabled
1349 );
1350 */
1351 return 0;
1352 }
1353
1354 static int
1355 e100_write_rs485(struct tty_struct *tty,
1356 const unsigned char *buf, int count)
1357 {
1358 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1359 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1360
1361 /* rs485 is always implicitly enabled if we're using the ioctl()
1362 * but it doesn't have to be set in the serial_rs485
1363 * (to be backward compatible with old apps)
1364 * So we store, set and restore it.
1365 */
1366 info->rs485.flags |= SER_RS485_ENABLED;
1367 /* rs_write now deals with RS485 if enabled */
1368 count = rs_write(tty, buf, count);
1369 if (!old_value)
1370 info->rs485.flags &= ~(SER_RS485_ENABLED);
1371 return count;
1372 }
1373
1374 #ifdef CONFIG_ETRAX_FAST_TIMER
1375 /* Timer function to toggle RTS when using FAST_TIMER */
1376 static void rs485_toggle_rts_timer_function(unsigned long data)
1377 {
1378 struct e100_serial *info = (struct e100_serial *)data;
1379
1380 fast_timers_rs485[info->line].function = NULL;
1381 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1382 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1383 e100_enable_rx(info);
1384 e100_enable_rx_irq(info);
1385 #endif
1386 }
1387 #endif
1388 #endif /* CONFIG_ETRAX_RS485 */
1389
1390 /*
1391 * ------------------------------------------------------------
1392 * rs_stop() and rs_start()
1393 *
1394 * This routines are called before setting or resetting tty->stopped.
1395 * They enable or disable transmitter using the XOFF registers, as necessary.
1396 * ------------------------------------------------------------
1397 */
1398
1399 static void
1400 rs_stop(struct tty_struct *tty)
1401 {
1402 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1403 if (info) {
1404 unsigned long flags;
1405 unsigned long xoff;
1406
1407 local_irq_save(flags);
1408 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1409 CIRC_CNT(info->xmit.head,
1410 info->xmit.tail,SERIAL_XMIT_SIZE)));
1411
1412 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1413 STOP_CHAR(info->port.tty));
1414 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1415 if (I_IXON(tty))
1416 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1417
1418 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1419 local_irq_restore(flags);
1420 }
1421 }
1422
1423 static void
1424 rs_start(struct tty_struct *tty)
1425 {
1426 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1427 if (info) {
1428 unsigned long flags;
1429 unsigned long xoff;
1430
1431 local_irq_save(flags);
1432 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1433 CIRC_CNT(info->xmit.head,
1434 info->xmit.tail,SERIAL_XMIT_SIZE)));
1435 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1436 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1437 if (I_IXON(tty))
1438 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1439
1440 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1441 if (!info->uses_dma_out &&
1442 info->xmit.head != info->xmit.tail && info->xmit.buf)
1443 e100_enable_serial_tx_ready_irq(info);
1444
1445 local_irq_restore(flags);
1446 }
1447 }
1448
1449 /*
1450 * ----------------------------------------------------------------------
1451 *
1452 * Here starts the interrupt handling routines. All of the following
1453 * subroutines are declared as inline and are folded into
1454 * rs_interrupt(). They were separated out for readability's sake.
1455 *
1456 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1457 * runs with interrupts turned off. People who may want to modify
1458 * rs_interrupt() should try to keep the interrupt handler as fast as
1459 * possible. After you are done making modifications, it is not a bad
1460 * idea to do:
1461 *
1462 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1463 *
1464 * and look at the resulting assemble code in serial.s.
1465 *
1466 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1467 * -----------------------------------------------------------------------
1468 */
1469
1470 /*
1471 * This routine is used by the interrupt handler to schedule
1472 * processing in the software interrupt portion of the driver.
1473 */
1474 static void rs_sched_event(struct e100_serial *info, int event)
1475 {
1476 if (info->event & (1 << event))
1477 return;
1478 info->event |= 1 << event;
1479 schedule_work(&info->work);
1480 }
1481
1482 /* The output DMA channel is free - use it to send as many chars as possible
1483 * NOTES:
1484 * We don't pay attention to info->x_char, which means if the TTY wants to
1485 * use XON/XOFF it will set info->x_char but we won't send any X char!
1486 *
1487 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1488 * buffer containing the X char, and skip updating xmit. We'd also have to
1489 * check if the last sent char was the X char when we enter this function
1490 * the next time, to avoid updating xmit with the sent X value.
1491 */
1492
1493 static void
1494 transmit_chars_dma(struct e100_serial *info)
1495 {
1496 unsigned int c, sentl;
1497 struct etrax_dma_descr *descr;
1498
1499 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1500 *info->oclrintradr =
1501 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1502 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1503
1504 #ifdef SERIAL_DEBUG_INTR
1505 if (info->line == SERIAL_DEBUG_LINE)
1506 printk("tc\n");
1507 #endif
1508 if (!info->tr_running) {
1509 /* weirdo... we shouldn't get here! */
1510 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1511 return;
1512 }
1513
1514 descr = &info->tr_descr;
1515
1516 /* first get the amount of bytes sent during the last DMA transfer,
1517 and update xmit accordingly */
1518
1519 /* if the stop bit was not set, all data has been sent */
1520 if (!(descr->status & d_stop)) {
1521 sentl = descr->sw_len;
1522 } else
1523 /* otherwise we find the amount of data sent here */
1524 sentl = descr->hw_len;
1525
1526 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1527
1528 /* update stats */
1529 info->icount.tx += sentl;
1530
1531 /* update xmit buffer */
1532 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1533
1534 /* if there is only a few chars left in the buf, wake up the blocked
1535 write if any */
1536 if (CIRC_CNT(info->xmit.head,
1537 info->xmit.tail,
1538 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1539 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1540
1541 /* find out the largest amount of consecutive bytes we want to send now */
1542
1543 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1544
1545 /* Don't send all in one DMA transfer - divide it so we wake up
1546 * application before all is sent
1547 */
1548
1549 if (c >= 4*WAKEUP_CHARS)
1550 c = c/2;
1551
1552 if (c <= 0) {
1553 /* our job here is done, don't schedule any new DMA transfer */
1554 info->tr_running = 0;
1555
1556 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1557 if (info->rs485.flags & SER_RS485_ENABLED) {
1558 /* Set a short timer to toggle RTS */
1559 start_one_shot_timer(&fast_timers_rs485[info->line],
1560 rs485_toggle_rts_timer_function,
1561 (unsigned long)info,
1562 info->char_time_usec*2,
1563 "RS-485");
1564 }
1565 #endif /* RS485 */
1566 return;
1567 }
1568
1569 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1570 /* set up the descriptor correctly for output */
1571 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1572 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1573 descr->sw_len = c;
1574 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1575 descr->status = 0;
1576
1577 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1578 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1579
1580 /* DMA is now running (hopefully) */
1581 } /* transmit_chars_dma */
1582
1583 static void
1584 start_transmit(struct e100_serial *info)
1585 {
1586 #if 0
1587 if (info->line == SERIAL_DEBUG_LINE)
1588 printk("x\n");
1589 #endif
1590
1591 info->tr_descr.sw_len = 0;
1592 info->tr_descr.hw_len = 0;
1593 info->tr_descr.status = 0;
1594 info->tr_running = 1;
1595 if (info->uses_dma_out)
1596 transmit_chars_dma(info);
1597 else
1598 e100_enable_serial_tx_ready_irq(info);
1599 } /* start_transmit */
1600
1601 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1602 static int serial_fast_timer_started = 0;
1603 static int serial_fast_timer_expired = 0;
1604 static void flush_timeout_function(unsigned long data);
1605 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1606 unsigned long timer_flags; \
1607 local_irq_save(timer_flags); \
1608 if (fast_timers[info->line].function == NULL) { \
1609 serial_fast_timer_started++; \
1610 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1611 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1612 start_one_shot_timer(&fast_timers[info->line], \
1613 flush_timeout_function, \
1614 (unsigned long)info, \
1615 (usec), \
1616 string); \
1617 } \
1618 else { \
1619 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1620 } \
1621 local_irq_restore(timer_flags); \
1622 }
1623 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1624
1625 #else
1626 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1627 #define START_FLUSH_FAST_TIMER(info, string)
1628 #endif
1629
1630 static struct etrax_recv_buffer *
1631 alloc_recv_buffer(unsigned int size)
1632 {
1633 struct etrax_recv_buffer *buffer;
1634
1635 buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC);
1636 if (!buffer)
1637 return NULL;
1638
1639 buffer->next = NULL;
1640 buffer->length = 0;
1641 buffer->error = TTY_NORMAL;
1642
1643 return buffer;
1644 }
1645
1646 static void
1647 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1648 {
1649 unsigned long flags;
1650
1651 local_irq_save(flags);
1652
1653 if (!info->first_recv_buffer)
1654 info->first_recv_buffer = buffer;
1655 else
1656 info->last_recv_buffer->next = buffer;
1657
1658 info->last_recv_buffer = buffer;
1659
1660 info->recv_cnt += buffer->length;
1661 if (info->recv_cnt > info->max_recv_cnt)
1662 info->max_recv_cnt = info->recv_cnt;
1663
1664 local_irq_restore(flags);
1665 }
1666
1667 static int
1668 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1669 {
1670 struct etrax_recv_buffer *buffer;
1671 if (info->uses_dma_in) {
1672 buffer = alloc_recv_buffer(4);
1673 if (!buffer)
1674 return 0;
1675
1676 buffer->length = 1;
1677 buffer->error = flag;
1678 buffer->buffer[0] = data;
1679
1680 append_recv_buffer(info, buffer);
1681
1682 info->icount.rx++;
1683 } else {
1684 tty_insert_flip_char(&info->port, data, flag);
1685 info->icount.rx++;
1686 }
1687
1688 return 1;
1689 }
1690
1691 static unsigned int handle_descr_data(struct e100_serial *info,
1692 struct etrax_dma_descr *descr,
1693 unsigned int recvl)
1694 {
1695 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1696
1697 if (info->recv_cnt + recvl > 65536) {
1698 printk(KERN_WARNING
1699 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1700 return 0;
1701 }
1702
1703 buffer->length = recvl;
1704
1705 if (info->errorcode == ERRCODE_SET_BREAK)
1706 buffer->error = TTY_BREAK;
1707 info->errorcode = 0;
1708
1709 append_recv_buffer(info, buffer);
1710
1711 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1712 if (!buffer)
1713 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1714
1715 descr->buf = virt_to_phys(buffer->buffer);
1716
1717 return recvl;
1718 }
1719
1720 static unsigned int handle_all_descr_data(struct e100_serial *info)
1721 {
1722 struct etrax_dma_descr *descr;
1723 unsigned int recvl;
1724 unsigned int ret = 0;
1725
1726 while (1)
1727 {
1728 descr = &info->rec_descr[info->cur_rec_descr];
1729
1730 if (descr == phys_to_virt(*info->idescradr))
1731 break;
1732
1733 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1734 info->cur_rec_descr = 0;
1735
1736 /* find out how many bytes were read */
1737
1738 /* if the eop bit was not set, all data has been received */
1739 if (!(descr->status & d_eop)) {
1740 recvl = descr->sw_len;
1741 } else {
1742 /* otherwise we find the amount of data received here */
1743 recvl = descr->hw_len;
1744 }
1745
1746 /* Reset the status information */
1747 descr->status = 0;
1748
1749 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1750 if (info->port.tty->stopped) {
1751 unsigned char *buf = phys_to_virt(descr->buf);
1752 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1753 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1754 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1755 }
1756 );
1757
1758 /* update stats */
1759 info->icount.rx += recvl;
1760
1761 ret += handle_descr_data(info, descr, recvl);
1762 }
1763
1764 return ret;
1765 }
1766
1767 static void receive_chars_dma(struct e100_serial *info)
1768 {
1769 struct tty_struct *tty;
1770 unsigned char rstat;
1771
1772 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1773 *info->iclrintradr =
1774 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1775 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1776
1777 tty = info->port.tty;
1778 if (!tty) /* Something wrong... */
1779 return;
1780
1781 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1782 if (info->uses_dma_in)
1783 e100_enable_serial_data_irq(info);
1784 #endif
1785
1786 if (info->errorcode == ERRCODE_INSERT_BREAK)
1787 add_char_and_flag(info, '\0', TTY_BREAK);
1788
1789 handle_all_descr_data(info);
1790
1791 /* Read the status register to detect errors */
1792 rstat = info->ioport[REG_STATUS];
1793 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1794 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1795 }
1796
1797 if (rstat & SER_ERROR_MASK) {
1798 /* If we got an error, we must reset it by reading the
1799 * data_in field
1800 */
1801 unsigned char data = info->ioport[REG_DATA];
1802
1803 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1804 ((rstat & SER_ERROR_MASK) << 8) | data);
1805
1806 if (rstat & SER_PAR_ERR_MASK)
1807 add_char_and_flag(info, data, TTY_PARITY);
1808 else if (rstat & SER_OVERRUN_MASK)
1809 add_char_and_flag(info, data, TTY_OVERRUN);
1810 else if (rstat & SER_FRAMING_ERR_MASK)
1811 add_char_and_flag(info, data, TTY_FRAME);
1812 }
1813
1814 START_FLUSH_FAST_TIMER(info, "receive_chars");
1815
1816 /* Restart the receiving DMA */
1817 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1818 }
1819
1820 static int start_recv_dma(struct e100_serial *info)
1821 {
1822 struct etrax_dma_descr *descr = info->rec_descr;
1823 struct etrax_recv_buffer *buffer;
1824 int i;
1825
1826 /* Set up the receiving descriptors */
1827 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1828 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1829 if (!buffer)
1830 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1831
1832 descr[i].ctrl = d_int;
1833 descr[i].buf = virt_to_phys(buffer->buffer);
1834 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1835 descr[i].hw_len = 0;
1836 descr[i].status = 0;
1837 descr[i].next = virt_to_phys(&descr[i+1]);
1838 }
1839
1840 /* Link the last descriptor to the first */
1841 descr[i-1].next = virt_to_phys(&descr[0]);
1842
1843 /* Start with the first descriptor in the list */
1844 info->cur_rec_descr = 0;
1845
1846 /* Start the DMA */
1847 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1848 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1849
1850 /* Input DMA should be running now */
1851 return 1;
1852 }
1853
1854 static void
1855 start_receive(struct e100_serial *info)
1856 {
1857 if (info->uses_dma_in) {
1858 /* reset the input dma channel to be sure it works */
1859
1860 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1861 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1862 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1863
1864 start_recv_dma(info);
1865 }
1866 }
1867
1868
1869 /* the bits in the MASK2 register are laid out like this:
1870 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1871 where I is the input channel and O is the output channel for the port.
1872 info->irq is the bit number for the DMAO_DESCR so to check the others we
1873 shift info->irq to the left.
1874 */
1875
1876 /* dma output channel interrupt handler
1877 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1878 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1879 */
1880
1881 static irqreturn_t
1882 tr_interrupt(int irq, void *dev_id)
1883 {
1884 struct e100_serial *info;
1885 unsigned long ireg;
1886 int i;
1887 int handled = 0;
1888
1889 /* find out the line that caused this irq and get it from rs_table */
1890
1891 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1892
1893 for (i = 0; i < NR_PORTS; i++) {
1894 info = rs_table + i;
1895 if (!info->enabled || !info->uses_dma_out)
1896 continue;
1897 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
1898 if (ireg & info->irq) {
1899 handled = 1;
1900 /* we can send a new dma bunch. make it so. */
1901 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
1902 /* Read jiffies_usec first,
1903 * we want this time to be as late as possible
1904 */
1905 info->last_tx_active_usec = GET_JIFFIES_USEC();
1906 info->last_tx_active = jiffies;
1907 transmit_chars_dma(info);
1908 }
1909
1910 /* FIXME: here we should really check for a change in the
1911 status lines and if so call status_handle(info) */
1912 }
1913 return IRQ_RETVAL(handled);
1914 } /* tr_interrupt */
1915
1916 /* dma input channel interrupt handler */
1917
1918 static irqreturn_t
1919 rec_interrupt(int irq, void *dev_id)
1920 {
1921 struct e100_serial *info;
1922 unsigned long ireg;
1923 int i;
1924 int handled = 0;
1925
1926 /* find out the line that caused this irq and get it from rs_table */
1927
1928 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1929
1930 for (i = 0; i < NR_PORTS; i++) {
1931 info = rs_table + i;
1932 if (!info->enabled || !info->uses_dma_in)
1933 continue;
1934 /* check for both dma_eop and dma_descr for the input dma channel */
1935 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
1936 handled = 1;
1937 /* we have received something */
1938 receive_chars_dma(info);
1939 }
1940
1941 /* FIXME: here we should really check for a change in the
1942 status lines and if so call status_handle(info) */
1943 }
1944 return IRQ_RETVAL(handled);
1945 } /* rec_interrupt */
1946
1947 static int force_eop_if_needed(struct e100_serial *info)
1948 {
1949 /* We check data_avail bit to determine if data has
1950 * arrived since last time
1951 */
1952 unsigned char rstat = info->ioport[REG_STATUS];
1953
1954 /* error or datavail? */
1955 if (rstat & SER_ERROR_MASK) {
1956 /* Some error has occurred. If there has been valid data, an
1957 * EOP interrupt will be made automatically. If no data, the
1958 * normal ser_interrupt should be enabled and handle it.
1959 * So do nothing!
1960 */
1961 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
1962 rstat | (info->line << 8));
1963 return 0;
1964 }
1965
1966 if (rstat & SER_DATA_AVAIL_MASK) {
1967 /* Ok data, no error, count it */
1968 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
1969 rstat | (info->line << 8)));
1970 /* Read data to clear status flags */
1971 (void)info->ioport[REG_DATA];
1972
1973 info->forced_eop = 0;
1974 START_FLUSH_FAST_TIMER(info, "magic");
1975 return 0;
1976 }
1977
1978 /* hit the timeout, force an EOP for the input
1979 * dma channel if we haven't already
1980 */
1981 if (!info->forced_eop) {
1982 info->forced_eop = 1;
1983 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
1984 FORCE_EOP(info);
1985 }
1986
1987 return 1;
1988 }
1989
1990 static void flush_to_flip_buffer(struct e100_serial *info)
1991 {
1992 struct etrax_recv_buffer *buffer;
1993 unsigned long flags;
1994
1995 local_irq_save(flags);
1996
1997 while ((buffer = info->first_recv_buffer) != NULL) {
1998 unsigned int count = buffer->length;
1999
2000 tty_insert_flip_string(&info->port, buffer->buffer, count);
2001 info->recv_cnt -= count;
2002
2003 if (count == buffer->length) {
2004 info->first_recv_buffer = buffer->next;
2005 kfree(buffer);
2006 } else {
2007 buffer->length -= count;
2008 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2009 buffer->error = TTY_NORMAL;
2010 }
2011 }
2012
2013 if (!info->first_recv_buffer)
2014 info->last_recv_buffer = NULL;
2015
2016 local_irq_restore(flags);
2017
2018 /* This includes a check for low-latency */
2019 tty_flip_buffer_push(&info->port);
2020 }
2021
2022 static void check_flush_timeout(struct e100_serial *info)
2023 {
2024 /* Flip what we've got (if we can) */
2025 flush_to_flip_buffer(info);
2026
2027 /* We might need to flip later, but not to fast
2028 * since the system is busy processing input... */
2029 if (info->first_recv_buffer)
2030 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2031
2032 /* Force eop last, since data might have come while we're processing
2033 * and if we started the slow timer above, we won't start a fast
2034 * below.
2035 */
2036 force_eop_if_needed(info);
2037 }
2038
2039 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2040 static void flush_timeout_function(unsigned long data)
2041 {
2042 struct e100_serial *info = (struct e100_serial *)data;
2043
2044 fast_timers[info->line].function = NULL;
2045 serial_fast_timer_expired++;
2046 TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line));
2047 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2048 check_flush_timeout(info);
2049 }
2050
2051 #else
2052
2053 /* dma fifo/buffer timeout handler
2054 forces an end-of-packet for the dma input channel if no chars
2055 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2056 */
2057
2058 static struct timer_list flush_timer;
2059
2060 static void
2061 timed_flush_handler(unsigned long ptr)
2062 {
2063 struct e100_serial *info;
2064 int i;
2065
2066 for (i = 0; i < NR_PORTS; i++) {
2067 info = rs_table + i;
2068 if (info->uses_dma_in)
2069 check_flush_timeout(info);
2070 }
2071
2072 /* restart flush timer */
2073 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2074 }
2075 #endif
2076
2077 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2078
2079 /* If there is an error (ie break) when the DMA is running and
2080 * there are no bytes in the fifo the DMA is stopped and we get no
2081 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2082 * transfer, and if it is without error we can turn the serial
2083 * interrupts off.
2084 */
2085
2086 /*
2087 BREAK handling on ETRAX 100:
2088 ETRAX will generate interrupt although there is no stop bit between the
2089 characters.
2090
2091 Depending on how long the break sequence is, the end of the breaksequence
2092 will look differently:
2093 | indicates start/end of a character.
2094
2095 B= Break character (0x00) with framing error.
2096 E= Error byte with parity error received after B characters.
2097 F= "Faked" valid byte received immediately after B characters.
2098 V= Valid byte
2099
2100 1.
2101 B BL ___________________________ V
2102 .._|__________|__________| |valid data |
2103
2104 Multiple frame errors with data == 0x00 (B),
2105 the timing matches up "perfectly" so no extra ending char is detected.
2106 The RXD pin is 1 in the last interrupt, in that case
2107 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2108 know if another byte will come and this really is case 2. below
2109 (e.g F=0xFF or 0xFE)
2110 If RXD pin is 0 we can expect another character (see 2. below).
2111
2112
2113 2.
2114
2115 B B E or F__________________..__ V
2116 .._|__________|__________|______ | |valid data
2117 "valid" or
2118 parity error
2119
2120 Multiple frame errors with data == 0x00 (B),
2121 but the part of the break trigs is interpreted as a start bit (and possibly
2122 some 0 bits followed by a number of 1 bits and a stop bit).
2123 Depending on parity settings etc. this last character can be either
2124 a fake "valid" char (F) or have a parity error (E).
2125
2126 If the character is valid it will be put in the buffer,
2127 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2128 will set the flags so the tty will handle it,
2129 if it's an error byte it will not be put in the buffer
2130 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2131
2132 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2133 of the last faulty char (B) and compares it with the current time:
2134 If the time elapsed time is less then 2*char_time_usec we will assume
2135 it's a faked F char and not a Valid char and set
2136 info->errorcode = ERRCODE_SET_BREAK.
2137
2138 Flaws in the above solution:
2139 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2140 We use the timer to distinguish a F character from a V character,
2141 if a V character is to close after the break we might make the wrong decision.
2142
2143 TODO: The break will be delayed until an F or V character is received.
2144
2145 */
2146
2147 static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2148 {
2149 unsigned long data_read;
2150
2151 /* Read data and status at the same time */
2152 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2153 more_data:
2154 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2155 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2156 }
2157 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2158
2159 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2160 IO_MASK(R_SERIAL0_READ, par_err) |
2161 IO_MASK(R_SERIAL0_READ, overrun) )) {
2162 /* An error */
2163 info->last_rx_active_usec = GET_JIFFIES_USEC();
2164 info->last_rx_active = jiffies;
2165 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2166 DLOG_INT_TRIG(
2167 if (!log_int_trig1_pos) {
2168 log_int_trig1_pos = log_int_pos;
2169 log_int(rdpc(), 0, 0);
2170 }
2171 );
2172
2173
2174 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2175 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2176 /* Most likely a break, but we get interrupts over and
2177 * over again.
2178 */
2179
2180 if (!info->break_detected_cnt) {
2181 DEBUG_LOG(info->line, "#BRK start\n", 0);
2182 }
2183 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2184 /* The RX pin is high now, so the break
2185 * must be over, but....
2186 * we can't really know if we will get another
2187 * last byte ending the break or not.
2188 * And we don't know if the byte (if any) will
2189 * have an error or look valid.
2190 */
2191 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2192 info->errorcode = ERRCODE_INSERT_BREAK;
2193 }
2194 info->break_detected_cnt++;
2195 } else {
2196 /* The error does not look like a break, but could be
2197 * the end of one
2198 */
2199 if (info->break_detected_cnt) {
2200 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2201 info->errorcode = ERRCODE_INSERT_BREAK;
2202 } else {
2203 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2204 data_in, data_read);
2205 char flag = TTY_NORMAL;
2206 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2207 tty_insert_flip_char(&info->port, 0, flag);
2208 info->icount.rx++;
2209 }
2210
2211 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2212 info->icount.parity++;
2213 flag = TTY_PARITY;
2214 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2215 info->icount.overrun++;
2216 flag = TTY_OVERRUN;
2217 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2218 info->icount.frame++;
2219 flag = TTY_FRAME;
2220 }
2221 tty_insert_flip_char(&info->port, data, flag);
2222 info->errorcode = 0;
2223 }
2224 info->break_detected_cnt = 0;
2225 }
2226 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2227 /* No error */
2228 DLOG_INT_TRIG(
2229 if (!log_int_trig1_pos) {
2230 if (log_int_pos >= log_int_size) {
2231 log_int_pos = 0;
2232 }
2233 log_int_trig0_pos = log_int_pos;
2234 log_int(rdpc(), 0, 0);
2235 }
2236 );
2237 tty_insert_flip_char(&info->port,
2238 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2239 TTY_NORMAL);
2240 } else {
2241 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2242 }
2243
2244
2245 info->icount.rx++;
2246 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2247 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2248 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2249 goto more_data;
2250 }
2251
2252 tty_flip_buffer_push(&info->port);
2253 }
2254
2255 static void handle_ser_rx_interrupt(struct e100_serial *info)
2256 {
2257 unsigned char rstat;
2258
2259 #ifdef SERIAL_DEBUG_INTR
2260 printk("Interrupt from serport %d\n", i);
2261 #endif
2262 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2263 if (!info->uses_dma_in) {
2264 handle_ser_rx_interrupt_no_dma(info);
2265 return;
2266 }
2267 /* DMA is used */
2268 rstat = info->ioport[REG_STATUS];
2269 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2270 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2271 }
2272
2273 if (rstat & SER_ERROR_MASK) {
2274 unsigned char data;
2275
2276 info->last_rx_active_usec = GET_JIFFIES_USEC();
2277 info->last_rx_active = jiffies;
2278 /* If we got an error, we must reset it by reading the
2279 * data_in field
2280 */
2281 data = info->ioport[REG_DATA];
2282 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2283 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2284 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2285 /* Most likely a break, but we get interrupts over and
2286 * over again.
2287 */
2288
2289 if (!info->break_detected_cnt) {
2290 DEBUG_LOG(info->line, "#BRK start\n", 0);
2291 }
2292 if (rstat & SER_RXD_MASK) {
2293 /* The RX pin is high now, so the break
2294 * must be over, but....
2295 * we can't really know if we will get another
2296 * last byte ending the break or not.
2297 * And we don't know if the byte (if any) will
2298 * have an error or look valid.
2299 */
2300 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2301 info->errorcode = ERRCODE_INSERT_BREAK;
2302 }
2303 info->break_detected_cnt++;
2304 } else {
2305 /* The error does not look like a break, but could be
2306 * the end of one
2307 */
2308 if (info->break_detected_cnt) {
2309 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2310 info->errorcode = ERRCODE_INSERT_BREAK;
2311 } else {
2312 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2313 info->icount.brk++;
2314 add_char_and_flag(info, '\0', TTY_BREAK);
2315 }
2316
2317 if (rstat & SER_PAR_ERR_MASK) {
2318 info->icount.parity++;
2319 add_char_and_flag(info, data, TTY_PARITY);
2320 } else if (rstat & SER_OVERRUN_MASK) {
2321 info->icount.overrun++;
2322 add_char_and_flag(info, data, TTY_OVERRUN);
2323 } else if (rstat & SER_FRAMING_ERR_MASK) {
2324 info->icount.frame++;
2325 add_char_and_flag(info, data, TTY_FRAME);
2326 }
2327
2328 info->errorcode = 0;
2329 }
2330 info->break_detected_cnt = 0;
2331 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2332 ((rstat & SER_ERROR_MASK) << 8) | data);
2333 }
2334 } else { /* It was a valid byte, now let the DMA do the rest */
2335 unsigned long curr_time_u = GET_JIFFIES_USEC();
2336 unsigned long curr_time = jiffies;
2337
2338 if (info->break_detected_cnt) {
2339 /* Detect if this character is a new valid char or the
2340 * last char in a break sequence: If LSBits are 0 and
2341 * MSBits are high AND the time is close to the
2342 * previous interrupt we should discard it.
2343 */
2344 long elapsed_usec =
2345 (curr_time - info->last_rx_active) * (1000000/HZ) +
2346 curr_time_u - info->last_rx_active_usec;
2347 if (elapsed_usec < 2*info->char_time_usec) {
2348 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2349 /* Report as BREAK (error) and let
2350 * receive_chars_dma() handle it
2351 */
2352 info->errorcode = ERRCODE_SET_BREAK;
2353 } else {
2354 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2355 }
2356 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2357 }
2358
2359 #ifdef SERIAL_DEBUG_INTR
2360 printk("** OK, disabling ser_interrupts\n");
2361 #endif
2362 e100_disable_serial_data_irq(info);
2363 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2364 info->break_detected_cnt = 0;
2365
2366 }
2367 /* Restarting the DMA never hurts */
2368 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2369 START_FLUSH_FAST_TIMER(info, "ser_int");
2370 } /* handle_ser_rx_interrupt */
2371
2372 static void handle_ser_tx_interrupt(struct e100_serial *info)
2373 {
2374 unsigned long flags;
2375
2376 if (info->x_char) {
2377 unsigned char rstat;
2378 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2379 local_irq_save(flags);
2380 rstat = info->ioport[REG_STATUS];
2381 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2382
2383 info->ioport[REG_TR_DATA] = info->x_char;
2384 info->icount.tx++;
2385 info->x_char = 0;
2386 /* We must enable since it is disabled in ser_interrupt */
2387 e100_enable_serial_tx_ready_irq(info);
2388 local_irq_restore(flags);
2389 return;
2390 }
2391 if (info->uses_dma_out) {
2392 unsigned char rstat;
2393 int i;
2394 /* We only use normal tx interrupt when sending x_char */
2395 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2396 local_irq_save(flags);
2397 rstat = info->ioport[REG_STATUS];
2398 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2399 e100_disable_serial_tx_ready_irq(info);
2400 if (info->port.tty->stopped)
2401 rs_stop(info->port.tty);
2402 /* Enable the DMA channel and tell it to continue */
2403 e100_enable_txdma_channel(info);
2404 /* Wait 12 cycles before doing the DMA command */
2405 for(i = 6; i > 0; i--)
2406 nop();
2407
2408 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2409 local_irq_restore(flags);
2410 return;
2411 }
2412 /* Normal char-by-char interrupt */
2413 if (info->xmit.head == info->xmit.tail
2414 || info->port.tty->stopped) {
2415 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2416 info->port.tty->stopped));
2417 e100_disable_serial_tx_ready_irq(info);
2418 info->tr_running = 0;
2419 return;
2420 }
2421 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2422 /* Send a byte, rs485 timing is critical so turn of ints */
2423 local_irq_save(flags);
2424 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2425 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2426 info->icount.tx++;
2427 if (info->xmit.head == info->xmit.tail) {
2428 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2429 if (info->rs485.flags & SER_RS485_ENABLED) {
2430 /* Set a short timer to toggle RTS */
2431 start_one_shot_timer(&fast_timers_rs485[info->line],
2432 rs485_toggle_rts_timer_function,
2433 (unsigned long)info,
2434 info->char_time_usec*2,
2435 "RS-485");
2436 }
2437 #endif /* RS485 */
2438 info->last_tx_active_usec = GET_JIFFIES_USEC();
2439 info->last_tx_active = jiffies;
2440 e100_disable_serial_tx_ready_irq(info);
2441 info->tr_running = 0;
2442 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2443 } else {
2444 /* We must enable since it is disabled in ser_interrupt */
2445 e100_enable_serial_tx_ready_irq(info);
2446 }
2447 local_irq_restore(flags);
2448
2449 if (CIRC_CNT(info->xmit.head,
2450 info->xmit.tail,
2451 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2452 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2453
2454 } /* handle_ser_tx_interrupt */
2455
2456 /* result of time measurements:
2457 * RX duration 54-60 us when doing something, otherwise 6-9 us
2458 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2459 */
2460 static irqreturn_t
2461 ser_interrupt(int irq, void *dev_id)
2462 {
2463 static volatile int tx_started = 0;
2464 struct e100_serial *info;
2465 int i;
2466 unsigned long flags;
2467 unsigned long irq_mask1_rd;
2468 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2469 int handled = 0;
2470 static volatile unsigned long reentered_ready_mask = 0;
2471
2472 local_irq_save(flags);
2473 irq_mask1_rd = *R_IRQ_MASK1_RD;
2474 /* First handle all rx interrupts with ints disabled */
2475 info = rs_table;
2476 irq_mask1_rd &= e100_ser_int_mask;
2477 for (i = 0; i < NR_PORTS; i++) {
2478 /* Which line caused the data irq? */
2479 if (irq_mask1_rd & data_mask) {
2480 handled = 1;
2481 handle_ser_rx_interrupt(info);
2482 }
2483 info += 1;
2484 data_mask <<= 2;
2485 }
2486 /* Handle tx interrupts with interrupts enabled so we
2487 * can take care of new data interrupts while transmitting
2488 * We protect the tx part with the tx_started flag.
2489 * We disable the tr_ready interrupts we are about to handle and
2490 * unblock the serial interrupt so new serial interrupts may come.
2491 *
2492 * If we get a new interrupt:
2493 * - it migth be due to synchronous serial ports.
2494 * - serial irq will be blocked by general irq handler.
2495 * - async data will be handled above (sync will be ignored).
2496 * - tx_started flag will prevent us from trying to send again and
2497 * we will exit fast - no need to unblock serial irq.
2498 * - Next (sync) serial interrupt handler will be runned with
2499 * disabled interrupt due to restore_flags() at end of function,
2500 * so sync handler will not be preempted or reentered.
2501 */
2502 if (!tx_started) {
2503 unsigned long ready_mask;
2504 unsigned long
2505 tx_started = 1;
2506 /* Only the tr_ready interrupts left */
2507 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2508 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2509 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2510 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2511 while (irq_mask1_rd) {
2512 /* Disable those we are about to handle */
2513 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2514 /* Unblock the serial interrupt */
2515 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2516
2517 local_irq_enable();
2518 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2519 info = rs_table;
2520 for (i = 0; i < NR_PORTS; i++) {
2521 /* Which line caused the ready irq? */
2522 if (irq_mask1_rd & ready_mask) {
2523 handled = 1;
2524 handle_ser_tx_interrupt(info);
2525 }
2526 info += 1;
2527 ready_mask <<= 2;
2528 }
2529 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2530 local_irq_disable();
2531 /* Handle reentered TX interrupt */
2532 irq_mask1_rd = reentered_ready_mask;
2533 }
2534 local_irq_disable();
2535 tx_started = 0;
2536 } else {
2537 unsigned long ready_mask;
2538 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2539 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2540 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2541 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2542 if (ready_mask) {
2543 reentered_ready_mask |= ready_mask;
2544 /* Disable those we are about to handle */
2545 *R_IRQ_MASK1_CLR = ready_mask;
2546 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2547 }
2548 }
2549
2550 local_irq_restore(flags);
2551 return IRQ_RETVAL(handled);
2552 } /* ser_interrupt */
2553 #endif
2554
2555 /*
2556 * -------------------------------------------------------------------
2557 * Here ends the serial interrupt routines.
2558 * -------------------------------------------------------------------
2559 */
2560
2561 /*
2562 * This routine is used to handle the "bottom half" processing for the
2563 * serial driver, known also the "software interrupt" processing.
2564 * This processing is done at the kernel interrupt level, after the
2565 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2566 * is where time-consuming activities which can not be done in the
2567 * interrupt driver proper are done; the interrupt driver schedules
2568 * them using rs_sched_event(), and they get done here.
2569 */
2570 static void
2571 do_softint(struct work_struct *work)
2572 {
2573 struct e100_serial *info;
2574 struct tty_struct *tty;
2575
2576 info = container_of(work, struct e100_serial, work);
2577
2578 tty = info->port.tty;
2579 if (!tty)
2580 return;
2581
2582 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2583 tty_wakeup(tty);
2584 }
2585
2586 static int
2587 startup(struct e100_serial * info)
2588 {
2589 unsigned long flags;
2590 unsigned long xmit_page;
2591 int i;
2592
2593 xmit_page = get_zeroed_page(GFP_KERNEL);
2594 if (!xmit_page)
2595 return -ENOMEM;
2596
2597 local_irq_save(flags);
2598
2599 /* if it was already initialized, skip this */
2600
2601 if (tty_port_initialized(&info->port)) {
2602 local_irq_restore(flags);
2603 free_page(xmit_page);
2604 return 0;
2605 }
2606
2607 if (info->xmit.buf)
2608 free_page(xmit_page);
2609 else
2610 info->xmit.buf = (unsigned char *) xmit_page;
2611
2612 #ifdef SERIAL_DEBUG_OPEN
2613 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2614 #endif
2615
2616 /*
2617 * Clear the FIFO buffers and disable them
2618 * (they will be reenabled in change_speed())
2619 */
2620
2621 /*
2622 * Reset the DMA channels and make sure their interrupts are cleared
2623 */
2624
2625 if (info->dma_in_enabled) {
2626 info->uses_dma_in = 1;
2627 e100_enable_rxdma_channel(info);
2628
2629 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2630
2631 /* Wait until reset cycle is complete */
2632 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2633 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2634
2635 /* Make sure the irqs are cleared */
2636 *info->iclrintradr =
2637 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2638 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2639 } else {
2640 e100_disable_rxdma_channel(info);
2641 }
2642
2643 if (info->dma_out_enabled) {
2644 info->uses_dma_out = 1;
2645 e100_enable_txdma_channel(info);
2646 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2647
2648 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2649 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2650
2651 /* Make sure the irqs are cleared */
2652 *info->oclrintradr =
2653 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2654 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2655 } else {
2656 e100_disable_txdma_channel(info);
2657 }
2658
2659 if (info->port.tty)
2660 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2661
2662 info->xmit.head = info->xmit.tail = 0;
2663 info->first_recv_buffer = info->last_recv_buffer = NULL;
2664 info->recv_cnt = info->max_recv_cnt = 0;
2665
2666 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2667 info->rec_descr[i].buf = 0;
2668
2669 /*
2670 * and set the speed and other flags of the serial port
2671 * this will start the rx/tx as well
2672 */
2673 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2674 e100_enable_serial_data_irq(info);
2675 #endif
2676 change_speed(info);
2677
2678 /* dummy read to reset any serial errors */
2679
2680 (void)info->ioport[REG_DATA];
2681
2682 /* enable the interrupts */
2683 if (info->uses_dma_out)
2684 e100_enable_txdma_irq(info);
2685
2686 e100_enable_rx_irq(info);
2687
2688 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2689
2690 /* setup the dma input descriptor and start dma */
2691
2692 start_receive(info);
2693
2694 /* for safety, make sure the descriptors last result is 0 bytes written */
2695
2696 info->tr_descr.sw_len = 0;
2697 info->tr_descr.hw_len = 0;
2698 info->tr_descr.status = 0;
2699
2700 /* enable RTS/DTR last */
2701
2702 e100_rts(info, 1);
2703 e100_dtr(info, 1);
2704
2705 tty_port_set_initialized(&info->port, 1);
2706
2707 local_irq_restore(flags);
2708 return 0;
2709 }
2710
2711 /*
2712 * This routine will shutdown a serial port; interrupts are disabled, and
2713 * DTR is dropped if the hangup on close termio flag is on.
2714 */
2715 static void
2716 shutdown(struct e100_serial * info)
2717 {
2718 unsigned long flags;
2719 struct etrax_dma_descr *descr = info->rec_descr;
2720 struct etrax_recv_buffer *buffer;
2721 int i;
2722
2723 /* shut down the transmitter and receiver */
2724 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2725 e100_disable_rx(info);
2726 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2727
2728 /* disable interrupts, reset dma channels */
2729 if (info->uses_dma_in) {
2730 e100_disable_rxdma_irq(info);
2731 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2732 info->uses_dma_in = 0;
2733 } else {
2734 e100_disable_serial_data_irq(info);
2735 }
2736
2737 if (info->uses_dma_out) {
2738 e100_disable_txdma_irq(info);
2739 info->tr_running = 0;
2740 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2741 info->uses_dma_out = 0;
2742 } else {
2743 e100_disable_serial_tx_ready_irq(info);
2744 info->tr_running = 0;
2745 }
2746
2747 if (!tty_port_initialized(&info->port))
2748 return;
2749
2750 #ifdef SERIAL_DEBUG_OPEN
2751 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2752 info->irq);
2753 #endif
2754
2755 local_irq_save(flags);
2756
2757 if (info->xmit.buf) {
2758 free_page((unsigned long)info->xmit.buf);
2759 info->xmit.buf = NULL;
2760 }
2761
2762 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2763 if (descr[i].buf) {
2764 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2765 kfree(buffer);
2766 descr[i].buf = 0;
2767 }
2768
2769 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
2770 /* hang up DTR and RTS if HUPCL is enabled */
2771 e100_dtr(info, 0);
2772 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2773 }
2774
2775 if (info->port.tty)
2776 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2777
2778 tty_port_set_initialized(&info->port, 0);
2779 local_irq_restore(flags);
2780 }
2781
2782
2783 /* change baud rate and other assorted parameters */
2784
2785 static void
2786 change_speed(struct e100_serial *info)
2787 {
2788 unsigned int cflag;
2789 unsigned long xoff;
2790 unsigned long flags;
2791 /* first some safety checks */
2792
2793 if (!info->port.tty)
2794 return;
2795 if (!info->ioport)
2796 return;
2797
2798 cflag = info->port.tty->termios.c_cflag;
2799
2800 /* possibly, the tx/rx should be disabled first to do this safely */
2801
2802 /* change baud-rate and write it to the hardware */
2803 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2804 /* Special baudrate */
2805 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2806 unsigned long alt_source =
2807 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2808 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2809 /* R_ALT_SER_BAUDRATE selects the source */
2810 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2811 (unsigned long)info->baud_base, info->custom_divisor));
2812 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2813 /* 0, 2-65535 (0=65536) */
2814 u16 divisor = info->custom_divisor;
2815 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2816 /* baudrate is 3.125MHz/custom_divisor */
2817 alt_source =
2818 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2819 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2820 alt_source = 0x11;
2821 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2822 *R_SERIAL_PRESCALE = divisor;
2823 info->baud = SERIAL_PRESCALE_BASE/divisor;
2824 }
2825 else
2826 {
2827 /* Bad baudbase, we don't support using timer0
2828 * for baudrate.
2829 */
2830 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2831 (unsigned long)info->baud_base, info->custom_divisor);
2832 }
2833 r_alt_ser_baudrate_shadow &= ~mask;
2834 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2835 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2836 } else {
2837 /* Normal baudrate */
2838 /* Make sure we use normal baudrate */
2839 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2840 unsigned long alt_source =
2841 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2842 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2843 r_alt_ser_baudrate_shadow &= ~mask;
2844 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2845 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2846
2847 info->baud = cflag_to_baud(cflag);
2848 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
2849 }
2850
2851 /* start with default settings and then fill in changes */
2852 local_irq_save(flags);
2853 /* 8 bit, no/even parity */
2854 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
2855 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
2856 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
2857
2858 /* 8 bit, no/even parity, 1 stop bit, no cts */
2859 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
2860 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
2861 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
2862 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
2863 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
2864
2865 if ((cflag & CSIZE) == CS7) {
2866 /* set 7 bit mode */
2867 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
2868 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
2869 }
2870
2871 if (cflag & CSTOPB) {
2872 /* set 2 stop bit mode */
2873 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
2874 }
2875
2876 if (cflag & PARENB) {
2877 /* enable parity */
2878 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
2879 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
2880 }
2881
2882 if (cflag & CMSPAR) {
2883 /* enable stick parity, PARODD mean Mark which matches ETRAX */
2884 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
2885 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
2886 }
2887 if (cflag & PARODD) {
2888 /* set odd parity (or Mark if CMSPAR) */
2889 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
2890 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
2891 }
2892
2893 if (cflag & CRTSCTS) {
2894 /* enable automatic CTS handling */
2895 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
2896 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
2897 }
2898
2899 /* make sure the tx and rx are enabled */
2900
2901 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
2902 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
2903
2904 /* actually write the control regs to the hardware */
2905
2906 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
2907 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
2908 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
2909 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
2910 if (info->port.tty->termios.c_iflag & IXON ) {
2911 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
2912 STOP_CHAR(info->port.tty)));
2913 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
2914 }
2915
2916 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
2917 local_irq_restore(flags);
2918
2919 update_char_time(info);
2920
2921 } /* change_speed */
2922
2923 /* start transmitting chars NOW */
2924
2925 static void
2926 rs_flush_chars(struct tty_struct *tty)
2927 {
2928 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2929 unsigned long flags;
2930
2931 if (info->tr_running ||
2932 info->xmit.head == info->xmit.tail ||
2933 tty->stopped ||
2934 !info->xmit.buf)
2935 return;
2936
2937 #ifdef SERIAL_DEBUG_FLOW
2938 printk("rs_flush_chars\n");
2939 #endif
2940
2941 /* this protection might not exactly be necessary here */
2942
2943 local_irq_save(flags);
2944 start_transmit(info);
2945 local_irq_restore(flags);
2946 }
2947
2948 static int rs_raw_write(struct tty_struct *tty,
2949 const unsigned char *buf, int count)
2950 {
2951 int c, ret = 0;
2952 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2953 unsigned long flags;
2954
2955 /* first some sanity checks */
2956
2957 if (!info->xmit.buf)
2958 return 0;
2959
2960 #ifdef SERIAL_DEBUG_DATA
2961 if (info->line == SERIAL_DEBUG_LINE)
2962 printk("rs_raw_write (%d), status %d\n",
2963 count, info->ioport[REG_STATUS]);
2964 #endif
2965
2966 local_save_flags(flags);
2967 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
2968 DFLOW(DEBUG_LOG(info->line, "ldisc\n"));
2969
2970
2971 /* The local_irq_disable/restore_flags pairs below are needed
2972 * because the DMA interrupt handler moves the info->xmit values.
2973 * the memcpy needs to be in the critical region unfortunately,
2974 * because we need to read xmit values, memcpy, write xmit values
2975 * in one atomic operation... this could perhaps be avoided by
2976 * more clever design.
2977 */
2978 local_irq_disable();
2979 while (count) {
2980 c = CIRC_SPACE_TO_END(info->xmit.head,
2981 info->xmit.tail,
2982 SERIAL_XMIT_SIZE);
2983
2984 if (count < c)
2985 c = count;
2986 if (c <= 0)
2987 break;
2988
2989 memcpy(info->xmit.buf + info->xmit.head, buf, c);
2990 info->xmit.head = (info->xmit.head + c) &
2991 (SERIAL_XMIT_SIZE-1);
2992 buf += c;
2993 count -= c;
2994 ret += c;
2995 }
2996 local_irq_restore(flags);
2997
2998 /* enable transmitter if not running, unless the tty is stopped
2999 * this does not need IRQ protection since if tr_running == 0
3000 * the IRQ's are not running anyway for this port.
3001 */
3002 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3003
3004 if (info->xmit.head != info->xmit.tail &&
3005 !tty->stopped &&
3006 !info->tr_running) {
3007 start_transmit(info);
3008 }
3009
3010 return ret;
3011 } /* raw_raw_write() */
3012
3013 static int
3014 rs_write(struct tty_struct *tty,
3015 const unsigned char *buf, int count)
3016 {
3017 #if defined(CONFIG_ETRAX_RS485)
3018 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3019
3020 if (info->rs485.flags & SER_RS485_ENABLED)
3021 {
3022 /* If we are in RS-485 mode, we need to toggle RTS and disable
3023 * the receiver before initiating a DMA transfer
3024 */
3025 #ifdef CONFIG_ETRAX_FAST_TIMER
3026 /* Abort any started timer */
3027 fast_timers_rs485[info->line].function = NULL;
3028 del_fast_timer(&fast_timers_rs485[info->line]);
3029 #endif
3030 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3031 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3032 e100_disable_rx(info);
3033 e100_enable_rx_irq(info);
3034 #endif
3035 if (info->rs485.delay_rts_before_send > 0)
3036 msleep(info->rs485.delay_rts_before_send);
3037 }
3038 #endif /* CONFIG_ETRAX_RS485 */
3039
3040 count = rs_raw_write(tty, buf, count);
3041
3042 #if defined(CONFIG_ETRAX_RS485)
3043 if (info->rs485.flags & SER_RS485_ENABLED)
3044 {
3045 unsigned int val;
3046 /* If we are in RS-485 mode the following has to be done:
3047 * wait until DMA is ready
3048 * wait on transmit shift register
3049 * toggle RTS
3050 * enable the receiver
3051 */
3052
3053 /* Sleep until all sent */
3054 tty_wait_until_sent(tty, 0);
3055 #ifdef CONFIG_ETRAX_FAST_TIMER
3056 /* Now sleep a little more so that shift register is empty */
3057 schedule_usleep(info->char_time_usec * 2);
3058 #endif
3059 /* wait on transmit shift register */
3060 do{
3061 get_lsr_info(info, &val);
3062 }while (!(val & TIOCSER_TEMT));
3063
3064 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3065
3066 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3067 e100_enable_rx(info);
3068 e100_enable_rxdma_irq(info);
3069 #endif
3070 }
3071 #endif /* CONFIG_ETRAX_RS485 */
3072
3073 return count;
3074 } /* rs_write */
3075
3076
3077 /* how much space is available in the xmit buffer? */
3078
3079 static int
3080 rs_write_room(struct tty_struct *tty)
3081 {
3082 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3083
3084 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3085 }
3086
3087 /* How many chars are in the xmit buffer?
3088 * This does not include any chars in the transmitter FIFO.
3089 * Use wait_until_sent for waiting for FIFO drain.
3090 */
3091
3092 static int
3093 rs_chars_in_buffer(struct tty_struct *tty)
3094 {
3095 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3096
3097 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3098 }
3099
3100 /* discard everything in the xmit buffer */
3101
3102 static void
3103 rs_flush_buffer(struct tty_struct *tty)
3104 {
3105 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3106 unsigned long flags;
3107
3108 local_irq_save(flags);
3109 info->xmit.head = info->xmit.tail = 0;
3110 local_irq_restore(flags);
3111
3112 tty_wakeup(tty);
3113 }
3114
3115 /*
3116 * This function is used to send a high-priority XON/XOFF character to
3117 * the device
3118 *
3119 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3120 * but we do it in handle_ser_tx_interrupt().
3121 * We disable DMA channel and enable tx ready interrupt and write the
3122 * character when possible.
3123 */
3124 static void rs_send_xchar(struct tty_struct *tty, char ch)
3125 {
3126 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3127 unsigned long flags;
3128 local_irq_save(flags);
3129 if (info->uses_dma_out) {
3130 /* Put the DMA on hold and disable the channel */
3131 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3132 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3133 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3134 e100_disable_txdma_channel(info);
3135 }
3136
3137 /* Must make sure transmitter is not stopped before we can transmit */
3138 if (tty->stopped)
3139 rs_start(tty);
3140
3141 /* Enable manual transmit interrupt and send from there */
3142 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3143 info->x_char = ch;
3144 e100_enable_serial_tx_ready_irq(info);
3145 local_irq_restore(flags);
3146 }
3147
3148 /*
3149 * ------------------------------------------------------------
3150 * rs_throttle()
3151 *
3152 * This routine is called by the upper-layer tty layer to signal that
3153 * incoming characters should be throttled.
3154 * ------------------------------------------------------------
3155 */
3156 static void
3157 rs_throttle(struct tty_struct * tty)
3158 {
3159 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3160 #ifdef SERIAL_DEBUG_THROTTLE
3161 printk("throttle %s ....\n", tty_name(tty));
3162 #endif
3163 DFLOW(DEBUG_LOG(info->line,"rs_throttle\n"));
3164
3165 /* Do RTS before XOFF since XOFF might take some time */
3166 if (C_CRTSCTS(tty)) {
3167 /* Turn off RTS line */
3168 e100_rts(info, 0);
3169 }
3170 if (I_IXOFF(tty))
3171 rs_send_xchar(tty, STOP_CHAR(tty));
3172
3173 }
3174
3175 static void
3176 rs_unthrottle(struct tty_struct * tty)
3177 {
3178 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3179 #ifdef SERIAL_DEBUG_THROTTLE
3180 printk("unthrottle %s ....\n", tty_name(tty));
3181 #endif
3182 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc\n"));
3183 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3184 /* Do RTS before XOFF since XOFF might take some time */
3185 if (C_CRTSCTS(tty)) {
3186 /* Assert RTS line */
3187 e100_rts(info, 1);
3188 }
3189
3190 if (I_IXOFF(tty)) {
3191 if (info->x_char)
3192 info->x_char = 0;
3193 else
3194 rs_send_xchar(tty, START_CHAR(tty));
3195 }
3196
3197 }
3198
3199 /*
3200 * ------------------------------------------------------------
3201 * rs_ioctl() and friends
3202 * ------------------------------------------------------------
3203 */
3204
3205 static int
3206 get_serial_info(struct e100_serial * info,
3207 struct serial_struct * retinfo)
3208 {
3209 struct serial_struct tmp;
3210
3211 /* this is all probably wrong, there are a lot of fields
3212 * here that we don't have in e100_serial and maybe we
3213 * should set them to something else than 0.
3214 */
3215
3216 memset(&tmp, 0, sizeof(tmp));
3217 tmp.type = info->type;
3218 tmp.line = info->line;
3219 tmp.port = (int)info->ioport;
3220 tmp.irq = info->irq;
3221 tmp.flags = info->port.flags;
3222 tmp.baud_base = info->baud_base;
3223 tmp.close_delay = info->port.close_delay;
3224 tmp.closing_wait = info->port.closing_wait;
3225 tmp.custom_divisor = info->custom_divisor;
3226 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3227 return -EFAULT;
3228 return 0;
3229 }
3230
3231 static int
3232 set_serial_info(struct e100_serial *info,
3233 struct serial_struct *new_info)
3234 {
3235 struct serial_struct new_serial;
3236 struct e100_serial old_info;
3237 int retval = 0;
3238
3239 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3240 return -EFAULT;
3241
3242 old_info = *info;
3243
3244 if (!capable(CAP_SYS_ADMIN)) {
3245 if ((new_serial.type != info->type) ||
3246 (new_serial.close_delay != info->port.close_delay) ||
3247 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3248 (info->port.flags & ~ASYNC_USR_MASK)))
3249 return -EPERM;
3250 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
3251 (new_serial.flags & ASYNC_USR_MASK));
3252 goto check_and_exit;
3253 }
3254
3255 if (info->port.count > 1)
3256 return -EBUSY;
3257
3258 /*
3259 * OK, past this point, all the error checking has been done.
3260 * At this point, we start making changes.....
3261 */
3262
3263 info->baud_base = new_serial.baud_base;
3264 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
3265 (new_serial.flags & ASYNC_FLAGS));
3266 info->custom_divisor = new_serial.custom_divisor;
3267 info->type = new_serial.type;
3268 info->port.close_delay = new_serial.close_delay;
3269 info->port.closing_wait = new_serial.closing_wait;
3270 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3271
3272 check_and_exit:
3273 if (tty_port_initialized(&info->port))
3274 change_speed(info);
3275 else
3276 retval = startup(info);
3277 return retval;
3278 }
3279
3280 /*
3281 * get_lsr_info - get line status register info
3282 *
3283 * Purpose: Let user call ioctl() to get info when the UART physically
3284 * is emptied. On bus types like RS485, the transmitter must
3285 * release the bus after transmitting. This must be done when
3286 * the transmit shift register is empty, not be done when the
3287 * transmit holding register is empty. This functionality
3288 * allows an RS485 driver to be written in user space.
3289 */
3290 static int
3291 get_lsr_info(struct e100_serial * info, unsigned int *value)
3292 {
3293 unsigned int result = TIOCSER_TEMT;
3294 unsigned long curr_time = jiffies;
3295 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3296 unsigned long elapsed_usec =
3297 (curr_time - info->last_tx_active) * 1000000/HZ +
3298 curr_time_usec - info->last_tx_active_usec;
3299
3300 if (info->xmit.head != info->xmit.tail ||
3301 elapsed_usec < 2*info->char_time_usec) {
3302 result = 0;
3303 }
3304
3305 if (copy_to_user(value, &result, sizeof(int)))
3306 return -EFAULT;
3307 return 0;
3308 }
3309
3310 #ifdef SERIAL_DEBUG_IO
3311 struct state_str
3312 {
3313 int state;
3314 const char *str;
3315 };
3316
3317 const struct state_str control_state_str[] = {
3318 {TIOCM_DTR, "DTR" },
3319 {TIOCM_RTS, "RTS"},
3320 {TIOCM_ST, "ST?" },
3321 {TIOCM_SR, "SR?" },
3322 {TIOCM_CTS, "CTS" },
3323 {TIOCM_CD, "CD" },
3324 {TIOCM_RI, "RI" },
3325 {TIOCM_DSR, "DSR" },
3326 {0, NULL }
3327 };
3328
3329 char *get_control_state_str(int MLines, char *s)
3330 {
3331 int i = 0;
3332
3333 s[0]='\0';
3334 while (control_state_str[i].str != NULL) {
3335 if (MLines & control_state_str[i].state) {
3336 if (s[0] != '\0') {
3337 strcat(s, ", ");
3338 }
3339 strcat(s, control_state_str[i].str);
3340 }
3341 i++;
3342 }
3343 return s;
3344 }
3345 #endif
3346
3347 static int
3348 rs_break(struct tty_struct *tty, int break_state)
3349 {
3350 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3351 unsigned long flags;
3352
3353 if (!info->ioport)
3354 return -EIO;
3355
3356 local_irq_save(flags);
3357 if (break_state == -1) {
3358 /* Go to manual mode and set the txd pin to 0 */
3359 /* Clear bit 7 (txd) and 6 (tr_enable) */
3360 info->tx_ctrl &= 0x3F;
3361 } else {
3362 /* Set bit 7 (txd) and 6 (tr_enable) */
3363 info->tx_ctrl |= (0x80 | 0x40);
3364 }
3365 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3366 local_irq_restore(flags);
3367 return 0;
3368 }
3369
3370 static int
3371 rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
3372 {
3373 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3374 unsigned long flags;
3375
3376 local_irq_save(flags);
3377
3378 if (clear & TIOCM_RTS)
3379 e100_rts(info, 0);
3380 if (clear & TIOCM_DTR)
3381 e100_dtr(info, 0);
3382 /* Handle FEMALE behaviour */
3383 if (clear & TIOCM_RI)
3384 e100_ri_out(info, 0);
3385 if (clear & TIOCM_CD)
3386 e100_cd_out(info, 0);
3387
3388 if (set & TIOCM_RTS)
3389 e100_rts(info, 1);
3390 if (set & TIOCM_DTR)
3391 e100_dtr(info, 1);
3392 /* Handle FEMALE behaviour */
3393 if (set & TIOCM_RI)
3394 e100_ri_out(info, 1);
3395 if (set & TIOCM_CD)
3396 e100_cd_out(info, 1);
3397
3398 local_irq_restore(flags);
3399 return 0;
3400 }
3401
3402 static int
3403 rs_tiocmget(struct tty_struct *tty)
3404 {
3405 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3406 unsigned int result;
3407 unsigned long flags;
3408
3409 local_irq_save(flags);
3410
3411 result =
3412 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3413 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3414 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3415 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3416 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3417 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3418
3419 local_irq_restore(flags);
3420
3421 #ifdef SERIAL_DEBUG_IO
3422 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3423 info->line, result, result);
3424 {
3425 char s[100];
3426
3427 get_control_state_str(result, s);
3428 printk(KERN_DEBUG "state: %s\n", s);
3429 }
3430 #endif
3431 return result;
3432
3433 }
3434
3435
3436 static int
3437 rs_ioctl(struct tty_struct *tty,
3438 unsigned int cmd, unsigned long arg)
3439 {
3440 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3441
3442 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3443 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3444 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3445 if (tty_io_error(tty))
3446 return -EIO;
3447 }
3448
3449 switch (cmd) {
3450 case TIOCGSERIAL:
3451 return get_serial_info(info,
3452 (struct serial_struct *) arg);
3453 case TIOCSSERIAL:
3454 return set_serial_info(info,
3455 (struct serial_struct *) arg);
3456 case TIOCSERGETLSR: /* Get line status register */
3457 return get_lsr_info(info, (unsigned int *) arg);
3458
3459 case TIOCSERGSTRUCT:
3460 if (copy_to_user((struct e100_serial *) arg,
3461 info, sizeof(struct e100_serial)))
3462 return -EFAULT;
3463 return 0;
3464
3465 #if defined(CONFIG_ETRAX_RS485)
3466 case TIOCSERSETRS485:
3467 {
3468 /* In this ioctl we still use the old structure
3469 * rs485_control for backward compatibility
3470 * (if we use serial_rs485, then old user-level code
3471 * wouldn't work anymore...).
3472 * The use of this ioctl is deprecated: use TIOCSRS485
3473 * instead.*/
3474 struct rs485_control rs485ctrl;
3475 struct serial_rs485 rs485data;
3476 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3477 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3478 sizeof(rs485ctrl)))
3479 return -EFAULT;
3480
3481 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3482 rs485data.flags = 0;
3483
3484 if (rs485ctrl.enabled)
3485 rs485data.flags |= SER_RS485_ENABLED;
3486 else
3487 rs485data.flags &= ~(SER_RS485_ENABLED);
3488
3489 if (rs485ctrl.rts_on_send)
3490 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3491 else
3492 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3493
3494 if (rs485ctrl.rts_after_sent)
3495 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3496 else
3497 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3498
3499 return e100_enable_rs485(tty, &rs485data);
3500 }
3501
3502 case TIOCSRS485:
3503 {
3504 /* This is the new version of TIOCSRS485, with new
3505 * data structure serial_rs485 */
3506 struct serial_rs485 rs485data;
3507 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3508 sizeof(rs485data)))
3509 return -EFAULT;
3510
3511 return e100_enable_rs485(tty, &rs485data);
3512 }
3513
3514 case TIOCGRS485:
3515 {
3516 struct serial_rs485 *rs485data =
3517 &(((struct e100_serial *)tty->driver_data)->rs485);
3518 /* This is the ioctl to get RS485 data from user-space */
3519 if (copy_to_user((struct serial_rs485 *) arg,
3520 rs485data,
3521 sizeof(struct serial_rs485)))
3522 return -EFAULT;
3523 break;
3524 }
3525
3526 case TIOCSERWRRS485:
3527 {
3528 struct rs485_write rs485wr;
3529 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3530 sizeof(rs485wr)))
3531 return -EFAULT;
3532
3533 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3534 }
3535 #endif
3536
3537 default:
3538 return -ENOIOCTLCMD;
3539 }
3540 return 0;
3541 }
3542
3543 static void
3544 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3545 {
3546 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3547
3548 change_speed(info);
3549
3550 /* Handle turning off CRTSCTS */
3551 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
3552 rs_start(tty);
3553
3554 }
3555
3556 /*
3557 * ------------------------------------------------------------
3558 * rs_close()
3559 *
3560 * This routine is called when the serial port gets closed. First, we
3561 * wait for the last remaining data to be sent. Then, we unlink its
3562 * S structure from the interrupt chain if necessary, and we free
3563 * that IRQ if nothing is left in the chain.
3564 * ------------------------------------------------------------
3565 */
3566 static void
3567 rs_close(struct tty_struct *tty, struct file * filp)
3568 {
3569 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3570 unsigned long flags;
3571
3572 if (!info)
3573 return;
3574
3575 /* interrupts are disabled for this entire function */
3576
3577 local_irq_save(flags);
3578
3579 if (tty_hung_up_p(filp)) {
3580 local_irq_restore(flags);
3581 return;
3582 }
3583
3584 #ifdef SERIAL_DEBUG_OPEN
3585 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3586 info->line, info->count);
3587 #endif
3588 if ((tty->count == 1) && (info->port.count != 1)) {
3589 /*
3590 * Uh, oh. tty->count is 1, which means that the tty
3591 * structure will be freed. Info->count should always
3592 * be one in these conditions. If it's greater than
3593 * one, we've got real problems, since it means the
3594 * serial port won't be shutdown.
3595 */
3596 printk(KERN_ERR
3597 "rs_close: bad serial port count; tty->count is 1, "
3598 "info->count is %d\n", info->port.count);
3599 info->port.count = 1;
3600 }
3601 if (--info->port.count < 0) {
3602 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
3603 info->line, info->port.count);
3604 info->port.count = 0;
3605 }
3606 if (info->port.count) {
3607 local_irq_restore(flags);
3608 return;
3609 }
3610 /*
3611 * Now we wait for the transmit buffer to clear; and we notify
3612 * the line discipline to only process XON/XOFF characters.
3613 */
3614 tty->closing = 1;
3615 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
3616 tty_wait_until_sent(tty, info->port.closing_wait);
3617 /*
3618 * At this point we stop accepting input. To do this, we
3619 * disable the serial receiver and the DMA receive interrupt.
3620 */
3621 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3622 e100_disable_serial_data_irq(info);
3623 #endif
3624
3625 e100_disable_rx(info);
3626 e100_disable_rx_irq(info);
3627
3628 if (tty_port_initialized(&info->port)) {
3629 /*
3630 * Before we drop DTR, make sure the UART transmitter
3631 * has completely drained; this is especially
3632 * important as we have a transmit FIFO!
3633 */
3634 rs_wait_until_sent(tty, HZ);
3635 }
3636
3637 shutdown(info);
3638 rs_flush_buffer(tty);
3639 tty_ldisc_flush(tty);
3640 tty->closing = 0;
3641 info->event = 0;
3642 info->port.tty = NULL;
3643 if (info->port.blocked_open) {
3644 if (info->port.close_delay)
3645 schedule_timeout_interruptible(info->port.close_delay);
3646 wake_up_interruptible(&info->port.open_wait);
3647 }
3648 local_irq_restore(flags);
3649 tty_port_set_active(&info->port, 0);
3650
3651 /* port closed */
3652
3653 #if defined(CONFIG_ETRAX_RS485)
3654 if (info->rs485.flags & SER_RS485_ENABLED) {
3655 info->rs485.flags &= ~(SER_RS485_ENABLED);
3656 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3657 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3658 #endif
3659 }
3660 #endif
3661
3662 /*
3663 * Release any allocated DMA irq's.
3664 */
3665 if (info->dma_in_enabled) {
3666 free_irq(info->dma_in_irq_nbr, info);
3667 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3668 info->uses_dma_in = 0;
3669 #ifdef SERIAL_DEBUG_OPEN
3670 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3671 info->dma_in_irq_description);
3672 #endif
3673 }
3674 if (info->dma_out_enabled) {
3675 free_irq(info->dma_out_irq_nbr, info);
3676 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3677 info->uses_dma_out = 0;
3678 #ifdef SERIAL_DEBUG_OPEN
3679 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3680 info->dma_out_irq_description);
3681 #endif
3682 }
3683 }
3684
3685 /*
3686 * rs_wait_until_sent() --- wait until the transmitter is empty
3687 */
3688 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3689 {
3690 unsigned long orig_jiffies;
3691 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3692 unsigned long curr_time = jiffies;
3693 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3694 long elapsed_usec =
3695 (curr_time - info->last_tx_active) * (1000000/HZ) +
3696 curr_time_usec - info->last_tx_active_usec;
3697
3698 /*
3699 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3700 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3701 */
3702 orig_jiffies = jiffies;
3703 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3704 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3705 (elapsed_usec < 2*info->char_time_usec)) {
3706 schedule_timeout_interruptible(1);
3707 if (signal_pending(current))
3708 break;
3709 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3710 break;
3711 curr_time = jiffies;
3712 curr_time_usec = GET_JIFFIES_USEC();
3713 elapsed_usec =
3714 (curr_time - info->last_tx_active) * (1000000/HZ) +
3715 curr_time_usec - info->last_tx_active_usec;
3716 }
3717 set_current_state(TASK_RUNNING);
3718 }
3719
3720 /*
3721 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3722 */
3723 void
3724 rs_hangup(struct tty_struct *tty)
3725 {
3726 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3727
3728 rs_flush_buffer(tty);
3729 shutdown(info);
3730 info->event = 0;
3731 info->port.count = 0;
3732 tty_port_set_active(&info->port, 0);
3733 info->port.tty = NULL;
3734 wake_up_interruptible(&info->port.open_wait);
3735 }
3736
3737 /*
3738 * ------------------------------------------------------------
3739 * rs_open() and friends
3740 * ------------------------------------------------------------
3741 */
3742 static int
3743 block_til_ready(struct tty_struct *tty, struct file * filp,
3744 struct e100_serial *info)
3745 {
3746 DECLARE_WAITQUEUE(wait, current);
3747 unsigned long flags;
3748 int retval;
3749 int do_clocal = 0;
3750
3751 /*
3752 * If non-blocking mode is set, or the port is not enabled,
3753 * then make the check up front and then exit.
3754 */
3755 if ((filp->f_flags & O_NONBLOCK) || tty_io_error(tty)) {
3756 tty_port_set_active(&info->port, 1);
3757 return 0;
3758 }
3759
3760 if (C_CLOCAL(tty))
3761 do_clocal = 1;
3762
3763 /*
3764 * Block waiting for the carrier detect and the line to become
3765 * free (i.e., not in use by the callout). While we are in
3766 * this loop, info->port.count is dropped by one, so that
3767 * rs_close() knows when to free things. We restore it upon
3768 * exit, either normal or abnormal.
3769 */
3770 retval = 0;
3771 add_wait_queue(&info->port.open_wait, &wait);
3772 #ifdef SERIAL_DEBUG_OPEN
3773 printk("block_til_ready before block: ttyS%d, count = %d\n",
3774 info->line, info->port.count);
3775 #endif
3776 local_irq_save(flags);
3777 info->port.count--;
3778 local_irq_restore(flags);
3779 info->port.blocked_open++;
3780 while (1) {
3781 local_irq_save(flags);
3782 /* assert RTS and DTR */
3783 e100_rts(info, 1);
3784 e100_dtr(info, 1);
3785 local_irq_restore(flags);
3786 set_current_state(TASK_INTERRUPTIBLE);
3787 if (tty_hung_up_p(filp) || !tty_port_initialized(&info->port)) {
3788 #ifdef SERIAL_DO_RESTART
3789 if (info->port.flags & ASYNC_HUP_NOTIFY)
3790 retval = -EAGAIN;
3791 else
3792 retval = -ERESTARTSYS;
3793 #else
3794 retval = -EAGAIN;
3795 #endif
3796 break;
3797 }
3798 if (do_clocal)
3799 /* && (do_clocal || DCD_IS_ASSERTED) */
3800 break;
3801 if (signal_pending(current)) {
3802 retval = -ERESTARTSYS;
3803 break;
3804 }
3805 #ifdef SERIAL_DEBUG_OPEN
3806 printk("block_til_ready blocking: ttyS%d, count = %d\n",
3807 info->line, info->port.count);
3808 #endif
3809 tty_unlock(tty);
3810 schedule();
3811 tty_lock(tty);
3812 }
3813 set_current_state(TASK_RUNNING);
3814 remove_wait_queue(&info->port.open_wait, &wait);
3815 if (!tty_hung_up_p(filp))
3816 info->port.count++;
3817 info->port.blocked_open--;
3818 #ifdef SERIAL_DEBUG_OPEN
3819 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
3820 info->line, info->port.count);
3821 #endif
3822 if (retval)
3823 return retval;
3824 tty_port_set_active(&info->port, 1);
3825 return 0;
3826 }
3827
3828 static void
3829 deinit_port(struct e100_serial *info)
3830 {
3831 if (info->dma_out_enabled) {
3832 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3833 free_irq(info->dma_out_irq_nbr, info);
3834 }
3835 if (info->dma_in_enabled) {
3836 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3837 free_irq(info->dma_in_irq_nbr, info);
3838 }
3839 }
3840
3841 /*
3842 * This routine is called whenever a serial port is opened.
3843 * It performs the serial-specific initialization for the tty structure.
3844 */
3845 static int
3846 rs_open(struct tty_struct *tty, struct file * filp)
3847 {
3848 struct e100_serial *info;
3849 int retval;
3850 int allocated_resources = 0;
3851
3852 info = rs_table + tty->index;
3853 if (!info->enabled)
3854 return -ENODEV;
3855
3856 #ifdef SERIAL_DEBUG_OPEN
3857 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
3858 info->port.count);
3859 #endif
3860
3861 info->port.count++;
3862 tty->driver_data = info;
3863 info->port.tty = tty;
3864
3865 info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY);
3866
3867 /*
3868 * If DMA is enabled try to allocate the irq's.
3869 */
3870 if (info->port.count == 1) {
3871 allocated_resources = 1;
3872 if (info->dma_in_enabled) {
3873 if (request_irq(info->dma_in_irq_nbr,
3874 rec_interrupt,
3875 info->dma_in_irq_flags,
3876 info->dma_in_irq_description,
3877 info)) {
3878 printk(KERN_WARNING "DMA irq '%s' busy; "
3879 "falling back to non-DMA mode\n",
3880 info->dma_in_irq_description);
3881 /* Make sure we never try to use DMA in */
3882 /* for the port again. */
3883 info->dma_in_enabled = 0;
3884 } else if (cris_request_dma(info->dma_in_nbr,
3885 info->dma_in_irq_description,
3886 DMA_VERBOSE_ON_ERROR,
3887 info->dma_owner)) {
3888 free_irq(info->dma_in_irq_nbr, info);
3889 printk(KERN_WARNING "DMA '%s' busy; "
3890 "falling back to non-DMA mode\n",
3891 info->dma_in_irq_description);
3892 /* Make sure we never try to use DMA in */
3893 /* for the port again. */
3894 info->dma_in_enabled = 0;
3895 }
3896 #ifdef SERIAL_DEBUG_OPEN
3897 else
3898 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3899 info->dma_in_irq_description);
3900 #endif
3901 }
3902 if (info->dma_out_enabled) {
3903 if (request_irq(info->dma_out_irq_nbr,
3904 tr_interrupt,
3905 info->dma_out_irq_flags,
3906 info->dma_out_irq_description,
3907 info)) {
3908 printk(KERN_WARNING "DMA irq '%s' busy; "
3909 "falling back to non-DMA mode\n",
3910 info->dma_out_irq_description);
3911 /* Make sure we never try to use DMA out */
3912 /* for the port again. */
3913 info->dma_out_enabled = 0;
3914 } else if (cris_request_dma(info->dma_out_nbr,
3915 info->dma_out_irq_description,
3916 DMA_VERBOSE_ON_ERROR,
3917 info->dma_owner)) {
3918 free_irq(info->dma_out_irq_nbr, info);
3919 printk(KERN_WARNING "DMA '%s' busy; "
3920 "falling back to non-DMA mode\n",
3921 info->dma_out_irq_description);
3922 /* Make sure we never try to use DMA out */
3923 /* for the port again. */
3924 info->dma_out_enabled = 0;
3925 }
3926 #ifdef SERIAL_DEBUG_OPEN
3927 else
3928 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3929 info->dma_out_irq_description);
3930 #endif
3931 }
3932 }
3933
3934 /*
3935 * Start up the serial port
3936 */
3937
3938 retval = startup(info);
3939 if (retval) {
3940 if (allocated_resources)
3941 deinit_port(info);
3942
3943 /* FIXME Decrease count info->port.count here too? */
3944 return retval;
3945 }
3946
3947
3948 retval = block_til_ready(tty, filp, info);
3949 if (retval) {
3950 #ifdef SERIAL_DEBUG_OPEN
3951 printk("rs_open returning after block_til_ready with %d\n",
3952 retval);
3953 #endif
3954 if (allocated_resources)
3955 deinit_port(info);
3956
3957 return retval;
3958 }
3959
3960 #ifdef SERIAL_DEBUG_OPEN
3961 printk("rs_open ttyS%d successful...\n", info->line);
3962 #endif
3963 DLOG_INT_TRIG( log_int_pos = 0);
3964
3965 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
3966 info->icount.rx = 0;
3967 } );
3968
3969 return 0;
3970 }
3971
3972 #ifdef CONFIG_PROC_FS
3973 /*
3974 * /proc fs routines....
3975 */
3976
3977 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
3978 {
3979 unsigned long tmp;
3980
3981 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
3982 info->line, (unsigned long)info->ioport, info->irq);
3983
3984 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
3985 seq_printf(m, "\n");
3986 return;
3987 }
3988
3989 seq_printf(m, " baud:%d", info->baud);
3990 seq_printf(m, " tx:%lu rx:%lu",
3991 (unsigned long)info->icount.tx,
3992 (unsigned long)info->icount.rx);
3993 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3994 if (tmp)
3995 seq_printf(m, " tx_pend:%lu/%lu",
3996 (unsigned long)tmp,
3997 (unsigned long)SERIAL_XMIT_SIZE);
3998
3999 seq_printf(m, " rx_pend:%lu/%lu",
4000 (unsigned long)info->recv_cnt,
4001 (unsigned long)info->max_recv_cnt);
4002
4003 #if 1
4004 if (info->port.tty) {
4005 if (info->port.tty->stopped)
4006 seq_printf(m, " stopped:%i",
4007 (int)info->port.tty->stopped);
4008 }
4009
4010 {
4011 unsigned char rstat = info->ioport[REG_STATUS];
4012 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4013 seq_printf(m, " xoff_detect:1");
4014 }
4015
4016 #endif
4017
4018 if (info->icount.frame)
4019 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4020
4021 if (info->icount.parity)
4022 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4023
4024 if (info->icount.brk)
4025 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4026
4027 if (info->icount.overrun)
4028 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4029
4030 /*
4031 * Last thing is the RS-232 status lines
4032 */
4033 if (!E100_RTS_GET(info))
4034 seq_puts(m, "|RTS");
4035 if (!E100_CTS_GET(info))
4036 seq_puts(m, "|CTS");
4037 if (!E100_DTR_GET(info))
4038 seq_puts(m, "|DTR");
4039 if (!E100_DSR_GET(info))
4040 seq_puts(m, "|DSR");
4041 if (!E100_CD_GET(info))
4042 seq_puts(m, "|CD");
4043 if (!E100_RI_GET(info))
4044 seq_puts(m, "|RI");
4045 seq_puts(m, "\n");
4046 }
4047
4048
4049 static int crisv10_proc_show(struct seq_file *m, void *v)
4050 {
4051 int i;
4052
4053 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4054
4055 for (i = 0; i < NR_PORTS; i++) {
4056 if (!rs_table[i].enabled)
4057 continue;
4058 seq_line_info(m, &rs_table[i]);
4059 }
4060 #ifdef DEBUG_LOG_INCLUDED
4061 for (i = 0; i < debug_log_pos; i++) {
4062 seq_printf(m, "%-4i %lu.%lu ",
4063 i, debug_log[i].time,
4064 timer_data_to_ns(debug_log[i].timer_data));
4065 seq_printf(m, debug_log[i].string, debug_log[i].value);
4066 }
4067 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4068 debug_log_pos = 0;
4069 #endif
4070 return 0;
4071 }
4072
4073 static int crisv10_proc_open(struct inode *inode, struct file *file)
4074 {
4075 return single_open(file, crisv10_proc_show, NULL);
4076 }
4077
4078 static const struct file_operations crisv10_proc_fops = {
4079 .owner = THIS_MODULE,
4080 .open = crisv10_proc_open,
4081 .read = seq_read,
4082 .llseek = seq_lseek,
4083 .release = single_release,
4084 };
4085 #endif
4086
4087
4088 /* Finally, routines used to initialize the serial driver. */
4089
4090 static void show_serial_version(void)
4091 {
4092 printk(KERN_INFO
4093 "ETRAX 100LX serial-driver %s, "
4094 "(c) 2000-2004 Axis Communications AB\r\n",
4095 &serial_version[11]); /* "$Revision: x.yy" */
4096 }
4097
4098 /* rs_init inits the driver at boot (using the initcall chain) */
4099
4100 static const struct tty_operations rs_ops = {
4101 .open = rs_open,
4102 .close = rs_close,
4103 .write = rs_write,
4104 .flush_chars = rs_flush_chars,
4105 .write_room = rs_write_room,
4106 .chars_in_buffer = rs_chars_in_buffer,
4107 .flush_buffer = rs_flush_buffer,
4108 .ioctl = rs_ioctl,
4109 .throttle = rs_throttle,
4110 .unthrottle = rs_unthrottle,
4111 .set_termios = rs_set_termios,
4112 .stop = rs_stop,
4113 .start = rs_start,
4114 .hangup = rs_hangup,
4115 .break_ctl = rs_break,
4116 .send_xchar = rs_send_xchar,
4117 .wait_until_sent = rs_wait_until_sent,
4118 .tiocmget = rs_tiocmget,
4119 .tiocmset = rs_tiocmset,
4120 #ifdef CONFIG_PROC_FS
4121 .proc_fops = &crisv10_proc_fops,
4122 #endif
4123 };
4124
4125 static int __init rs_init(void)
4126 {
4127 int i;
4128 struct e100_serial *info;
4129 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4130
4131 if (!driver)
4132 return -ENOMEM;
4133
4134 show_serial_version();
4135
4136 /* Setup the timed flush handler system */
4137
4138 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4139 setup_timer(&flush_timer, timed_flush_handler, 0);
4140 mod_timer(&flush_timer, jiffies + 5);
4141 #endif
4142
4143 #if defined(CONFIG_ETRAX_RS485)
4144 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4145 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
4146 rs485_pa_bit)) {
4147 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4148 "RS485 pin\n");
4149 put_tty_driver(driver);
4150 return -EBUSY;
4151 }
4152 #endif
4153 #endif
4154
4155 /* Initialize the tty_driver structure */
4156
4157 driver->driver_name = "serial";
4158 driver->name = "ttyS";
4159 driver->major = TTY_MAJOR;
4160 driver->minor_start = 64;
4161 driver->type = TTY_DRIVER_TYPE_SERIAL;
4162 driver->subtype = SERIAL_TYPE_NORMAL;
4163 driver->init_termios = tty_std_termios;
4164 driver->init_termios.c_cflag =
4165 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4166 driver->init_termios.c_ispeed = 115200;
4167 driver->init_termios.c_ospeed = 115200;
4168 driver->flags = TTY_DRIVER_REAL_RAW;
4169
4170 tty_set_operations(driver, &rs_ops);
4171 serial_driver = driver;
4172
4173 /* do some initializing for the separate ports */
4174 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4175 if (info->enabled) {
4176 if (cris_request_io_interface(info->io_if,
4177 info->io_if_description)) {
4178 printk(KERN_ERR "ETRAX100LX async serial: "
4179 "Could not allocate IO pins for "
4180 "%s, port %d\n",
4181 info->io_if_description, i);
4182 info->enabled = 0;
4183 }
4184 }
4185 tty_port_init(&info->port);
4186 info->uses_dma_in = 0;
4187 info->uses_dma_out = 0;
4188 info->line = i;
4189 info->port.tty = NULL;
4190 info->type = PORT_ETRAX;
4191 info->tr_running = 0;
4192 info->forced_eop = 0;
4193 info->baud_base = DEF_BAUD_BASE;
4194 info->custom_divisor = 0;
4195 info->x_char = 0;
4196 info->event = 0;
4197 info->xmit.buf = NULL;
4198 info->xmit.tail = info->xmit.head = 0;
4199 info->first_recv_buffer = info->last_recv_buffer = NULL;
4200 info->recv_cnt = info->max_recv_cnt = 0;
4201 info->last_tx_active_usec = 0;
4202 info->last_tx_active = 0;
4203
4204 #if defined(CONFIG_ETRAX_RS485)
4205 /* Set sane defaults */
4206 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4207 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4208 info->rs485.delay_rts_before_send = 0;
4209 info->rs485.flags &= ~(SER_RS485_ENABLED);
4210 #endif
4211 INIT_WORK(&info->work, do_softint);
4212
4213 if (info->enabled) {
4214 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4215 serial_driver->name, info->line, info->ioport);
4216 }
4217 tty_port_link_device(&info->port, driver, i);
4218 }
4219
4220 if (tty_register_driver(driver))
4221 panic("Couldn't register serial driver\n");
4222
4223 #ifdef CONFIG_ETRAX_FAST_TIMER
4224 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4225 memset(fast_timers, 0, sizeof(fast_timers));
4226 #endif
4227 #ifdef CONFIG_ETRAX_RS485
4228 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4229 #endif
4230 fast_timer_init();
4231 #endif
4232
4233 #ifndef CONFIG_ETRAX_KGDB
4234 /* Not needed in simulator. May only complicate stuff. */
4235 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4236
4237 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4238 IRQF_SHARED, "serial ", driver))
4239 panic("%s: Failed to request irq8", __func__);
4240
4241 #endif
4242
4243 return 0;
4244 }
4245
4246 /* this makes sure that rs_init is called during kernel boot */
4247 device_initcall(rs_init);
Linux with added FPC-III support