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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / mpc52xx_uart.c
blob3970d6a9aaca42e4dd459bd483b06599f77884fd
1 /*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32 #undef DEBUG
33
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/tty_flip.h>
38 #include <linux/serial.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/delay.h>
42 #include <linux/io.h>
43 #include <linux/of.h>
44 #include <linux/of_platform.h>
45 #include <linux/clk.h>
46
47 #include <asm/mpc52xx.h>
48 #include <asm/mpc52xx_psc.h>
49
50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
51 #define SUPPORT_SYSRQ
52 #endif
53
54 #include <linux/serial_core.h>
55
56
57 /* We've been assigned a range on the "Low-density serial ports" major */
58 #define SERIAL_PSC_MAJOR 204
59 #define SERIAL_PSC_MINOR 148
60
61
62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
63
64
65 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
71 * the console_init
72 */
73
74 /* lookup table for matching device nodes to index numbers */
75 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
76
77 static void mpc52xx_uart_of_enumerate(void);
78
79
80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
81
82
83 /* Forward declaration of the interruption handling routine */
84 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
86
87 /* ======================================================================== */
88 /* PSC fifo operations for isolating differences between 52xx and 512x */
89 /* ======================================================================== */
90
91 struct psc_ops {
92 void (*fifo_init)(struct uart_port *port);
93 int (*raw_rx_rdy)(struct uart_port *port);
94 int (*raw_tx_rdy)(struct uart_port *port);
95 int (*rx_rdy)(struct uart_port *port);
96 int (*tx_rdy)(struct uart_port *port);
97 int (*tx_empty)(struct uart_port *port);
98 void (*stop_rx)(struct uart_port *port);
99 void (*start_tx)(struct uart_port *port);
100 void (*stop_tx)(struct uart_port *port);
101 void (*rx_clr_irq)(struct uart_port *port);
102 void (*tx_clr_irq)(struct uart_port *port);
103 void (*write_char)(struct uart_port *port, unsigned char c);
104 unsigned char (*read_char)(struct uart_port *port);
105 void (*cw_disable_ints)(struct uart_port *port);
106 void (*cw_restore_ints)(struct uart_port *port);
107 unsigned int (*set_baudrate)(struct uart_port *port,
108 struct ktermios *new,
109 struct ktermios *old);
110 int (*clock_alloc)(struct uart_port *port);
111 void (*clock_relse)(struct uart_port *port);
112 int (*clock)(struct uart_port *port, int enable);
113 int (*fifoc_init)(void);
114 void (*fifoc_uninit)(void);
115 void (*get_irq)(struct uart_port *, struct device_node *);
116 irqreturn_t (*handle_irq)(struct uart_port *port);
117 u16 (*get_status)(struct uart_port *port);
118 u8 (*get_ipcr)(struct uart_port *port);
119 void (*command)(struct uart_port *port, u8 cmd);
120 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
121 void (*set_rts)(struct uart_port *port, int state);
122 void (*enable_ms)(struct uart_port *port);
123 void (*set_sicr)(struct uart_port *port, u32 val);
124 void (*set_imr)(struct uart_port *port, u16 val);
125 u8 (*get_mr1)(struct uart_port *port);
126 };
127
128 /* setting the prescaler and divisor reg is common for all chips */
129 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
130 u16 prescaler, unsigned int divisor)
131 {
132 /* select prescaler */
133 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
134 out_8(&psc->ctur, divisor >> 8);
135 out_8(&psc->ctlr, divisor & 0xff);
136 }
137
138 static u16 mpc52xx_psc_get_status(struct uart_port *port)
139 {
140 return in_be16(&PSC(port)->mpc52xx_psc_status);
141 }
142
143 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
144 {
145 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
146 }
147
148 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
149 {
150 out_8(&PSC(port)->command, cmd);
151 }
152
153 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
154 {
155 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
156 out_8(&PSC(port)->mode, mr1);
157 out_8(&PSC(port)->mode, mr2);
158 }
159
160 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
161 {
162 if (state)
163 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
164 else
165 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
166 }
167
168 static void mpc52xx_psc_enable_ms(struct uart_port *port)
169 {
170 struct mpc52xx_psc __iomem *psc = PSC(port);
171
172 /* clear D_*-bits by reading them */
173 in_8(&psc->mpc52xx_psc_ipcr);
174 /* enable CTS and DCD as IPC interrupts */
175 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
176
177 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
178 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
179 }
180
181 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
182 {
183 out_be32(&PSC(port)->sicr, val);
184 }
185
186 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
187 {
188 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
189 }
190
191 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
192 {
193 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
194 return in_8(&PSC(port)->mode);
195 }
196
197 #ifdef CONFIG_PPC_MPC52xx
198 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
199 static void mpc52xx_psc_fifo_init(struct uart_port *port)
200 {
201 struct mpc52xx_psc __iomem *psc = PSC(port);
202 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
203
204 out_8(&fifo->rfcntl, 0x00);
205 out_be16(&fifo->rfalarm, 0x1ff);
206 out_8(&fifo->tfcntl, 0x07);
207 out_be16(&fifo->tfalarm, 0x80);
208
209 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
210 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
211 }
212
213 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
214 {
215 return in_be16(&PSC(port)->mpc52xx_psc_status)
216 & MPC52xx_PSC_SR_RXRDY;
217 }
218
219 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
220 {
221 return in_be16(&PSC(port)->mpc52xx_psc_status)
222 & MPC52xx_PSC_SR_TXRDY;
223 }
224
225
226 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
227 {
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
229 & port->read_status_mask
230 & MPC52xx_PSC_IMR_RXRDY;
231 }
232
233 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
234 {
235 return in_be16(&PSC(port)->mpc52xx_psc_isr)
236 & port->read_status_mask
237 & MPC52xx_PSC_IMR_TXRDY;
238 }
239
240 static int mpc52xx_psc_tx_empty(struct uart_port *port)
241 {
242 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
243
244 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
245 }
246
247 static void mpc52xx_psc_start_tx(struct uart_port *port)
248 {
249 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
250 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
251 }
252
253 static void mpc52xx_psc_stop_tx(struct uart_port *port)
254 {
255 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
256 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
257 }
258
259 static void mpc52xx_psc_stop_rx(struct uart_port *port)
260 {
261 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
262 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
263 }
264
265 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
266 {
267 }
268
269 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
270 {
271 }
272
273 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
274 {
275 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
276 }
277
278 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
279 {
280 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
281 }
282
283 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
284 {
285 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
286 }
287
288 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
289 {
290 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
291 }
292
293 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
294 struct ktermios *new,
295 struct ktermios *old)
296 {
297 unsigned int baud;
298 unsigned int divisor;
299
300 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
301 baud = uart_get_baud_rate(port, new, old,
302 port->uartclk / (32 * 0xffff) + 1,
303 port->uartclk / 32);
304 divisor = (port->uartclk + 16 * baud) / (32 * baud);
305
306 /* enable the /32 prescaler and set the divisor */
307 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
308 return baud;
309 }
310
311 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
312 struct ktermios *new,
313 struct ktermios *old)
314 {
315 unsigned int baud;
316 unsigned int divisor;
317 u16 prescaler;
318
319 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
320 * ipb freq */
321 baud = uart_get_baud_rate(port, new, old,
322 port->uartclk / (32 * 0xffff) + 1,
323 port->uartclk / 4);
324 divisor = (port->uartclk + 2 * baud) / (4 * baud);
325
326 /* select the proper prescaler and set the divisor
327 * prefer high prescaler for more tolerance on low baudrates */
328 if (divisor > 0xffff || baud <= 115200) {
329 divisor = (divisor + 4) / 8;
330 prescaler = 0xdd00; /* /32 */
331 } else
332 prescaler = 0xff00; /* /4 */
333 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
334 return baud;
335 }
336
337 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
338 {
339 port->irqflags = 0;
340 port->irq = irq_of_parse_and_map(np, 0);
341 }
342
343 /* 52xx specific interrupt handler. The caller holds the port lock */
344 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
345 {
346 return mpc5xxx_uart_process_int(port);
347 }
348
349 static const struct psc_ops mpc52xx_psc_ops = {
350 .fifo_init = mpc52xx_psc_fifo_init,
351 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
352 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
353 .rx_rdy = mpc52xx_psc_rx_rdy,
354 .tx_rdy = mpc52xx_psc_tx_rdy,
355 .tx_empty = mpc52xx_psc_tx_empty,
356 .stop_rx = mpc52xx_psc_stop_rx,
357 .start_tx = mpc52xx_psc_start_tx,
358 .stop_tx = mpc52xx_psc_stop_tx,
359 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
360 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
361 .write_char = mpc52xx_psc_write_char,
362 .read_char = mpc52xx_psc_read_char,
363 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
364 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
365 .set_baudrate = mpc5200_psc_set_baudrate,
366 .get_irq = mpc52xx_psc_get_irq,
367 .handle_irq = mpc52xx_psc_handle_irq,
368 .get_status = mpc52xx_psc_get_status,
369 .get_ipcr = mpc52xx_psc_get_ipcr,
370 .command = mpc52xx_psc_command,
371 .set_mode = mpc52xx_psc_set_mode,
372 .set_rts = mpc52xx_psc_set_rts,
373 .enable_ms = mpc52xx_psc_enable_ms,
374 .set_sicr = mpc52xx_psc_set_sicr,
375 .set_imr = mpc52xx_psc_set_imr,
376 .get_mr1 = mpc52xx_psc_get_mr1,
377 };
378
379 static const struct psc_ops mpc5200b_psc_ops = {
380 .fifo_init = mpc52xx_psc_fifo_init,
381 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
382 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
383 .rx_rdy = mpc52xx_psc_rx_rdy,
384 .tx_rdy = mpc52xx_psc_tx_rdy,
385 .tx_empty = mpc52xx_psc_tx_empty,
386 .stop_rx = mpc52xx_psc_stop_rx,
387 .start_tx = mpc52xx_psc_start_tx,
388 .stop_tx = mpc52xx_psc_stop_tx,
389 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
390 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
391 .write_char = mpc52xx_psc_write_char,
392 .read_char = mpc52xx_psc_read_char,
393 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
394 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
395 .set_baudrate = mpc5200b_psc_set_baudrate,
396 .get_irq = mpc52xx_psc_get_irq,
397 .handle_irq = mpc52xx_psc_handle_irq,
398 .get_status = mpc52xx_psc_get_status,
399 .get_ipcr = mpc52xx_psc_get_ipcr,
400 .command = mpc52xx_psc_command,
401 .set_mode = mpc52xx_psc_set_mode,
402 .set_rts = mpc52xx_psc_set_rts,
403 .enable_ms = mpc52xx_psc_enable_ms,
404 .set_sicr = mpc52xx_psc_set_sicr,
405 .set_imr = mpc52xx_psc_set_imr,
406 .get_mr1 = mpc52xx_psc_get_mr1,
407 };
408
409 #endif /* CONFIG_PPC_MPC52xx */
410
411 #ifdef CONFIG_PPC_MPC512x
412 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
413
414 /* PSC FIFO Controller for mpc512x */
415 struct psc_fifoc {
416 u32 fifoc_cmd;
417 u32 fifoc_int;
418 u32 fifoc_dma;
419 u32 fifoc_axe;
420 u32 fifoc_debug;
421 };
422
423 static struct psc_fifoc __iomem *psc_fifoc;
424 static unsigned int psc_fifoc_irq;
425 static struct clk *psc_fifoc_clk;
426
427 static void mpc512x_psc_fifo_init(struct uart_port *port)
428 {
429 /* /32 prescaler */
430 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
431
432 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
433 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
434 out_be32(&FIFO_512x(port)->txalarm, 1);
435 out_be32(&FIFO_512x(port)->tximr, 0);
436
437 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
438 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
439 out_be32(&FIFO_512x(port)->rxalarm, 1);
440 out_be32(&FIFO_512x(port)->rximr, 0);
441
442 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
443 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
444 }
445
446 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
447 {
448 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
449 }
450
451 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
452 {
453 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
454 }
455
456 static int mpc512x_psc_rx_rdy(struct uart_port *port)
457 {
458 return in_be32(&FIFO_512x(port)->rxsr)
459 & in_be32(&FIFO_512x(port)->rximr)
460 & MPC512x_PSC_FIFO_ALARM;
461 }
462
463 static int mpc512x_psc_tx_rdy(struct uart_port *port)
464 {
465 return in_be32(&FIFO_512x(port)->txsr)
466 & in_be32(&FIFO_512x(port)->tximr)
467 & MPC512x_PSC_FIFO_ALARM;
468 }
469
470 static int mpc512x_psc_tx_empty(struct uart_port *port)
471 {
472 return in_be32(&FIFO_512x(port)->txsr)
473 & MPC512x_PSC_FIFO_EMPTY;
474 }
475
476 static void mpc512x_psc_stop_rx(struct uart_port *port)
477 {
478 unsigned long rx_fifo_imr;
479
480 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
481 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
482 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
483 }
484
485 static void mpc512x_psc_start_tx(struct uart_port *port)
486 {
487 unsigned long tx_fifo_imr;
488
489 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
490 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
491 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
492 }
493
494 static void mpc512x_psc_stop_tx(struct uart_port *port)
495 {
496 unsigned long tx_fifo_imr;
497
498 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
499 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
500 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
501 }
502
503 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
504 {
505 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
506 }
507
508 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
509 {
510 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
511 }
512
513 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
514 {
515 out_8(&FIFO_512x(port)->txdata_8, c);
516 }
517
518 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
519 {
520 return in_8(&FIFO_512x(port)->rxdata_8);
521 }
522
523 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
524 {
525 port->read_status_mask =
526 in_be32(&FIFO_512x(port)->tximr) << 16 |
527 in_be32(&FIFO_512x(port)->rximr);
528 out_be32(&FIFO_512x(port)->tximr, 0);
529 out_be32(&FIFO_512x(port)->rximr, 0);
530 }
531
532 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
533 {
534 out_be32(&FIFO_512x(port)->tximr,
535 (port->read_status_mask >> 16) & 0x7f);
536 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
537 }
538
539 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
540 struct ktermios *new,
541 struct ktermios *old)
542 {
543 unsigned int baud;
544 unsigned int divisor;
545
546 /*
547 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
548 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
549 * Furthermore, it states that "After reset, the prescaler by 10
550 * for the UART mode is selected", but the reset register value is
551 * 0x0000 which means a /32 prescaler. This is wrong.
552 *
553 * In reality using /32 prescaler doesn't work, as it is not supported!
554 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
555 * Chapter 4.1 PSC in UART Mode.
556 * Calculate with a /16 prescaler here.
557 */
558
559 /* uartclk contains the ips freq */
560 baud = uart_get_baud_rate(port, new, old,
561 port->uartclk / (16 * 0xffff) + 1,
562 port->uartclk / 16);
563 divisor = (port->uartclk + 8 * baud) / (16 * baud);
564
565 /* enable the /16 prescaler and set the divisor */
566 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
567 return baud;
568 }
569
570 /* Init PSC FIFO Controller */
571 static int __init mpc512x_psc_fifoc_init(void)
572 {
573 int err;
574 struct device_node *np;
575 struct clk *clk;
576
577 /* default error code, potentially overwritten by clock calls */
578 err = -ENODEV;
579
580 np = of_find_compatible_node(NULL, NULL,
581 "fsl,mpc5121-psc-fifo");
582 if (!np) {
583 pr_err("%s: Can't find FIFOC node\n", __func__);
584 goto out_err;
585 }
586
587 clk = of_clk_get(np, 0);
588 if (IS_ERR(clk)) {
589 /* backwards compat with device trees that lack clock specs */
590 clk = clk_get_sys(np->name, "ipg");
591 }
592 if (IS_ERR(clk)) {
593 pr_err("%s: Can't lookup FIFO clock\n", __func__);
594 err = PTR_ERR(clk);
595 goto out_ofnode_put;
596 }
597 if (clk_prepare_enable(clk)) {
598 pr_err("%s: Can't enable FIFO clock\n", __func__);
599 clk_put(clk);
600 goto out_ofnode_put;
601 }
602 psc_fifoc_clk = clk;
603
604 psc_fifoc = of_iomap(np, 0);
605 if (!psc_fifoc) {
606 pr_err("%s: Can't map FIFOC\n", __func__);
607 goto out_clk_disable;
608 }
609
610 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
611 if (psc_fifoc_irq == 0) {
612 pr_err("%s: Can't get FIFOC irq\n", __func__);
613 goto out_unmap;
614 }
615
616 of_node_put(np);
617 return 0;
618
619 out_unmap:
620 iounmap(psc_fifoc);
621 out_clk_disable:
622 clk_disable_unprepare(psc_fifoc_clk);
623 clk_put(psc_fifoc_clk);
624 out_ofnode_put:
625 of_node_put(np);
626 out_err:
627 return err;
628 }
629
630 static void __exit mpc512x_psc_fifoc_uninit(void)
631 {
632 iounmap(psc_fifoc);
633
634 /* disable the clock, errors are not fatal */
635 if (psc_fifoc_clk) {
636 clk_disable_unprepare(psc_fifoc_clk);
637 clk_put(psc_fifoc_clk);
638 psc_fifoc_clk = NULL;
639 }
640 }
641
642 /* 512x specific interrupt handler. The caller holds the port lock */
643 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
644 {
645 unsigned long fifoc_int;
646 int psc_num;
647
648 /* Read pending PSC FIFOC interrupts */
649 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
650
651 /* Check if it is an interrupt for this port */
652 psc_num = (port->mapbase & 0xf00) >> 8;
653 if (test_bit(psc_num, &fifoc_int) ||
654 test_bit(psc_num + 16, &fifoc_int))
655 return mpc5xxx_uart_process_int(port);
656
657 return IRQ_NONE;
658 }
659
660 static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
661 static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
662
663 /* called from within the .request_port() callback (allocation) */
664 static int mpc512x_psc_alloc_clock(struct uart_port *port)
665 {
666 int psc_num;
667 struct clk *clk;
668 int err;
669
670 psc_num = (port->mapbase & 0xf00) >> 8;
671
672 clk = devm_clk_get(port->dev, "mclk");
673 if (IS_ERR(clk)) {
674 dev_err(port->dev, "Failed to get MCLK!\n");
675 err = PTR_ERR(clk);
676 goto out_err;
677 }
678 err = clk_prepare_enable(clk);
679 if (err) {
680 dev_err(port->dev, "Failed to enable MCLK!\n");
681 goto out_err;
682 }
683 psc_mclk_clk[psc_num] = clk;
684
685 clk = devm_clk_get(port->dev, "ipg");
686 if (IS_ERR(clk)) {
687 dev_err(port->dev, "Failed to get IPG clock!\n");
688 err = PTR_ERR(clk);
689 goto out_err;
690 }
691 err = clk_prepare_enable(clk);
692 if (err) {
693 dev_err(port->dev, "Failed to enable IPG clock!\n");
694 goto out_err;
695 }
696 psc_ipg_clk[psc_num] = clk;
697
698 return 0;
699
700 out_err:
701 if (psc_mclk_clk[psc_num]) {
702 clk_disable_unprepare(psc_mclk_clk[psc_num]);
703 psc_mclk_clk[psc_num] = NULL;
704 }
705 if (psc_ipg_clk[psc_num]) {
706 clk_disable_unprepare(psc_ipg_clk[psc_num]);
707 psc_ipg_clk[psc_num] = NULL;
708 }
709 return err;
710 }
711
712 /* called from within the .release_port() callback (release) */
713 static void mpc512x_psc_relse_clock(struct uart_port *port)
714 {
715 int psc_num;
716 struct clk *clk;
717
718 psc_num = (port->mapbase & 0xf00) >> 8;
719 clk = psc_mclk_clk[psc_num];
720 if (clk) {
721 clk_disable_unprepare(clk);
722 psc_mclk_clk[psc_num] = NULL;
723 }
724 if (psc_ipg_clk[psc_num]) {
725 clk_disable_unprepare(psc_ipg_clk[psc_num]);
726 psc_ipg_clk[psc_num] = NULL;
727 }
728 }
729
730 /* implementation of the .clock() callback (enable/disable) */
731 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
732 {
733 int psc_num;
734 struct clk *psc_clk;
735 int ret;
736
737 if (uart_console(port))
738 return 0;
739
740 psc_num = (port->mapbase & 0xf00) >> 8;
741 psc_clk = psc_mclk_clk[psc_num];
742 if (!psc_clk) {
743 dev_err(port->dev, "Failed to get PSC clock entry!\n");
744 return -ENODEV;
745 }
746
747 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
748 if (enable) {
749 ret = clk_enable(psc_clk);
750 if (ret)
751 dev_err(port->dev, "Failed to enable MCLK!\n");
752 return ret;
753 } else {
754 clk_disable(psc_clk);
755 return 0;
756 }
757 }
758
759 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
760 {
761 port->irqflags = IRQF_SHARED;
762 port->irq = psc_fifoc_irq;
763 }
764 #endif
765
766 #ifdef CONFIG_PPC_MPC512x
767
768 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
769 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
770
771 static void mpc5125_psc_fifo_init(struct uart_port *port)
772 {
773 /* /32 prescaler */
774 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
775
776 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
777 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
778 out_be32(&FIFO_5125(port)->txalarm, 1);
779 out_be32(&FIFO_5125(port)->tximr, 0);
780
781 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
782 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
783 out_be32(&FIFO_5125(port)->rxalarm, 1);
784 out_be32(&FIFO_5125(port)->rximr, 0);
785
786 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
787 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
788 }
789
790 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
791 {
792 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
793 }
794
795 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
796 {
797 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
798 }
799
800 static int mpc5125_psc_rx_rdy(struct uart_port *port)
801 {
802 return in_be32(&FIFO_5125(port)->rxsr) &
803 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
804 }
805
806 static int mpc5125_psc_tx_rdy(struct uart_port *port)
807 {
808 return in_be32(&FIFO_5125(port)->txsr) &
809 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
810 }
811
812 static int mpc5125_psc_tx_empty(struct uart_port *port)
813 {
814 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
815 }
816
817 static void mpc5125_psc_stop_rx(struct uart_port *port)
818 {
819 unsigned long rx_fifo_imr;
820
821 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
822 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
823 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
824 }
825
826 static void mpc5125_psc_start_tx(struct uart_port *port)
827 {
828 unsigned long tx_fifo_imr;
829
830 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
831 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
832 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
833 }
834
835 static void mpc5125_psc_stop_tx(struct uart_port *port)
836 {
837 unsigned long tx_fifo_imr;
838
839 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
840 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
841 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
842 }
843
844 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
845 {
846 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
847 }
848
849 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
850 {
851 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
852 }
853
854 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
855 {
856 out_8(&FIFO_5125(port)->txdata_8, c);
857 }
858
859 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
860 {
861 return in_8(&FIFO_5125(port)->rxdata_8);
862 }
863
864 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
865 {
866 port->read_status_mask =
867 in_be32(&FIFO_5125(port)->tximr) << 16 |
868 in_be32(&FIFO_5125(port)->rximr);
869 out_be32(&FIFO_5125(port)->tximr, 0);
870 out_be32(&FIFO_5125(port)->rximr, 0);
871 }
872
873 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
874 {
875 out_be32(&FIFO_5125(port)->tximr,
876 (port->read_status_mask >> 16) & 0x7f);
877 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
878 }
879
880 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
881 u8 prescaler, unsigned int divisor)
882 {
883 /* select prescaler */
884 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
885 out_8(&psc->ctur, divisor >> 8);
886 out_8(&psc->ctlr, divisor & 0xff);
887 }
888
889 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
890 struct ktermios *new,
891 struct ktermios *old)
892 {
893 unsigned int baud;
894 unsigned int divisor;
895
896 /*
897 * Calculate with a /16 prescaler here.
898 */
899
900 /* uartclk contains the ips freq */
901 baud = uart_get_baud_rate(port, new, old,
902 port->uartclk / (16 * 0xffff) + 1,
903 port->uartclk / 16);
904 divisor = (port->uartclk + 8 * baud) / (16 * baud);
905
906 /* enable the /16 prescaler and set the divisor */
907 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
908 return baud;
909 }
910
911 /*
912 * MPC5125 have compatible PSC FIFO Controller.
913 * Special init not needed.
914 */
915 static u16 mpc5125_psc_get_status(struct uart_port *port)
916 {
917 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
918 }
919
920 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
921 {
922 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
923 }
924
925 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
926 {
927 out_8(&PSC_5125(port)->command, cmd);
928 }
929
930 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
931 {
932 out_8(&PSC_5125(port)->mr1, mr1);
933 out_8(&PSC_5125(port)->mr2, mr2);
934 }
935
936 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
937 {
938 if (state & TIOCM_RTS)
939 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
940 else
941 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
942 }
943
944 static void mpc5125_psc_enable_ms(struct uart_port *port)
945 {
946 struct mpc5125_psc __iomem *psc = PSC_5125(port);
947
948 /* clear D_*-bits by reading them */
949 in_8(&psc->mpc52xx_psc_ipcr);
950 /* enable CTS and DCD as IPC interrupts */
951 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
952
953 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
954 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
955 }
956
957 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
958 {
959 out_be32(&PSC_5125(port)->sicr, val);
960 }
961
962 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
963 {
964 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
965 }
966
967 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
968 {
969 return in_8(&PSC_5125(port)->mr1);
970 }
971
972 static const struct psc_ops mpc5125_psc_ops = {
973 .fifo_init = mpc5125_psc_fifo_init,
974 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
975 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
976 .rx_rdy = mpc5125_psc_rx_rdy,
977 .tx_rdy = mpc5125_psc_tx_rdy,
978 .tx_empty = mpc5125_psc_tx_empty,
979 .stop_rx = mpc5125_psc_stop_rx,
980 .start_tx = mpc5125_psc_start_tx,
981 .stop_tx = mpc5125_psc_stop_tx,
982 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
983 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
984 .write_char = mpc5125_psc_write_char,
985 .read_char = mpc5125_psc_read_char,
986 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
987 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
988 .set_baudrate = mpc5125_psc_set_baudrate,
989 .clock_alloc = mpc512x_psc_alloc_clock,
990 .clock_relse = mpc512x_psc_relse_clock,
991 .clock = mpc512x_psc_endis_clock,
992 .fifoc_init = mpc512x_psc_fifoc_init,
993 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
994 .get_irq = mpc512x_psc_get_irq,
995 .handle_irq = mpc512x_psc_handle_irq,
996 .get_status = mpc5125_psc_get_status,
997 .get_ipcr = mpc5125_psc_get_ipcr,
998 .command = mpc5125_psc_command,
999 .set_mode = mpc5125_psc_set_mode,
1000 .set_rts = mpc5125_psc_set_rts,
1001 .enable_ms = mpc5125_psc_enable_ms,
1002 .set_sicr = mpc5125_psc_set_sicr,
1003 .set_imr = mpc5125_psc_set_imr,
1004 .get_mr1 = mpc5125_psc_get_mr1,
1005 };
1006
1007 static const struct psc_ops mpc512x_psc_ops = {
1008 .fifo_init = mpc512x_psc_fifo_init,
1009 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1010 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1011 .rx_rdy = mpc512x_psc_rx_rdy,
1012 .tx_rdy = mpc512x_psc_tx_rdy,
1013 .tx_empty = mpc512x_psc_tx_empty,
1014 .stop_rx = mpc512x_psc_stop_rx,
1015 .start_tx = mpc512x_psc_start_tx,
1016 .stop_tx = mpc512x_psc_stop_tx,
1017 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1018 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1019 .write_char = mpc512x_psc_write_char,
1020 .read_char = mpc512x_psc_read_char,
1021 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1022 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1023 .set_baudrate = mpc512x_psc_set_baudrate,
1024 .clock_alloc = mpc512x_psc_alloc_clock,
1025 .clock_relse = mpc512x_psc_relse_clock,
1026 .clock = mpc512x_psc_endis_clock,
1027 .fifoc_init = mpc512x_psc_fifoc_init,
1028 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1029 .get_irq = mpc512x_psc_get_irq,
1030 .handle_irq = mpc512x_psc_handle_irq,
1031 .get_status = mpc52xx_psc_get_status,
1032 .get_ipcr = mpc52xx_psc_get_ipcr,
1033 .command = mpc52xx_psc_command,
1034 .set_mode = mpc52xx_psc_set_mode,
1035 .set_rts = mpc52xx_psc_set_rts,
1036 .enable_ms = mpc52xx_psc_enable_ms,
1037 .set_sicr = mpc52xx_psc_set_sicr,
1038 .set_imr = mpc52xx_psc_set_imr,
1039 .get_mr1 = mpc52xx_psc_get_mr1,
1040 };
1041 #endif /* CONFIG_PPC_MPC512x */
1042
1043
1044 static const struct psc_ops *psc_ops;
1045
1046 /* ======================================================================== */
1047 /* UART operations */
1048 /* ======================================================================== */
1049
1050 static unsigned int
1051 mpc52xx_uart_tx_empty(struct uart_port *port)
1052 {
1053 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1054 }
1055
1056 static void
1057 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1058 {
1059 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1060 }
1061
1062 static unsigned int
1063 mpc52xx_uart_get_mctrl(struct uart_port *port)
1064 {
1065 unsigned int ret = TIOCM_DSR;
1066 u8 status = psc_ops->get_ipcr(port);
1067
1068 if (!(status & MPC52xx_PSC_CTS))
1069 ret |= TIOCM_CTS;
1070 if (!(status & MPC52xx_PSC_DCD))
1071 ret |= TIOCM_CAR;
1072
1073 return ret;
1074 }
1075
1076 static void
1077 mpc52xx_uart_stop_tx(struct uart_port *port)
1078 {
1079 /* port->lock taken by caller */
1080 psc_ops->stop_tx(port);
1081 }
1082
1083 static void
1084 mpc52xx_uart_start_tx(struct uart_port *port)
1085 {
1086 /* port->lock taken by caller */
1087 psc_ops->start_tx(port);
1088 }
1089
1090 static void
1091 mpc52xx_uart_stop_rx(struct uart_port *port)
1092 {
1093 /* port->lock taken by caller */
1094 psc_ops->stop_rx(port);
1095 }
1096
1097 static void
1098 mpc52xx_uart_enable_ms(struct uart_port *port)
1099 {
1100 psc_ops->enable_ms(port);
1101 }
1102
1103 static void
1104 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1105 {
1106 unsigned long flags;
1107 spin_lock_irqsave(&port->lock, flags);
1108
1109 if (ctl == -1)
1110 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1111 else
1112 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1113
1114 spin_unlock_irqrestore(&port->lock, flags);
1115 }
1116
1117 static int
1118 mpc52xx_uart_startup(struct uart_port *port)
1119 {
1120 int ret;
1121
1122 if (psc_ops->clock) {
1123 ret = psc_ops->clock(port, 1);
1124 if (ret)
1125 return ret;
1126 }
1127
1128 /* Request IRQ */
1129 ret = request_irq(port->irq, mpc52xx_uart_int,
1130 port->irqflags, "mpc52xx_psc_uart", port);
1131 if (ret)
1132 return ret;
1133
1134 /* Reset/activate the port, clear and enable interrupts */
1135 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1136 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1137
1138 /*
1139 * According to Freescale's support the RST_TX command can produce a
1140 * spike on the TX pin. So they recommend to delay "for one character".
1141 * One millisecond should be enough for everyone.
1142 */
1143 msleep(1);
1144
1145 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1146
1147 psc_ops->fifo_init(port);
1148
1149 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1150 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1151
1152 return 0;
1153 }
1154
1155 static void
1156 mpc52xx_uart_shutdown(struct uart_port *port)
1157 {
1158 /* Shut down the port. Leave TX active if on a console port */
1159 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1160 if (!uart_console(port))
1161 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1162
1163 port->read_status_mask = 0;
1164 psc_ops->set_imr(port, port->read_status_mask);
1165
1166 if (psc_ops->clock)
1167 psc_ops->clock(port, 0);
1168
1169 /* Disable interrupt */
1170 psc_ops->cw_disable_ints(port);
1171
1172 /* Release interrupt */
1173 free_irq(port->irq, port);
1174 }
1175
1176 static void
1177 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1178 struct ktermios *old)
1179 {
1180 unsigned long flags;
1181 unsigned char mr1, mr2;
1182 unsigned int j;
1183 unsigned int baud;
1184
1185 /* Prepare what we're gonna write */
1186 mr1 = 0;
1187
1188 switch (new->c_cflag & CSIZE) {
1189 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1190 break;
1191 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1192 break;
1193 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1194 break;
1195 case CS8:
1196 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1197 }
1198
1199 if (new->c_cflag & PARENB) {
1200 if (new->c_cflag & CMSPAR)
1201 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1202
1203 /* With CMSPAR, PARODD also means high parity (same as termios) */
1204 mr1 |= (new->c_cflag & PARODD) ?
1205 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1206 } else {
1207 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1208 }
1209
1210 mr2 = 0;
1211
1212 if (new->c_cflag & CSTOPB)
1213 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1214 else
1215 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1216 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1217 MPC52xx_PSC_MODE_ONE_STOP;
1218
1219 if (new->c_cflag & CRTSCTS) {
1220 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1221 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1222 }
1223
1224 /* Get the lock */
1225 spin_lock_irqsave(&port->lock, flags);
1226
1227 /* Do our best to flush TX & RX, so we don't lose anything */
1228 /* But we don't wait indefinitely ! */
1229 j = 5000000; /* Maximum wait */
1230 /* FIXME Can't receive chars since set_termios might be called at early
1231 * boot for the console, all stuff is not yet ready to receive at that
1232 * time and that just makes the kernel oops */
1233 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1234 while (!mpc52xx_uart_tx_empty(port) && --j)
1235 udelay(1);
1236
1237 if (!j)
1238 printk(KERN_ERR "mpc52xx_uart.c: "
1239 "Unable to flush RX & TX fifos in-time in set_termios."
1240 "Some chars may have been lost.\n");
1241
1242 /* Reset the TX & RX */
1243 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1244 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1245
1246 /* Send new mode settings */
1247 psc_ops->set_mode(port, mr1, mr2);
1248 baud = psc_ops->set_baudrate(port, new, old);
1249
1250 /* Update the per-port timeout */
1251 uart_update_timeout(port, new->c_cflag, baud);
1252
1253 if (UART_ENABLE_MS(port, new->c_cflag))
1254 mpc52xx_uart_enable_ms(port);
1255
1256 /* Reenable TX & RX */
1257 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1258 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1259
1260 /* We're all set, release the lock */
1261 spin_unlock_irqrestore(&port->lock, flags);
1262 }
1263
1264 static const char *
1265 mpc52xx_uart_type(struct uart_port *port)
1266 {
1267 /*
1268 * We keep using PORT_MPC52xx for historic reasons although it applies
1269 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1270 */
1271 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1272 }
1273
1274 static void
1275 mpc52xx_uart_release_port(struct uart_port *port)
1276 {
1277 if (psc_ops->clock_relse)
1278 psc_ops->clock_relse(port);
1279
1280 /* remapped by us ? */
1281 if (port->flags & UPF_IOREMAP) {
1282 iounmap(port->membase);
1283 port->membase = NULL;
1284 }
1285
1286 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1287 }
1288
1289 static int
1290 mpc52xx_uart_request_port(struct uart_port *port)
1291 {
1292 int err;
1293
1294 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1295 port->membase = ioremap(port->mapbase,
1296 sizeof(struct mpc52xx_psc));
1297
1298 if (!port->membase)
1299 return -EINVAL;
1300
1301 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1302 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1303
1304 if (err)
1305 goto out_membase;
1306
1307 if (psc_ops->clock_alloc) {
1308 err = psc_ops->clock_alloc(port);
1309 if (err)
1310 goto out_mapregion;
1311 }
1312
1313 return 0;
1314
1315 out_mapregion:
1316 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1317 out_membase:
1318 if (port->flags & UPF_IOREMAP) {
1319 iounmap(port->membase);
1320 port->membase = NULL;
1321 }
1322 return err;
1323 }
1324
1325 static void
1326 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1327 {
1328 if ((flags & UART_CONFIG_TYPE)
1329 && (mpc52xx_uart_request_port(port) == 0))
1330 port->type = PORT_MPC52xx;
1331 }
1332
1333 static int
1334 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1335 {
1336 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1337 return -EINVAL;
1338
1339 if ((ser->irq != port->irq) ||
1340 (ser->io_type != UPIO_MEM) ||
1341 (ser->baud_base != port->uartclk) ||
1342 (ser->iomem_base != (void *)port->mapbase) ||
1343 (ser->hub6 != 0))
1344 return -EINVAL;
1345
1346 return 0;
1347 }
1348
1349
1350 static struct uart_ops mpc52xx_uart_ops = {
1351 .tx_empty = mpc52xx_uart_tx_empty,
1352 .set_mctrl = mpc52xx_uart_set_mctrl,
1353 .get_mctrl = mpc52xx_uart_get_mctrl,
1354 .stop_tx = mpc52xx_uart_stop_tx,
1355 .start_tx = mpc52xx_uart_start_tx,
1356 .stop_rx = mpc52xx_uart_stop_rx,
1357 .enable_ms = mpc52xx_uart_enable_ms,
1358 .break_ctl = mpc52xx_uart_break_ctl,
1359 .startup = mpc52xx_uart_startup,
1360 .shutdown = mpc52xx_uart_shutdown,
1361 .set_termios = mpc52xx_uart_set_termios,
1362 /* .pm = mpc52xx_uart_pm, Not supported yet */
1363 .type = mpc52xx_uart_type,
1364 .release_port = mpc52xx_uart_release_port,
1365 .request_port = mpc52xx_uart_request_port,
1366 .config_port = mpc52xx_uart_config_port,
1367 .verify_port = mpc52xx_uart_verify_port
1368 };
1369
1370
1371 /* ======================================================================== */
1372 /* Interrupt handling */
1373 /* ======================================================================== */
1374
1375 static inline int
1376 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1377 {
1378 struct tty_port *tport = &port->state->port;
1379 unsigned char ch, flag;
1380 unsigned short status;
1381
1382 /* While we can read, do so ! */
1383 while (psc_ops->raw_rx_rdy(port)) {
1384 /* Get the char */
1385 ch = psc_ops->read_char(port);
1386
1387 /* Handle sysreq char */
1388 #ifdef SUPPORT_SYSRQ
1389 if (uart_handle_sysrq_char(port, ch)) {
1390 port->sysrq = 0;
1391 continue;
1392 }
1393 #endif
1394
1395 /* Store it */
1396
1397 flag = TTY_NORMAL;
1398 port->icount.rx++;
1399
1400 status = psc_ops->get_status(port);
1401
1402 if (status & (MPC52xx_PSC_SR_PE |
1403 MPC52xx_PSC_SR_FE |
1404 MPC52xx_PSC_SR_RB)) {
1405
1406 if (status & MPC52xx_PSC_SR_RB) {
1407 flag = TTY_BREAK;
1408 uart_handle_break(port);
1409 port->icount.brk++;
1410 } else if (status & MPC52xx_PSC_SR_PE) {
1411 flag = TTY_PARITY;
1412 port->icount.parity++;
1413 }
1414 else if (status & MPC52xx_PSC_SR_FE) {
1415 flag = TTY_FRAME;
1416 port->icount.frame++;
1417 }
1418
1419 /* Clear error condition */
1420 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1421
1422 }
1423 tty_insert_flip_char(tport, ch, flag);
1424 if (status & MPC52xx_PSC_SR_OE) {
1425 /*
1426 * Overrun is special, since it's
1427 * reported immediately, and doesn't
1428 * affect the current character
1429 */
1430 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1431 port->icount.overrun++;
1432 }
1433 }
1434
1435 spin_unlock(&port->lock);
1436 tty_flip_buffer_push(tport);
1437 spin_lock(&port->lock);
1438
1439 return psc_ops->raw_rx_rdy(port);
1440 }
1441
1442 static inline int
1443 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1444 {
1445 struct circ_buf *xmit = &port->state->xmit;
1446
1447 /* Process out of band chars */
1448 if (port->x_char) {
1449 psc_ops->write_char(port, port->x_char);
1450 port->icount.tx++;
1451 port->x_char = 0;
1452 return 1;
1453 }
1454
1455 /* Nothing to do ? */
1456 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1457 mpc52xx_uart_stop_tx(port);
1458 return 0;
1459 }
1460
1461 /* Send chars */
1462 while (psc_ops->raw_tx_rdy(port)) {
1463 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1464 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1465 port->icount.tx++;
1466 if (uart_circ_empty(xmit))
1467 break;
1468 }
1469
1470 /* Wake up */
1471 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1472 uart_write_wakeup(port);
1473
1474 /* Maybe we're done after all */
1475 if (uart_circ_empty(xmit)) {
1476 mpc52xx_uart_stop_tx(port);
1477 return 0;
1478 }
1479
1480 return 1;
1481 }
1482
1483 static irqreturn_t
1484 mpc5xxx_uart_process_int(struct uart_port *port)
1485 {
1486 unsigned long pass = ISR_PASS_LIMIT;
1487 unsigned int keepgoing;
1488 u8 status;
1489
1490 /* While we have stuff to do, we continue */
1491 do {
1492 /* If we don't find anything to do, we stop */
1493 keepgoing = 0;
1494
1495 psc_ops->rx_clr_irq(port);
1496 if (psc_ops->rx_rdy(port))
1497 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1498
1499 psc_ops->tx_clr_irq(port);
1500 if (psc_ops->tx_rdy(port))
1501 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1502
1503 status = psc_ops->get_ipcr(port);
1504 if (status & MPC52xx_PSC_D_DCD)
1505 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1506
1507 if (status & MPC52xx_PSC_D_CTS)
1508 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1509
1510 /* Limit number of iteration */
1511 if (!(--pass))
1512 keepgoing = 0;
1513
1514 } while (keepgoing);
1515
1516 return IRQ_HANDLED;
1517 }
1518
1519 static irqreturn_t
1520 mpc52xx_uart_int(int irq, void *dev_id)
1521 {
1522 struct uart_port *port = dev_id;
1523 irqreturn_t ret;
1524
1525 spin_lock(&port->lock);
1526
1527 ret = psc_ops->handle_irq(port);
1528
1529 spin_unlock(&port->lock);
1530
1531 return ret;
1532 }
1533
1534 /* ======================================================================== */
1535 /* Console ( if applicable ) */
1536 /* ======================================================================== */
1537
1538 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1539
1540 static void __init
1541 mpc52xx_console_get_options(struct uart_port *port,
1542 int *baud, int *parity, int *bits, int *flow)
1543 {
1544 unsigned char mr1;
1545
1546 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1547
1548 /* Read the mode registers */
1549 mr1 = psc_ops->get_mr1(port);
1550
1551 /* CT{U,L}R are write-only ! */
1552 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1553
1554 /* Parse them */
1555 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1556 case MPC52xx_PSC_MODE_5_BITS:
1557 *bits = 5;
1558 break;
1559 case MPC52xx_PSC_MODE_6_BITS:
1560 *bits = 6;
1561 break;
1562 case MPC52xx_PSC_MODE_7_BITS:
1563 *bits = 7;
1564 break;
1565 case MPC52xx_PSC_MODE_8_BITS:
1566 default:
1567 *bits = 8;
1568 }
1569
1570 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1571 *parity = 'n';
1572 else
1573 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1574 }
1575
1576 static void
1577 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1578 {
1579 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1580 unsigned int i, j;
1581
1582 /* Disable interrupts */
1583 psc_ops->cw_disable_ints(port);
1584
1585 /* Wait the TX buffer to be empty */
1586 j = 5000000; /* Maximum wait */
1587 while (!mpc52xx_uart_tx_empty(port) && --j)
1588 udelay(1);
1589
1590 /* Write all the chars */
1591 for (i = 0; i < count; i++, s++) {
1592 /* Line return handling */
1593 if (*s == '\n')
1594 psc_ops->write_char(port, '\r');
1595
1596 /* Send the char */
1597 psc_ops->write_char(port, *s);
1598
1599 /* Wait the TX buffer to be empty */
1600 j = 20000; /* Maximum wait */
1601 while (!mpc52xx_uart_tx_empty(port) && --j)
1602 udelay(1);
1603 }
1604
1605 /* Restore interrupt state */
1606 psc_ops->cw_restore_ints(port);
1607 }
1608
1609
1610 static int __init
1611 mpc52xx_console_setup(struct console *co, char *options)
1612 {
1613 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1614 struct device_node *np = mpc52xx_uart_nodes[co->index];
1615 unsigned int uartclk;
1616 struct resource res;
1617 int ret;
1618
1619 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1620 int bits = 8;
1621 int parity = 'n';
1622 int flow = 'n';
1623
1624 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1625 co, co->index, options);
1626
1627 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1628 pr_debug("PSC%x out of range\n", co->index);
1629 return -EINVAL;
1630 }
1631
1632 if (!np) {
1633 pr_debug("PSC%x not found in device tree\n", co->index);
1634 return -EINVAL;
1635 }
1636
1637 pr_debug("Console on ttyPSC%x is %s\n",
1638 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1639
1640 /* Fetch register locations */
1641 ret = of_address_to_resource(np, 0, &res);
1642 if (ret) {
1643 pr_debug("Could not get resources for PSC%x\n", co->index);
1644 return ret;
1645 }
1646
1647 uartclk = mpc5xxx_get_bus_frequency(np);
1648 if (uartclk == 0) {
1649 pr_debug("Could not find uart clock frequency!\n");
1650 return -EINVAL;
1651 }
1652
1653 /* Basic port init. Needed since we use some uart_??? func before
1654 * real init for early access */
1655 spin_lock_init(&port->lock);
1656 port->uartclk = uartclk;
1657 port->ops = &mpc52xx_uart_ops;
1658 port->mapbase = res.start;
1659 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1660 port->irq = irq_of_parse_and_map(np, 0);
1661
1662 if (port->membase == NULL)
1663 return -EINVAL;
1664
1665 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1666 (void *)port->mapbase, port->membase,
1667 port->irq, port->uartclk);
1668
1669 /* Setup the port parameters accoding to options */
1670 if (options)
1671 uart_parse_options(options, &baud, &parity, &bits, &flow);
1672 else
1673 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1674
1675 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1676 baud, bits, parity, flow);
1677
1678 return uart_set_options(port, co, baud, parity, bits, flow);
1679 }
1680
1681
1682 static struct uart_driver mpc52xx_uart_driver;
1683
1684 static struct console mpc52xx_console = {
1685 .name = "ttyPSC",
1686 .write = mpc52xx_console_write,
1687 .device = uart_console_device,
1688 .setup = mpc52xx_console_setup,
1689 .flags = CON_PRINTBUFFER,
1690 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1691 .data = &mpc52xx_uart_driver,
1692 };
1693
1694
1695 static int __init
1696 mpc52xx_console_init(void)
1697 {
1698 mpc52xx_uart_of_enumerate();
1699 register_console(&mpc52xx_console);
1700 return 0;
1701 }
1702
1703 console_initcall(mpc52xx_console_init);
1704
1705 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1706 #else
1707 #define MPC52xx_PSC_CONSOLE NULL
1708 #endif
1709
1710
1711 /* ======================================================================== */
1712 /* UART Driver */
1713 /* ======================================================================== */
1714
1715 static struct uart_driver mpc52xx_uart_driver = {
1716 .driver_name = "mpc52xx_psc_uart",
1717 .dev_name = "ttyPSC",
1718 .major = SERIAL_PSC_MAJOR,
1719 .minor = SERIAL_PSC_MINOR,
1720 .nr = MPC52xx_PSC_MAXNUM,
1721 .cons = MPC52xx_PSC_CONSOLE,
1722 };
1723
1724 /* ======================================================================== */
1725 /* OF Platform Driver */
1726 /* ======================================================================== */
1727
1728 static const struct of_device_id mpc52xx_uart_of_match[] = {
1729 #ifdef CONFIG_PPC_MPC52xx
1730 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1731 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1732 /* binding used by old lite5200 device trees: */
1733 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1734 /* binding used by efika: */
1735 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1736 #endif
1737 #ifdef CONFIG_PPC_MPC512x
1738 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1739 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1740 #endif
1741 {},
1742 };
1743
1744 static int mpc52xx_uart_of_probe(struct platform_device *op)
1745 {
1746 int idx = -1;
1747 unsigned int uartclk;
1748 struct uart_port *port = NULL;
1749 struct resource res;
1750 int ret;
1751
1752 /* Check validity & presence */
1753 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1754 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1755 break;
1756 if (idx >= MPC52xx_PSC_MAXNUM)
1757 return -EINVAL;
1758 pr_debug("Found %s assigned to ttyPSC%x\n",
1759 mpc52xx_uart_nodes[idx]->full_name, idx);
1760
1761 /* set the uart clock to the input clock of the psc, the different
1762 * prescalers are taken into account in the set_baudrate() methods
1763 * of the respective chip */
1764 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1765 if (uartclk == 0) {
1766 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1767 return -EINVAL;
1768 }
1769
1770 /* Init the port structure */
1771 port = &mpc52xx_uart_ports[idx];
1772
1773 spin_lock_init(&port->lock);
1774 port->uartclk = uartclk;
1775 port->fifosize = 512;
1776 port->iotype = UPIO_MEM;
1777 port->flags = UPF_BOOT_AUTOCONF |
1778 (uart_console(port) ? 0 : UPF_IOREMAP);
1779 port->line = idx;
1780 port->ops = &mpc52xx_uart_ops;
1781 port->dev = &op->dev;
1782
1783 /* Search for IRQ and mapbase */
1784 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1785 if (ret)
1786 return ret;
1787
1788 port->mapbase = res.start;
1789 if (!port->mapbase) {
1790 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1791 return -EINVAL;
1792 }
1793
1794 psc_ops->get_irq(port, op->dev.of_node);
1795 if (port->irq == 0) {
1796 dev_dbg(&op->dev, "Could not get irq\n");
1797 return -EINVAL;
1798 }
1799
1800 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1801 (void *)port->mapbase, port->irq, port->uartclk);
1802
1803 /* Add the port to the uart sub-system */
1804 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1805 if (ret)
1806 return ret;
1807
1808 platform_set_drvdata(op, (void *)port);
1809 return 0;
1810 }
1811
1812 static int
1813 mpc52xx_uart_of_remove(struct platform_device *op)
1814 {
1815 struct uart_port *port = platform_get_drvdata(op);
1816
1817 if (port)
1818 uart_remove_one_port(&mpc52xx_uart_driver, port);
1819
1820 return 0;
1821 }
1822
1823 #ifdef CONFIG_PM
1824 static int
1825 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1826 {
1827 struct uart_port *port = platform_get_drvdata(op);
1828
1829 if (port)
1830 uart_suspend_port(&mpc52xx_uart_driver, port);
1831
1832 return 0;
1833 }
1834
1835 static int
1836 mpc52xx_uart_of_resume(struct platform_device *op)
1837 {
1838 struct uart_port *port = platform_get_drvdata(op);
1839
1840 if (port)
1841 uart_resume_port(&mpc52xx_uart_driver, port);
1842
1843 return 0;
1844 }
1845 #endif
1846
1847 static void
1848 mpc52xx_uart_of_assign(struct device_node *np)
1849 {
1850 int i;
1851
1852 /* Find the first free PSC number */
1853 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1854 if (mpc52xx_uart_nodes[i] == NULL) {
1855 of_node_get(np);
1856 mpc52xx_uart_nodes[i] = np;
1857 return;
1858 }
1859 }
1860 }
1861
1862 static void
1863 mpc52xx_uart_of_enumerate(void)
1864 {
1865 static int enum_done;
1866 struct device_node *np;
1867 const struct of_device_id *match;
1868 int i;
1869
1870 if (enum_done)
1871 return;
1872
1873 /* Assign index to each PSC in device tree */
1874 for_each_matching_node(np, mpc52xx_uart_of_match) {
1875 match = of_match_node(mpc52xx_uart_of_match, np);
1876 psc_ops = match->data;
1877 mpc52xx_uart_of_assign(np);
1878 }
1879
1880 enum_done = 1;
1881
1882 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1883 if (mpc52xx_uart_nodes[i])
1884 pr_debug("%s assigned to ttyPSC%x\n",
1885 mpc52xx_uart_nodes[i]->full_name, i);
1886 }
1887 }
1888
1889 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1890
1891 static struct platform_driver mpc52xx_uart_of_driver = {
1892 .probe = mpc52xx_uart_of_probe,
1893 .remove = mpc52xx_uart_of_remove,
1894 #ifdef CONFIG_PM
1895 .suspend = mpc52xx_uart_of_suspend,
1896 .resume = mpc52xx_uart_of_resume,
1897 #endif
1898 .driver = {
1899 .name = "mpc52xx-psc-uart",
1900 .of_match_table = mpc52xx_uart_of_match,
1901 },
1902 };
1903
1904
1905 /* ======================================================================== */
1906 /* Module */
1907 /* ======================================================================== */
1908
1909 static int __init
1910 mpc52xx_uart_init(void)
1911 {
1912 int ret;
1913
1914 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1915
1916 ret = uart_register_driver(&mpc52xx_uart_driver);
1917 if (ret) {
1918 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1919 __FILE__, ret);
1920 return ret;
1921 }
1922
1923 mpc52xx_uart_of_enumerate();
1924
1925 /*
1926 * Map the PSC FIFO Controller and init if on MPC512x.
1927 */
1928 if (psc_ops && psc_ops->fifoc_init) {
1929 ret = psc_ops->fifoc_init();
1930 if (ret)
1931 goto err_init;
1932 }
1933
1934 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1935 if (ret) {
1936 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1937 __FILE__, ret);
1938 goto err_reg;
1939 }
1940
1941 return 0;
1942 err_reg:
1943 if (psc_ops && psc_ops->fifoc_uninit)
1944 psc_ops->fifoc_uninit();
1945 err_init:
1946 uart_unregister_driver(&mpc52xx_uart_driver);
1947 return ret;
1948 }
1949
1950 static void __exit
1951 mpc52xx_uart_exit(void)
1952 {
1953 if (psc_ops->fifoc_uninit)
1954 psc_ops->fifoc_uninit();
1955
1956 platform_driver_unregister(&mpc52xx_uart_of_driver);
1957 uart_unregister_driver(&mpc52xx_uart_driver);
1958 }
1959
1960
1961 module_init(mpc52xx_uart_init);
1962 module_exit(mpc52xx_uart_exit);
1963
1964 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1965 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1966 MODULE_LICENSE("GPL");
Linux with added FPC-III support