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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blobf44615fa474de233748b4f72133b8bf3fc272bf5
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/io.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
49 #include <linux/of.h>
50
51 #include <asm/irq.h>
52
53 #include "samsung.h"
54
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 !defined(MODULE)
57
58 extern void printascii(const char *);
59
60 __printf(1, 2)
61 static void dbg(const char *fmt, ...)
62 {
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
67 vscnprintf(buff, sizeof(buff), fmt, va);
68 va_end(va);
69
70 printascii(buff);
71 }
72
73 #else
74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75 #endif
76
77 /* UART name and device definitions */
78
79 #define S3C24XX_SERIAL_NAME "ttySAC"
80 #define S3C24XX_SERIAL_MAJOR 204
81 #define S3C24XX_SERIAL_MINOR 64
82
83 #define S3C24XX_TX_PIO 1
84 #define S3C24XX_TX_DMA 2
85 #define S3C24XX_RX_PIO 1
86 #define S3C24XX_RX_DMA 2
87 /* macros to change one thing to another */
88
89 #define tx_enabled(port) ((port)->unused[0])
90 #define rx_enabled(port) ((port)->unused[1])
91
92 /* flag to ignore all characters coming in */
93 #define RXSTAT_DUMMY_READ (0x10000000)
94
95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96 {
97 return container_of(port, struct s3c24xx_uart_port, port);
98 }
99
100 /* translate a port to the device name */
101
102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103 {
104 return to_platform_device(port->dev)->name;
105 }
106
107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108 {
109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
110 }
111
112 /*
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
116 */
117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118 {
119 return to_ourport(port)->info->type == PORT_S3C6400;
120 }
121
122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
123 {
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143 }
144
145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
146 {
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158 }
159
160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
161 {
162 struct s3c24xx_uart_port *ourport = to_ourport(port);
163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
167
168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
173 else
174 disable_irq_nosync(ourport->tx_irq);
175
176 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
177 dmaengine_pause(dma->tx_chan);
178 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
179 dmaengine_terminate_all(dma->tx_chan);
180 dma_sync_single_for_cpu(ourport->port.dev,
181 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
182 async_tx_ack(dma->tx_desc);
183 count = dma->tx_bytes_requested - state.residue;
184 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
185 port->icount.tx += count;
186 }
187
188 tx_enabled(port) = 0;
189 ourport->tx_in_progress = 0;
190
191 if (port->flags & UPF_CONS_FLOW)
192 s3c24xx_serial_rx_enable(port);
193
194 ourport->tx_mode = 0;
195 }
196
197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
198
199 static void s3c24xx_serial_tx_dma_complete(void *args)
200 {
201 struct s3c24xx_uart_port *ourport = args;
202 struct uart_port *port = &ourport->port;
203 struct circ_buf *xmit = &port->state->xmit;
204 struct s3c24xx_uart_dma *dma = ourport->dma;
205 struct dma_tx_state state;
206 unsigned long flags;
207 int count;
208
209
210 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
211 count = dma->tx_bytes_requested - state.residue;
212 async_tx_ack(dma->tx_desc);
213
214 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
215 dma->tx_size, DMA_TO_DEVICE);
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
220 port->icount.tx += count;
221 ourport->tx_in_progress = 0;
222
223 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
224 uart_write_wakeup(port);
225
226 s3c24xx_serial_start_next_tx(ourport);
227 spin_unlock_irqrestore(&port->lock, flags);
228 }
229
230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
231 {
232 struct uart_port *port = &ourport->port;
233 u32 ucon;
234
235 /* Mask Tx interrupt */
236 if (s3c24xx_serial_has_interrupt_mask(port))
237 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
238 else
239 disable_irq_nosync(ourport->tx_irq);
240
241 /* Enable tx dma mode */
242 ucon = rd_regl(port, S3C2410_UCON);
243 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
244 ucon |= (dma_get_cache_alignment() >= 16) ?
245 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
246 ucon |= S3C64XX_UCON_TXMODE_DMA;
247 wr_regl(port, S3C2410_UCON, ucon);
248
249 ourport->tx_mode = S3C24XX_TX_DMA;
250 }
251
252 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
253 {
254 struct uart_port *port = &ourport->port;
255 u32 ucon, ufcon;
256
257 /* Set ufcon txtrig */
258 ourport->tx_in_progress = S3C24XX_TX_PIO;
259 ufcon = rd_regl(port, S3C2410_UFCON);
260 wr_regl(port, S3C2410_UFCON, ufcon);
261
262 /* Enable tx pio mode */
263 ucon = rd_regl(port, S3C2410_UCON);
264 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
265 ucon |= S3C64XX_UCON_TXMODE_CPU;
266 wr_regl(port, S3C2410_UCON, ucon);
267
268 /* Unmask Tx interrupt */
269 if (s3c24xx_serial_has_interrupt_mask(port))
270 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
271 S3C64XX_UINTM);
272 else
273 enable_irq(ourport->tx_irq);
274
275 ourport->tx_mode = S3C24XX_TX_PIO;
276 }
277
278 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
279 {
280 if (ourport->tx_mode != S3C24XX_TX_PIO)
281 enable_tx_pio(ourport);
282 }
283
284 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
285 unsigned int count)
286 {
287 struct uart_port *port = &ourport->port;
288 struct circ_buf *xmit = &port->state->xmit;
289 struct s3c24xx_uart_dma *dma = ourport->dma;
290
291
292 if (ourport->tx_mode != S3C24XX_TX_DMA)
293 enable_tx_dma(ourport);
294
295 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
296 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
297
298 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
299 dma->tx_size, DMA_TO_DEVICE);
300
301 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
302 dma->tx_transfer_addr, dma->tx_size,
303 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
304 if (!dma->tx_desc) {
305 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
306 return -EIO;
307 }
308
309 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
310 dma->tx_desc->callback_param = ourport;
311 dma->tx_bytes_requested = dma->tx_size;
312
313 ourport->tx_in_progress = S3C24XX_TX_DMA;
314 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
315 dma_async_issue_pending(dma->tx_chan);
316 return 0;
317 }
318
319 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
320 {
321 struct uart_port *port = &ourport->port;
322 struct circ_buf *xmit = &port->state->xmit;
323 unsigned long count;
324
325 /* Get data size up to the end of buffer */
326 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
327
328 if (!count) {
329 s3c24xx_serial_stop_tx(port);
330 return;
331 }
332
333 if (!ourport->dma || !ourport->dma->tx_chan ||
334 count < ourport->min_dma_size ||
335 xmit->tail & (dma_get_cache_alignment() - 1))
336 s3c24xx_serial_start_tx_pio(ourport);
337 else
338 s3c24xx_serial_start_tx_dma(ourport, count);
339 }
340
341 static void s3c24xx_serial_start_tx(struct uart_port *port)
342 {
343 struct s3c24xx_uart_port *ourport = to_ourport(port);
344 struct circ_buf *xmit = &port->state->xmit;
345
346 if (!tx_enabled(port)) {
347 if (port->flags & UPF_CONS_FLOW)
348 s3c24xx_serial_rx_disable(port);
349
350 tx_enabled(port) = 1;
351 if (!ourport->dma || !ourport->dma->tx_chan)
352 s3c24xx_serial_start_tx_pio(ourport);
353 }
354
355 if (ourport->dma && ourport->dma->tx_chan) {
356 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
357 s3c24xx_serial_start_next_tx(ourport);
358 }
359 }
360
361 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
362 struct tty_port *tty, int count)
363 {
364 struct s3c24xx_uart_dma *dma = ourport->dma;
365 int copied;
366
367 if (!count)
368 return;
369
370 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
371 dma->rx_size, DMA_FROM_DEVICE);
372
373 ourport->port.icount.rx += count;
374 if (!tty) {
375 dev_err(ourport->port.dev, "No tty port\n");
376 return;
377 }
378 copied = tty_insert_flip_string(tty,
379 ((unsigned char *)(ourport->dma->rx_buf)), count);
380 if (copied != count) {
381 WARN_ON(1);
382 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
383 }
384 }
385
386 static void s3c24xx_serial_stop_rx(struct uart_port *port)
387 {
388 struct s3c24xx_uart_port *ourport = to_ourport(port);
389 struct s3c24xx_uart_dma *dma = ourport->dma;
390 struct tty_port *t = &port->state->port;
391 struct dma_tx_state state;
392 enum dma_status dma_status;
393 unsigned int received;
394
395 if (rx_enabled(port)) {
396 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
397 if (s3c24xx_serial_has_interrupt_mask(port))
398 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
399 S3C64XX_UINTM);
400 else
401 disable_irq_nosync(ourport->rx_irq);
402 rx_enabled(port) = 0;
403 }
404 if (dma && dma->rx_chan) {
405 dmaengine_pause(dma->tx_chan);
406 dma_status = dmaengine_tx_status(dma->rx_chan,
407 dma->rx_cookie, &state);
408 if (dma_status == DMA_IN_PROGRESS ||
409 dma_status == DMA_PAUSED) {
410 received = dma->rx_bytes_requested - state.residue;
411 dmaengine_terminate_all(dma->rx_chan);
412 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
413 }
414 }
415 }
416
417 static inline struct s3c24xx_uart_info
418 *s3c24xx_port_to_info(struct uart_port *port)
419 {
420 return to_ourport(port)->info;
421 }
422
423 static inline struct s3c2410_uartcfg
424 *s3c24xx_port_to_cfg(struct uart_port *port)
425 {
426 struct s3c24xx_uart_port *ourport;
427
428 if (port->dev == NULL)
429 return NULL;
430
431 ourport = container_of(port, struct s3c24xx_uart_port, port);
432 return ourport->cfg;
433 }
434
435 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
436 unsigned long ufstat)
437 {
438 struct s3c24xx_uart_info *info = ourport->info;
439
440 if (ufstat & info->rx_fifofull)
441 return ourport->port.fifosize;
442
443 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
444 }
445
446 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
447 static void s3c24xx_serial_rx_dma_complete(void *args)
448 {
449 struct s3c24xx_uart_port *ourport = args;
450 struct uart_port *port = &ourport->port;
451
452 struct s3c24xx_uart_dma *dma = ourport->dma;
453 struct tty_port *t = &port->state->port;
454 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
455
456 struct dma_tx_state state;
457 unsigned long flags;
458 int received;
459
460 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
461 received = dma->rx_bytes_requested - state.residue;
462 async_tx_ack(dma->rx_desc);
463
464 spin_lock_irqsave(&port->lock, flags);
465
466 if (received)
467 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
468
469 if (tty) {
470 tty_flip_buffer_push(t);
471 tty_kref_put(tty);
472 }
473
474 s3c64xx_start_rx_dma(ourport);
475
476 spin_unlock_irqrestore(&port->lock, flags);
477 }
478
479 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
480 {
481 struct s3c24xx_uart_dma *dma = ourport->dma;
482
483 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
484 dma->rx_size, DMA_FROM_DEVICE);
485
486 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
487 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT);
489 if (!dma->rx_desc) {
490 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
491 return;
492 }
493
494 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
495 dma->rx_desc->callback_param = ourport;
496 dma->rx_bytes_requested = dma->rx_size;
497
498 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
499 dma_async_issue_pending(dma->rx_chan);
500 }
501
502 /* ? - where has parity gone?? */
503 #define S3C2410_UERSTAT_PARITY (0x1000)
504
505 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
506 {
507 struct uart_port *port = &ourport->port;
508 unsigned int ucon;
509
510 /* set Rx mode to DMA mode */
511 ucon = rd_regl(port, S3C2410_UCON);
512 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
513 S3C64XX_UCON_TIMEOUT_MASK |
514 S3C64XX_UCON_EMPTYINT_EN |
515 S3C64XX_UCON_DMASUS_EN |
516 S3C64XX_UCON_TIMEOUT_EN |
517 S3C64XX_UCON_RXMODE_MASK);
518 ucon |= S3C64XX_UCON_RXBURST_16 |
519 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
520 S3C64XX_UCON_EMPTYINT_EN |
521 S3C64XX_UCON_TIMEOUT_EN |
522 S3C64XX_UCON_RXMODE_DMA;
523 wr_regl(port, S3C2410_UCON, ucon);
524
525 ourport->rx_mode = S3C24XX_RX_DMA;
526 }
527
528 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
529 {
530 struct uart_port *port = &ourport->port;
531 unsigned int ucon;
532
533 /* set Rx mode to DMA mode */
534 ucon = rd_regl(port, S3C2410_UCON);
535 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
536 S3C64XX_UCON_EMPTYINT_EN |
537 S3C64XX_UCON_DMASUS_EN |
538 S3C64XX_UCON_TIMEOUT_EN |
539 S3C64XX_UCON_RXMODE_MASK);
540 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
541 S3C64XX_UCON_TIMEOUT_EN |
542 S3C64XX_UCON_RXMODE_CPU;
543 wr_regl(port, S3C2410_UCON, ucon);
544
545 ourport->rx_mode = S3C24XX_RX_PIO;
546 }
547
548 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
549
550 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
551 {
552 unsigned int utrstat, ufstat, received;
553 struct s3c24xx_uart_port *ourport = dev_id;
554 struct uart_port *port = &ourport->port;
555 struct s3c24xx_uart_dma *dma = ourport->dma;
556 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
557 struct tty_port *t = &port->state->port;
558 unsigned long flags;
559 struct dma_tx_state state;
560
561 utrstat = rd_regl(port, S3C2410_UTRSTAT);
562 ufstat = rd_regl(port, S3C2410_UFSTAT);
563
564 spin_lock_irqsave(&port->lock, flags);
565
566 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
567 s3c64xx_start_rx_dma(ourport);
568 if (ourport->rx_mode == S3C24XX_RX_PIO)
569 enable_rx_dma(ourport);
570 goto finish;
571 }
572
573 if (ourport->rx_mode == S3C24XX_RX_DMA) {
574 dmaengine_pause(dma->rx_chan);
575 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
576 dmaengine_terminate_all(dma->rx_chan);
577 received = dma->rx_bytes_requested - state.residue;
578 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
579
580 enable_rx_pio(ourport);
581 }
582
583 s3c24xx_serial_rx_drain_fifo(ourport);
584
585 if (tty) {
586 tty_flip_buffer_push(t);
587 tty_kref_put(tty);
588 }
589
590 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
591
592 finish:
593 spin_unlock_irqrestore(&port->lock, flags);
594
595 return IRQ_HANDLED;
596 }
597
598 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
599 {
600 struct uart_port *port = &ourport->port;
601 unsigned int ufcon, ch, flag, ufstat, uerstat;
602 unsigned int fifocnt = 0;
603 int max_count = port->fifosize;
604
605 while (max_count-- > 0) {
606 /*
607 * Receive all characters known to be in FIFO
608 * before reading FIFO level again
609 */
610 if (fifocnt == 0) {
611 ufstat = rd_regl(port, S3C2410_UFSTAT);
612 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
613 if (fifocnt == 0)
614 break;
615 }
616 fifocnt--;
617
618 uerstat = rd_regl(port, S3C2410_UERSTAT);
619 ch = rd_regb(port, S3C2410_URXH);
620
621 if (port->flags & UPF_CONS_FLOW) {
622 int txe = s3c24xx_serial_txempty_nofifo(port);
623
624 if (rx_enabled(port)) {
625 if (!txe) {
626 rx_enabled(port) = 0;
627 continue;
628 }
629 } else {
630 if (txe) {
631 ufcon = rd_regl(port, S3C2410_UFCON);
632 ufcon |= S3C2410_UFCON_RESETRX;
633 wr_regl(port, S3C2410_UFCON, ufcon);
634 rx_enabled(port) = 1;
635 return;
636 }
637 continue;
638 }
639 }
640
641 /* insert the character into the buffer */
642
643 flag = TTY_NORMAL;
644 port->icount.rx++;
645
646 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
647 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
648 ch, uerstat);
649
650 /* check for break */
651 if (uerstat & S3C2410_UERSTAT_BREAK) {
652 dbg("break!\n");
653 port->icount.brk++;
654 if (uart_handle_break(port))
655 continue; /* Ignore character */
656 }
657
658 if (uerstat & S3C2410_UERSTAT_FRAME)
659 port->icount.frame++;
660 if (uerstat & S3C2410_UERSTAT_OVERRUN)
661 port->icount.overrun++;
662
663 uerstat &= port->read_status_mask;
664
665 if (uerstat & S3C2410_UERSTAT_BREAK)
666 flag = TTY_BREAK;
667 else if (uerstat & S3C2410_UERSTAT_PARITY)
668 flag = TTY_PARITY;
669 else if (uerstat & (S3C2410_UERSTAT_FRAME |
670 S3C2410_UERSTAT_OVERRUN))
671 flag = TTY_FRAME;
672 }
673
674 if (uart_handle_sysrq_char(port, ch))
675 continue; /* Ignore character */
676
677 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
678 ch, flag);
679 }
680
681 tty_flip_buffer_push(&port->state->port);
682 }
683
684 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
685 {
686 struct s3c24xx_uart_port *ourport = dev_id;
687 struct uart_port *port = &ourport->port;
688 unsigned long flags;
689
690 spin_lock_irqsave(&port->lock, flags);
691 s3c24xx_serial_rx_drain_fifo(ourport);
692 spin_unlock_irqrestore(&port->lock, flags);
693
694 return IRQ_HANDLED;
695 }
696
697
698 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
699 {
700 struct s3c24xx_uart_port *ourport = dev_id;
701
702 if (ourport->dma && ourport->dma->rx_chan)
703 return s3c24xx_serial_rx_chars_dma(dev_id);
704 return s3c24xx_serial_rx_chars_pio(dev_id);
705 }
706
707 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
708 {
709 struct s3c24xx_uart_port *ourport = id;
710 struct uart_port *port = &ourport->port;
711 struct circ_buf *xmit = &port->state->xmit;
712 unsigned long flags;
713 int count, dma_count = 0;
714
715 spin_lock_irqsave(&port->lock, flags);
716
717 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
718
719 if (ourport->dma && ourport->dma->tx_chan &&
720 count >= ourport->min_dma_size) {
721 int align = dma_get_cache_alignment() -
722 (xmit->tail & (dma_get_cache_alignment() - 1));
723 if (count-align >= ourport->min_dma_size) {
724 dma_count = count-align;
725 count = align;
726 }
727 }
728
729 if (port->x_char) {
730 wr_regb(port, S3C2410_UTXH, port->x_char);
731 port->icount.tx++;
732 port->x_char = 0;
733 goto out;
734 }
735
736 /* if there isn't anything more to transmit, or the uart is now
737 * stopped, disable the uart and exit
738 */
739
740 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
741 s3c24xx_serial_stop_tx(port);
742 goto out;
743 }
744
745 /* try and drain the buffer... */
746
747 if (count > port->fifosize) {
748 count = port->fifosize;
749 dma_count = 0;
750 }
751
752 while (!uart_circ_empty(xmit) && count > 0) {
753 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
754 break;
755
756 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
757 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
758 port->icount.tx++;
759 count--;
760 }
761
762 if (!count && dma_count) {
763 s3c24xx_serial_start_tx_dma(ourport, dma_count);
764 goto out;
765 }
766
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
768 spin_unlock(&port->lock);
769 uart_write_wakeup(port);
770 spin_lock(&port->lock);
771 }
772
773 if (uart_circ_empty(xmit))
774 s3c24xx_serial_stop_tx(port);
775
776 out:
777 spin_unlock_irqrestore(&port->lock, flags);
778 return IRQ_HANDLED;
779 }
780
781 /* interrupt handler for s3c64xx and later SoC's.*/
782 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
783 {
784 struct s3c24xx_uart_port *ourport = id;
785 struct uart_port *port = &ourport->port;
786 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
787 irqreturn_t ret = IRQ_HANDLED;
788
789 if (pend & S3C64XX_UINTM_RXD_MSK) {
790 ret = s3c24xx_serial_rx_chars(irq, id);
791 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
792 }
793 if (pend & S3C64XX_UINTM_TXD_MSK) {
794 ret = s3c24xx_serial_tx_chars(irq, id);
795 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
796 }
797 return ret;
798 }
799
800 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
801 {
802 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
803 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
804 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
805
806 if (ufcon & S3C2410_UFCON_FIFOMODE) {
807 if ((ufstat & info->tx_fifomask) != 0 ||
808 (ufstat & info->tx_fifofull))
809 return 0;
810
811 return 1;
812 }
813
814 return s3c24xx_serial_txempty_nofifo(port);
815 }
816
817 /* no modem control lines */
818 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
819 {
820 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
821
822 if (umstat & S3C2410_UMSTAT_CTS)
823 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
824 else
825 return TIOCM_CAR | TIOCM_DSR;
826 }
827
828 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
829 {
830 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
831
832 if (mctrl & TIOCM_RTS)
833 umcon |= S3C2410_UMCOM_RTS_LOW;
834 else
835 umcon &= ~S3C2410_UMCOM_RTS_LOW;
836
837 wr_regl(port, S3C2410_UMCON, umcon);
838 }
839
840 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
841 {
842 unsigned long flags;
843 unsigned int ucon;
844
845 spin_lock_irqsave(&port->lock, flags);
846
847 ucon = rd_regl(port, S3C2410_UCON);
848
849 if (break_state)
850 ucon |= S3C2410_UCON_SBREAK;
851 else
852 ucon &= ~S3C2410_UCON_SBREAK;
853
854 wr_regl(port, S3C2410_UCON, ucon);
855
856 spin_unlock_irqrestore(&port->lock, flags);
857 }
858
859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
860 {
861 struct s3c24xx_uart_dma *dma = p->dma;
862 dma_cap_mask_t mask;
863 unsigned long flags;
864
865 /* Default slave configuration parameters */
866 dma->rx_conf.direction = DMA_DEV_TO_MEM;
867 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
868 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
869 dma->rx_conf.src_maxburst = 16;
870
871 dma->tx_conf.direction = DMA_MEM_TO_DEV;
872 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
873 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
874 if (dma_get_cache_alignment() >= 16)
875 dma->tx_conf.dst_maxburst = 16;
876 else
877 dma->tx_conf.dst_maxburst = 1;
878
879 dma_cap_zero(mask);
880 dma_cap_set(DMA_SLAVE, mask);
881
882 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
883 dma->rx_param, p->port.dev, "rx");
884 if (!dma->rx_chan)
885 return -ENODEV;
886
887 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
888
889 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
890 dma->tx_param, p->port.dev, "tx");
891 if (!dma->tx_chan) {
892 dma_release_channel(dma->rx_chan);
893 return -ENODEV;
894 }
895
896 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
897
898 /* RX buffer */
899 dma->rx_size = PAGE_SIZE;
900
901 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
902
903 if (!dma->rx_buf) {
904 dma_release_channel(dma->rx_chan);
905 dma_release_channel(dma->tx_chan);
906 return -ENOMEM;
907 }
908
909 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
910 dma->rx_size, DMA_FROM_DEVICE);
911
912 spin_lock_irqsave(&p->port.lock, flags);
913
914 /* TX buffer */
915 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
916 p->port.state->xmit.buf,
917 UART_XMIT_SIZE, DMA_TO_DEVICE);
918
919 spin_unlock_irqrestore(&p->port.lock, flags);
920
921 return 0;
922 }
923
924 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
925 {
926 struct s3c24xx_uart_dma *dma = p->dma;
927
928 if (dma->rx_chan) {
929 dmaengine_terminate_all(dma->rx_chan);
930 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
931 dma->rx_size, DMA_FROM_DEVICE);
932 kfree(dma->rx_buf);
933 dma_release_channel(dma->rx_chan);
934 dma->rx_chan = NULL;
935 }
936
937 if (dma->tx_chan) {
938 dmaengine_terminate_all(dma->tx_chan);
939 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
940 UART_XMIT_SIZE, DMA_TO_DEVICE);
941 dma_release_channel(dma->tx_chan);
942 dma->tx_chan = NULL;
943 }
944 }
945
946 static void s3c24xx_serial_shutdown(struct uart_port *port)
947 {
948 struct s3c24xx_uart_port *ourport = to_ourport(port);
949
950 if (ourport->tx_claimed) {
951 if (!s3c24xx_serial_has_interrupt_mask(port))
952 free_irq(ourport->tx_irq, ourport);
953 tx_enabled(port) = 0;
954 ourport->tx_claimed = 0;
955 ourport->tx_mode = 0;
956 }
957
958 if (ourport->rx_claimed) {
959 if (!s3c24xx_serial_has_interrupt_mask(port))
960 free_irq(ourport->rx_irq, ourport);
961 ourport->rx_claimed = 0;
962 rx_enabled(port) = 0;
963 }
964
965 /* Clear pending interrupts and mask all interrupts */
966 if (s3c24xx_serial_has_interrupt_mask(port)) {
967 free_irq(port->irq, ourport);
968
969 wr_regl(port, S3C64XX_UINTP, 0xf);
970 wr_regl(port, S3C64XX_UINTM, 0xf);
971 }
972
973 if (ourport->dma)
974 s3c24xx_serial_release_dma(ourport);
975
976 ourport->tx_in_progress = 0;
977 }
978
979 static int s3c24xx_serial_startup(struct uart_port *port)
980 {
981 struct s3c24xx_uart_port *ourport = to_ourport(port);
982 int ret;
983
984 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
985 port, (unsigned long long)port->mapbase, port->membase);
986
987 rx_enabled(port) = 1;
988
989 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
990 s3c24xx_serial_portname(port), ourport);
991
992 if (ret != 0) {
993 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
994 return ret;
995 }
996
997 ourport->rx_claimed = 1;
998
999 dbg("requesting tx irq...\n");
1000
1001 tx_enabled(port) = 1;
1002
1003 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1004 s3c24xx_serial_portname(port), ourport);
1005
1006 if (ret) {
1007 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1008 goto err;
1009 }
1010
1011 ourport->tx_claimed = 1;
1012
1013 dbg("s3c24xx_serial_startup ok\n");
1014
1015 /* the port reset code should have done the correct
1016 * register setup for the port controls */
1017
1018 return ret;
1019
1020 err:
1021 s3c24xx_serial_shutdown(port);
1022 return ret;
1023 }
1024
1025 static int s3c64xx_serial_startup(struct uart_port *port)
1026 {
1027 struct s3c24xx_uart_port *ourport = to_ourport(port);
1028 unsigned long flags;
1029 unsigned int ufcon;
1030 int ret;
1031
1032 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1033 port, (unsigned long long)port->mapbase, port->membase);
1034
1035 wr_regl(port, S3C64XX_UINTM, 0xf);
1036 if (ourport->dma) {
1037 ret = s3c24xx_serial_request_dma(ourport);
1038 if (ret < 0) {
1039 dev_warn(port->dev, "DMA request failed\n");
1040 return ret;
1041 }
1042 }
1043
1044 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1045 s3c24xx_serial_portname(port), ourport);
1046 if (ret) {
1047 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1048 return ret;
1049 }
1050
1051 /* For compatibility with s3c24xx Soc's */
1052 rx_enabled(port) = 1;
1053 ourport->rx_claimed = 1;
1054 tx_enabled(port) = 0;
1055 ourport->tx_claimed = 1;
1056
1057 spin_lock_irqsave(&port->lock, flags);
1058
1059 ufcon = rd_regl(port, S3C2410_UFCON);
1060 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1061 if (!uart_console(port))
1062 ufcon |= S3C2410_UFCON_RESETTX;
1063 wr_regl(port, S3C2410_UFCON, ufcon);
1064
1065 enable_rx_pio(ourport);
1066
1067 spin_unlock_irqrestore(&port->lock, flags);
1068
1069 /* Enable Rx Interrupt */
1070 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1071
1072 dbg("s3c64xx_serial_startup ok\n");
1073 return ret;
1074 }
1075
1076 /* power power management control */
1077
1078 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1079 unsigned int old)
1080 {
1081 struct s3c24xx_uart_port *ourport = to_ourport(port);
1082 int timeout = 10000;
1083
1084 ourport->pm_level = level;
1085
1086 switch (level) {
1087 case 3:
1088 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1089 udelay(100);
1090
1091 if (!IS_ERR(ourport->baudclk))
1092 clk_disable_unprepare(ourport->baudclk);
1093
1094 clk_disable_unprepare(ourport->clk);
1095 break;
1096
1097 case 0:
1098 clk_prepare_enable(ourport->clk);
1099
1100 if (!IS_ERR(ourport->baudclk))
1101 clk_prepare_enable(ourport->baudclk);
1102
1103 break;
1104 default:
1105 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1106 }
1107 }
1108
1109 /* baud rate calculation
1110 *
1111 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1112 * of different sources, including the peripheral clock ("pclk") and an
1113 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1114 * with a programmable extra divisor.
1115 *
1116 * The following code goes through the clock sources, and calculates the
1117 * baud clocks (and the resultant actual baud rates) and then tries to
1118 * pick the closest one and select that.
1119 *
1120 */
1121
1122 #define MAX_CLK_NAME_LENGTH 15
1123
1124 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1125 {
1126 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1127 unsigned int ucon;
1128
1129 if (info->num_clks == 1)
1130 return 0;
1131
1132 ucon = rd_regl(port, S3C2410_UCON);
1133 ucon &= info->clksel_mask;
1134 return ucon >> info->clksel_shift;
1135 }
1136
1137 static void s3c24xx_serial_setsource(struct uart_port *port,
1138 unsigned int clk_sel)
1139 {
1140 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1141 unsigned int ucon;
1142
1143 if (info->num_clks == 1)
1144 return;
1145
1146 ucon = rd_regl(port, S3C2410_UCON);
1147 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1148 return;
1149
1150 ucon &= ~info->clksel_mask;
1151 ucon |= clk_sel << info->clksel_shift;
1152 wr_regl(port, S3C2410_UCON, ucon);
1153 }
1154
1155 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1156 unsigned int req_baud, struct clk **best_clk,
1157 unsigned int *clk_num)
1158 {
1159 struct s3c24xx_uart_info *info = ourport->info;
1160 struct clk *clk;
1161 unsigned long rate;
1162 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1163 char clkname[MAX_CLK_NAME_LENGTH];
1164 int calc_deviation, deviation = (1 << 30) - 1;
1165
1166 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1167 ourport->info->def_clk_sel;
1168 for (cnt = 0; cnt < info->num_clks; cnt++) {
1169 if (!(clk_sel & (1 << cnt)))
1170 continue;
1171
1172 sprintf(clkname, "clk_uart_baud%d", cnt);
1173 clk = clk_get(ourport->port.dev, clkname);
1174 if (IS_ERR(clk))
1175 continue;
1176
1177 rate = clk_get_rate(clk);
1178 if (!rate)
1179 continue;
1180
1181 if (ourport->info->has_divslot) {
1182 unsigned long div = rate / req_baud;
1183
1184 /* The UDIVSLOT register on the newer UARTs allows us to
1185 * get a divisor adjustment of 1/16th on the baud clock.
1186 *
1187 * We don't keep the UDIVSLOT value (the 16ths we
1188 * calculated by not multiplying the baud by 16) as it
1189 * is easy enough to recalculate.
1190 */
1191
1192 quot = div / 16;
1193 baud = rate / div;
1194 } else {
1195 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1196 baud = rate / (quot * 16);
1197 }
1198 quot--;
1199
1200 calc_deviation = req_baud - baud;
1201 if (calc_deviation < 0)
1202 calc_deviation = -calc_deviation;
1203
1204 if (calc_deviation < deviation) {
1205 *best_clk = clk;
1206 best_quot = quot;
1207 *clk_num = cnt;
1208 deviation = calc_deviation;
1209 }
1210 }
1211
1212 return best_quot;
1213 }
1214
1215 /* udivslot_table[]
1216 *
1217 * This table takes the fractional value of the baud divisor and gives
1218 * the recommended setting for the UDIVSLOT register.
1219 */
1220 static u16 udivslot_table[16] = {
1221 [0] = 0x0000,
1222 [1] = 0x0080,
1223 [2] = 0x0808,
1224 [3] = 0x0888,
1225 [4] = 0x2222,
1226 [5] = 0x4924,
1227 [6] = 0x4A52,
1228 [7] = 0x54AA,
1229 [8] = 0x5555,
1230 [9] = 0xD555,
1231 [10] = 0xD5D5,
1232 [11] = 0xDDD5,
1233 [12] = 0xDDDD,
1234 [13] = 0xDFDD,
1235 [14] = 0xDFDF,
1236 [15] = 0xFFDF,
1237 };
1238
1239 static void s3c24xx_serial_set_termios(struct uart_port *port,
1240 struct ktermios *termios,
1241 struct ktermios *old)
1242 {
1243 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1244 struct s3c24xx_uart_port *ourport = to_ourport(port);
1245 struct clk *clk = ERR_PTR(-EINVAL);
1246 unsigned long flags;
1247 unsigned int baud, quot, clk_sel = 0;
1248 unsigned int ulcon;
1249 unsigned int umcon;
1250 unsigned int udivslot = 0;
1251
1252 /*
1253 * We don't support modem control lines.
1254 */
1255 termios->c_cflag &= ~(HUPCL | CMSPAR);
1256 termios->c_cflag |= CLOCAL;
1257
1258 /*
1259 * Ask the core to calculate the divisor for us.
1260 */
1261
1262 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1263 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1264 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1265 quot = port->custom_divisor;
1266 if (IS_ERR(clk))
1267 return;
1268
1269 /* check to see if we need to change clock source */
1270
1271 if (ourport->baudclk != clk) {
1272 clk_prepare_enable(clk);
1273
1274 s3c24xx_serial_setsource(port, clk_sel);
1275
1276 if (!IS_ERR(ourport->baudclk)) {
1277 clk_disable_unprepare(ourport->baudclk);
1278 ourport->baudclk = ERR_PTR(-EINVAL);
1279 }
1280
1281 ourport->baudclk = clk;
1282 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1283 }
1284
1285 if (ourport->info->has_divslot) {
1286 unsigned int div = ourport->baudclk_rate / baud;
1287
1288 if (cfg->has_fracval) {
1289 udivslot = (div & 15);
1290 dbg("fracval = %04x\n", udivslot);
1291 } else {
1292 udivslot = udivslot_table[div & 15];
1293 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1294 }
1295 }
1296
1297 switch (termios->c_cflag & CSIZE) {
1298 case CS5:
1299 dbg("config: 5bits/char\n");
1300 ulcon = S3C2410_LCON_CS5;
1301 break;
1302 case CS6:
1303 dbg("config: 6bits/char\n");
1304 ulcon = S3C2410_LCON_CS6;
1305 break;
1306 case CS7:
1307 dbg("config: 7bits/char\n");
1308 ulcon = S3C2410_LCON_CS7;
1309 break;
1310 case CS8:
1311 default:
1312 dbg("config: 8bits/char\n");
1313 ulcon = S3C2410_LCON_CS8;
1314 break;
1315 }
1316
1317 /* preserve original lcon IR settings */
1318 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1319
1320 if (termios->c_cflag & CSTOPB)
1321 ulcon |= S3C2410_LCON_STOPB;
1322
1323 if (termios->c_cflag & PARENB) {
1324 if (termios->c_cflag & PARODD)
1325 ulcon |= S3C2410_LCON_PODD;
1326 else
1327 ulcon |= S3C2410_LCON_PEVEN;
1328 } else {
1329 ulcon |= S3C2410_LCON_PNONE;
1330 }
1331
1332 spin_lock_irqsave(&port->lock, flags);
1333
1334 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1335 ulcon, quot, udivslot);
1336
1337 wr_regl(port, S3C2410_ULCON, ulcon);
1338 wr_regl(port, S3C2410_UBRDIV, quot);
1339
1340 umcon = rd_regl(port, S3C2410_UMCON);
1341 if (termios->c_cflag & CRTSCTS) {
1342 umcon |= S3C2410_UMCOM_AFC;
1343 /* Disable RTS when RX FIFO contains 63 bytes */
1344 umcon &= ~S3C2412_UMCON_AFC_8;
1345 } else {
1346 umcon &= ~S3C2410_UMCOM_AFC;
1347 }
1348 wr_regl(port, S3C2410_UMCON, umcon);
1349
1350 if (ourport->info->has_divslot)
1351 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1352
1353 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1354 rd_regl(port, S3C2410_ULCON),
1355 rd_regl(port, S3C2410_UCON),
1356 rd_regl(port, S3C2410_UFCON));
1357
1358 /*
1359 * Update the per-port timeout.
1360 */
1361 uart_update_timeout(port, termios->c_cflag, baud);
1362
1363 /*
1364 * Which character status flags are we interested in?
1365 */
1366 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1367 if (termios->c_iflag & INPCK)
1368 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1369 S3C2410_UERSTAT_PARITY;
1370 /*
1371 * Which character status flags should we ignore?
1372 */
1373 port->ignore_status_mask = 0;
1374 if (termios->c_iflag & IGNPAR)
1375 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1376 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1377 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1378
1379 /*
1380 * Ignore all characters if CREAD is not set.
1381 */
1382 if ((termios->c_cflag & CREAD) == 0)
1383 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1384
1385 spin_unlock_irqrestore(&port->lock, flags);
1386 }
1387
1388 static const char *s3c24xx_serial_type(struct uart_port *port)
1389 {
1390 switch (port->type) {
1391 case PORT_S3C2410:
1392 return "S3C2410";
1393 case PORT_S3C2440:
1394 return "S3C2440";
1395 case PORT_S3C2412:
1396 return "S3C2412";
1397 case PORT_S3C6400:
1398 return "S3C6400/10";
1399 default:
1400 return NULL;
1401 }
1402 }
1403
1404 #define MAP_SIZE (0x100)
1405
1406 static void s3c24xx_serial_release_port(struct uart_port *port)
1407 {
1408 release_mem_region(port->mapbase, MAP_SIZE);
1409 }
1410
1411 static int s3c24xx_serial_request_port(struct uart_port *port)
1412 {
1413 const char *name = s3c24xx_serial_portname(port);
1414 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1415 }
1416
1417 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1418 {
1419 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1420
1421 if (flags & UART_CONFIG_TYPE &&
1422 s3c24xx_serial_request_port(port) == 0)
1423 port->type = info->type;
1424 }
1425
1426 /*
1427 * verify the new serial_struct (for TIOCSSERIAL).
1428 */
1429 static int
1430 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1431 {
1432 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1433
1434 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1435 return -EINVAL;
1436
1437 return 0;
1438 }
1439
1440
1441 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1442
1443 static struct console s3c24xx_serial_console;
1444
1445 static int __init s3c24xx_serial_console_init(void)
1446 {
1447 register_console(&s3c24xx_serial_console);
1448 return 0;
1449 }
1450 console_initcall(s3c24xx_serial_console_init);
1451
1452 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1453 #else
1454 #define S3C24XX_SERIAL_CONSOLE NULL
1455 #endif
1456
1457 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1458 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1459 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1460 unsigned char c);
1461 #endif
1462
1463 static struct uart_ops s3c24xx_serial_ops = {
1464 .pm = s3c24xx_serial_pm,
1465 .tx_empty = s3c24xx_serial_tx_empty,
1466 .get_mctrl = s3c24xx_serial_get_mctrl,
1467 .set_mctrl = s3c24xx_serial_set_mctrl,
1468 .stop_tx = s3c24xx_serial_stop_tx,
1469 .start_tx = s3c24xx_serial_start_tx,
1470 .stop_rx = s3c24xx_serial_stop_rx,
1471 .break_ctl = s3c24xx_serial_break_ctl,
1472 .startup = s3c24xx_serial_startup,
1473 .shutdown = s3c24xx_serial_shutdown,
1474 .set_termios = s3c24xx_serial_set_termios,
1475 .type = s3c24xx_serial_type,
1476 .release_port = s3c24xx_serial_release_port,
1477 .request_port = s3c24xx_serial_request_port,
1478 .config_port = s3c24xx_serial_config_port,
1479 .verify_port = s3c24xx_serial_verify_port,
1480 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1481 .poll_get_char = s3c24xx_serial_get_poll_char,
1482 .poll_put_char = s3c24xx_serial_put_poll_char,
1483 #endif
1484 };
1485
1486 static struct uart_driver s3c24xx_uart_drv = {
1487 .owner = THIS_MODULE,
1488 .driver_name = "s3c2410_serial",
1489 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1490 .cons = S3C24XX_SERIAL_CONSOLE,
1491 .dev_name = S3C24XX_SERIAL_NAME,
1492 .major = S3C24XX_SERIAL_MAJOR,
1493 .minor = S3C24XX_SERIAL_MINOR,
1494 };
1495
1496 #define __PORT_LOCK_UNLOCKED(i) \
1497 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1498 static struct s3c24xx_uart_port
1499 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1500 [0] = {
1501 .port = {
1502 .lock = __PORT_LOCK_UNLOCKED(0),
1503 .iotype = UPIO_MEM,
1504 .uartclk = 0,
1505 .fifosize = 16,
1506 .ops = &s3c24xx_serial_ops,
1507 .flags = UPF_BOOT_AUTOCONF,
1508 .line = 0,
1509 }
1510 },
1511 [1] = {
1512 .port = {
1513 .lock = __PORT_LOCK_UNLOCKED(1),
1514 .iotype = UPIO_MEM,
1515 .uartclk = 0,
1516 .fifosize = 16,
1517 .ops = &s3c24xx_serial_ops,
1518 .flags = UPF_BOOT_AUTOCONF,
1519 .line = 1,
1520 }
1521 },
1522 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1523
1524 [2] = {
1525 .port = {
1526 .lock = __PORT_LOCK_UNLOCKED(2),
1527 .iotype = UPIO_MEM,
1528 .uartclk = 0,
1529 .fifosize = 16,
1530 .ops = &s3c24xx_serial_ops,
1531 .flags = UPF_BOOT_AUTOCONF,
1532 .line = 2,
1533 }
1534 },
1535 #endif
1536 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1537 [3] = {
1538 .port = {
1539 .lock = __PORT_LOCK_UNLOCKED(3),
1540 .iotype = UPIO_MEM,
1541 .uartclk = 0,
1542 .fifosize = 16,
1543 .ops = &s3c24xx_serial_ops,
1544 .flags = UPF_BOOT_AUTOCONF,
1545 .line = 3,
1546 }
1547 }
1548 #endif
1549 };
1550 #undef __PORT_LOCK_UNLOCKED
1551
1552 /* s3c24xx_serial_resetport
1553 *
1554 * reset the fifos and other the settings.
1555 */
1556
1557 static void s3c24xx_serial_resetport(struct uart_port *port,
1558 struct s3c2410_uartcfg *cfg)
1559 {
1560 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1561 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1562 unsigned int ucon_mask;
1563
1564 ucon_mask = info->clksel_mask;
1565 if (info->type == PORT_S3C2440)
1566 ucon_mask |= S3C2440_UCON0_DIVMASK;
1567
1568 ucon &= ucon_mask;
1569 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1570
1571 /* reset both fifos */
1572 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1573 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1574
1575 /* some delay is required after fifo reset */
1576 udelay(1);
1577 }
1578
1579
1580 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1581
1582 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1583 unsigned long val, void *data)
1584 {
1585 struct s3c24xx_uart_port *port;
1586 struct uart_port *uport;
1587
1588 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1589 uport = &port->port;
1590
1591 /* check to see if port is enabled */
1592
1593 if (port->pm_level != 0)
1594 return 0;
1595
1596 /* try and work out if the baudrate is changing, we can detect
1597 * a change in rate, but we do not have support for detecting
1598 * a disturbance in the clock-rate over the change.
1599 */
1600
1601 if (IS_ERR(port->baudclk))
1602 goto exit;
1603
1604 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1605 goto exit;
1606
1607 if (val == CPUFREQ_PRECHANGE) {
1608 /* we should really shut the port down whilst the
1609 * frequency change is in progress. */
1610
1611 } else if (val == CPUFREQ_POSTCHANGE) {
1612 struct ktermios *termios;
1613 struct tty_struct *tty;
1614
1615 if (uport->state == NULL)
1616 goto exit;
1617
1618 tty = uport->state->port.tty;
1619
1620 if (tty == NULL)
1621 goto exit;
1622
1623 termios = &tty->termios;
1624
1625 if (termios == NULL) {
1626 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1627 goto exit;
1628 }
1629
1630 s3c24xx_serial_set_termios(uport, termios, NULL);
1631 }
1632
1633 exit:
1634 return 0;
1635 }
1636
1637 static inline int
1638 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1639 {
1640 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1641
1642 return cpufreq_register_notifier(&port->freq_transition,
1643 CPUFREQ_TRANSITION_NOTIFIER);
1644 }
1645
1646 static inline void
1647 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1648 {
1649 cpufreq_unregister_notifier(&port->freq_transition,
1650 CPUFREQ_TRANSITION_NOTIFIER);
1651 }
1652
1653 #else
1654 static inline int
1655 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1656 {
1657 return 0;
1658 }
1659
1660 static inline void
1661 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1662 {
1663 }
1664 #endif
1665
1666 /* s3c24xx_serial_init_port
1667 *
1668 * initialise a single serial port from the platform device given
1669 */
1670
1671 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1672 struct platform_device *platdev)
1673 {
1674 struct uart_port *port = &ourport->port;
1675 struct s3c2410_uartcfg *cfg = ourport->cfg;
1676 struct resource *res;
1677 int ret;
1678
1679 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1680
1681 if (platdev == NULL)
1682 return -ENODEV;
1683
1684 if (port->mapbase != 0)
1685 return -EINVAL;
1686
1687 /* setup info for port */
1688 port->dev = &platdev->dev;
1689
1690 /* Startup sequence is different for s3c64xx and higher SoC's */
1691 if (s3c24xx_serial_has_interrupt_mask(port))
1692 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1693
1694 port->uartclk = 1;
1695
1696 if (cfg->uart_flags & UPF_CONS_FLOW) {
1697 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1698 port->flags |= UPF_CONS_FLOW;
1699 }
1700
1701 /* sort our the physical and virtual addresses for each UART */
1702
1703 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1704 if (res == NULL) {
1705 dev_err(port->dev, "failed to find memory resource for uart\n");
1706 return -EINVAL;
1707 }
1708
1709 dbg("resource %pR)\n", res);
1710
1711 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1712 if (!port->membase) {
1713 dev_err(port->dev, "failed to remap controller address\n");
1714 return -EBUSY;
1715 }
1716
1717 port->mapbase = res->start;
1718 ret = platform_get_irq(platdev, 0);
1719 if (ret < 0)
1720 port->irq = 0;
1721 else {
1722 port->irq = ret;
1723 ourport->rx_irq = ret;
1724 ourport->tx_irq = ret + 1;
1725 }
1726
1727 ret = platform_get_irq(platdev, 1);
1728 if (ret > 0)
1729 ourport->tx_irq = ret;
1730 /*
1731 * DMA is currently supported only on DT platforms, if DMA properties
1732 * are specified.
1733 */
1734 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1735 "dmas", NULL)) {
1736 ourport->dma = devm_kzalloc(port->dev,
1737 sizeof(*ourport->dma),
1738 GFP_KERNEL);
1739 if (!ourport->dma) {
1740 ret = -ENOMEM;
1741 goto err;
1742 }
1743 }
1744
1745 ourport->clk = clk_get(&platdev->dev, "uart");
1746 if (IS_ERR(ourport->clk)) {
1747 pr_err("%s: Controller clock not found\n",
1748 dev_name(&platdev->dev));
1749 ret = PTR_ERR(ourport->clk);
1750 goto err;
1751 }
1752
1753 ret = clk_prepare_enable(ourport->clk);
1754 if (ret) {
1755 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1756 clk_put(ourport->clk);
1757 goto err;
1758 }
1759
1760 /* Keep all interrupts masked and cleared */
1761 if (s3c24xx_serial_has_interrupt_mask(port)) {
1762 wr_regl(port, S3C64XX_UINTM, 0xf);
1763 wr_regl(port, S3C64XX_UINTP, 0xf);
1764 wr_regl(port, S3C64XX_UINTSP, 0xf);
1765 }
1766
1767 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1768 &port->mapbase, port->membase, port->irq,
1769 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1770
1771 /* reset the fifos (and setup the uart) */
1772 s3c24xx_serial_resetport(port, cfg);
1773
1774 return 0;
1775
1776 err:
1777 port->mapbase = 0;
1778 return ret;
1779 }
1780
1781 /* Device driver serial port probe */
1782
1783 static const struct of_device_id s3c24xx_uart_dt_match[];
1784 static int probe_index;
1785
1786 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1787 struct platform_device *pdev)
1788 {
1789 #ifdef CONFIG_OF
1790 if (pdev->dev.of_node) {
1791 const struct of_device_id *match;
1792 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1793 return (struct s3c24xx_serial_drv_data *)match->data;
1794 }
1795 #endif
1796 return (struct s3c24xx_serial_drv_data *)
1797 platform_get_device_id(pdev)->driver_data;
1798 }
1799
1800 static int s3c24xx_serial_probe(struct platform_device *pdev)
1801 {
1802 struct device_node *np = pdev->dev.of_node;
1803 struct s3c24xx_uart_port *ourport;
1804 int index = probe_index;
1805 int ret;
1806
1807 if (np) {
1808 ret = of_alias_get_id(np, "serial");
1809 if (ret >= 0)
1810 index = ret;
1811 }
1812
1813 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1814
1815 ourport = &s3c24xx_serial_ports[index];
1816
1817 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1818 if (!ourport->drv_data) {
1819 dev_err(&pdev->dev, "could not find driver data\n");
1820 return -ENODEV;
1821 }
1822
1823 ourport->baudclk = ERR_PTR(-EINVAL);
1824 ourport->info = ourport->drv_data->info;
1825 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1826 dev_get_platdata(&pdev->dev) :
1827 ourport->drv_data->def_cfg;
1828
1829 if (np)
1830 of_property_read_u32(np,
1831 "samsung,uart-fifosize", &ourport->port.fifosize);
1832
1833 if (ourport->drv_data->fifosize[index])
1834 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1835 else if (ourport->info->fifosize)
1836 ourport->port.fifosize = ourport->info->fifosize;
1837
1838 /*
1839 * DMA transfers must be aligned at least to cache line size,
1840 * so find minimal transfer size suitable for DMA mode
1841 */
1842 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1843 dma_get_cache_alignment());
1844
1845 dbg("%s: initialising port %p...\n", __func__, ourport);
1846
1847 ret = s3c24xx_serial_init_port(ourport, pdev);
1848 if (ret < 0)
1849 return ret;
1850
1851 if (!s3c24xx_uart_drv.state) {
1852 ret = uart_register_driver(&s3c24xx_uart_drv);
1853 if (ret < 0) {
1854 pr_err("Failed to register Samsung UART driver\n");
1855 return ret;
1856 }
1857 }
1858
1859 dbg("%s: adding port\n", __func__);
1860 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1861 platform_set_drvdata(pdev, &ourport->port);
1862
1863 /*
1864 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1865 * so that a potential re-enablement through the pm-callback overlaps
1866 * and keeps the clock enabled in this case.
1867 */
1868 clk_disable_unprepare(ourport->clk);
1869
1870 ret = s3c24xx_serial_cpufreq_register(ourport);
1871 if (ret < 0)
1872 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1873
1874 probe_index++;
1875
1876 return 0;
1877 }
1878
1879 static int s3c24xx_serial_remove(struct platform_device *dev)
1880 {
1881 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1882
1883 if (port) {
1884 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1885 uart_remove_one_port(&s3c24xx_uart_drv, port);
1886 }
1887
1888 uart_unregister_driver(&s3c24xx_uart_drv);
1889
1890 return 0;
1891 }
1892
1893 /* UART power management code */
1894 #ifdef CONFIG_PM_SLEEP
1895 static int s3c24xx_serial_suspend(struct device *dev)
1896 {
1897 struct uart_port *port = s3c24xx_dev_to_port(dev);
1898
1899 if (port)
1900 uart_suspend_port(&s3c24xx_uart_drv, port);
1901
1902 return 0;
1903 }
1904
1905 static int s3c24xx_serial_resume(struct device *dev)
1906 {
1907 struct uart_port *port = s3c24xx_dev_to_port(dev);
1908 struct s3c24xx_uart_port *ourport = to_ourport(port);
1909
1910 if (port) {
1911 clk_prepare_enable(ourport->clk);
1912 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1913 clk_disable_unprepare(ourport->clk);
1914
1915 uart_resume_port(&s3c24xx_uart_drv, port);
1916 }
1917
1918 return 0;
1919 }
1920
1921 static int s3c24xx_serial_resume_noirq(struct device *dev)
1922 {
1923 struct uart_port *port = s3c24xx_dev_to_port(dev);
1924
1925 if (port) {
1926 /* restore IRQ mask */
1927 if (s3c24xx_serial_has_interrupt_mask(port)) {
1928 unsigned int uintm = 0xf;
1929 if (tx_enabled(port))
1930 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1931 if (rx_enabled(port))
1932 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1933 wr_regl(port, S3C64XX_UINTM, uintm);
1934 }
1935 }
1936
1937 return 0;
1938 }
1939
1940 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1941 .suspend = s3c24xx_serial_suspend,
1942 .resume = s3c24xx_serial_resume,
1943 .resume_noirq = s3c24xx_serial_resume_noirq,
1944 };
1945 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1946
1947 #else /* !CONFIG_PM_SLEEP */
1948
1949 #define SERIAL_SAMSUNG_PM_OPS NULL
1950 #endif /* CONFIG_PM_SLEEP */
1951
1952 /* Console code */
1953
1954 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1955
1956 static struct uart_port *cons_uart;
1957
1958 static int
1959 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1960 {
1961 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1962 unsigned long ufstat, utrstat;
1963
1964 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1965 /* fifo mode - check amount of data in fifo registers... */
1966
1967 ufstat = rd_regl(port, S3C2410_UFSTAT);
1968 return (ufstat & info->tx_fifofull) ? 0 : 1;
1969 }
1970
1971 /* in non-fifo mode, we go and use the tx buffer empty */
1972
1973 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1974 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1975 }
1976
1977 static bool
1978 s3c24xx_port_configured(unsigned int ucon)
1979 {
1980 /* consider the serial port configured if the tx/rx mode set */
1981 return (ucon & 0xf) != 0;
1982 }
1983
1984 #ifdef CONFIG_CONSOLE_POLL
1985 /*
1986 * Console polling routines for writing and reading from the uart while
1987 * in an interrupt or debug context.
1988 */
1989
1990 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1991 {
1992 struct s3c24xx_uart_port *ourport = to_ourport(port);
1993 unsigned int ufstat;
1994
1995 ufstat = rd_regl(port, S3C2410_UFSTAT);
1996 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1997 return NO_POLL_CHAR;
1998
1999 return rd_regb(port, S3C2410_URXH);
2000 }
2001
2002 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2003 unsigned char c)
2004 {
2005 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2006 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2007
2008 /* not possible to xmit on unconfigured port */
2009 if (!s3c24xx_port_configured(ucon))
2010 return;
2011
2012 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2013 cpu_relax();
2014 wr_regb(port, S3C2410_UTXH, c);
2015 }
2016
2017 #endif /* CONFIG_CONSOLE_POLL */
2018
2019 static void
2020 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2021 {
2022 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2023
2024 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2025 cpu_relax();
2026 wr_regb(port, S3C2410_UTXH, ch);
2027 }
2028
2029 static void
2030 s3c24xx_serial_console_write(struct console *co, const char *s,
2031 unsigned int count)
2032 {
2033 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2034
2035 /* not possible to xmit on unconfigured port */
2036 if (!s3c24xx_port_configured(ucon))
2037 return;
2038
2039 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2040 }
2041
2042 static void __init
2043 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2044 int *parity, int *bits)
2045 {
2046 struct clk *clk;
2047 unsigned int ulcon;
2048 unsigned int ucon;
2049 unsigned int ubrdiv;
2050 unsigned long rate;
2051 unsigned int clk_sel;
2052 char clk_name[MAX_CLK_NAME_LENGTH];
2053
2054 ulcon = rd_regl(port, S3C2410_ULCON);
2055 ucon = rd_regl(port, S3C2410_UCON);
2056 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2057
2058 dbg("s3c24xx_serial_get_options: port=%p\n"
2059 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2060 port, ulcon, ucon, ubrdiv);
2061
2062 if (s3c24xx_port_configured(ucon)) {
2063 switch (ulcon & S3C2410_LCON_CSMASK) {
2064 case S3C2410_LCON_CS5:
2065 *bits = 5;
2066 break;
2067 case S3C2410_LCON_CS6:
2068 *bits = 6;
2069 break;
2070 case S3C2410_LCON_CS7:
2071 *bits = 7;
2072 break;
2073 case S3C2410_LCON_CS8:
2074 default:
2075 *bits = 8;
2076 break;
2077 }
2078
2079 switch (ulcon & S3C2410_LCON_PMASK) {
2080 case S3C2410_LCON_PEVEN:
2081 *parity = 'e';
2082 break;
2083
2084 case S3C2410_LCON_PODD:
2085 *parity = 'o';
2086 break;
2087
2088 case S3C2410_LCON_PNONE:
2089 default:
2090 *parity = 'n';
2091 }
2092
2093 /* now calculate the baud rate */
2094
2095 clk_sel = s3c24xx_serial_getsource(port);
2096 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2097
2098 clk = clk_get(port->dev, clk_name);
2099 if (!IS_ERR(clk))
2100 rate = clk_get_rate(clk);
2101 else
2102 rate = 1;
2103
2104 *baud = rate / (16 * (ubrdiv + 1));
2105 dbg("calculated baud %d\n", *baud);
2106 }
2107
2108 }
2109
2110 static int __init
2111 s3c24xx_serial_console_setup(struct console *co, char *options)
2112 {
2113 struct uart_port *port;
2114 int baud = 9600;
2115 int bits = 8;
2116 int parity = 'n';
2117 int flow = 'n';
2118
2119 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2120 co, co->index, options);
2121
2122 /* is this a valid port */
2123
2124 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2125 co->index = 0;
2126
2127 port = &s3c24xx_serial_ports[co->index].port;
2128
2129 /* is the port configured? */
2130
2131 if (port->mapbase == 0x0)
2132 return -ENODEV;
2133
2134 cons_uart = port;
2135
2136 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2137
2138 /*
2139 * Check whether an invalid uart number has been specified, and
2140 * if so, search for the first available port that does have
2141 * console support.
2142 */
2143 if (options)
2144 uart_parse_options(options, &baud, &parity, &bits, &flow);
2145 else
2146 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2147
2148 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2149
2150 return uart_set_options(port, co, baud, parity, bits, flow);
2151 }
2152
2153 static struct console s3c24xx_serial_console = {
2154 .name = S3C24XX_SERIAL_NAME,
2155 .device = uart_console_device,
2156 .flags = CON_PRINTBUFFER,
2157 .index = -1,
2158 .write = s3c24xx_serial_console_write,
2159 .setup = s3c24xx_serial_console_setup,
2160 .data = &s3c24xx_uart_drv,
2161 };
2162 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2163
2164 #ifdef CONFIG_CPU_S3C2410
2165 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2166 .info = &(struct s3c24xx_uart_info) {
2167 .name = "Samsung S3C2410 UART",
2168 .type = PORT_S3C2410,
2169 .fifosize = 16,
2170 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2171 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2172 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2173 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2174 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2175 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2176 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2177 .num_clks = 2,
2178 .clksel_mask = S3C2410_UCON_CLKMASK,
2179 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2180 },
2181 .def_cfg = &(struct s3c2410_uartcfg) {
2182 .ucon = S3C2410_UCON_DEFAULT,
2183 .ufcon = S3C2410_UFCON_DEFAULT,
2184 },
2185 };
2186 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2187 #else
2188 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2189 #endif
2190
2191 #ifdef CONFIG_CPU_S3C2412
2192 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2193 .info = &(struct s3c24xx_uart_info) {
2194 .name = "Samsung S3C2412 UART",
2195 .type = PORT_S3C2412,
2196 .fifosize = 64,
2197 .has_divslot = 1,
2198 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2199 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2200 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2201 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2202 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2203 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2204 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2205 .num_clks = 4,
2206 .clksel_mask = S3C2412_UCON_CLKMASK,
2207 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2208 },
2209 .def_cfg = &(struct s3c2410_uartcfg) {
2210 .ucon = S3C2410_UCON_DEFAULT,
2211 .ufcon = S3C2410_UFCON_DEFAULT,
2212 },
2213 };
2214 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2215 #else
2216 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2217 #endif
2218
2219 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2220 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2221 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2222 .info = &(struct s3c24xx_uart_info) {
2223 .name = "Samsung S3C2440 UART",
2224 .type = PORT_S3C2440,
2225 .fifosize = 64,
2226 .has_divslot = 1,
2227 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2228 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2229 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2230 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2231 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2232 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2233 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2234 .num_clks = 4,
2235 .clksel_mask = S3C2412_UCON_CLKMASK,
2236 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2237 },
2238 .def_cfg = &(struct s3c2410_uartcfg) {
2239 .ucon = S3C2410_UCON_DEFAULT,
2240 .ufcon = S3C2410_UFCON_DEFAULT,
2241 },
2242 };
2243 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2244 #else
2245 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2246 #endif
2247
2248 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2249 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2250 .info = &(struct s3c24xx_uart_info) {
2251 .name = "Samsung S3C6400 UART",
2252 .type = PORT_S3C6400,
2253 .fifosize = 64,
2254 .has_divslot = 1,
2255 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2256 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2257 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2258 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2259 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2260 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2261 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2262 .num_clks = 4,
2263 .clksel_mask = S3C6400_UCON_CLKMASK,
2264 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2265 },
2266 .def_cfg = &(struct s3c2410_uartcfg) {
2267 .ucon = S3C2410_UCON_DEFAULT,
2268 .ufcon = S3C2410_UFCON_DEFAULT,
2269 },
2270 };
2271 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2272 #else
2273 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2274 #endif
2275
2276 #ifdef CONFIG_CPU_S5PV210
2277 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2278 .info = &(struct s3c24xx_uart_info) {
2279 .name = "Samsung S5PV210 UART",
2280 .type = PORT_S3C6400,
2281 .has_divslot = 1,
2282 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2283 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2284 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2285 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2286 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2287 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2288 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2289 .num_clks = 2,
2290 .clksel_mask = S5PV210_UCON_CLKMASK,
2291 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2292 },
2293 .def_cfg = &(struct s3c2410_uartcfg) {
2294 .ucon = S5PV210_UCON_DEFAULT,
2295 .ufcon = S5PV210_UFCON_DEFAULT,
2296 },
2297 .fifosize = { 256, 64, 16, 16 },
2298 };
2299 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2300 #else
2301 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2302 #endif
2303
2304 #if defined(CONFIG_ARCH_EXYNOS)
2305 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2306 .info = &(struct s3c24xx_uart_info) { \
2307 .name = "Samsung Exynos UART", \
2308 .type = PORT_S3C6400, \
2309 .has_divslot = 1, \
2310 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2311 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2312 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2313 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2314 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2315 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2316 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2317 .num_clks = 1, \
2318 .clksel_mask = 0, \
2319 .clksel_shift = 0, \
2320 }, \
2321 .def_cfg = &(struct s3c2410_uartcfg) { \
2322 .ucon = S5PV210_UCON_DEFAULT, \
2323 .ufcon = S5PV210_UFCON_DEFAULT, \
2324 .has_fracval = 1, \
2325 } \
2326
2327 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2328 EXYNOS_COMMON_SERIAL_DRV_DATA,
2329 .fifosize = { 256, 64, 16, 16 },
2330 };
2331
2332 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2333 EXYNOS_COMMON_SERIAL_DRV_DATA,
2334 .fifosize = { 64, 256, 16, 256 },
2335 };
2336
2337 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2338 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2339 #else
2340 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2341 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2342 #endif
2343
2344 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2345 {
2346 .name = "s3c2410-uart",
2347 .driver_data = S3C2410_SERIAL_DRV_DATA,
2348 }, {
2349 .name = "s3c2412-uart",
2350 .driver_data = S3C2412_SERIAL_DRV_DATA,
2351 }, {
2352 .name = "s3c2440-uart",
2353 .driver_data = S3C2440_SERIAL_DRV_DATA,
2354 }, {
2355 .name = "s3c6400-uart",
2356 .driver_data = S3C6400_SERIAL_DRV_DATA,
2357 }, {
2358 .name = "s5pv210-uart",
2359 .driver_data = S5PV210_SERIAL_DRV_DATA,
2360 }, {
2361 .name = "exynos4210-uart",
2362 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2363 }, {
2364 .name = "exynos5433-uart",
2365 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2366 },
2367 { },
2368 };
2369 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2370
2371 #ifdef CONFIG_OF
2372 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2373 { .compatible = "samsung,s3c2410-uart",
2374 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2375 { .compatible = "samsung,s3c2412-uart",
2376 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2377 { .compatible = "samsung,s3c2440-uart",
2378 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2379 { .compatible = "samsung,s3c6400-uart",
2380 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2381 { .compatible = "samsung,s5pv210-uart",
2382 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2383 { .compatible = "samsung,exynos4210-uart",
2384 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2385 { .compatible = "samsung,exynos5433-uart",
2386 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2387 {},
2388 };
2389 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2390 #endif
2391
2392 static struct platform_driver samsung_serial_driver = {
2393 .probe = s3c24xx_serial_probe,
2394 .remove = s3c24xx_serial_remove,
2395 .id_table = s3c24xx_serial_driver_ids,
2396 .driver = {
2397 .name = "samsung-uart",
2398 .pm = SERIAL_SAMSUNG_PM_OPS,
2399 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2400 },
2401 };
2402
2403 module_platform_driver(samsung_serial_driver);
2404
2405 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2406 /*
2407 * Early console.
2408 */
2409
2410 struct samsung_early_console_data {
2411 u32 txfull_mask;
2412 };
2413
2414 static void samsung_early_busyuart(struct uart_port *port)
2415 {
2416 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2417 ;
2418 }
2419
2420 static void samsung_early_busyuart_fifo(struct uart_port *port)
2421 {
2422 struct samsung_early_console_data *data = port->private_data;
2423
2424 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2425 ;
2426 }
2427
2428 static void samsung_early_putc(struct uart_port *port, int c)
2429 {
2430 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2431 samsung_early_busyuart_fifo(port);
2432 else
2433 samsung_early_busyuart(port);
2434
2435 writeb(c, port->membase + S3C2410_UTXH);
2436 }
2437
2438 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2439 {
2440 struct earlycon_device *dev = con->data;
2441
2442 uart_console_write(&dev->port, s, n, samsung_early_putc);
2443 }
2444
2445 static int __init samsung_early_console_setup(struct earlycon_device *device,
2446 const char *opt)
2447 {
2448 if (!device->port.membase)
2449 return -ENODEV;
2450
2451 device->con->write = samsung_early_write;
2452 return 0;
2453 }
2454
2455 /* S3C2410 */
2456 static struct samsung_early_console_data s3c2410_early_console_data = {
2457 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2458 };
2459
2460 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2461 const char *opt)
2462 {
2463 device->port.private_data = &s3c2410_early_console_data;
2464 return samsung_early_console_setup(device, opt);
2465 }
2466 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2467 s3c2410_early_console_setup);
2468
2469 /* S3C2412, S3C2440, S3C64xx */
2470 static struct samsung_early_console_data s3c2440_early_console_data = {
2471 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2472 };
2473
2474 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2475 const char *opt)
2476 {
2477 device->port.private_data = &s3c2440_early_console_data;
2478 return samsung_early_console_setup(device, opt);
2479 }
2480 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2481 s3c2440_early_console_setup);
2482 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2483 s3c2440_early_console_setup);
2484 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2485 s3c2440_early_console_setup);
2486
2487 /* S5PV210, EXYNOS */
2488 static struct samsung_early_console_data s5pv210_early_console_data = {
2489 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2490 };
2491
2492 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2493 const char *opt)
2494 {
2495 device->port.private_data = &s5pv210_early_console_data;
2496 return samsung_early_console_setup(device, opt);
2497 }
2498 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2499 s5pv210_early_console_setup);
2500 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2501 s5pv210_early_console_setup);
2502 #endif
2503
2504 MODULE_ALIAS("platform:samsung-uart");
2505 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2506 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2507 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support