?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / sc16is7xx.c
blob793395451982d8e65d495345b9f8bfc17bd24e6c
1 /*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/regmap.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/spi/spi.h>
31 #include <linux/uaccess.h>
32
33 #define SC16IS7XX_NAME "sc16is7xx"
34 #define SC16IS7XX_MAX_DEVS 8
35
36 /* SC16IS7XX register definitions */
37 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
38 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
39 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
40 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
41 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
42 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
43 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
44 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
45 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
46 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
47 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
48 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
49 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
50 * - only on 75x/76x
51 */
52 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
53 * - only on 75x/76x
54 */
55 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
56 * - only on 75x/76x
57 */
58 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
59 * - only on 75x/76x
60 */
61 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
62
63 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
64 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
65 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
66
67 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
68 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
69 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
70
71 /* Enhanced Register set: Only if (LCR == 0xBF) */
72 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
73 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
74 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
75 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
76 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
77
78 /* IER register bits */
79 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
80 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
81 * interrupt */
82 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
83 * interrupt */
84 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
85 * interrupt */
86
87 /* IER register bits - write only if (EFR[4] == 1) */
88 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
89 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
90 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
91 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
92
93 /* FCR register bits */
94 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
95 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
96 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
97 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
98 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
99
100 /* FCR register bits - write only if (EFR[4] == 1) */
101 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
102 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
103
104 /* IIR register bits */
105 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
106 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
107 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
108 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
109 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
110 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
111 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
112 * - only on 75x/76x
113 */
114 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
115 * - only on 75x/76x
116 */
117 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
118 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 * from active (LOW)
120 * to inactive (HIGH)
121 */
122 /* LCR register bits */
123 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
124 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
125 *
126 * Word length bits table:
127 * 00 -> 5 bit words
128 * 01 -> 6 bit words
129 * 10 -> 7 bit words
130 * 11 -> 8 bit words
131 */
132 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
133 *
134 * STOP length bit table:
135 * 0 -> 1 stop bit
136 * 1 -> 1-1.5 stop bits if
137 * word length is 5,
138 * 2 stop bits otherwise
139 */
140 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
141 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
142 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
143 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
144 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
145 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
146 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
147 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
148 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
149 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
150 * reg set */
151 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
152 * reg set */
153
154 /* MCR register bits */
155 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
156 * - only on 75x/76x
157 */
158 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
159 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
160 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
161 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 * - write enabled
171 * if (EFR[4] == 1)
172 */
173
174 /* LSR register bits */
175 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
176 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
177 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
178 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
179 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
180 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
181 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
182 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
183 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
184
185 /* MSR register bits */
186 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
187 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 * or (IO4)
189 * - only on 75x/76x
190 */
191 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 * or (IO7)
193 * - only on 75x/76x
194 */
195 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 * or (IO6)
197 * - only on 75x/76x
198 */
199 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
200 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
201 * - only on 75x/76x
202 */
203 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
204 * - only on 75x/76x
205 */
206 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
207 * - only on 75x/76x
208 */
209 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210
211 /*
212 * TCR register bits
213 * TCR trigger levels are available from 0 to 60 characters with a granularity
214 * of four.
215 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
216 * no built-in hardware check to make sure this condition is met. Also, the TCR
217 * must be programmed with this condition before auto RTS or software flow
218 * control is enabled to avoid spurious operation of the device.
219 */
220 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
221 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222
223 /*
224 * TLR register bits
225 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
226 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
227 * trigger levels. Trigger levels from 4 characters to 60 characters are
228 * available with a granularity of four.
229 *
230 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
231 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
232 * the trigger level defined in FCR is discarded. This applies to both transmit
233 * FIFO and receive FIFO trigger level setting.
234 *
235 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
236 * default state, that is, '00'.
237 */
238 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
239 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
240
241 /* IOControl register bits (Only 750/760) */
242 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
243 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
244 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
245
246 /* EFCR register bits */
247 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
248 * mode (RS485) */
249 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
250 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
251 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
252 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
253 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
254 * 0 = rate upto 115.2 kbit/s
255 * - Only 750/760
256 * 1 = rate upto 1.152 Mbit/s
257 * - Only 760
258 */
259
260 /* EFR register bits */
261 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
262 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
263 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
264 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
265 * and writing to IER[7:4],
266 * FCR[5:4], MCR[7:5]
267 */
268 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
269 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
270 *
271 * SWFLOW bits 3 & 2 table:
272 * 00 -> no transmitter flow
273 * control
274 * 01 -> transmitter generates
275 * XON2 and XOFF2
276 * 10 -> transmitter generates
277 * XON1 and XOFF1
278 * 11 -> transmitter generates
279 * XON1, XON2, XOFF1 and
280 * XOFF2
281 */
282 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
283 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
284 *
285 * SWFLOW bits 3 & 2 table:
286 * 00 -> no received flow
287 * control
288 * 01 -> receiver compares
289 * XON2 and XOFF2
290 * 10 -> receiver compares
291 * XON1 and XOFF1
292 * 11 -> receiver compares
293 * XON1, XON2, XOFF1 and
294 * XOFF2
295 */
296
297 /* Misc definitions */
298 #define SC16IS7XX_FIFO_SIZE (64)
299 #define SC16IS7XX_REG_SHIFT 2
300
301 struct sc16is7xx_devtype {
302 char name[10];
303 int nr_gpio;
304 int nr_uart;
305 };
306
307 #define SC16IS7XX_RECONF_MD (1 << 0)
308 #define SC16IS7XX_RECONF_IER (1 << 1)
309 #define SC16IS7XX_RECONF_RS485 (1 << 2)
310
311 struct sc16is7xx_one_config {
312 unsigned int flags;
313 u8 ier_clear;
314 };
315
316 struct sc16is7xx_one {
317 struct uart_port port;
318 u8 line;
319 struct kthread_work tx_work;
320 struct kthread_work reg_work;
321 struct sc16is7xx_one_config config;
322 };
323
324 struct sc16is7xx_port {
325 const struct sc16is7xx_devtype *devtype;
326 struct regmap *regmap;
327 struct clk *clk;
328 #ifdef CONFIG_GPIOLIB
329 struct gpio_chip gpio;
330 #endif
331 unsigned char buf[SC16IS7XX_FIFO_SIZE];
332 struct kthread_worker kworker;
333 struct task_struct *kworker_task;
334 struct kthread_work irq_work;
335 struct sc16is7xx_one p[0];
336 };
337
338 static unsigned long sc16is7xx_lines;
339
340 static struct uart_driver sc16is7xx_uart = {
341 .owner = THIS_MODULE,
342 .dev_name = "ttySC",
343 .nr = SC16IS7XX_MAX_DEVS,
344 };
345
346 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
347 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
348
349 static int sc16is7xx_line(struct uart_port *port)
350 {
351 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
352
353 return one->line;
354 }
355
356 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
357 {
358 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
359 unsigned int val = 0;
360 const u8 line = sc16is7xx_line(port);
361
362 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
363
364 return val;
365 }
366
367 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
368 {
369 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
370 const u8 line = sc16is7xx_line(port);
371
372 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
373 }
374
375 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
376 {
377 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
378 const u8 line = sc16is7xx_line(port);
379 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
380
381 regcache_cache_bypass(s->regmap, true);
382 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
383 regcache_cache_bypass(s->regmap, false);
384 }
385
386 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
387 {
388 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
389 const u8 line = sc16is7xx_line(port);
390 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
391
392 /*
393 * Don't send zero-length data, at least on SPI it confuses the chip
394 * delivering wrong TXLVL data.
395 */
396 if (unlikely(!to_send))
397 return;
398
399 regcache_cache_bypass(s->regmap, true);
400 regmap_raw_write(s->regmap, addr, s->buf, to_send);
401 regcache_cache_bypass(s->regmap, false);
402 }
403
404 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
405 u8 mask, u8 val)
406 {
407 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
408 const u8 line = sc16is7xx_line(port);
409
410 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
411 mask, val);
412 }
413
414 static int sc16is7xx_alloc_line(void)
415 {
416 int i;
417
418 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
419
420 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
421 if (!test_and_set_bit(i, &sc16is7xx_lines))
422 break;
423
424 return i;
425 }
426
427 static void sc16is7xx_power(struct uart_port *port, int on)
428 {
429 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
430 SC16IS7XX_IER_SLEEP_BIT,
431 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
432 }
433
434 static const struct sc16is7xx_devtype sc16is74x_devtype = {
435 .name = "SC16IS74X",
436 .nr_gpio = 0,
437 .nr_uart = 1,
438 };
439
440 static const struct sc16is7xx_devtype sc16is750_devtype = {
441 .name = "SC16IS750",
442 .nr_gpio = 8,
443 .nr_uart = 1,
444 };
445
446 static const struct sc16is7xx_devtype sc16is752_devtype = {
447 .name = "SC16IS752",
448 .nr_gpio = 8,
449 .nr_uart = 2,
450 };
451
452 static const struct sc16is7xx_devtype sc16is760_devtype = {
453 .name = "SC16IS760",
454 .nr_gpio = 8,
455 .nr_uart = 1,
456 };
457
458 static const struct sc16is7xx_devtype sc16is762_devtype = {
459 .name = "SC16IS762",
460 .nr_gpio = 8,
461 .nr_uart = 2,
462 };
463
464 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
465 {
466 switch (reg >> SC16IS7XX_REG_SHIFT) {
467 case SC16IS7XX_RHR_REG:
468 case SC16IS7XX_IIR_REG:
469 case SC16IS7XX_LSR_REG:
470 case SC16IS7XX_MSR_REG:
471 case SC16IS7XX_TXLVL_REG:
472 case SC16IS7XX_RXLVL_REG:
473 case SC16IS7XX_IOSTATE_REG:
474 return true;
475 default:
476 break;
477 }
478
479 return false;
480 }
481
482 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
483 {
484 switch (reg >> SC16IS7XX_REG_SHIFT) {
485 case SC16IS7XX_RHR_REG:
486 return true;
487 default:
488 break;
489 }
490
491 return false;
492 }
493
494 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
495 {
496 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
497 u8 lcr;
498 u8 prescaler = 0;
499 unsigned long clk = port->uartclk, div = clk / 16 / baud;
500
501 if (div > 0xffff) {
502 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
503 div /= 4;
504 }
505
506 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
507
508 /* Open the LCR divisors for configuration */
509 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
510 SC16IS7XX_LCR_CONF_MODE_B);
511
512 /* Enable enhanced features */
513 regcache_cache_bypass(s->regmap, true);
514 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
515 SC16IS7XX_EFR_ENABLE_BIT);
516 regcache_cache_bypass(s->regmap, false);
517
518 /* Put LCR back to the normal mode */
519 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
520
521 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
522 SC16IS7XX_MCR_CLKSEL_BIT,
523 prescaler);
524
525 /* Open the LCR divisors for configuration */
526 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
527 SC16IS7XX_LCR_CONF_MODE_A);
528
529 /* Write the new divisor */
530 regcache_cache_bypass(s->regmap, true);
531 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
532 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
533 regcache_cache_bypass(s->regmap, false);
534
535 /* Put LCR back to the normal mode */
536 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
537
538 return DIV_ROUND_CLOSEST(clk / 16, div);
539 }
540
541 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
542 unsigned int iir)
543 {
544 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
545 unsigned int lsr = 0, ch, flag, bytes_read, i;
546 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
547
548 if (unlikely(rxlen >= sizeof(s->buf))) {
549 dev_warn_ratelimited(port->dev,
550 "ttySC%i: Possible RX FIFO overrun: %d\n",
551 port->line, rxlen);
552 port->icount.buf_overrun++;
553 /* Ensure sanity of RX level */
554 rxlen = sizeof(s->buf);
555 }
556
557 while (rxlen) {
558 /* Only read lsr if there are possible errors in FIFO */
559 if (read_lsr) {
560 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
561 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
562 read_lsr = false; /* No errors left in FIFO */
563 } else
564 lsr = 0;
565
566 if (read_lsr) {
567 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
568 bytes_read = 1;
569 } else {
570 sc16is7xx_fifo_read(port, rxlen);
571 bytes_read = rxlen;
572 }
573
574 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
575
576 port->icount.rx++;
577 flag = TTY_NORMAL;
578
579 if (unlikely(lsr)) {
580 if (lsr & SC16IS7XX_LSR_BI_BIT) {
581 port->icount.brk++;
582 if (uart_handle_break(port))
583 continue;
584 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
585 port->icount.parity++;
586 else if (lsr & SC16IS7XX_LSR_FE_BIT)
587 port->icount.frame++;
588 else if (lsr & SC16IS7XX_LSR_OE_BIT)
589 port->icount.overrun++;
590
591 lsr &= port->read_status_mask;
592 if (lsr & SC16IS7XX_LSR_BI_BIT)
593 flag = TTY_BREAK;
594 else if (lsr & SC16IS7XX_LSR_PE_BIT)
595 flag = TTY_PARITY;
596 else if (lsr & SC16IS7XX_LSR_FE_BIT)
597 flag = TTY_FRAME;
598 else if (lsr & SC16IS7XX_LSR_OE_BIT)
599 flag = TTY_OVERRUN;
600 }
601
602 for (i = 0; i < bytes_read; ++i) {
603 ch = s->buf[i];
604 if (uart_handle_sysrq_char(port, ch))
605 continue;
606
607 if (lsr & port->ignore_status_mask)
608 continue;
609
610 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
611 flag);
612 }
613 rxlen -= bytes_read;
614 }
615
616 tty_flip_buffer_push(&port->state->port);
617 }
618
619 static void sc16is7xx_handle_tx(struct uart_port *port)
620 {
621 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
622 struct circ_buf *xmit = &port->state->xmit;
623 unsigned int txlen, to_send, i;
624
625 if (unlikely(port->x_char)) {
626 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
627 port->icount.tx++;
628 port->x_char = 0;
629 return;
630 }
631
632 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
633 return;
634
635 /* Get length of data pending in circular buffer */
636 to_send = uart_circ_chars_pending(xmit);
637 if (likely(to_send)) {
638 /* Limit to size of TX FIFO */
639 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
640 if (txlen > SC16IS7XX_FIFO_SIZE) {
641 dev_err_ratelimited(port->dev,
642 "chip reports %d free bytes in TX fifo, but it only has %d",
643 txlen, SC16IS7XX_FIFO_SIZE);
644 txlen = 0;
645 }
646 to_send = (to_send > txlen) ? txlen : to_send;
647
648 /* Add data to send */
649 port->icount.tx += to_send;
650
651 /* Convert to linear buffer */
652 for (i = 0; i < to_send; ++i) {
653 s->buf[i] = xmit->buf[xmit->tail];
654 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
655 }
656
657 sc16is7xx_fifo_write(port, to_send);
658 }
659
660 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
661 uart_write_wakeup(port);
662 }
663
664 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
665 {
666 struct uart_port *port = &s->p[portno].port;
667
668 do {
669 unsigned int iir, rxlen;
670
671 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
672 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
673 break;
674
675 iir &= SC16IS7XX_IIR_ID_MASK;
676
677 switch (iir) {
678 case SC16IS7XX_IIR_RDI_SRC:
679 case SC16IS7XX_IIR_RLSE_SRC:
680 case SC16IS7XX_IIR_RTOI_SRC:
681 case SC16IS7XX_IIR_XOFFI_SRC:
682 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
683 if (rxlen)
684 sc16is7xx_handle_rx(port, rxlen, iir);
685 break;
686 case SC16IS7XX_IIR_THRI_SRC:
687 sc16is7xx_handle_tx(port);
688 break;
689 default:
690 dev_err_ratelimited(port->dev,
691 "ttySC%i: Unexpected interrupt: %x",
692 port->line, iir);
693 break;
694 }
695 } while (1);
696 }
697
698 static void sc16is7xx_ist(struct kthread_work *ws)
699 {
700 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
701 int i;
702
703 for (i = 0; i < s->devtype->nr_uart; ++i)
704 sc16is7xx_port_irq(s, i);
705 }
706
707 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
708 {
709 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
710
711 kthread_queue_work(&s->kworker, &s->irq_work);
712
713 return IRQ_HANDLED;
714 }
715
716 static void sc16is7xx_tx_proc(struct kthread_work *ws)
717 {
718 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
719
720 if ((port->rs485.flags & SER_RS485_ENABLED) &&
721 (port->rs485.delay_rts_before_send > 0))
722 msleep(port->rs485.delay_rts_before_send);
723
724 sc16is7xx_handle_tx(port);
725 }
726
727 static void sc16is7xx_reconf_rs485(struct uart_port *port)
728 {
729 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
730 SC16IS7XX_EFCR_RTS_INVERT_BIT;
731 u32 efcr = 0;
732 struct serial_rs485 *rs485 = &port->rs485;
733 unsigned long irqflags;
734
735 spin_lock_irqsave(&port->lock, irqflags);
736 if (rs485->flags & SER_RS485_ENABLED) {
737 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
738
739 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
740 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
741 }
742 spin_unlock_irqrestore(&port->lock, irqflags);
743
744 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
745 }
746
747 static void sc16is7xx_reg_proc(struct kthread_work *ws)
748 {
749 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
750 struct sc16is7xx_one_config config;
751 unsigned long irqflags;
752
753 spin_lock_irqsave(&one->port.lock, irqflags);
754 config = one->config;
755 memset(&one->config, 0, sizeof(one->config));
756 spin_unlock_irqrestore(&one->port.lock, irqflags);
757
758 if (config.flags & SC16IS7XX_RECONF_MD) {
759 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
760 SC16IS7XX_MCR_LOOP_BIT,
761 (one->port.mctrl & TIOCM_LOOP) ?
762 SC16IS7XX_MCR_LOOP_BIT : 0);
763 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
764 SC16IS7XX_MCR_RTS_BIT,
765 (one->port.mctrl & TIOCM_RTS) ?
766 SC16IS7XX_MCR_RTS_BIT : 0);
767 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
768 SC16IS7XX_MCR_DTR_BIT,
769 (one->port.mctrl & TIOCM_DTR) ?
770 SC16IS7XX_MCR_DTR_BIT : 0);
771 }
772 if (config.flags & SC16IS7XX_RECONF_IER)
773 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
774 config.ier_clear, 0);
775
776 if (config.flags & SC16IS7XX_RECONF_RS485)
777 sc16is7xx_reconf_rs485(&one->port);
778 }
779
780 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
781 {
782 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
783 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
784
785 one->config.flags |= SC16IS7XX_RECONF_IER;
786 one->config.ier_clear |= bit;
787 kthread_queue_work(&s->kworker, &one->reg_work);
788 }
789
790 static void sc16is7xx_stop_tx(struct uart_port *port)
791 {
792 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
793 }
794
795 static void sc16is7xx_stop_rx(struct uart_port *port)
796 {
797 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
798 }
799
800 static void sc16is7xx_start_tx(struct uart_port *port)
801 {
802 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
803 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
804
805 kthread_queue_work(&s->kworker, &one->tx_work);
806 }
807
808 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
809 {
810 unsigned int lsr;
811
812 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
813
814 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
815 }
816
817 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
818 {
819 /* DCD and DSR are not wired and CTS/RTS is handled automatically
820 * so just indicate DSR and CAR asserted
821 */
822 return TIOCM_DSR | TIOCM_CAR;
823 }
824
825 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
826 {
827 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
828 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
829
830 one->config.flags |= SC16IS7XX_RECONF_MD;
831 kthread_queue_work(&s->kworker, &one->reg_work);
832 }
833
834 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
835 {
836 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
837 SC16IS7XX_LCR_TXBREAK_BIT,
838 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
839 }
840
841 static void sc16is7xx_set_termios(struct uart_port *port,
842 struct ktermios *termios,
843 struct ktermios *old)
844 {
845 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
846 unsigned int lcr, flow = 0;
847 int baud;
848
849 /* Mask termios capabilities we don't support */
850 termios->c_cflag &= ~CMSPAR;
851
852 /* Word size */
853 switch (termios->c_cflag & CSIZE) {
854 case CS5:
855 lcr = SC16IS7XX_LCR_WORD_LEN_5;
856 break;
857 case CS6:
858 lcr = SC16IS7XX_LCR_WORD_LEN_6;
859 break;
860 case CS7:
861 lcr = SC16IS7XX_LCR_WORD_LEN_7;
862 break;
863 case CS8:
864 lcr = SC16IS7XX_LCR_WORD_LEN_8;
865 break;
866 default:
867 lcr = SC16IS7XX_LCR_WORD_LEN_8;
868 termios->c_cflag &= ~CSIZE;
869 termios->c_cflag |= CS8;
870 break;
871 }
872
873 /* Parity */
874 if (termios->c_cflag & PARENB) {
875 lcr |= SC16IS7XX_LCR_PARITY_BIT;
876 if (!(termios->c_cflag & PARODD))
877 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
878 }
879
880 /* Stop bits */
881 if (termios->c_cflag & CSTOPB)
882 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
883
884 /* Set read status mask */
885 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
886 if (termios->c_iflag & INPCK)
887 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
888 SC16IS7XX_LSR_FE_BIT;
889 if (termios->c_iflag & (BRKINT | PARMRK))
890 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
891
892 /* Set status ignore mask */
893 port->ignore_status_mask = 0;
894 if (termios->c_iflag & IGNBRK)
895 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
896 if (!(termios->c_cflag & CREAD))
897 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
898
899 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
900 SC16IS7XX_LCR_CONF_MODE_B);
901
902 /* Configure flow control */
903 regcache_cache_bypass(s->regmap, true);
904 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
905 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
906 if (termios->c_cflag & CRTSCTS)
907 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
908 SC16IS7XX_EFR_AUTORTS_BIT;
909 if (termios->c_iflag & IXON)
910 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
911 if (termios->c_iflag & IXOFF)
912 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
913
914 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
915 regcache_cache_bypass(s->regmap, false);
916
917 /* Update LCR register */
918 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
919
920 /* Get baud rate generator configuration */
921 baud = uart_get_baud_rate(port, termios, old,
922 port->uartclk / 16 / 4 / 0xffff,
923 port->uartclk / 16);
924
925 /* Setup baudrate generator */
926 baud = sc16is7xx_set_baud(port, baud);
927
928 /* Update timeout according to new baud rate */
929 uart_update_timeout(port, termios->c_cflag, baud);
930 }
931
932 static int sc16is7xx_config_rs485(struct uart_port *port,
933 struct serial_rs485 *rs485)
934 {
935 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
936 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
937
938 if (rs485->flags & SER_RS485_ENABLED) {
939 bool rts_during_rx, rts_during_tx;
940
941 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
942 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
943
944 if (rts_during_rx == rts_during_tx)
945 dev_err(port->dev,
946 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
947 rts_during_tx, rts_during_rx);
948
949 /*
950 * RTS signal is handled by HW, it's timing can't be influenced.
951 * However, it's sometimes useful to delay TX even without RTS
952 * control therefore we try to handle .delay_rts_before_send.
953 */
954 if (rs485->delay_rts_after_send)
955 return -EINVAL;
956 }
957
958 port->rs485 = *rs485;
959 one->config.flags |= SC16IS7XX_RECONF_RS485;
960 kthread_queue_work(&s->kworker, &one->reg_work);
961
962 return 0;
963 }
964
965 static int sc16is7xx_startup(struct uart_port *port)
966 {
967 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
968 unsigned int val;
969
970 sc16is7xx_power(port, 1);
971
972 /* Reset FIFOs*/
973 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
974 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
975 udelay(5);
976 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
977 SC16IS7XX_FCR_FIFO_BIT);
978
979 /* Enable EFR */
980 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
981 SC16IS7XX_LCR_CONF_MODE_B);
982
983 regcache_cache_bypass(s->regmap, true);
984
985 /* Enable write access to enhanced features and internal clock div */
986 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
987 SC16IS7XX_EFR_ENABLE_BIT);
988
989 /* Enable TCR/TLR */
990 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
991 SC16IS7XX_MCR_TCRTLR_BIT,
992 SC16IS7XX_MCR_TCRTLR_BIT);
993
994 /* Configure flow control levels */
995 /* Flow control halt level 48, resume level 24 */
996 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
997 SC16IS7XX_TCR_RX_RESUME(24) |
998 SC16IS7XX_TCR_RX_HALT(48));
999
1000 regcache_cache_bypass(s->regmap, false);
1001
1002 /* Now, initialize the UART */
1003 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1004
1005 /* Enable the Rx and Tx FIFO */
1006 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1007 SC16IS7XX_EFCR_RXDISABLE_BIT |
1008 SC16IS7XX_EFCR_TXDISABLE_BIT,
1009 0);
1010
1011 /* Enable RX, TX interrupts */
1012 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1013 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1014
1015 return 0;
1016 }
1017
1018 static void sc16is7xx_shutdown(struct uart_port *port)
1019 {
1020 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1021
1022 /* Disable all interrupts */
1023 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1024 /* Disable TX/RX */
1025 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1026 SC16IS7XX_EFCR_RXDISABLE_BIT |
1027 SC16IS7XX_EFCR_TXDISABLE_BIT,
1028 SC16IS7XX_EFCR_RXDISABLE_BIT |
1029 SC16IS7XX_EFCR_TXDISABLE_BIT);
1030
1031 sc16is7xx_power(port, 0);
1032
1033 kthread_flush_worker(&s->kworker);
1034 }
1035
1036 static const char *sc16is7xx_type(struct uart_port *port)
1037 {
1038 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1039
1040 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1041 }
1042
1043 static int sc16is7xx_request_port(struct uart_port *port)
1044 {
1045 /* Do nothing */
1046 return 0;
1047 }
1048
1049 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1050 {
1051 if (flags & UART_CONFIG_TYPE)
1052 port->type = PORT_SC16IS7XX;
1053 }
1054
1055 static int sc16is7xx_verify_port(struct uart_port *port,
1056 struct serial_struct *s)
1057 {
1058 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1059 return -EINVAL;
1060 if (s->irq != port->irq)
1061 return -EINVAL;
1062
1063 return 0;
1064 }
1065
1066 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1067 unsigned int oldstate)
1068 {
1069 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1070 }
1071
1072 static void sc16is7xx_null_void(struct uart_port *port)
1073 {
1074 /* Do nothing */
1075 }
1076
1077 static const struct uart_ops sc16is7xx_ops = {
1078 .tx_empty = sc16is7xx_tx_empty,
1079 .set_mctrl = sc16is7xx_set_mctrl,
1080 .get_mctrl = sc16is7xx_get_mctrl,
1081 .stop_tx = sc16is7xx_stop_tx,
1082 .start_tx = sc16is7xx_start_tx,
1083 .stop_rx = sc16is7xx_stop_rx,
1084 .break_ctl = sc16is7xx_break_ctl,
1085 .startup = sc16is7xx_startup,
1086 .shutdown = sc16is7xx_shutdown,
1087 .set_termios = sc16is7xx_set_termios,
1088 .type = sc16is7xx_type,
1089 .request_port = sc16is7xx_request_port,
1090 .release_port = sc16is7xx_null_void,
1091 .config_port = sc16is7xx_config_port,
1092 .verify_port = sc16is7xx_verify_port,
1093 .pm = sc16is7xx_pm,
1094 };
1095
1096 #ifdef CONFIG_GPIOLIB
1097 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1098 {
1099 unsigned int val;
1100 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1101 struct uart_port *port = &s->p[0].port;
1102
1103 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1104
1105 return !!(val & BIT(offset));
1106 }
1107
1108 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1109 {
1110 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1111 struct uart_port *port = &s->p[0].port;
1112
1113 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1114 val ? BIT(offset) : 0);
1115 }
1116
1117 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1118 unsigned offset)
1119 {
1120 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1121 struct uart_port *port = &s->p[0].port;
1122
1123 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1124
1125 return 0;
1126 }
1127
1128 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1129 unsigned offset, int val)
1130 {
1131 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1132 struct uart_port *port = &s->p[0].port;
1133 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1134
1135 if (val)
1136 state |= BIT(offset);
1137 else
1138 state &= ~BIT(offset);
1139 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1140 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1141 BIT(offset));
1142
1143 return 0;
1144 }
1145 #endif
1146
1147 static int sc16is7xx_probe(struct device *dev,
1148 const struct sc16is7xx_devtype *devtype,
1149 struct regmap *regmap, int irq, unsigned long flags)
1150 {
1151 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
1152 unsigned long freq, *pfreq = dev_get_platdata(dev);
1153 int i, ret;
1154 struct sc16is7xx_port *s;
1155
1156 if (IS_ERR(regmap))
1157 return PTR_ERR(regmap);
1158
1159 /* Alloc port structure */
1160 s = devm_kzalloc(dev, sizeof(*s) +
1161 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1162 GFP_KERNEL);
1163 if (!s) {
1164 dev_err(dev, "Error allocating port structure\n");
1165 return -ENOMEM;
1166 }
1167
1168 s->clk = devm_clk_get(dev, NULL);
1169 if (IS_ERR(s->clk)) {
1170 if (pfreq)
1171 freq = *pfreq;
1172 else
1173 return PTR_ERR(s->clk);
1174 } else {
1175 clk_prepare_enable(s->clk);
1176 freq = clk_get_rate(s->clk);
1177 }
1178
1179 s->regmap = regmap;
1180 s->devtype = devtype;
1181 dev_set_drvdata(dev, s);
1182
1183 kthread_init_worker(&s->kworker);
1184 kthread_init_work(&s->irq_work, sc16is7xx_ist);
1185 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1186 "sc16is7xx");
1187 if (IS_ERR(s->kworker_task)) {
1188 ret = PTR_ERR(s->kworker_task);
1189 goto out_clk;
1190 }
1191 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1192
1193 #ifdef CONFIG_GPIOLIB
1194 if (devtype->nr_gpio) {
1195 /* Setup GPIO cotroller */
1196 s->gpio.owner = THIS_MODULE;
1197 s->gpio.parent = dev;
1198 s->gpio.label = dev_name(dev);
1199 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1200 s->gpio.get = sc16is7xx_gpio_get;
1201 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1202 s->gpio.set = sc16is7xx_gpio_set;
1203 s->gpio.base = -1;
1204 s->gpio.ngpio = devtype->nr_gpio;
1205 s->gpio.can_sleep = 1;
1206 ret = gpiochip_add_data(&s->gpio, s);
1207 if (ret)
1208 goto out_thread;
1209 }
1210 #endif
1211
1212 /* reset device, purging any pending irq / data */
1213 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1214 SC16IS7XX_IOCONTROL_SRESET_BIT);
1215
1216 for (i = 0; i < devtype->nr_uart; ++i) {
1217 s->p[i].line = i;
1218 /* Initialize port data */
1219 s->p[i].port.dev = dev;
1220 s->p[i].port.irq = irq;
1221 s->p[i].port.type = PORT_SC16IS7XX;
1222 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1223 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1224 s->p[i].port.iotype = UPIO_PORT;
1225 s->p[i].port.uartclk = freq;
1226 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1227 s->p[i].port.ops = &sc16is7xx_ops;
1228 s->p[i].port.line = sc16is7xx_alloc_line();
1229 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1230 ret = -ENOMEM;
1231 goto out_ports;
1232 }
1233
1234 /* Disable all interrupts */
1235 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1236 /* Disable TX/RX */
1237 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1238 SC16IS7XX_EFCR_RXDISABLE_BIT |
1239 SC16IS7XX_EFCR_TXDISABLE_BIT);
1240 /* Initialize kthread work structs */
1241 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1242 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1243 /* Register port */
1244 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1245
1246 /* Enable EFR */
1247 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1248 SC16IS7XX_LCR_CONF_MODE_B);
1249
1250 regcache_cache_bypass(s->regmap, true);
1251
1252 /* Enable write access to enhanced features */
1253 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1254 SC16IS7XX_EFR_ENABLE_BIT);
1255
1256 regcache_cache_bypass(s->regmap, false);
1257
1258 /* Restore access to general registers */
1259 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1260
1261 /* Go to suspend mode */
1262 sc16is7xx_power(&s->p[i].port, 0);
1263 }
1264
1265 /* Setup interrupt */
1266 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1267 flags, dev_name(dev), s);
1268 if (!ret)
1269 return 0;
1270
1271 out_ports:
1272 for (i--; i >= 0; i--) {
1273 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1274 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1275 }
1276
1277 #ifdef CONFIG_GPIOLIB
1278 if (devtype->nr_gpio)
1279 gpiochip_remove(&s->gpio);
1280
1281 out_thread:
1282 #endif
1283 kthread_stop(s->kworker_task);
1284
1285 out_clk:
1286 if (!IS_ERR(s->clk))
1287 clk_disable_unprepare(s->clk);
1288
1289 return ret;
1290 }
1291
1292 static int sc16is7xx_remove(struct device *dev)
1293 {
1294 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1295 int i;
1296
1297 #ifdef CONFIG_GPIOLIB
1298 if (s->devtype->nr_gpio)
1299 gpiochip_remove(&s->gpio);
1300 #endif
1301
1302 for (i = 0; i < s->devtype->nr_uart; i++) {
1303 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1304 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1305 sc16is7xx_power(&s->p[i].port, 0);
1306 }
1307
1308 kthread_flush_worker(&s->kworker);
1309 kthread_stop(s->kworker_task);
1310
1311 if (!IS_ERR(s->clk))
1312 clk_disable_unprepare(s->clk);
1313
1314 return 0;
1315 }
1316
1317 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1318 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1319 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1320 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1321 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1322 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1323 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1324 { }
1325 };
1326 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1327
1328 static struct regmap_config regcfg = {
1329 .reg_bits = 7,
1330 .pad_bits = 1,
1331 .val_bits = 8,
1332 .cache_type = REGCACHE_RBTREE,
1333 .volatile_reg = sc16is7xx_regmap_volatile,
1334 .precious_reg = sc16is7xx_regmap_precious,
1335 };
1336
1337 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1338 static int sc16is7xx_spi_probe(struct spi_device *spi)
1339 {
1340 const struct sc16is7xx_devtype *devtype;
1341 unsigned long flags = 0;
1342 struct regmap *regmap;
1343 int ret;
1344
1345 /* Setup SPI bus */
1346 spi->bits_per_word = 8;
1347 /* only supports mode 0 on SC16IS762 */
1348 spi->mode = spi->mode ? : SPI_MODE_0;
1349 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1350 ret = spi_setup(spi);
1351 if (ret)
1352 return ret;
1353
1354 if (spi->dev.of_node) {
1355 const struct of_device_id *of_id =
1356 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1357
1358 if (!of_id)
1359 return -ENODEV;
1360
1361 devtype = (struct sc16is7xx_devtype *)of_id->data;
1362 } else {
1363 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1364
1365 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1366 flags = IRQF_TRIGGER_FALLING;
1367 }
1368
1369 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1370 (devtype->nr_uart - 1);
1371 regmap = devm_regmap_init_spi(spi, &regcfg);
1372
1373 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1374 }
1375
1376 static int sc16is7xx_spi_remove(struct spi_device *spi)
1377 {
1378 return sc16is7xx_remove(&spi->dev);
1379 }
1380
1381 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1382 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1383 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1384 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1385 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1386 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1387 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1388 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1389 { }
1390 };
1391
1392 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1393
1394 static struct spi_driver sc16is7xx_spi_uart_driver = {
1395 .driver = {
1396 .name = SC16IS7XX_NAME,
1397 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1398 },
1399 .probe = sc16is7xx_spi_probe,
1400 .remove = sc16is7xx_spi_remove,
1401 .id_table = sc16is7xx_spi_id_table,
1402 };
1403
1404 MODULE_ALIAS("spi:sc16is7xx");
1405 #endif
1406
1407 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1408 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1409 const struct i2c_device_id *id)
1410 {
1411 const struct sc16is7xx_devtype *devtype;
1412 unsigned long flags = 0;
1413 struct regmap *regmap;
1414
1415 if (i2c->dev.of_node) {
1416 const struct of_device_id *of_id =
1417 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1418
1419 if (!of_id)
1420 return -ENODEV;
1421
1422 devtype = (struct sc16is7xx_devtype *)of_id->data;
1423 } else {
1424 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1425 flags = IRQF_TRIGGER_FALLING;
1426 }
1427
1428 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1429 (devtype->nr_uart - 1);
1430 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1431
1432 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1433 }
1434
1435 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1436 {
1437 return sc16is7xx_remove(&client->dev);
1438 }
1439
1440 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1441 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1442 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1443 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1444 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1445 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1446 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1447 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1448 { }
1449 };
1450 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1451
1452 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1453 .driver = {
1454 .name = SC16IS7XX_NAME,
1455 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1456 },
1457 .probe = sc16is7xx_i2c_probe,
1458 .remove = sc16is7xx_i2c_remove,
1459 .id_table = sc16is7xx_i2c_id_table,
1460 };
1461
1462 #endif
1463
1464 static int __init sc16is7xx_init(void)
1465 {
1466 int ret;
1467
1468 ret = uart_register_driver(&sc16is7xx_uart);
1469 if (ret) {
1470 pr_err("Registering UART driver failed\n");
1471 return ret;
1472 }
1473
1474 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1475 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1476 if (ret < 0) {
1477 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1478 return ret;
1479 }
1480 #endif
1481
1482 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1483 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1484 if (ret < 0) {
1485 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1486 return ret;
1487 }
1488 #endif
1489 return ret;
1490 }
1491 module_init(sc16is7xx_init);
1492
1493 static void __exit sc16is7xx_exit(void)
1494 {
1495 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1496 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1497 #endif
1498
1499 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1500 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1501 #endif
1502 uart_unregister_driver(&sc16is7xx_uart);
1503 }
1504 module_exit(sc16is7xx_exit);
1505
1506 MODULE_LICENSE("GPL");
1507 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1508 MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux with added FPC-III support