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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / sunzilog.c
blob8b6ace3410292f407f9974552db4b8ef1a4d51c6
1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35 #include <linux/of_device.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/setup.h>
41
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47 #include <linux/sunserialcore.h>
48
49 #include "sunzilog.h"
50
51 /* On 32-bit sparcs we need to delay after register accesses
52 * to accommodate sun4 systems, but we do not need to flush writes.
53 * On 64-bit sparc we only need to flush single writes to ensure
54 * completion.
55 */
56 #ifndef CONFIG_SPARC64
57 #define ZSDELAY() udelay(5)
58 #define ZSDELAY_LONG() udelay(20)
59 #define ZS_WSYNC(channel) do { } while (0)
60 #else
61 #define ZSDELAY()
62 #define ZSDELAY_LONG()
63 #define ZS_WSYNC(__channel) \
64 readb(&((__channel)->control))
65 #endif
66
67 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
68 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
69
70 /*
71 * We wrap our port structure around the generic uart_port.
72 */
73 struct uart_sunzilog_port {
74 struct uart_port port;
75
76 /* IRQ servicing chain. */
77 struct uart_sunzilog_port *next;
78
79 /* Current values of Zilog write registers. */
80 unsigned char curregs[NUM_ZSREGS];
81
82 unsigned int flags;
83 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
84 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
85 #define SUNZILOG_FLAG_IS_CONS 0x00000004
86 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
87 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
88 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
89 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
90 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
91 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
92 #define SUNZILOG_FLAG_ESCC 0x00000200
93 #define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
94
95 unsigned int cflag;
96
97 unsigned char parity_mask;
98 unsigned char prev_status;
99
100 #ifdef CONFIG_SERIO
101 struct serio serio;
102 int serio_open;
103 #endif
104 };
105
106 static void sunzilog_putchar(struct uart_port *port, int ch);
107
108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
109 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
110
111 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
113 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
114 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
115 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
116 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
117 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
118 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
119 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
120
121 /* Reading and writing Zilog8530 registers. The delays are to make this
122 * driver work on the Sun4 which needs a settling delay after each chip
123 * register access, other machines handle this in hardware via auxiliary
124 * flip-flops which implement the settle time we do in software.
125 *
126 * The port lock must be held and local IRQs must be disabled
127 * when {read,write}_zsreg is invoked.
128 */
129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
130 unsigned char reg)
131 {
132 unsigned char retval;
133
134 writeb(reg, &channel->control);
135 ZSDELAY();
136 retval = readb(&channel->control);
137 ZSDELAY();
138
139 return retval;
140 }
141
142 static void write_zsreg(struct zilog_channel __iomem *channel,
143 unsigned char reg, unsigned char value)
144 {
145 writeb(reg, &channel->control);
146 ZSDELAY();
147 writeb(value, &channel->control);
148 ZSDELAY();
149 }
150
151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
152 {
153 int i;
154
155 for (i = 0; i < 32; i++) {
156 unsigned char regval;
157
158 regval = readb(&channel->control);
159 ZSDELAY();
160 if (regval & Rx_CH_AV)
161 break;
162
163 regval = read_zsreg(channel, R1);
164 readb(&channel->data);
165 ZSDELAY();
166
167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
168 writeb(ERR_RES, &channel->control);
169 ZSDELAY();
170 ZS_WSYNC(channel);
171 }
172 }
173 }
174
175 /* This function must only be called when the TX is not busy. The UART
176 * port lock must be held and local interrupts disabled.
177 */
178 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
179 {
180 int i;
181 int escc;
182 unsigned char r15;
183
184 /* Let pending transmits finish. */
185 for (i = 0; i < 1000; i++) {
186 unsigned char stat = read_zsreg(channel, R1);
187 if (stat & ALL_SNT)
188 break;
189 udelay(100);
190 }
191
192 writeb(ERR_RES, &channel->control);
193 ZSDELAY();
194 ZS_WSYNC(channel);
195
196 sunzilog_clear_fifo(channel);
197
198 /* Disable all interrupts. */
199 write_zsreg(channel, R1,
200 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
201
202 /* Set parity, sync config, stop bits, and clock divisor. */
203 write_zsreg(channel, R4, regs[R4]);
204
205 /* Set misc. TX/RX control bits. */
206 write_zsreg(channel, R10, regs[R10]);
207
208 /* Set TX/RX controls sans the enable bits. */
209 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
210 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
211
212 /* Synchronous mode config. */
213 write_zsreg(channel, R6, regs[R6]);
214 write_zsreg(channel, R7, regs[R7]);
215
216 /* Don't mess with the interrupt vector (R2, unused by us) and
217 * master interrupt control (R9). We make sure this is setup
218 * properly at probe time then never touch it again.
219 */
220
221 /* Disable baud generator. */
222 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
223
224 /* Clock mode control. */
225 write_zsreg(channel, R11, regs[R11]);
226
227 /* Lower and upper byte of baud rate generator divisor. */
228 write_zsreg(channel, R12, regs[R12]);
229 write_zsreg(channel, R13, regs[R13]);
230
231 /* Now rewrite R14, with BRENAB (if set). */
232 write_zsreg(channel, R14, regs[R14]);
233
234 /* External status interrupt control. */
235 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
236
237 /* ESCC Extension Register */
238 r15 = read_zsreg(channel, R15);
239 if (r15 & 0x01) {
240 write_zsreg(channel, R7, regs[R7p]);
241
242 /* External status interrupt and FIFO control. */
243 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
244 escc = 1;
245 } else {
246 /* Clear FIFO bit case it is an issue */
247 regs[R15] &= ~FIFOEN;
248 escc = 0;
249 }
250
251 /* Reset external status interrupts. */
252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
254
255 /* Rewrite R3/R5, this time without enables masked. */
256 write_zsreg(channel, R3, regs[R3]);
257 write_zsreg(channel, R5, regs[R5]);
258
259 /* Rewrite R1, this time without IRQ enabled masked. */
260 write_zsreg(channel, R1, regs[R1]);
261
262 return escc;
263 }
264
265 /* Reprogram the Zilog channel HW registers with the copies found in the
266 * software state struct. If the transmitter is busy, we defer this update
267 * until the next TX complete interrupt. Else, we do it right now.
268 *
269 * The UART port lock must be held and local interrupts disabled.
270 */
271 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
272 struct zilog_channel __iomem *channel)
273 {
274 if (!ZS_REGS_HELD(up)) {
275 if (ZS_TX_ACTIVE(up)) {
276 up->flags |= SUNZILOG_FLAG_REGS_HELD;
277 } else {
278 __load_zsregs(channel, up->curregs);
279 }
280 }
281 }
282
283 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
284 {
285 unsigned int cur_cflag = up->cflag;
286 int brg, new_baud;
287
288 up->cflag &= ~CBAUD;
289 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
290
291 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
292 up->curregs[R12] = (brg & 0xff);
293 up->curregs[R13] = (brg >> 8) & 0xff;
294 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
295 }
296
297 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
298 unsigned char ch, int is_break)
299 {
300 if (ZS_IS_KEYB(up)) {
301 /* Stop-A is handled by drivers/char/keyboard.c now. */
302 #ifdef CONFIG_SERIO
303 if (up->serio_open)
304 serio_interrupt(&up->serio, ch, 0);
305 #endif
306 } else if (ZS_IS_MOUSE(up)) {
307 int ret = suncore_mouse_baud_detection(ch, is_break);
308
309 switch (ret) {
310 case 2:
311 sunzilog_change_mouse_baud(up);
312 /* fallthru */
313 case 1:
314 break;
315
316 case 0:
317 #ifdef CONFIG_SERIO
318 if (up->serio_open)
319 serio_interrupt(&up->serio, ch, 0);
320 #endif
321 break;
322 }
323 }
324 }
325
326 static struct tty_port *
327 sunzilog_receive_chars(struct uart_sunzilog_port *up,
328 struct zilog_channel __iomem *channel)
329 {
330 struct tty_port *port = NULL;
331 unsigned char ch, r1, flag;
332
333 if (up->port.state != NULL) /* Unopened serial console */
334 port = &up->port.state->port;
335
336 for (;;) {
337
338 r1 = read_zsreg(channel, R1);
339 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
340 writeb(ERR_RES, &channel->control);
341 ZSDELAY();
342 ZS_WSYNC(channel);
343 }
344
345 ch = readb(&channel->control);
346 ZSDELAY();
347
348 /* This funny hack depends upon BRK_ABRT not interfering
349 * with the other bits we care about in R1.
350 */
351 if (ch & BRK_ABRT)
352 r1 |= BRK_ABRT;
353
354 if (!(ch & Rx_CH_AV))
355 break;
356
357 ch = readb(&channel->data);
358 ZSDELAY();
359
360 ch &= up->parity_mask;
361
362 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
363 sunzilog_kbdms_receive_chars(up, ch, 0);
364 continue;
365 }
366
367 /* A real serial line, record the character and status. */
368 flag = TTY_NORMAL;
369 up->port.icount.rx++;
370 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
371 if (r1 & BRK_ABRT) {
372 r1 &= ~(PAR_ERR | CRC_ERR);
373 up->port.icount.brk++;
374 if (uart_handle_break(&up->port))
375 continue;
376 }
377 else if (r1 & PAR_ERR)
378 up->port.icount.parity++;
379 else if (r1 & CRC_ERR)
380 up->port.icount.frame++;
381 if (r1 & Rx_OVR)
382 up->port.icount.overrun++;
383 r1 &= up->port.read_status_mask;
384 if (r1 & BRK_ABRT)
385 flag = TTY_BREAK;
386 else if (r1 & PAR_ERR)
387 flag = TTY_PARITY;
388 else if (r1 & CRC_ERR)
389 flag = TTY_FRAME;
390 }
391 if (uart_handle_sysrq_char(&up->port, ch) || !port)
392 continue;
393
394 if (up->port.ignore_status_mask == 0xff ||
395 (r1 & up->port.ignore_status_mask) == 0) {
396 tty_insert_flip_char(port, ch, flag);
397 }
398 if (r1 & Rx_OVR)
399 tty_insert_flip_char(port, 0, TTY_OVERRUN);
400 }
401
402 return port;
403 }
404
405 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
406 struct zilog_channel __iomem *channel)
407 {
408 unsigned char status;
409
410 status = readb(&channel->control);
411 ZSDELAY();
412
413 writeb(RES_EXT_INT, &channel->control);
414 ZSDELAY();
415 ZS_WSYNC(channel);
416
417 if (status & BRK_ABRT) {
418 if (ZS_IS_MOUSE(up))
419 sunzilog_kbdms_receive_chars(up, 0, 1);
420 if (ZS_IS_CONS(up)) {
421 /* Wait for BREAK to deassert to avoid potentially
422 * confusing the PROM.
423 */
424 while (1) {
425 status = readb(&channel->control);
426 ZSDELAY();
427 if (!(status & BRK_ABRT))
428 break;
429 }
430 sun_do_break();
431 return;
432 }
433 }
434
435 if (ZS_WANTS_MODEM_STATUS(up)) {
436 if (status & SYNC)
437 up->port.icount.dsr++;
438
439 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
440 * But it does not tell us which bit has changed, we have to keep
441 * track of this ourselves.
442 */
443 if ((status ^ up->prev_status) ^ DCD)
444 uart_handle_dcd_change(&up->port,
445 (status & DCD));
446 if ((status ^ up->prev_status) ^ CTS)
447 uart_handle_cts_change(&up->port,
448 (status & CTS));
449
450 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
451 }
452
453 up->prev_status = status;
454 }
455
456 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
457 struct zilog_channel __iomem *channel)
458 {
459 struct circ_buf *xmit;
460
461 if (ZS_IS_CONS(up)) {
462 unsigned char status = readb(&channel->control);
463 ZSDELAY();
464
465 /* TX still busy? Just wait for the next TX done interrupt.
466 *
467 * It can occur because of how we do serial console writes. It would
468 * be nice to transmit console writes just like we normally would for
469 * a TTY line. (ie. buffered and TX interrupt driven). That is not
470 * easy because console writes cannot sleep. One solution might be
471 * to poll on enough port->xmit space becoming free. -DaveM
472 */
473 if (!(status & Tx_BUF_EMP))
474 return;
475 }
476
477 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
478
479 if (ZS_REGS_HELD(up)) {
480 __load_zsregs(channel, up->curregs);
481 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
482 }
483
484 if (ZS_TX_STOPPED(up)) {
485 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
486 goto ack_tx_int;
487 }
488
489 if (up->port.x_char) {
490 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
491 writeb(up->port.x_char, &channel->data);
492 ZSDELAY();
493 ZS_WSYNC(channel);
494
495 up->port.icount.tx++;
496 up->port.x_char = 0;
497 return;
498 }
499
500 if (up->port.state == NULL)
501 goto ack_tx_int;
502 xmit = &up->port.state->xmit;
503 if (uart_circ_empty(xmit))
504 goto ack_tx_int;
505
506 if (uart_tx_stopped(&up->port))
507 goto ack_tx_int;
508
509 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
510 writeb(xmit->buf[xmit->tail], &channel->data);
511 ZSDELAY();
512 ZS_WSYNC(channel);
513
514 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
515 up->port.icount.tx++;
516
517 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 uart_write_wakeup(&up->port);
519
520 return;
521
522 ack_tx_int:
523 writeb(RES_Tx_P, &channel->control);
524 ZSDELAY();
525 ZS_WSYNC(channel);
526 }
527
528 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
529 {
530 struct uart_sunzilog_port *up = dev_id;
531
532 while (up) {
533 struct zilog_channel __iomem *channel
534 = ZILOG_CHANNEL_FROM_PORT(&up->port);
535 struct tty_port *port;
536 unsigned char r3;
537
538 spin_lock(&up->port.lock);
539 r3 = read_zsreg(channel, R3);
540
541 /* Channel A */
542 port = NULL;
543 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
544 writeb(RES_H_IUS, &channel->control);
545 ZSDELAY();
546 ZS_WSYNC(channel);
547
548 if (r3 & CHARxIP)
549 port = sunzilog_receive_chars(up, channel);
550 if (r3 & CHAEXT)
551 sunzilog_status_handle(up, channel);
552 if (r3 & CHATxIP)
553 sunzilog_transmit_chars(up, channel);
554 }
555 spin_unlock(&up->port.lock);
556
557 if (port)
558 tty_flip_buffer_push(port);
559
560 /* Channel B */
561 up = up->next;
562 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
563
564 spin_lock(&up->port.lock);
565 port = NULL;
566 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
567 writeb(RES_H_IUS, &channel->control);
568 ZSDELAY();
569 ZS_WSYNC(channel);
570
571 if (r3 & CHBRxIP)
572 port = sunzilog_receive_chars(up, channel);
573 if (r3 & CHBEXT)
574 sunzilog_status_handle(up, channel);
575 if (r3 & CHBTxIP)
576 sunzilog_transmit_chars(up, channel);
577 }
578 spin_unlock(&up->port.lock);
579
580 if (port)
581 tty_flip_buffer_push(port);
582
583 up = up->next;
584 }
585
586 return IRQ_HANDLED;
587 }
588
589 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
590 * port lock, it is acquired here.
591 */
592 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
593 {
594 struct zilog_channel __iomem *channel;
595 unsigned char status;
596
597 channel = ZILOG_CHANNEL_FROM_PORT(port);
598 status = readb(&channel->control);
599 ZSDELAY();
600
601 return status;
602 }
603
604 /* The port lock is not held. */
605 static unsigned int sunzilog_tx_empty(struct uart_port *port)
606 {
607 unsigned long flags;
608 unsigned char status;
609 unsigned int ret;
610
611 spin_lock_irqsave(&port->lock, flags);
612
613 status = sunzilog_read_channel_status(port);
614
615 spin_unlock_irqrestore(&port->lock, flags);
616
617 if (status & Tx_BUF_EMP)
618 ret = TIOCSER_TEMT;
619 else
620 ret = 0;
621
622 return ret;
623 }
624
625 /* The port lock is held and interrupts are disabled. */
626 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
627 {
628 unsigned char status;
629 unsigned int ret;
630
631 status = sunzilog_read_channel_status(port);
632
633 ret = 0;
634 if (status & DCD)
635 ret |= TIOCM_CAR;
636 if (status & SYNC)
637 ret |= TIOCM_DSR;
638 if (status & CTS)
639 ret |= TIOCM_CTS;
640
641 return ret;
642 }
643
644 /* The port lock is held and interrupts are disabled. */
645 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
646 {
647 struct uart_sunzilog_port *up =
648 container_of(port, struct uart_sunzilog_port, port);
649 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
650 unsigned char set_bits, clear_bits;
651
652 set_bits = clear_bits = 0;
653
654 if (mctrl & TIOCM_RTS)
655 set_bits |= RTS;
656 else
657 clear_bits |= RTS;
658 if (mctrl & TIOCM_DTR)
659 set_bits |= DTR;
660 else
661 clear_bits |= DTR;
662
663 /* NOTE: Not subject to 'transmitter active' rule. */
664 up->curregs[R5] |= set_bits;
665 up->curregs[R5] &= ~clear_bits;
666 write_zsreg(channel, R5, up->curregs[R5]);
667 }
668
669 /* The port lock is held and interrupts are disabled. */
670 static void sunzilog_stop_tx(struct uart_port *port)
671 {
672 struct uart_sunzilog_port *up =
673 container_of(port, struct uart_sunzilog_port, port);
674
675 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
676 }
677
678 /* The port lock is held and interrupts are disabled. */
679 static void sunzilog_start_tx(struct uart_port *port)
680 {
681 struct uart_sunzilog_port *up =
682 container_of(port, struct uart_sunzilog_port, port);
683 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
684 unsigned char status;
685
686 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
687 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
688
689 status = readb(&channel->control);
690 ZSDELAY();
691
692 /* TX busy? Just wait for the TX done interrupt. */
693 if (!(status & Tx_BUF_EMP))
694 return;
695
696 /* Send the first character to jump-start the TX done
697 * IRQ sending engine.
698 */
699 if (port->x_char) {
700 writeb(port->x_char, &channel->data);
701 ZSDELAY();
702 ZS_WSYNC(channel);
703
704 port->icount.tx++;
705 port->x_char = 0;
706 } else {
707 struct circ_buf *xmit = &port->state->xmit;
708
709 if (uart_circ_empty(xmit))
710 return;
711 writeb(xmit->buf[xmit->tail], &channel->data);
712 ZSDELAY();
713 ZS_WSYNC(channel);
714
715 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
716 port->icount.tx++;
717
718 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
719 uart_write_wakeup(&up->port);
720 }
721 }
722
723 /* The port lock is held. */
724 static void sunzilog_stop_rx(struct uart_port *port)
725 {
726 struct uart_sunzilog_port *up = UART_ZILOG(port);
727 struct zilog_channel __iomem *channel;
728
729 if (ZS_IS_CONS(up))
730 return;
731
732 channel = ZILOG_CHANNEL_FROM_PORT(port);
733
734 /* Disable all RX interrupts. */
735 up->curregs[R1] &= ~RxINT_MASK;
736 sunzilog_maybe_update_regs(up, channel);
737 }
738
739 /* The port lock is held. */
740 static void sunzilog_enable_ms(struct uart_port *port)
741 {
742 struct uart_sunzilog_port *up =
743 container_of(port, struct uart_sunzilog_port, port);
744 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
745 unsigned char new_reg;
746
747 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
748 if (new_reg != up->curregs[R15]) {
749 up->curregs[R15] = new_reg;
750
751 /* NOTE: Not subject to 'transmitter active' rule. */
752 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
753 }
754 }
755
756 /* The port lock is not held. */
757 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
758 {
759 struct uart_sunzilog_port *up =
760 container_of(port, struct uart_sunzilog_port, port);
761 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
762 unsigned char set_bits, clear_bits, new_reg;
763 unsigned long flags;
764
765 set_bits = clear_bits = 0;
766
767 if (break_state)
768 set_bits |= SND_BRK;
769 else
770 clear_bits |= SND_BRK;
771
772 spin_lock_irqsave(&port->lock, flags);
773
774 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
775 if (new_reg != up->curregs[R5]) {
776 up->curregs[R5] = new_reg;
777
778 /* NOTE: Not subject to 'transmitter active' rule. */
779 write_zsreg(channel, R5, up->curregs[R5]);
780 }
781
782 spin_unlock_irqrestore(&port->lock, flags);
783 }
784
785 static void __sunzilog_startup(struct uart_sunzilog_port *up)
786 {
787 struct zilog_channel __iomem *channel;
788
789 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
790 up->prev_status = readb(&channel->control);
791
792 /* Enable receiver and transmitter. */
793 up->curregs[R3] |= RxENAB;
794 up->curregs[R5] |= TxENAB;
795
796 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
797 sunzilog_maybe_update_regs(up, channel);
798 }
799
800 static int sunzilog_startup(struct uart_port *port)
801 {
802 struct uart_sunzilog_port *up = UART_ZILOG(port);
803 unsigned long flags;
804
805 if (ZS_IS_CONS(up))
806 return 0;
807
808 spin_lock_irqsave(&port->lock, flags);
809 __sunzilog_startup(up);
810 spin_unlock_irqrestore(&port->lock, flags);
811 return 0;
812 }
813
814 /*
815 * The test for ZS_IS_CONS is explained by the following e-mail:
816 *****
817 * From: Russell King <rmk@arm.linux.org.uk>
818 * Date: Sun, 8 Dec 2002 10:18:38 +0000
819 *
820 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
821 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
822 * > and I noticed that something is not right with reference
823 * > counting in this case. It seems that when the console
824 * > is open by kernel initially, this is not accounted
825 * > as an open, and uart_startup is not called.
826 *
827 * That is correct. We are unable to call uart_startup when the serial
828 * console is initialised because it may need to allocate memory (as
829 * request_irq does) and the memory allocators may not have been
830 * initialised.
831 *
832 * 1. initialise the port into a state where it can send characters in the
833 * console write method.
834 *
835 * 2. don't do the actual hardware shutdown in your shutdown() method (but
836 * do the normal software shutdown - ie, free irqs etc)
837 *****
838 */
839 static void sunzilog_shutdown(struct uart_port *port)
840 {
841 struct uart_sunzilog_port *up = UART_ZILOG(port);
842 struct zilog_channel __iomem *channel;
843 unsigned long flags;
844
845 if (ZS_IS_CONS(up))
846 return;
847
848 spin_lock_irqsave(&port->lock, flags);
849
850 channel = ZILOG_CHANNEL_FROM_PORT(port);
851
852 /* Disable receiver and transmitter. */
853 up->curregs[R3] &= ~RxENAB;
854 up->curregs[R5] &= ~TxENAB;
855
856 /* Disable all interrupts and BRK assertion. */
857 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
858 up->curregs[R5] &= ~SND_BRK;
859 sunzilog_maybe_update_regs(up, channel);
860
861 spin_unlock_irqrestore(&port->lock, flags);
862 }
863
864 /* Shared by TTY driver and serial console setup. The port lock is held
865 * and local interrupts are disabled.
866 */
867 static void
868 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
869 unsigned int iflag, int brg)
870 {
871
872 up->curregs[R10] = NRZ;
873 up->curregs[R11] = TCBR | RCBR;
874
875 /* Program BAUD and clock source. */
876 up->curregs[R4] &= ~XCLK_MASK;
877 up->curregs[R4] |= X16CLK;
878 up->curregs[R12] = brg & 0xff;
879 up->curregs[R13] = (brg >> 8) & 0xff;
880 up->curregs[R14] = BRSRC | BRENAB;
881
882 /* Character size, stop bits, and parity. */
883 up->curregs[R3] &= ~RxN_MASK;
884 up->curregs[R5] &= ~TxN_MASK;
885 switch (cflag & CSIZE) {
886 case CS5:
887 up->curregs[R3] |= Rx5;
888 up->curregs[R5] |= Tx5;
889 up->parity_mask = 0x1f;
890 break;
891 case CS6:
892 up->curregs[R3] |= Rx6;
893 up->curregs[R5] |= Tx6;
894 up->parity_mask = 0x3f;
895 break;
896 case CS7:
897 up->curregs[R3] |= Rx7;
898 up->curregs[R5] |= Tx7;
899 up->parity_mask = 0x7f;
900 break;
901 case CS8:
902 default:
903 up->curregs[R3] |= Rx8;
904 up->curregs[R5] |= Tx8;
905 up->parity_mask = 0xff;
906 break;
907 }
908 up->curregs[R4] &= ~0x0c;
909 if (cflag & CSTOPB)
910 up->curregs[R4] |= SB2;
911 else
912 up->curregs[R4] |= SB1;
913 if (cflag & PARENB)
914 up->curregs[R4] |= PAR_ENAB;
915 else
916 up->curregs[R4] &= ~PAR_ENAB;
917 if (!(cflag & PARODD))
918 up->curregs[R4] |= PAR_EVEN;
919 else
920 up->curregs[R4] &= ~PAR_EVEN;
921
922 up->port.read_status_mask = Rx_OVR;
923 if (iflag & INPCK)
924 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
925 if (iflag & (IGNBRK | BRKINT | PARMRK))
926 up->port.read_status_mask |= BRK_ABRT;
927
928 up->port.ignore_status_mask = 0;
929 if (iflag & IGNPAR)
930 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
931 if (iflag & IGNBRK) {
932 up->port.ignore_status_mask |= BRK_ABRT;
933 if (iflag & IGNPAR)
934 up->port.ignore_status_mask |= Rx_OVR;
935 }
936
937 if ((cflag & CREAD) == 0)
938 up->port.ignore_status_mask = 0xff;
939 }
940
941 /* The port lock is not held. */
942 static void
943 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
944 struct ktermios *old)
945 {
946 struct uart_sunzilog_port *up =
947 container_of(port, struct uart_sunzilog_port, port);
948 unsigned long flags;
949 int baud, brg;
950
951 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
952
953 spin_lock_irqsave(&up->port.lock, flags);
954
955 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
956
957 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
958
959 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
960 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
961 else
962 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
963
964 up->cflag = termios->c_cflag;
965
966 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
967
968 uart_update_timeout(port, termios->c_cflag, baud);
969
970 spin_unlock_irqrestore(&up->port.lock, flags);
971 }
972
973 static const char *sunzilog_type(struct uart_port *port)
974 {
975 struct uart_sunzilog_port *up = UART_ZILOG(port);
976
977 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
978 }
979
980 /* We do not request/release mappings of the registers here, this
981 * happens at early serial probe time.
982 */
983 static void sunzilog_release_port(struct uart_port *port)
984 {
985 }
986
987 static int sunzilog_request_port(struct uart_port *port)
988 {
989 return 0;
990 }
991
992 /* These do not need to do anything interesting either. */
993 static void sunzilog_config_port(struct uart_port *port, int flags)
994 {
995 }
996
997 /* We do not support letting the user mess with the divisor, IRQ, etc. */
998 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
999 {
1000 return -EINVAL;
1001 }
1002
1003 #ifdef CONFIG_CONSOLE_POLL
1004 static int sunzilog_get_poll_char(struct uart_port *port)
1005 {
1006 unsigned char ch, r1;
1007 struct uart_sunzilog_port *up =
1008 container_of(port, struct uart_sunzilog_port, port);
1009 struct zilog_channel __iomem *channel
1010 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1011
1012
1013 r1 = read_zsreg(channel, R1);
1014 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1015 writeb(ERR_RES, &channel->control);
1016 ZSDELAY();
1017 ZS_WSYNC(channel);
1018 }
1019
1020 ch = readb(&channel->control);
1021 ZSDELAY();
1022
1023 /* This funny hack depends upon BRK_ABRT not interfering
1024 * with the other bits we care about in R1.
1025 */
1026 if (ch & BRK_ABRT)
1027 r1 |= BRK_ABRT;
1028
1029 if (!(ch & Rx_CH_AV))
1030 return NO_POLL_CHAR;
1031
1032 ch = readb(&channel->data);
1033 ZSDELAY();
1034
1035 ch &= up->parity_mask;
1036 return ch;
1037 }
1038
1039 static void sunzilog_put_poll_char(struct uart_port *port,
1040 unsigned char ch)
1041 {
1042 struct uart_sunzilog_port *up =
1043 container_of(port, struct uart_sunzilog_port, port);
1044
1045 sunzilog_putchar(&up->port, ch);
1046 }
1047 #endif /* CONFIG_CONSOLE_POLL */
1048
1049 static struct uart_ops sunzilog_pops = {
1050 .tx_empty = sunzilog_tx_empty,
1051 .set_mctrl = sunzilog_set_mctrl,
1052 .get_mctrl = sunzilog_get_mctrl,
1053 .stop_tx = sunzilog_stop_tx,
1054 .start_tx = sunzilog_start_tx,
1055 .stop_rx = sunzilog_stop_rx,
1056 .enable_ms = sunzilog_enable_ms,
1057 .break_ctl = sunzilog_break_ctl,
1058 .startup = sunzilog_startup,
1059 .shutdown = sunzilog_shutdown,
1060 .set_termios = sunzilog_set_termios,
1061 .type = sunzilog_type,
1062 .release_port = sunzilog_release_port,
1063 .request_port = sunzilog_request_port,
1064 .config_port = sunzilog_config_port,
1065 .verify_port = sunzilog_verify_port,
1066 #ifdef CONFIG_CONSOLE_POLL
1067 .poll_get_char = sunzilog_get_poll_char,
1068 .poll_put_char = sunzilog_put_poll_char,
1069 #endif
1070 };
1071
1072 static int uart_chip_count;
1073 static struct uart_sunzilog_port *sunzilog_port_table;
1074 static struct zilog_layout __iomem **sunzilog_chip_regs;
1075
1076 static struct uart_sunzilog_port *sunzilog_irq_chain;
1077
1078 static struct uart_driver sunzilog_reg = {
1079 .owner = THIS_MODULE,
1080 .driver_name = "sunzilog",
1081 .dev_name = "ttyS",
1082 .major = TTY_MAJOR,
1083 };
1084
1085 static int __init sunzilog_alloc_tables(int num_sunzilog)
1086 {
1087 struct uart_sunzilog_port *up;
1088 unsigned long size;
1089 int num_channels = num_sunzilog * 2;
1090 int i;
1091
1092 size = num_channels * sizeof(struct uart_sunzilog_port);
1093 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1094 if (!sunzilog_port_table)
1095 return -ENOMEM;
1096
1097 for (i = 0; i < num_channels; i++) {
1098 up = &sunzilog_port_table[i];
1099
1100 spin_lock_init(&up->port.lock);
1101
1102 if (i == 0)
1103 sunzilog_irq_chain = up;
1104
1105 if (i < num_channels - 1)
1106 up->next = up + 1;
1107 else
1108 up->next = NULL;
1109 }
1110
1111 size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1112 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1113 if (!sunzilog_chip_regs) {
1114 kfree(sunzilog_port_table);
1115 sunzilog_irq_chain = NULL;
1116 return -ENOMEM;
1117 }
1118
1119 return 0;
1120 }
1121
1122 static void sunzilog_free_tables(void)
1123 {
1124 kfree(sunzilog_port_table);
1125 sunzilog_irq_chain = NULL;
1126 kfree(sunzilog_chip_regs);
1127 }
1128
1129 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1130
1131 static void sunzilog_putchar(struct uart_port *port, int ch)
1132 {
1133 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1134 int loops = ZS_PUT_CHAR_MAX_DELAY;
1135
1136 /* This is a timed polling loop so do not switch the explicit
1137 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1138 */
1139 do {
1140 unsigned char val = readb(&channel->control);
1141 if (val & Tx_BUF_EMP) {
1142 ZSDELAY();
1143 break;
1144 }
1145 udelay(5);
1146 } while (--loops);
1147
1148 writeb(ch, &channel->data);
1149 ZSDELAY();
1150 ZS_WSYNC(channel);
1151 }
1152
1153 #ifdef CONFIG_SERIO
1154
1155 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1156
1157 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1158 {
1159 struct uart_sunzilog_port *up = serio->port_data;
1160 unsigned long flags;
1161
1162 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1163
1164 sunzilog_putchar(&up->port, ch);
1165
1166 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1167
1168 return 0;
1169 }
1170
1171 static int sunzilog_serio_open(struct serio *serio)
1172 {
1173 struct uart_sunzilog_port *up = serio->port_data;
1174 unsigned long flags;
1175 int ret;
1176
1177 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1178 if (!up->serio_open) {
1179 up->serio_open = 1;
1180 ret = 0;
1181 } else
1182 ret = -EBUSY;
1183 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1184
1185 return ret;
1186 }
1187
1188 static void sunzilog_serio_close(struct serio *serio)
1189 {
1190 struct uart_sunzilog_port *up = serio->port_data;
1191 unsigned long flags;
1192
1193 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1194 up->serio_open = 0;
1195 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1196 }
1197
1198 #endif /* CONFIG_SERIO */
1199
1200 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1201 static void
1202 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1203 {
1204 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1205 unsigned long flags;
1206 int locked = 1;
1207
1208 if (up->port.sysrq || oops_in_progress)
1209 locked = spin_trylock_irqsave(&up->port.lock, flags);
1210 else
1211 spin_lock_irqsave(&up->port.lock, flags);
1212
1213 uart_console_write(&up->port, s, count, sunzilog_putchar);
1214 udelay(2);
1215
1216 if (locked)
1217 spin_unlock_irqrestore(&up->port.lock, flags);
1218 }
1219
1220 static int __init sunzilog_console_setup(struct console *con, char *options)
1221 {
1222 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1223 unsigned long flags;
1224 int baud, brg;
1225
1226 if (up->port.type != PORT_SUNZILOG)
1227 return -1;
1228
1229 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1230 (sunzilog_reg.minor - 64) + con->index, con->index);
1231
1232 /* Get firmware console settings. */
1233 sunserial_console_termios(con, up->port.dev->of_node);
1234
1235 /* Firmware console speed is limited to 150-->38400 baud so
1236 * this hackish cflag thing is OK.
1237 */
1238 switch (con->cflag & CBAUD) {
1239 case B150: baud = 150; break;
1240 case B300: baud = 300; break;
1241 case B600: baud = 600; break;
1242 case B1200: baud = 1200; break;
1243 case B2400: baud = 2400; break;
1244 case B4800: baud = 4800; break;
1245 default: case B9600: baud = 9600; break;
1246 case B19200: baud = 19200; break;
1247 case B38400: baud = 38400; break;
1248 }
1249
1250 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1251
1252 spin_lock_irqsave(&up->port.lock, flags);
1253
1254 up->curregs[R15] |= BRKIE;
1255 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1256
1257 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1258 __sunzilog_startup(up);
1259
1260 spin_unlock_irqrestore(&up->port.lock, flags);
1261
1262 return 0;
1263 }
1264
1265 static struct console sunzilog_console_ops = {
1266 .name = "ttyS",
1267 .write = sunzilog_console_write,
1268 .device = uart_console_device,
1269 .setup = sunzilog_console_setup,
1270 .flags = CON_PRINTBUFFER,
1271 .index = -1,
1272 .data = &sunzilog_reg,
1273 };
1274
1275 static inline struct console *SUNZILOG_CONSOLE(void)
1276 {
1277 return &sunzilog_console_ops;
1278 }
1279
1280 #else
1281 #define SUNZILOG_CONSOLE() (NULL)
1282 #endif
1283
1284 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1285 {
1286 int baud, brg;
1287
1288 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1289 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1290 baud = 1200;
1291 } else {
1292 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1293 baud = 4800;
1294 }
1295
1296 up->curregs[R15] |= BRKIE;
1297 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1298 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1299 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1300 __sunzilog_startup(up);
1301 }
1302
1303 #ifdef CONFIG_SERIO
1304 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1305 {
1306 struct serio *serio = &up->serio;
1307
1308 serio->port_data = up;
1309
1310 serio->id.type = SERIO_RS232;
1311 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1312 serio->id.proto = SERIO_SUNKBD;
1313 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1314 } else {
1315 serio->id.proto = SERIO_SUN;
1316 serio->id.extra = 1;
1317 strlcpy(serio->name, "zsms", sizeof(serio->name));
1318 }
1319 strlcpy(serio->phys,
1320 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1321 "zs/serio0" : "zs/serio1"),
1322 sizeof(serio->phys));
1323
1324 serio->write = sunzilog_serio_write;
1325 serio->open = sunzilog_serio_open;
1326 serio->close = sunzilog_serio_close;
1327 serio->dev.parent = up->port.dev;
1328
1329 serio_register_port(serio);
1330 }
1331 #endif
1332
1333 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1334 {
1335 struct zilog_channel __iomem *channel;
1336 unsigned long flags;
1337 int baud, brg;
1338
1339 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1340
1341 spin_lock_irqsave(&up->port.lock, flags);
1342 if (ZS_IS_CHANNEL_A(up)) {
1343 write_zsreg(channel, R9, FHWRES);
1344 ZSDELAY_LONG();
1345 (void) read_zsreg(channel, R0);
1346 }
1347
1348 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1349 SUNZILOG_FLAG_CONS_MOUSE)) {
1350 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1351 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1352 up->curregs[R3] = RxENAB | Rx8;
1353 up->curregs[R5] = TxENAB | Tx8;
1354 up->curregs[R6] = 0x00; /* SDLC Address */
1355 up->curregs[R7] = 0x7E; /* SDLC Flag */
1356 up->curregs[R9] = NV;
1357 up->curregs[R7p] = 0x00;
1358 sunzilog_init_kbdms(up);
1359 /* Only enable interrupts if an ISR handler available */
1360 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1361 up->curregs[R9] |= MIE;
1362 write_zsreg(channel, R9, up->curregs[R9]);
1363 } else {
1364 /* Normal serial TTY. */
1365 up->parity_mask = 0xff;
1366 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1367 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1368 up->curregs[R3] = RxENAB | Rx8;
1369 up->curregs[R5] = TxENAB | Tx8;
1370 up->curregs[R6] = 0x00; /* SDLC Address */
1371 up->curregs[R7] = 0x7E; /* SDLC Flag */
1372 up->curregs[R9] = NV;
1373 up->curregs[R10] = NRZ;
1374 up->curregs[R11] = TCBR | RCBR;
1375 baud = 9600;
1376 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1377 up->curregs[R12] = (brg & 0xff);
1378 up->curregs[R13] = (brg >> 8) & 0xff;
1379 up->curregs[R14] = BRSRC | BRENAB;
1380 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1381 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1382 if (__load_zsregs(channel, up->curregs)) {
1383 up->flags |= SUNZILOG_FLAG_ESCC;
1384 }
1385 /* Only enable interrupts if an ISR handler available */
1386 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1387 up->curregs[R9] |= MIE;
1388 write_zsreg(channel, R9, up->curregs[R9]);
1389 }
1390
1391 spin_unlock_irqrestore(&up->port.lock, flags);
1392
1393 #ifdef CONFIG_SERIO
1394 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1395 SUNZILOG_FLAG_CONS_MOUSE))
1396 sunzilog_register_serio(up);
1397 #endif
1398 }
1399
1400 static int zilog_irq;
1401
1402 static int zs_probe(struct platform_device *op)
1403 {
1404 static int kbm_inst, uart_inst;
1405 int inst;
1406 struct uart_sunzilog_port *up;
1407 struct zilog_layout __iomem *rp;
1408 int keyboard_mouse = 0;
1409 int err;
1410
1411 if (of_find_property(op->dev.of_node, "keyboard", NULL))
1412 keyboard_mouse = 1;
1413
1414 /* uarts must come before keyboards/mice */
1415 if (keyboard_mouse)
1416 inst = uart_chip_count + kbm_inst;
1417 else
1418 inst = uart_inst;
1419
1420 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1421 sizeof(struct zilog_layout),
1422 "zs");
1423 if (!sunzilog_chip_regs[inst])
1424 return -ENOMEM;
1425
1426 rp = sunzilog_chip_regs[inst];
1427
1428 if (!zilog_irq)
1429 zilog_irq = op->archdata.irqs[0];
1430
1431 up = &sunzilog_port_table[inst * 2];
1432
1433 /* Channel A */
1434 up[0].port.mapbase = op->resource[0].start + 0x00;
1435 up[0].port.membase = (void __iomem *) &rp->channelA;
1436 up[0].port.iotype = UPIO_MEM;
1437 up[0].port.irq = op->archdata.irqs[0];
1438 up[0].port.uartclk = ZS_CLOCK;
1439 up[0].port.fifosize = 1;
1440 up[0].port.ops = &sunzilog_pops;
1441 up[0].port.type = PORT_SUNZILOG;
1442 up[0].port.flags = 0;
1443 up[0].port.line = (inst * 2) + 0;
1444 up[0].port.dev = &op->dev;
1445 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1446 if (keyboard_mouse)
1447 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1448 sunzilog_init_hw(&up[0]);
1449
1450 /* Channel B */
1451 up[1].port.mapbase = op->resource[0].start + 0x04;
1452 up[1].port.membase = (void __iomem *) &rp->channelB;
1453 up[1].port.iotype = UPIO_MEM;
1454 up[1].port.irq = op->archdata.irqs[0];
1455 up[1].port.uartclk = ZS_CLOCK;
1456 up[1].port.fifosize = 1;
1457 up[1].port.ops = &sunzilog_pops;
1458 up[1].port.type = PORT_SUNZILOG;
1459 up[1].port.flags = 0;
1460 up[1].port.line = (inst * 2) + 1;
1461 up[1].port.dev = &op->dev;
1462 up[1].flags |= 0;
1463 if (keyboard_mouse)
1464 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1465 sunzilog_init_hw(&up[1]);
1466
1467 if (!keyboard_mouse) {
1468 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1469 &sunzilog_reg, up[0].port.line,
1470 false))
1471 up->flags |= SUNZILOG_FLAG_IS_CONS;
1472 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1473 if (err) {
1474 of_iounmap(&op->resource[0],
1475 rp, sizeof(struct zilog_layout));
1476 return err;
1477 }
1478 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1479 &sunzilog_reg, up[1].port.line,
1480 false))
1481 up->flags |= SUNZILOG_FLAG_IS_CONS;
1482 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1483 if (err) {
1484 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1485 of_iounmap(&op->resource[0],
1486 rp, sizeof(struct zilog_layout));
1487 return err;
1488 }
1489 uart_inst++;
1490 } else {
1491 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1492 "is a %s\n",
1493 dev_name(&op->dev),
1494 (unsigned long long) up[0].port.mapbase,
1495 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1496 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1497 "is a %s\n",
1498 dev_name(&op->dev),
1499 (unsigned long long) up[1].port.mapbase,
1500 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1501 kbm_inst++;
1502 }
1503
1504 platform_set_drvdata(op, &up[0]);
1505
1506 return 0;
1507 }
1508
1509 static void zs_remove_one(struct uart_sunzilog_port *up)
1510 {
1511 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1512 #ifdef CONFIG_SERIO
1513 serio_unregister_port(&up->serio);
1514 #endif
1515 } else
1516 uart_remove_one_port(&sunzilog_reg, &up->port);
1517 }
1518
1519 static int zs_remove(struct platform_device *op)
1520 {
1521 struct uart_sunzilog_port *up = platform_get_drvdata(op);
1522 struct zilog_layout __iomem *regs;
1523
1524 zs_remove_one(&up[0]);
1525 zs_remove_one(&up[1]);
1526
1527 regs = sunzilog_chip_regs[up[0].port.line / 2];
1528 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1529
1530 return 0;
1531 }
1532
1533 static const struct of_device_id zs_match[] = {
1534 {
1535 .name = "zs",
1536 },
1537 {},
1538 };
1539 MODULE_DEVICE_TABLE(of, zs_match);
1540
1541 static struct platform_driver zs_driver = {
1542 .driver = {
1543 .name = "zs",
1544 .of_match_table = zs_match,
1545 },
1546 .probe = zs_probe,
1547 .remove = zs_remove,
1548 };
1549
1550 static int __init sunzilog_init(void)
1551 {
1552 struct device_node *dp;
1553 int err;
1554 int num_keybms = 0;
1555 int num_sunzilog = 0;
1556
1557 for_each_node_by_name(dp, "zs") {
1558 num_sunzilog++;
1559 if (of_find_property(dp, "keyboard", NULL))
1560 num_keybms++;
1561 }
1562
1563 if (num_sunzilog) {
1564 err = sunzilog_alloc_tables(num_sunzilog);
1565 if (err)
1566 goto out;
1567
1568 uart_chip_count = num_sunzilog - num_keybms;
1569
1570 err = sunserial_register_minors(&sunzilog_reg,
1571 uart_chip_count * 2);
1572 if (err)
1573 goto out_free_tables;
1574 }
1575
1576 err = platform_driver_register(&zs_driver);
1577 if (err)
1578 goto out_unregister_uart;
1579
1580 if (zilog_irq) {
1581 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1582 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1583 "zs", sunzilog_irq_chain);
1584 if (err)
1585 goto out_unregister_driver;
1586
1587 /* Enable Interrupts */
1588 while (up) {
1589 struct zilog_channel __iomem *channel;
1590
1591 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1592 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1593 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1594 up->curregs[R9] |= MIE;
1595 write_zsreg(channel, R9, up->curregs[R9]);
1596 up = up->next;
1597 }
1598 }
1599
1600 out:
1601 return err;
1602
1603 out_unregister_driver:
1604 platform_driver_unregister(&zs_driver);
1605
1606 out_unregister_uart:
1607 if (num_sunzilog) {
1608 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1609 sunzilog_reg.cons = NULL;
1610 }
1611
1612 out_free_tables:
1613 sunzilog_free_tables();
1614 goto out;
1615 }
1616
1617 static void __exit sunzilog_exit(void)
1618 {
1619 platform_driver_unregister(&zs_driver);
1620
1621 if (zilog_irq) {
1622 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1623
1624 /* Disable Interrupts */
1625 while (up) {
1626 struct zilog_channel __iomem *channel;
1627
1628 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1629 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1630 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1631 up->curregs[R9] &= ~MIE;
1632 write_zsreg(channel, R9, up->curregs[R9]);
1633 up = up->next;
1634 }
1635
1636 free_irq(zilog_irq, sunzilog_irq_chain);
1637 zilog_irq = 0;
1638 }
1639
1640 if (sunzilog_reg.nr) {
1641 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1642 sunzilog_free_tables();
1643 }
1644 }
1645
1646 module_init(sunzilog_init);
1647 module_exit(sunzilog_exit);
1648
1649 MODULE_AUTHOR("David S. Miller");
1650 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1651 MODULE_VERSION("2.0");
1652 MODULE_LICENSE("GPL");
Linux with added FPC-III support