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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / tty / serial / vt8500_serial.c
blob6b85adce0ac9d13b4d2dece11a5e694db7899159
1 /*
2 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
3 *
4 * Based on msm_serial.c, which is:
5 * Copyright (C) 2007 Google, Inc.
6 * Author: Robert Love <rlove@google.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #if defined(CONFIG_SERIAL_VT8500_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
20 #endif
21
22 #include <linux/hrtimer.h>
23 #include <linux/delay.h>
24 #include <linux/io.h>
25 #include <linux/ioport.h>
26 #include <linux/irq.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/tty.h>
30 #include <linux/tty_flip.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/err.h>
38
39 /*
40 * UART Register offsets
41 */
42
43 #define VT8500_URTDR 0x0000 /* Transmit data */
44 #define VT8500_URRDR 0x0004 /* Receive data */
45 #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
46 #define VT8500_URLCR 0x000C /* Line control */
47 #define VT8500_URICR 0x0010 /* IrDA control */
48 #define VT8500_URIER 0x0014 /* Interrupt enable */
49 #define VT8500_URISR 0x0018 /* Interrupt status */
50 #define VT8500_URUSR 0x001c /* UART status */
51 #define VT8500_URFCR 0x0020 /* FIFO control */
52 #define VT8500_URFIDX 0x0024 /* FIFO index */
53 #define VT8500_URBKR 0x0028 /* Break signal count */
54 #define VT8500_URTOD 0x002c /* Time out divisor */
55 #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
56 #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
57
58 /*
59 * Interrupt enable and status bits
60 */
61
62 #define TXDE (1 << 0) /* Tx Data empty */
63 #define RXDF (1 << 1) /* Rx Data full */
64 #define TXFAE (1 << 2) /* Tx FIFO almost empty */
65 #define TXFE (1 << 3) /* Tx FIFO empty */
66 #define RXFAF (1 << 4) /* Rx FIFO almost full */
67 #define RXFF (1 << 5) /* Rx FIFO full */
68 #define TXUDR (1 << 6) /* Tx underrun */
69 #define RXOVER (1 << 7) /* Rx overrun */
70 #define PER (1 << 8) /* Parity error */
71 #define FER (1 << 9) /* Frame error */
72 #define TCTS (1 << 10) /* Toggle of CTS */
73 #define RXTOUT (1 << 11) /* Rx timeout */
74 #define BKDONE (1 << 12) /* Break signal done */
75 #define ERR (1 << 13) /* AHB error response */
76
77 #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
78 #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
79
80 /*
81 * Line control bits
82 */
83
84 #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
85 #define VT8500_RXEN (1 << 1) /* Enable receive logic */
86 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
87 #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
88 #define VT8500_PARENB (1 << 4) /* Enable parity */
89 #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
90 #define VT8500_RTS (1 << 6) /* Ready to send */
91 #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
92 #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
93 #define VT8500_BREAK (1 << 9) /* Initiate break signal */
94 #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
95 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
96
97 /*
98 * Capability flags (driver-internal)
99 */
100
101 #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
102
103 #define VT8500_RECOMMENDED_CLK 12000000
104 #define VT8500_OVERSAMPLING_DIVISOR 13
105 #define VT8500_MAX_PORTS 6
106
107 struct vt8500_port {
108 struct uart_port uart;
109 char name[16];
110 struct clk *clk;
111 unsigned int clk_predivisor;
112 unsigned int ier;
113 unsigned int vt8500_uart_flags;
114 };
115
116 /*
117 * we use this variable to keep track of which ports
118 * have been allocated as we can't use pdev->id in
119 * devicetree
120 */
121 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
122
123 static inline void vt8500_write(struct uart_port *port, unsigned int val,
124 unsigned int off)
125 {
126 writel(val, port->membase + off);
127 }
128
129 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
130 {
131 return readl(port->membase + off);
132 }
133
134 static void vt8500_stop_tx(struct uart_port *port)
135 {
136 struct vt8500_port *vt8500_port = container_of(port,
137 struct vt8500_port,
138 uart);
139
140 vt8500_port->ier &= ~TX_FIFO_INTS;
141 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
142 }
143
144 static void vt8500_stop_rx(struct uart_port *port)
145 {
146 struct vt8500_port *vt8500_port = container_of(port,
147 struct vt8500_port,
148 uart);
149
150 vt8500_port->ier &= ~RX_FIFO_INTS;
151 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
152 }
153
154 static void vt8500_enable_ms(struct uart_port *port)
155 {
156 struct vt8500_port *vt8500_port = container_of(port,
157 struct vt8500_port,
158 uart);
159
160 vt8500_port->ier |= TCTS;
161 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
162 }
163
164 static void handle_rx(struct uart_port *port)
165 {
166 struct tty_port *tport = &port->state->port;
167
168 /*
169 * Handle overrun
170 */
171 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
172 port->icount.overrun++;
173 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
174 }
175
176 /* and now the main RX loop */
177 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
178 unsigned int c;
179 char flag = TTY_NORMAL;
180
181 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
182
183 /* Mask conditions we're ignorning. */
184 c &= ~port->read_status_mask;
185
186 if (c & FER) {
187 port->icount.frame++;
188 flag = TTY_FRAME;
189 } else if (c & PER) {
190 port->icount.parity++;
191 flag = TTY_PARITY;
192 }
193 port->icount.rx++;
194
195 if (!uart_handle_sysrq_char(port, c))
196 tty_insert_flip_char(tport, c, flag);
197 }
198
199 spin_unlock(&port->lock);
200 tty_flip_buffer_push(tport);
201 spin_lock(&port->lock);
202 }
203
204 static void handle_tx(struct uart_port *port)
205 {
206 struct circ_buf *xmit = &port->state->xmit;
207
208 if (port->x_char) {
209 writeb(port->x_char, port->membase + VT8500_TXFIFO);
210 port->icount.tx++;
211 port->x_char = 0;
212 }
213 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
214 vt8500_stop_tx(port);
215 return;
216 }
217
218 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
219 if (uart_circ_empty(xmit))
220 break;
221
222 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
223
224 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
225 port->icount.tx++;
226 }
227
228 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
229 uart_write_wakeup(port);
230
231 if (uart_circ_empty(xmit))
232 vt8500_stop_tx(port);
233 }
234
235 static void vt8500_start_tx(struct uart_port *port)
236 {
237 struct vt8500_port *vt8500_port = container_of(port,
238 struct vt8500_port,
239 uart);
240
241 vt8500_port->ier &= ~TX_FIFO_INTS;
242 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
243 handle_tx(port);
244 vt8500_port->ier |= TX_FIFO_INTS;
245 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
246 }
247
248 static void handle_delta_cts(struct uart_port *port)
249 {
250 port->icount.cts++;
251 wake_up_interruptible(&port->state->port.delta_msr_wait);
252 }
253
254 static irqreturn_t vt8500_irq(int irq, void *dev_id)
255 {
256 struct uart_port *port = dev_id;
257 unsigned long isr;
258
259 spin_lock(&port->lock);
260 isr = vt8500_read(port, VT8500_URISR);
261
262 /* Acknowledge active status bits */
263 vt8500_write(port, isr, VT8500_URISR);
264
265 if (isr & RX_FIFO_INTS)
266 handle_rx(port);
267 if (isr & TX_FIFO_INTS)
268 handle_tx(port);
269 if (isr & TCTS)
270 handle_delta_cts(port);
271
272 spin_unlock(&port->lock);
273
274 return IRQ_HANDLED;
275 }
276
277 static unsigned int vt8500_tx_empty(struct uart_port *port)
278 {
279 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
280 TIOCSER_TEMT : 0;
281 }
282
283 static unsigned int vt8500_get_mctrl(struct uart_port *port)
284 {
285 unsigned int usr;
286
287 usr = vt8500_read(port, VT8500_URUSR);
288 if (usr & (1 << 4))
289 return TIOCM_CTS;
290 else
291 return 0;
292 }
293
294 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
295 {
296 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
297
298 if (mctrl & TIOCM_RTS)
299 lcr |= VT8500_RTS;
300 else
301 lcr &= ~VT8500_RTS;
302
303 vt8500_write(port, lcr, VT8500_URLCR);
304 }
305
306 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
307 {
308 if (break_ctl)
309 vt8500_write(port,
310 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
311 VT8500_URLCR);
312 }
313
314 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
315 {
316 struct vt8500_port *vt8500_port =
317 container_of(port, struct vt8500_port, uart);
318 unsigned long div;
319 unsigned int loops = 1000;
320
321 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
322 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
323
324 /* Effective baud rate */
325 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
326
327 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
328 cpu_relax();
329
330 vt8500_write(port, div, VT8500_URDIV);
331
332 /* Break signal timing depends on baud rate, update accordingly */
333 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
334
335 return baud;
336 }
337
338 static int vt8500_startup(struct uart_port *port)
339 {
340 struct vt8500_port *vt8500_port =
341 container_of(port, struct vt8500_port, uart);
342 int ret;
343
344 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
345 "vt8500_serial%d", port->line);
346
347 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
348 vt8500_port->name, port);
349 if (unlikely(ret))
350 return ret;
351
352 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
353
354 return 0;
355 }
356
357 static void vt8500_shutdown(struct uart_port *port)
358 {
359 struct vt8500_port *vt8500_port =
360 container_of(port, struct vt8500_port, uart);
361
362 vt8500_port->ier = 0;
363
364 /* disable interrupts and FIFOs */
365 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
366 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
367 free_irq(port->irq, port);
368 }
369
370 static void vt8500_set_termios(struct uart_port *port,
371 struct ktermios *termios,
372 struct ktermios *old)
373 {
374 struct vt8500_port *vt8500_port =
375 container_of(port, struct vt8500_port, uart);
376 unsigned long flags;
377 unsigned int baud, lcr;
378 unsigned int loops = 1000;
379
380 spin_lock_irqsave(&port->lock, flags);
381
382 /* calculate and set baud rate */
383 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
384 baud = vt8500_set_baud_rate(port, baud);
385 if (tty_termios_baud_rate(termios))
386 tty_termios_encode_baud_rate(termios, baud, baud);
387
388 /* calculate parity */
389 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
390 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
391 if (termios->c_cflag & PARENB) {
392 lcr |= VT8500_PARENB;
393 termios->c_cflag &= ~CMSPAR;
394 if (termios->c_cflag & PARODD)
395 lcr |= VT8500_PARODD;
396 }
397
398 /* calculate bits per char */
399 lcr &= ~VT8500_CS8;
400 switch (termios->c_cflag & CSIZE) {
401 case CS7:
402 break;
403 case CS8:
404 default:
405 lcr |= VT8500_CS8;
406 termios->c_cflag &= ~CSIZE;
407 termios->c_cflag |= CS8;
408 break;
409 }
410
411 /* calculate stop bits */
412 lcr &= ~VT8500_CSTOPB;
413 if (termios->c_cflag & CSTOPB)
414 lcr |= VT8500_CSTOPB;
415
416 lcr &= ~VT8500_SWRTSCTS;
417 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
418 lcr |= VT8500_SWRTSCTS;
419
420 /* set parity, bits per char, and stop bit */
421 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
422
423 /* Configure status bits to ignore based on termio flags. */
424 port->read_status_mask = 0;
425 if (termios->c_iflag & IGNPAR)
426 port->read_status_mask = FER | PER;
427
428 uart_update_timeout(port, termios->c_cflag, baud);
429
430 /* Reset FIFOs */
431 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
432 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
433 && --loops)
434 cpu_relax();
435
436 /* Every possible FIFO-related interrupt */
437 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
438
439 /*
440 * CTS flow control
441 */
442 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
443 vt8500_port->ier |= TCTS;
444
445 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
446 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
447
448 spin_unlock_irqrestore(&port->lock, flags);
449 }
450
451 static const char *vt8500_type(struct uart_port *port)
452 {
453 struct vt8500_port *vt8500_port =
454 container_of(port, struct vt8500_port, uart);
455 return vt8500_port->name;
456 }
457
458 static void vt8500_release_port(struct uart_port *port)
459 {
460 }
461
462 static int vt8500_request_port(struct uart_port *port)
463 {
464 return 0;
465 }
466
467 static void vt8500_config_port(struct uart_port *port, int flags)
468 {
469 port->type = PORT_VT8500;
470 }
471
472 static int vt8500_verify_port(struct uart_port *port,
473 struct serial_struct *ser)
474 {
475 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
476 return -EINVAL;
477 if (unlikely(port->irq != ser->irq))
478 return -EINVAL;
479 return 0;
480 }
481
482 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
483 static struct uart_driver vt8500_uart_driver;
484
485 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
486
487 static void wait_for_xmitr(struct uart_port *port)
488 {
489 unsigned int status, tmout = 10000;
490
491 /* Wait up to 10ms for the character(s) to be sent. */
492 do {
493 status = vt8500_read(port, VT8500_URFIDX);
494
495 if (--tmout == 0)
496 break;
497 udelay(1);
498 } while (status & 0x10);
499 }
500
501 static void vt8500_console_putchar(struct uart_port *port, int c)
502 {
503 wait_for_xmitr(port);
504 writeb(c, port->membase + VT8500_TXFIFO);
505 }
506
507 static void vt8500_console_write(struct console *co, const char *s,
508 unsigned int count)
509 {
510 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
511 unsigned long ier;
512
513 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
514
515 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
516 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
517
518 uart_console_write(&vt8500_port->uart, s, count,
519 vt8500_console_putchar);
520
521 /*
522 * Finally, wait for transmitter to become empty
523 * and switch back to FIFO
524 */
525 wait_for_xmitr(&vt8500_port->uart);
526 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
527 }
528
529 static int __init vt8500_console_setup(struct console *co, char *options)
530 {
531 struct vt8500_port *vt8500_port;
532 int baud = 9600;
533 int bits = 8;
534 int parity = 'n';
535 int flow = 'n';
536
537 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
538 return -ENXIO;
539
540 vt8500_port = vt8500_uart_ports[co->index];
541
542 if (!vt8500_port)
543 return -ENODEV;
544
545 if (options)
546 uart_parse_options(options, &baud, &parity, &bits, &flow);
547
548 return uart_set_options(&vt8500_port->uart,
549 co, baud, parity, bits, flow);
550 }
551
552 static struct console vt8500_console = {
553 .name = "ttyWMT",
554 .write = vt8500_console_write,
555 .device = uart_console_device,
556 .setup = vt8500_console_setup,
557 .flags = CON_PRINTBUFFER,
558 .index = -1,
559 .data = &vt8500_uart_driver,
560 };
561
562 #define VT8500_CONSOLE (&vt8500_console)
563
564 #else
565 #define VT8500_CONSOLE NULL
566 #endif
567
568 #ifdef CONFIG_CONSOLE_POLL
569 static int vt8500_get_poll_char(struct uart_port *port)
570 {
571 unsigned int status = vt8500_read(port, VT8500_URFIDX);
572
573 if (!(status & 0x1f00))
574 return NO_POLL_CHAR;
575
576 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
577 }
578
579 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
580 {
581 unsigned int status, tmout = 10000;
582
583 do {
584 status = vt8500_read(port, VT8500_URFIDX);
585
586 if (--tmout == 0)
587 break;
588 udelay(1);
589 } while (status & 0x10);
590
591 vt8500_write(port, c, VT8500_TXFIFO);
592 }
593 #endif
594
595 static struct uart_ops vt8500_uart_pops = {
596 .tx_empty = vt8500_tx_empty,
597 .set_mctrl = vt8500_set_mctrl,
598 .get_mctrl = vt8500_get_mctrl,
599 .stop_tx = vt8500_stop_tx,
600 .start_tx = vt8500_start_tx,
601 .stop_rx = vt8500_stop_rx,
602 .enable_ms = vt8500_enable_ms,
603 .break_ctl = vt8500_break_ctl,
604 .startup = vt8500_startup,
605 .shutdown = vt8500_shutdown,
606 .set_termios = vt8500_set_termios,
607 .type = vt8500_type,
608 .release_port = vt8500_release_port,
609 .request_port = vt8500_request_port,
610 .config_port = vt8500_config_port,
611 .verify_port = vt8500_verify_port,
612 #ifdef CONFIG_CONSOLE_POLL
613 .poll_get_char = vt8500_get_poll_char,
614 .poll_put_char = vt8500_put_poll_char,
615 #endif
616 };
617
618 static struct uart_driver vt8500_uart_driver = {
619 .owner = THIS_MODULE,
620 .driver_name = "vt8500_serial",
621 .dev_name = "ttyWMT",
622 .nr = 6,
623 .cons = VT8500_CONSOLE,
624 };
625
626 static unsigned int vt8500_flags; /* none required so far */
627 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
628
629 static const struct of_device_id wmt_dt_ids[] = {
630 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
631 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
632 {}
633 };
634
635 static int vt8500_serial_probe(struct platform_device *pdev)
636 {
637 struct vt8500_port *vt8500_port;
638 struct resource *mmres, *irqres;
639 struct device_node *np = pdev->dev.of_node;
640 const struct of_device_id *match;
641 const unsigned int *flags;
642 int ret;
643 int port;
644
645 match = of_match_device(wmt_dt_ids, &pdev->dev);
646 if (!match)
647 return -EINVAL;
648
649 flags = match->data;
650
651 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
653 if (!mmres || !irqres)
654 return -ENODEV;
655
656 if (np) {
657 port = of_alias_get_id(np, "serial");
658 if (port >= VT8500_MAX_PORTS)
659 port = -1;
660 } else {
661 port = -1;
662 }
663
664 if (port < 0) {
665 /* calculate the port id */
666 port = find_first_zero_bit(vt8500_ports_in_use,
667 VT8500_MAX_PORTS);
668 }
669
670 if (port >= VT8500_MAX_PORTS)
671 return -ENODEV;
672
673 /* reserve the port id */
674 if (test_and_set_bit(port, vt8500_ports_in_use)) {
675 /* port already in use - shouldn't really happen */
676 return -EBUSY;
677 }
678
679 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
680 GFP_KERNEL);
681 if (!vt8500_port)
682 return -ENOMEM;
683
684 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
685 if (IS_ERR(vt8500_port->uart.membase))
686 return PTR_ERR(vt8500_port->uart.membase);
687
688 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
689 if (IS_ERR(vt8500_port->clk)) {
690 dev_err(&pdev->dev, "failed to get clock\n");
691 return -EINVAL;
692 }
693
694 ret = clk_prepare_enable(vt8500_port->clk);
695 if (ret) {
696 dev_err(&pdev->dev, "failed to enable clock\n");
697 return ret;
698 }
699
700 vt8500_port->vt8500_uart_flags = *flags;
701 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
702 clk_get_rate(vt8500_port->clk),
703 VT8500_RECOMMENDED_CLK
704 );
705 vt8500_port->uart.type = PORT_VT8500;
706 vt8500_port->uart.iotype = UPIO_MEM;
707 vt8500_port->uart.mapbase = mmres->start;
708 vt8500_port->uart.irq = irqres->start;
709 vt8500_port->uart.fifosize = 16;
710 vt8500_port->uart.ops = &vt8500_uart_pops;
711 vt8500_port->uart.line = port;
712 vt8500_port->uart.dev = &pdev->dev;
713 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
714
715 /* Serial core uses the magic "16" everywhere - adjust for it */
716 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
717 vt8500_port->clk_predivisor /
718 VT8500_OVERSAMPLING_DIVISOR;
719
720 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
721 "VT8500 UART%d", pdev->id);
722
723 vt8500_uart_ports[port] = vt8500_port;
724
725 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
726
727 platform_set_drvdata(pdev, vt8500_port);
728
729 return 0;
730 }
731
732 static struct platform_driver vt8500_platform_driver = {
733 .probe = vt8500_serial_probe,
734 .driver = {
735 .name = "vt8500_serial",
736 .of_match_table = wmt_dt_ids,
737 .suppress_bind_attrs = true,
738 },
739 };
740
741 static int __init vt8500_serial_init(void)
742 {
743 int ret;
744
745 ret = uart_register_driver(&vt8500_uart_driver);
746 if (unlikely(ret))
747 return ret;
748
749 ret = platform_driver_register(&vt8500_platform_driver);
750
751 if (unlikely(ret))
752 uart_unregister_driver(&vt8500_uart_driver);
753
754 return ret;
755 }
756 device_initcall(vt8500_serial_init);
Linux with added FPC-III support