drivers/tty/serial/zs.h

   1 /*
   2  * zs.h: Definitions for the DECstation Z85C30 serial driver.
   3  *
   4  * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
   5  * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
   6  *
   7  * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
   8  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   9  * Copyright (C) 2004, 2005, 2007  Maciej W. Rozycki
  10  */
  11 #ifndef _SERIAL_ZS_H
  12 #define _SERIAL_ZS_H
  13
  14 #ifdef __KERNEL__
  15
  16 #define ZS_NUM_REGS 16
  17
  18 /*
  19  * This is our internal structure for each serial port's state.
  20  */
  21 struct zs_port {
  22         struct zs_scc   *scc;                   /* Containing SCC.  */
  23         struct uart_port port;                  /* Underlying UART.  */
  24
  25         int             clk_mode;               /* May be 1, 16, 32, or 64.  */
  26
  27         unsigned int    tty_break;              /* Set on BREAK condition.  */
  28         int             tx_stopped;             /* Output is suspended.  */
  29
  30         unsigned int    mctrl;                  /* State of modem lines.  */
  31         u8              brk;                    /* BREAK state from RR0.  */
  32
  33         u8              regs[ZS_NUM_REGS];      /* Channel write registers.  */
  34 };
  35
  36 /*
  37  * Per-SCC state for locking and the interrupt handler.
  38  */
  39 struct zs_scc {
  40         struct zs_port  zport[2];
  41         spinlock_t      zlock;
  42         atomic_t        irq_guard;
  43         int             initialised;
  44 };
  45
  46 #endif /* __KERNEL__ */
  47
  48 /*
  49  * Conversion routines to/from brg time constants from/to bits per second.
  50  */
  51 #define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
  52 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
  53
  54 /*
  55  * The Zilog register set.
  56  */
  57
  58 /* Write Register 0 (Command) */
  59 #define R0              0       /* Register selects */
  60 #define R1              1
  61 #define R2              2
  62 #define R3              3
  63 #define R4              4
  64 #define R5              5
  65 #define R6              6
  66 #define R7              7
  67 #define R8              8
  68 #define R9              9
  69 #define R10             10
  70 #define R11             11
  71 #define R12             12
  72 #define R13             13
  73 #define R14             14
  74 #define R15             15
  75
  76 #define NULLCODE        0       /* Null Code */
  77 #define POINT_HIGH      0x8     /* Select upper half of registers */
  78 #define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
  79 #define SEND_ABORT      0x18    /* HDLC Abort */
  80 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
  81 #define RES_Tx_P        0x28    /* Reset TxINT Pending */
  82 #define ERR_RES         0x30    /* Error Reset */
  83 #define RES_H_IUS       0x38    /* Reset highest IUS */
  84
  85 #define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
  86 #define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
  87 #define RES_EOM_L       0xC0    /* Reset EOM latch */
  88
  89 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
  90 #define EXT_INT_ENAB    0x1     /* Ext Int Enable */
  91 #define TxINT_ENAB      0x2     /* Tx Int Enable */
  92 #define PAR_SPEC        0x4     /* Parity is special condition */
  93
  94 #define RxINT_DISAB     0       /* Rx Int Disable */
  95 #define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
  96 #define RxINT_ALL       0x10    /* Int on all Rx Characters or error */
  97 #define RxINT_ERR       0x18    /* Int on error only */
  98 #define RxINT_MASK      0x18
  99
 100 #define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
 101 #define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
 102 #define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
 103
 104 /* Write Register 2 (Interrupt Vector) */
 105
 106 /* Write Register 3 (Receive Parameters and Control) */
 107 #define RxENABLE        0x1     /* Rx Enable */
 108 #define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 109 #define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 110 #define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 111 #define ENT_HM          0x10    /* Enter Hunt Mode */
 112 #define AUTO_ENAB       0x20    /* Auto Enables */
 113 #define Rx5             0x0     /* Rx 5 Bits/Character */
 114 #define Rx7             0x40    /* Rx 7 Bits/Character */
 115 #define Rx6             0x80    /* Rx 6 Bits/Character */
 116 #define Rx8             0xc0    /* Rx 8 Bits/Character */
 117 #define RxNBITS_MASK    0xc0
 118
 119 /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
 120 #define PAR_ENA         0x1     /* Parity Enable */
 121 #define PAR_EVEN        0x2     /* Parity Even/Odd* */
 122
 123 #define SYNC_ENAB       0       /* Sync Modes Enable */
 124 #define SB1             0x4     /* 1 stop bit/char */
 125 #define SB15            0x8     /* 1.5 stop bits/char */
 126 #define SB2             0xc     /* 2 stop bits/char */
 127 #define SB_MASK         0xc
 128
 129 #define MONSYNC         0       /* 8 Bit Sync character */
 130 #define BISYNC          0x10    /* 16 bit sync character */
 131 #define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 132 #define EXTSYNC         0x30    /* External Sync Mode */
 133
 134 #define X1CLK           0x0     /* x1 clock mode */
 135 #define X16CLK          0x40    /* x16 clock mode */
 136 #define X32CLK          0x80    /* x32 clock mode */
 137 #define X64CLK          0xc0    /* x64 clock mode */
 138 #define XCLK_MASK       0xc0
 139
 140 /* Write Register 5 (Transmit Parameters and Controls) */
 141 #define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 142 #define RTS             0x2     /* RTS */
 143 #define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 144 #define TxENAB          0x8     /* Tx Enable */
 145 #define SND_BRK         0x10    /* Send Break */
 146 #define Tx5             0x0     /* Tx 5 bits (or less)/character */
 147 #define Tx7             0x20    /* Tx 7 bits/character */
 148 #define Tx6             0x40    /* Tx 6 bits/character */
 149 #define Tx8             0x60    /* Tx 8 bits/character */
 150 #define TxNBITS_MASK    0x60
 151 #define DTR             0x80    /* DTR */
 152
 153 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 154
 155 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 156
 157 /* Write Register 8 (Transmit Buffer) */
 158
 159 /* Write Register 9 (Master Interrupt Control) */
 160 #define VIS             1       /* Vector Includes Status */
 161 #define NV              2       /* No Vector */
 162 #define DLC             4       /* Disable Lower Chain */
 163 #define MIE             8       /* Master Interrupt Enable */
 164 #define STATHI          0x10    /* Status high */
 165 #define SOFTACK         0x20    /* Software Interrupt Acknowledge */
 166 #define NORESET         0       /* No reset on write to R9 */
 167 #define CHRB            0x40    /* Reset channel B */
 168 #define CHRA            0x80    /* Reset channel A */
 169 #define FHWRES          0xc0    /* Force hardware reset */
 170
 171 /* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
 172 #define BIT6            1       /* 6 bit/8bit sync */
 173 #define LOOPMODE        2       /* SDLC Loop mode */
 174 #define ABUNDER         4       /* Abort/flag on SDLC xmit underrun */
 175 #define MARKIDLE        8       /* Mark/flag on idle */
 176 #define GAOP            0x10    /* Go active on poll */
 177 #define NRZ             0       /* NRZ mode */
 178 #define NRZI            0x20    /* NRZI mode */
 179 #define FM1             0x40    /* FM1 (transition = 1) */
 180 #define FM0             0x60    /* FM0 (transition = 0) */
 181 #define CRCPS           0x80    /* CRC Preset I/O */
 182
 183 /* Write Register 11 (Clock Mode Control) */
 184 #define TRxCXT          0       /* TRxC = Xtal output */
 185 #define TRxCTC          1       /* TRxC = Transmit clock */
 186 #define TRxCBR          2       /* TRxC = BR Generator Output */
 187 #define TRxCDP          3       /* TRxC = DPLL output */
 188 #define TRxCOI          4       /* TRxC O/I */
 189 #define TCRTxCP         0       /* Transmit clock = RTxC pin */
 190 #define TCTRxCP         8       /* Transmit clock = TRxC pin */
 191 #define TCBR            0x10    /* Transmit clock = BR Generator output */
 192 #define TCDPLL          0x18    /* Transmit clock = DPLL output */
 193 #define RCRTxCP         0       /* Receive clock = RTxC pin */
 194 #define RCTRxCP         0x20    /* Receive clock = TRxC pin */
 195 #define RCBR            0x40    /* Receive clock = BR Generator output */
 196 #define RCDPLL          0x60    /* Receive clock = DPLL output */
 197 #define RTxCX           0x80    /* RTxC Xtal/No Xtal */
 198
 199 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
 200
 201 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
 202
 203 /* Write Register 14 (Miscellaneous Control Bits) */
 204 #define BRENABL         1       /* Baud rate generator enable */
 205 #define BRSRC           2       /* Baud rate generator source */
 206 #define DTRREQ          4       /* DTR/Request function */
 207 #define AUTOECHO        8       /* Auto Echo */
 208 #define LOOPBAK         0x10    /* Local loopback */
 209 #define SEARCH          0x20    /* Enter search mode */
 210 #define RMC             0x40    /* Reset missing clock */
 211 #define DISDPLL         0x60    /* Disable DPLL */
 212 #define SSBR            0x80    /* Set DPLL source = BR generator */
 213 #define SSRTxC          0xa0    /* Set DPLL source = RTxC */
 214 #define SFMM            0xc0    /* Set FM mode */
 215 #define SNRZI           0xe0    /* Set NRZI mode */
 216
 217 /* Write Register 15 (External/Status Interrupt Control) */
 218 #define WR7P_EN         1       /* WR7 Prime SDLC Feature Enable */
 219 #define ZCIE            2       /* Zero count IE */
 220 #define DCDIE           8       /* DCD IE */
 221 #define SYNCIE          0x10    /* Sync/hunt IE */
 222 #define CTSIE           0x20    /* CTS IE */
 223 #define TxUIE           0x40    /* Tx Underrun/EOM IE */
 224 #define BRKIE           0x80    /* Break/Abort IE */
 225
 226
 227 /* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
 228 #define Rx_CH_AV        0x1     /* Rx Character Available */
 229 #define ZCOUNT          0x2     /* Zero count */
 230 #define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 231 #define DCD             0x8     /* DCD */
 232 #define SYNC_HUNT       0x10    /* Sync/hunt */
 233 #define CTS             0x20    /* CTS */
 234 #define TxEOM           0x40    /* Tx underrun */
 235 #define BRK_ABRT        0x80    /* Break/Abort */
 236
 237 /* Read Register 1 (Special Receive Condition Status) */
 238 #define ALL_SNT         0x1     /* All sent */
 239 /* Residue Data for 8 Rx bits/char programmed */
 240 #define RES3            0x8     /* 0/3 */
 241 #define RES4            0x4     /* 0/4 */
 242 #define RES5            0xc     /* 0/5 */
 243 #define RES6            0x2     /* 0/6 */
 244 #define RES7            0xa     /* 0/7 */
 245 #define RES8            0x6     /* 0/8 */
 246 #define RES18           0xe     /* 1/8 */
 247 #define RES28           0x0     /* 2/8 */
 248 /* Special Rx Condition Interrupts */
 249 #define PAR_ERR         0x10    /* Parity Error */
 250 #define Rx_OVR          0x20    /* Rx Overrun Error */
 251 #define FRM_ERR         0x40    /* CRC/Framing Error */
 252 #define END_FR          0x80    /* End of Frame (SDLC) */
 253
 254 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
 255
 256 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
 257
 258 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
 259 #define CHBEXT          0x1     /* Channel B Ext/Stat IP */
 260 #define CHBTxIP         0x2     /* Channel B Tx IP */
 261 #define CHBRxIP         0x4     /* Channel B Rx IP */
 262 #define CHAEXT          0x8     /* Channel A Ext/Stat IP */
 263 #define CHATxIP         0x10    /* Channel A Tx IP */
 264 #define CHARxIP         0x20    /* Channel A Rx IP */
 265
 266 /* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
 267
 268 /* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
 269
 270 /* Read Register 8 (Receive Data) */
 271
 272 /* Read Register 10 (Miscellaneous Status Bits) */
 273 #define ONLOOP          2       /* On loop */
 274 #define LOOPSEND        0x10    /* Loop sending */
 275 #define CLK2MIS         0x40    /* Two clocks missing */
 276 #define CLK1MIS         0x80    /* One clock missing */
 277
 278 /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
 279
 280 /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
 281
 282 /* Read Register 15 (External/Status Interrupt Control (WR15)) */
 283
 284 #endif /* _SERIAL_ZS_H */