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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / video / fbdev / aty / atyfb_base.c
blob11026e726b68468d2e8de7e159ad5003001b5610
1 /*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38 /******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
57 #include <linux/mm.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/compiler.h>
62 #include <linux/console.h>
63 #include <linux/fb.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
69 #include <linux/backlight.h>
70 #include <linux/reboot.h>
71 #include <linux/dmi.h>
72
73 #include <asm/io.h>
74 #include <linux/uaccess.h>
75
76 #include <video/mach64.h>
77 #include "atyfb.h"
78 #include "ati_ids.h"
79
80 #ifdef __powerpc__
81 #include <asm/machdep.h>
82 #include <asm/prom.h>
83 #include "../macmodes.h"
84 #endif
85 #ifdef __sparc__
86 #include <asm/fbio.h>
87 #include <asm/oplib.h>
88 #include <asm/prom.h>
89 #endif
90
91 #ifdef CONFIG_ADB_PMU
92 #include <linux/adb.h>
93 #include <linux/pmu.h>
94 #endif
95 #ifdef CONFIG_BOOTX_TEXT
96 #include <asm/btext.h>
97 #endif
98 #ifdef CONFIG_PMAC_BACKLIGHT
99 #include <asm/backlight.h>
100 #endif
101
102 /*
103 * Debug flags.
104 */
105 #undef DEBUG
106 /*#define DEBUG*/
107
108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
109 /* - must be large enough to catch all GUI-Regs */
110 /* - must be aligned to a PAGE boundary */
111 #define GUI_RESERVE (1 * PAGE_SIZE)
112
113 /* FIXME: remove the FAIL definition */
114 #define FAIL(msg) do { \
115 if (!(var->activate & FB_ACTIVATE_TEST)) \
116 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 return -EINVAL; \
118 } while (0)
119 #define FAIL_MAX(msg, x, _max_) do { \
120 if (x > _max_) { \
121 if (!(var->activate & FB_ACTIVATE_TEST)) \
122 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
123 return -EINVAL; \
124 } \
125 } while (0)
126 #ifdef DEBUG
127 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #else
129 #define DPRINTK(fmt, args...)
130 #endif
131
132 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
133 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134
135 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
136 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
137 static const u32 lt_lcd_regs[] = {
138 CNFG_PANEL_LG,
139 LCD_GEN_CNTL_LG,
140 DSTN_CONTROL_LG,
141 HFB_PITCH_ADDR_LG,
142 HORZ_STRETCHING_LG,
143 VERT_STRETCHING_LG,
144 0, /* EXT_VERT_STRETCH */
145 LT_GIO_LG,
146 POWER_MANAGEMENT_LG
147 };
148
149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
150 {
151 if (M64_HAS(LT_LCD_REGS)) {
152 aty_st_le32(lt_lcd_regs[index], val, par);
153 } else {
154 unsigned long temp;
155
156 /* write addr byte */
157 temp = aty_ld_le32(LCD_INDEX, par);
158 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
159 /* write the register value */
160 aty_st_le32(LCD_DATA, val, par);
161 }
162 }
163
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
165 {
166 if (M64_HAS(LT_LCD_REGS)) {
167 return aty_ld_le32(lt_lcd_regs[index], par);
168 } else {
169 unsigned long temp;
170
171 /* write addr byte */
172 temp = aty_ld_le32(LCD_INDEX, par);
173 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
174 /* read the register value */
175 return aty_ld_le32(LCD_DATA, par);
176 }
177 }
178 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
179
180 #ifdef CONFIG_FB_ATY_GENERIC_LCD
181 /*
182 * ATIReduceRatio --
183 *
184 * Reduce a fraction by factoring out the largest common divider of the
185 * fraction's numerator and denominator.
186 */
187 static void ATIReduceRatio(int *Numerator, int *Denominator)
188 {
189 int Multiplier, Divider, Remainder;
190
191 Multiplier = *Numerator;
192 Divider = *Denominator;
193
194 while ((Remainder = Multiplier % Divider)) {
195 Multiplier = Divider;
196 Divider = Remainder;
197 }
198
199 *Numerator /= Divider;
200 *Denominator /= Divider;
201 }
202 #endif
203 /*
204 * The Hardware parameters for each card
205 */
206
207 struct pci_mmap_map {
208 unsigned long voff;
209 unsigned long poff;
210 unsigned long size;
211 unsigned long prot_flag;
212 unsigned long prot_mask;
213 };
214
215 static const struct fb_fix_screeninfo atyfb_fix = {
216 .id = "ATY Mach64",
217 .type = FB_TYPE_PACKED_PIXELS,
218 .visual = FB_VISUAL_PSEUDOCOLOR,
219 .xpanstep = 8,
220 .ypanstep = 1,
221 };
222
223 /*
224 * Frame buffer device API
225 */
226
227 static int atyfb_open(struct fb_info *info, int user);
228 static int atyfb_release(struct fb_info *info, int user);
229 static int atyfb_check_var(struct fb_var_screeninfo *var,
230 struct fb_info *info);
231 static int atyfb_set_par(struct fb_info *info);
232 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
233 u_int transp, struct fb_info *info);
234 static int atyfb_pan_display(struct fb_var_screeninfo *var,
235 struct fb_info *info);
236 static int atyfb_blank(int blank, struct fb_info *info);
237 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
238 #ifdef __sparc__
239 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
240 #endif
241 static int atyfb_sync(struct fb_info *info);
242
243 /*
244 * Internal routines
245 */
246
247 static int aty_init(struct fb_info *info);
248
249 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
250
251 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
252 static int aty_var_to_crtc(const struct fb_info *info,
253 const struct fb_var_screeninfo *var,
254 struct crtc *crtc);
255 static int aty_crtc_to_var(const struct crtc *crtc,
256 struct fb_var_screeninfo *var);
257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
258 #ifdef CONFIG_PPC
259 static int read_aty_sense(const struct atyfb_par *par);
260 #endif
261
262 static DEFINE_MUTEX(reboot_lock);
263 static struct fb_info *reboot_info;
264
265 /*
266 * Interface used by the world
267 */
268
269 static struct fb_var_screeninfo default_var = {
270 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
271 640, 480, 640, 480, 0, 0, 8, 0,
272 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
273 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
274 0, FB_VMODE_NONINTERLACED
275 };
276
277 static struct fb_videomode defmode = {
278 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
279 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
280 0, FB_VMODE_NONINTERLACED
281 };
282
283 static struct fb_ops atyfb_ops = {
284 .owner = THIS_MODULE,
285 .fb_open = atyfb_open,
286 .fb_release = atyfb_release,
287 .fb_check_var = atyfb_check_var,
288 .fb_set_par = atyfb_set_par,
289 .fb_setcolreg = atyfb_setcolreg,
290 .fb_pan_display = atyfb_pan_display,
291 .fb_blank = atyfb_blank,
292 .fb_ioctl = atyfb_ioctl,
293 .fb_fillrect = atyfb_fillrect,
294 .fb_copyarea = atyfb_copyarea,
295 .fb_imageblit = atyfb_imageblit,
296 #ifdef __sparc__
297 .fb_mmap = atyfb_mmap,
298 #endif
299 .fb_sync = atyfb_sync,
300 };
301
302 static bool noaccel;
303 static bool nomtrr;
304 static int vram;
305 static int pll;
306 static int mclk;
307 static int xclk;
308 static int comp_sync = -1;
309 static char *mode;
310
311 #ifdef CONFIG_PMAC_BACKLIGHT
312 static int backlight = 1;
313 #else
314 static int backlight = 0;
315 #endif
316
317 #ifdef CONFIG_PPC
318 static int default_vmode = VMODE_CHOOSE;
319 static int default_cmode = CMODE_CHOOSE;
320
321 module_param_named(vmode, default_vmode, int, 0);
322 MODULE_PARM_DESC(vmode, "int: video mode for mac");
323 module_param_named(cmode, default_cmode, int, 0);
324 MODULE_PARM_DESC(cmode, "int: color mode for mac");
325 #endif
326
327 #ifdef CONFIG_ATARI
328 static unsigned int mach64_count = 0;
329 static unsigned long phys_vmembase[FB_MAX] = { 0, };
330 static unsigned long phys_size[FB_MAX] = { 0, };
331 static unsigned long phys_guiregbase[FB_MAX] = { 0, };
332 #endif
333
334 /* top -> down is an evolution of mach64 chipset, any corrections? */
335 #define ATI_CHIP_88800GX (M64F_GX)
336 #define ATI_CHIP_88800CX (M64F_GX)
337
338 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
339 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
340
341 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
342 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
343
344 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
345 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
346 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
347
348 /* FIXME what is this chip? */
349 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
350
351 /* make sets shorter */
352 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
353
354 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
355 /*#define ATI_CHIP_264GTDVD ?*/
356 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
357
358 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
359 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
360 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
361
362 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM)
363 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM | M64F_MOBIL_BUS)
364
365 static struct {
366 u16 pci_id;
367 const char *name;
368 int pll, mclk, xclk, ecp_max;
369 u32 features;
370 } aty_chips[] = {
371 #ifdef CONFIG_FB_ATY_GX
372 /* Mach64 GX */
373 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
374 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
375 #endif /* CONFIG_FB_ATY_GX */
376
377 #ifdef CONFIG_FB_ATY_CT
378 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
379 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
380
381 /* FIXME what is this chip? */
382 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
383
384 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
385 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
386
387 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
388 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
389
390 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
391
392 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
393
394 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
395 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
396 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398
399 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
400 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
401 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
402 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
403 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404
405 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
406 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
407 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
408 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
409 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
410
411 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
412 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
413 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
416 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
417
418 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
419 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
420 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422 #endif /* CONFIG_FB_ATY_CT */
423 };
424
425 /*
426 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
427 * unless the auxiliary register aperture is used.
428 */
429 static void aty_fudge_framebuffer_len(struct fb_info *info)
430 {
431 struct atyfb_par *par = (struct atyfb_par *) info->par;
432
433 if (!par->aux_start &&
434 (info->fix.smem_len == 0x800000 ||
435 (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
436 info->fix.smem_len -= GUI_RESERVE;
437 }
438
439 static int correct_chipset(struct atyfb_par *par)
440 {
441 u8 rev;
442 u16 type;
443 u32 chip_id;
444 const char *name;
445 int i;
446
447 for (i = (int)ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
448 if (par->pci_id == aty_chips[i].pci_id)
449 break;
450
451 if (i < 0)
452 return -ENODEV;
453
454 name = aty_chips[i].name;
455 par->pll_limits.pll_max = aty_chips[i].pll;
456 par->pll_limits.mclk = aty_chips[i].mclk;
457 par->pll_limits.xclk = aty_chips[i].xclk;
458 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
459 par->features = aty_chips[i].features;
460
461 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
462 type = chip_id & CFG_CHIP_TYPE;
463 rev = (chip_id & CFG_CHIP_REV) >> 24;
464
465 switch (par->pci_id) {
466 #ifdef CONFIG_FB_ATY_GX
467 case PCI_CHIP_MACH64GX:
468 if (type != 0x00d7)
469 return -ENODEV;
470 break;
471 case PCI_CHIP_MACH64CX:
472 if (type != 0x0057)
473 return -ENODEV;
474 break;
475 #endif
476 #ifdef CONFIG_FB_ATY_CT
477 case PCI_CHIP_MACH64VT:
478 switch (rev & 0x07) {
479 case 0x00:
480 switch (rev & 0xc0) {
481 case 0x00:
482 name = "ATI264VT (A3) (Mach64 VT)";
483 par->pll_limits.pll_max = 170;
484 par->pll_limits.mclk = 67;
485 par->pll_limits.xclk = 67;
486 par->pll_limits.ecp_max = 80;
487 par->features = ATI_CHIP_264VT;
488 break;
489 case 0x40:
490 name = "ATI264VT2 (A4) (Mach64 VT)";
491 par->pll_limits.pll_max = 200;
492 par->pll_limits.mclk = 67;
493 par->pll_limits.xclk = 67;
494 par->pll_limits.ecp_max = 80;
495 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
496 break;
497 }
498 break;
499 case 0x01:
500 name = "ATI264VT3 (B1) (Mach64 VT)";
501 par->pll_limits.pll_max = 200;
502 par->pll_limits.mclk = 67;
503 par->pll_limits.xclk = 67;
504 par->pll_limits.ecp_max = 80;
505 par->features = ATI_CHIP_264VTB;
506 break;
507 case 0x02:
508 name = "ATI264VT3 (B2) (Mach64 VT)";
509 par->pll_limits.pll_max = 200;
510 par->pll_limits.mclk = 67;
511 par->pll_limits.xclk = 67;
512 par->pll_limits.ecp_max = 80;
513 par->features = ATI_CHIP_264VT3;
514 break;
515 }
516 break;
517 case PCI_CHIP_MACH64GT:
518 switch (rev & 0x07) {
519 case 0x01:
520 name = "3D RAGE II (Mach64 GT)";
521 par->pll_limits.pll_max = 170;
522 par->pll_limits.mclk = 67;
523 par->pll_limits.xclk = 67;
524 par->pll_limits.ecp_max = 80;
525 par->features = ATI_CHIP_264GTB;
526 break;
527 case 0x02:
528 name = "3D RAGE II+ (Mach64 GT)";
529 par->pll_limits.pll_max = 200;
530 par->pll_limits.mclk = 67;
531 par->pll_limits.xclk = 67;
532 par->pll_limits.ecp_max = 100;
533 par->features = ATI_CHIP_264GTB;
534 break;
535 }
536 break;
537 #endif
538 }
539
540 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
541 return 0;
542 }
543
544 static char ram_dram[] __maybe_unused = "DRAM";
545 static char ram_resv[] __maybe_unused = "RESV";
546 #ifdef CONFIG_FB_ATY_GX
547 static char ram_vram[] = "VRAM";
548 #endif /* CONFIG_FB_ATY_GX */
549 #ifdef CONFIG_FB_ATY_CT
550 static char ram_edo[] = "EDO";
551 static char ram_sdram[] = "SDRAM (1:1)";
552 static char ram_sgram[] = "SGRAM (1:1)";
553 static char ram_sdram32[] = "SDRAM (2:1) (32-bit)";
554 static char ram_wram[] = "WRAM";
555 static char ram_off[] = "OFF";
556 #endif /* CONFIG_FB_ATY_CT */
557
558
559 #ifdef CONFIG_FB_ATY_GX
560 static char *aty_gx_ram[8] = {
561 ram_dram, ram_vram, ram_vram, ram_dram,
562 ram_dram, ram_vram, ram_vram, ram_resv
563 };
564 #endif /* CONFIG_FB_ATY_GX */
565
566 #ifdef CONFIG_FB_ATY_CT
567 static char *aty_ct_ram[8] = {
568 ram_off, ram_dram, ram_edo, ram_edo,
569 ram_sdram, ram_sgram, ram_wram, ram_resv
570 };
571 static char *aty_xl_ram[8] = {
572 ram_off, ram_dram, ram_edo, ram_edo,
573 ram_sdram, ram_sgram, ram_sdram32, ram_resv
574 };
575 #endif /* CONFIG_FB_ATY_CT */
576
577 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var,
578 struct atyfb_par *par)
579 {
580 u32 pixclock = var->pixclock;
581 #ifdef CONFIG_FB_ATY_GENERIC_LCD
582 u32 lcd_on_off;
583 par->pll.ct.xres = 0;
584 if (par->lcd_table != 0) {
585 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
586 if (lcd_on_off & LCD_ON) {
587 par->pll.ct.xres = var->xres;
588 pixclock = par->lcd_pixclock;
589 }
590 }
591 #endif
592 return pixclock;
593 }
594
595 #if defined(CONFIG_PPC)
596
597 /*
598 * Apple monitor sense
599 */
600
601 static int read_aty_sense(const struct atyfb_par *par)
602 {
603 int sense, i;
604
605 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
606 __delay(200);
607 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
608 __delay(2000);
609 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
610 sense = ((i & 0x3000) >> 3) | (i & 0x100);
611
612 /* drive each sense line low in turn and collect the other 2 */
613 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
614 __delay(2000);
615 i = aty_ld_le32(GP_IO, par);
616 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
617 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
618 __delay(200);
619
620 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
621 __delay(2000);
622 i = aty_ld_le32(GP_IO, par);
623 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
624 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
625 __delay(200);
626
627 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
628 __delay(2000);
629 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
630 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
631 return sense;
632 }
633
634 #endif /* defined(CONFIG_PPC) */
635
636 /* ------------------------------------------------------------------------- */
637
638 /*
639 * CRTC programming
640 */
641
642 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
643 {
644 #ifdef CONFIG_FB_ATY_GENERIC_LCD
645 if (par->lcd_table != 0) {
646 if (!M64_HAS(LT_LCD_REGS)) {
647 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
648 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
649 }
650 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
651 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
652
653
654 /* switch to non shadow registers */
655 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
656 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
657
658 /* save stretching */
659 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
660 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
661 if (!M64_HAS(LT_LCD_REGS))
662 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
663 }
664 #endif
665 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
666 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
667 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
668 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
669 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
670 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
671 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
672
673 #ifdef CONFIG_FB_ATY_GENERIC_LCD
674 if (par->lcd_table != 0) {
675 /* switch to shadow registers */
676 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
677 SHADOW_EN | SHADOW_RW_EN, par);
678
679 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
680 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
681 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
682 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
683
684 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
685 }
686 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
687 }
688
689 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
690 {
691 #ifdef CONFIG_FB_ATY_GENERIC_LCD
692 if (par->lcd_table != 0) {
693 /* stop CRTC */
694 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl &
695 ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
696
697 /* update non-shadow registers first */
698 aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
699 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
700 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
701
702 /* temporarily disable stretching */
703 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching &
704 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
705 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching &
706 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
707 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
708 }
709 #endif
710 /* turn off CRT */
711 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
712
713 DPRINTK("setting up CRTC\n");
714 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
715 ((((crtc->h_tot_disp >> 16) & 0xff) + 1) << 3),
716 (((crtc->v_tot_disp >> 16) & 0x7ff) + 1),
717 (crtc->h_sync_strt_wid & 0x200000) ? 'N' : 'P',
718 (crtc->v_sync_strt_wid & 0x200000) ? 'N' : 'P',
719 (crtc->gen_cntl & CRTC_CSYNC_EN) ? 'P' : 'N');
720
721 DPRINTK("CRTC_H_TOTAL_DISP: %x\n", crtc->h_tot_disp);
722 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n", crtc->h_sync_strt_wid);
723 DPRINTK("CRTC_V_TOTAL_DISP: %x\n", crtc->v_tot_disp);
724 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n", crtc->v_sync_strt_wid);
725 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
726 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
727 DPRINTK("CRTC_GEN_CNTL: %x\n", crtc->gen_cntl);
728
729 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
730 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
731 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
732 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
733 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
734 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
735
736 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
737 #if 0
738 FIXME
739 if (par->accel_flags & FB_ACCELF_TEXT)
740 aty_init_engine(par, info);
741 #endif
742 #ifdef CONFIG_FB_ATY_GENERIC_LCD
743 /* after setting the CRTC registers we should set the LCD registers. */
744 if (par->lcd_table != 0) {
745 /* switch to shadow registers */
746 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
747 SHADOW_EN | SHADOW_RW_EN, par);
748
749 DPRINTK("set shadow CRT to %ix%i %c%c\n",
750 ((((crtc->shadow_h_tot_disp >> 16) & 0xff) + 1) << 3),
751 (((crtc->shadow_v_tot_disp >> 16) & 0x7ff) + 1),
752 (crtc->shadow_h_sync_strt_wid & 0x200000) ? 'N' : 'P',
753 (crtc->shadow_v_sync_strt_wid & 0x200000) ? 'N' : 'P');
754
755 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n",
756 crtc->shadow_h_tot_disp);
757 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n",
758 crtc->shadow_h_sync_strt_wid);
759 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n",
760 crtc->shadow_v_tot_disp);
761 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n",
762 crtc->shadow_v_sync_strt_wid);
763
764 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
765 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
766 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
767 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
768
769 /* restore CRTC selection & shadow state and enable stretching */
770 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
771 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
772 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
773 if (!M64_HAS(LT_LCD_REGS))
774 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
775
776 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
777 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
778 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
779 if (!M64_HAS(LT_LCD_REGS)) {
780 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
781 aty_ld_le32(LCD_INDEX, par);
782 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
783 }
784 }
785 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
786 }
787
788 static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp)
789 {
790 u32 line_length = vxres * bpp / 8;
791
792 if (par->ram_type == SGRAM ||
793 (!M64_HAS(XL_MEM) && par->ram_type == WRAM))
794 line_length = (line_length + 63) & ~63;
795
796 return line_length;
797 }
798
799 static int aty_var_to_crtc(const struct fb_info *info,
800 const struct fb_var_screeninfo *var,
801 struct crtc *crtc)
802 {
803 struct atyfb_par *par = (struct atyfb_par *) info->par;
804 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
805 u32 sync, vmode, vdisplay;
806 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
807 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
808 u32 pix_width, dp_pix_width, dp_chain_mask;
809 u32 line_length;
810
811 /* input */
812 xres = (var->xres + 7) & ~7;
813 yres = var->yres;
814 vxres = (var->xres_virtual + 7) & ~7;
815 vyres = var->yres_virtual;
816 xoffset = (var->xoffset + 7) & ~7;
817 yoffset = var->yoffset;
818 bpp = var->bits_per_pixel;
819 if (bpp == 16)
820 bpp = (var->green.length == 5) ? 15 : 16;
821 sync = var->sync;
822 vmode = var->vmode;
823
824 /* convert (and round up) and validate */
825 if (vxres < xres + xoffset)
826 vxres = xres + xoffset;
827 h_disp = xres;
828
829 if (vyres < yres + yoffset)
830 vyres = yres + yoffset;
831 v_disp = yres;
832
833 if (bpp <= 8) {
834 bpp = 8;
835 pix_width = CRTC_PIX_WIDTH_8BPP;
836 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
837 BYTE_ORDER_LSB_TO_MSB;
838 dp_chain_mask = DP_CHAIN_8BPP;
839 } else if (bpp <= 15) {
840 bpp = 16;
841 pix_width = CRTC_PIX_WIDTH_15BPP;
842 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
843 BYTE_ORDER_LSB_TO_MSB;
844 dp_chain_mask = DP_CHAIN_15BPP;
845 } else if (bpp <= 16) {
846 bpp = 16;
847 pix_width = CRTC_PIX_WIDTH_16BPP;
848 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
849 BYTE_ORDER_LSB_TO_MSB;
850 dp_chain_mask = DP_CHAIN_16BPP;
851 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
852 bpp = 24;
853 pix_width = CRTC_PIX_WIDTH_24BPP;
854 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
855 BYTE_ORDER_LSB_TO_MSB;
856 dp_chain_mask = DP_CHAIN_24BPP;
857 } else if (bpp <= 32) {
858 bpp = 32;
859 pix_width = CRTC_PIX_WIDTH_32BPP;
860 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
861 BYTE_ORDER_LSB_TO_MSB;
862 dp_chain_mask = DP_CHAIN_32BPP;
863 } else
864 FAIL("invalid bpp");
865
866 line_length = calc_line_length(par, vxres, bpp);
867
868 if (vyres * line_length > info->fix.smem_len)
869 FAIL("not enough video RAM");
870
871 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
872 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
873
874 if ((xres > 1920) || (yres > 1200)) {
875 FAIL("MACH64 chips are designed for max 1920x1200\n"
876 "select another resolution.");
877 }
878 h_sync_strt = h_disp + var->right_margin;
879 h_sync_end = h_sync_strt + var->hsync_len;
880 h_sync_dly = var->right_margin & 7;
881 h_total = h_sync_end + h_sync_dly + var->left_margin;
882
883 v_sync_strt = v_disp + var->lower_margin;
884 v_sync_end = v_sync_strt + var->vsync_len;
885 v_total = v_sync_end + var->upper_margin;
886
887 #ifdef CONFIG_FB_ATY_GENERIC_LCD
888 if (par->lcd_table != 0) {
889 if (!M64_HAS(LT_LCD_REGS)) {
890 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
891 crtc->lcd_index = lcd_index &
892 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS |
893 LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
894 aty_st_le32(LCD_INDEX, lcd_index, par);
895 }
896
897 if (!M64_HAS(MOBIL_BUS))
898 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
899
900 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
901 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
902
903 crtc->lcd_gen_cntl &=
904 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
905 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
906 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
907 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
908
909 if ((crtc->lcd_gen_cntl & LCD_ON) &&
910 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
911 /*
912 * We cannot display the mode on the LCD. If the CRT is
913 * enabled we can turn off the LCD.
914 * If the CRT is off, it isn't a good idea to switch it
915 * on; we don't know if one is connected. So it's better
916 * to fail then.
917 */
918 if (crtc->lcd_gen_cntl & CRT_ON) {
919 if (!(var->activate & FB_ACTIVATE_TEST))
920 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
921 crtc->lcd_gen_cntl &= ~LCD_ON;
922 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
923 } else {
924 if (!(var->activate & FB_ACTIVATE_TEST))
925 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
926 return -EINVAL;
927 }
928 }
929 }
930
931 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
932 int VScan = 1;
933 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
934 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
935 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
936
937 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
938
939 /*
940 * This is horror! When we simulate, say 640x480 on an 800x600
941 * LCD monitor, the CRTC should be programmed 800x600 values for
942 * the non visible part, but 640x480 for the visible part.
943 * This code has been tested on a laptop with it's 1400x1050 LCD
944 * monitor and a conventional monitor both switched on.
945 * Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
946 * works with little glitches also with DOUBLESCAN modes
947 */
948 if (yres < par->lcd_height) {
949 VScan = par->lcd_height / yres;
950 if (VScan > 1) {
951 VScan = 2;
952 vmode |= FB_VMODE_DOUBLE;
953 }
954 }
955
956 h_sync_strt = h_disp + par->lcd_right_margin;
957 h_sync_end = h_sync_strt + par->lcd_hsync_len;
958 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
959 h_total = h_disp + par->lcd_hblank_len;
960
961 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
962 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
963 v_total = v_disp + par->lcd_vblank_len / VScan;
964 }
965 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
966
967 h_disp = (h_disp >> 3) - 1;
968 h_sync_strt = (h_sync_strt >> 3) - 1;
969 h_sync_end = (h_sync_end >> 3) - 1;
970 h_total = (h_total >> 3) - 1;
971 h_sync_wid = h_sync_end - h_sync_strt;
972
973 FAIL_MAX("h_disp too large", h_disp, 0xff);
974 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
975 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
976 if (h_sync_wid > 0x1f)
977 h_sync_wid = 0x1f;
978 FAIL_MAX("h_total too large", h_total, 0x1ff);
979
980 if (vmode & FB_VMODE_DOUBLE) {
981 v_disp <<= 1;
982 v_sync_strt <<= 1;
983 v_sync_end <<= 1;
984 v_total <<= 1;
985 }
986
987 vdisplay = yres;
988 #ifdef CONFIG_FB_ATY_GENERIC_LCD
989 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
990 vdisplay = par->lcd_height;
991 #endif
992
993 v_disp--;
994 v_sync_strt--;
995 v_sync_end--;
996 v_total--;
997 v_sync_wid = v_sync_end - v_sync_strt;
998
999 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
1000 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
1001 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
1002 if (v_sync_wid > 0x1f)
1003 v_sync_wid = 0x1f;
1004 FAIL_MAX("v_total too large", v_total, 0x7ff);
1005
1006 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
1007
1008 /* output */
1009 crtc->vxres = vxres;
1010 crtc->vyres = vyres;
1011 crtc->xoffset = xoffset;
1012 crtc->yoffset = yoffset;
1013 crtc->bpp = bpp;
1014 crtc->off_pitch =
1015 ((yoffset * line_length + xoffset * bpp / 8) / 8) |
1016 ((line_length / bpp) << 22);
1017 crtc->vline_crnt_vline = 0;
1018
1019 crtc->h_tot_disp = h_total | (h_disp << 16);
1020 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly << 8) |
1021 ((h_sync_strt & 0x100) << 4) | (h_sync_wid << 16) |
1022 (h_sync_pol << 21);
1023 crtc->v_tot_disp = v_total | (v_disp << 16);
1024 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1025 (v_sync_pol << 21);
1026
1027 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
1028 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
1029 crtc->gen_cntl |= CRTC_VGA_LINEAR;
1030
1031 /* Enable doublescan mode if requested */
1032 if (vmode & FB_VMODE_DOUBLE)
1033 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
1034 /* Enable interlaced mode if requested */
1035 if (vmode & FB_VMODE_INTERLACED)
1036 crtc->gen_cntl |= CRTC_INTERLACE_EN;
1037 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1038 if (par->lcd_table != 0) {
1039 vdisplay = yres;
1040 if (vmode & FB_VMODE_DOUBLE)
1041 vdisplay <<= 1;
1042 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
1043 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1044 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1045 USE_SHADOWED_VEND |
1046 USE_SHADOWED_ROWCUR |
1047 SHADOW_EN | SHADOW_RW_EN);
1048 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR/* | LOCK_8DOT*/;
1049
1050 /* MOBILITY M1 tested, FIXME: LT */
1051 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1052 if (!M64_HAS(LT_LCD_REGS))
1053 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1054 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1055
1056 crtc->horz_stretching &= ~(HORZ_STRETCH_RATIO |
1057 HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1058 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1059 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1060 do {
1061 /*
1062 * The horizontal blender misbehaves when
1063 * HDisplay is less than a certain threshold
1064 * (440 for a 1024-wide panel). It doesn't
1065 * stretch such modes enough. Use pixel
1066 * replication instead of blending to stretch
1067 * modes that can be made to exactly fit the
1068 * panel width. The undocumented "NoLCDBlend"
1069 * option allows the pixel-replicated mode to
1070 * be slightly wider or narrower than the
1071 * panel width. It also causes a mode that is
1072 * exactly half as wide as the panel to be
1073 * pixel-replicated, rather than blended.
1074 */
1075 int HDisplay = xres & ~7;
1076 int nStretch = par->lcd_width / HDisplay;
1077 int Remainder = par->lcd_width % HDisplay;
1078
1079 if ((!Remainder && ((nStretch > 2))) ||
1080 (((HDisplay * 16) / par->lcd_width) < 7)) {
1081 static const char StretchLoops[] = { 10, 12, 13, 15, 16 };
1082 int horz_stretch_loop = -1, BestRemainder;
1083 int Numerator = HDisplay, Denominator = par->lcd_width;
1084 int Index = 5;
1085 ATIReduceRatio(&Numerator, &Denominator);
1086
1087 BestRemainder = (Numerator * 16) / Denominator;
1088 while (--Index >= 0) {
1089 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1090 Denominator;
1091 if (Remainder < BestRemainder) {
1092 horz_stretch_loop = Index;
1093 if (!(BestRemainder = Remainder))
1094 break;
1095 }
1096 }
1097
1098 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1099 int horz_stretch_ratio = 0, Accumulator = 0;
1100 int reuse_previous = 1;
1101
1102 Index = StretchLoops[horz_stretch_loop];
1103
1104 while (--Index >= 0) {
1105 if (Accumulator > 0)
1106 horz_stretch_ratio |= reuse_previous;
1107 else
1108 Accumulator += Denominator;
1109 Accumulator -= Numerator;
1110 reuse_previous <<= 1;
1111 }
1112
1113 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1114 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1115 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1116 break; /* Out of the do { ... } while (0) */
1117 }
1118 }
1119
1120 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1121 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1122 } while (0);
1123 }
1124
1125 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1126 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1127 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1128
1129 if (!M64_HAS(LT_LCD_REGS) &&
1130 xres <= (M64_HAS(MOBIL_BUS) ? 1024 : 800))
1131 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1132 } else {
1133 /*
1134 * Don't use vertical blending if the mode is too wide
1135 * or not vertically stretched.
1136 */
1137 crtc->vert_stretching = 0;
1138 }
1139 /* copy to shadow crtc */
1140 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1141 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1142 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1143 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1144 }
1145 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1146
1147 if (M64_HAS(MAGIC_FIFO)) {
1148 /* FIXME: display FIFO low watermark values */
1149 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1150 }
1151 crtc->dp_pix_width = dp_pix_width;
1152 crtc->dp_chain_mask = dp_chain_mask;
1153
1154 return 0;
1155 }
1156
1157 static int aty_crtc_to_var(const struct crtc *crtc,
1158 struct fb_var_screeninfo *var)
1159 {
1160 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1161 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1162 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1163 u32 pix_width;
1164 u32 double_scan, interlace;
1165
1166 /* input */
1167 h_total = crtc->h_tot_disp & 0x1ff;
1168 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1169 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1170 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1171 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1172 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1173 v_total = crtc->v_tot_disp & 0x7ff;
1174 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1175 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1176 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1177 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1178 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1179 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1180 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1181 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1182
1183 /* convert */
1184 xres = (h_disp + 1) * 8;
1185 yres = v_disp + 1;
1186 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1187 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1188 hslen = h_sync_wid * 8;
1189 upper = v_total - v_sync_strt - v_sync_wid;
1190 lower = v_sync_strt - v_disp;
1191 vslen = v_sync_wid;
1192 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1193 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1194 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1195
1196 switch (pix_width) {
1197 #if 0
1198 case CRTC_PIX_WIDTH_4BPP:
1199 bpp = 4;
1200 var->red.offset = 0;
1201 var->red.length = 8;
1202 var->green.offset = 0;
1203 var->green.length = 8;
1204 var->blue.offset = 0;
1205 var->blue.length = 8;
1206 var->transp.offset = 0;
1207 var->transp.length = 0;
1208 break;
1209 #endif
1210 case CRTC_PIX_WIDTH_8BPP:
1211 bpp = 8;
1212 var->red.offset = 0;
1213 var->red.length = 8;
1214 var->green.offset = 0;
1215 var->green.length = 8;
1216 var->blue.offset = 0;
1217 var->blue.length = 8;
1218 var->transp.offset = 0;
1219 var->transp.length = 0;
1220 break;
1221 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1222 bpp = 16;
1223 var->red.offset = 10;
1224 var->red.length = 5;
1225 var->green.offset = 5;
1226 var->green.length = 5;
1227 var->blue.offset = 0;
1228 var->blue.length = 5;
1229 var->transp.offset = 0;
1230 var->transp.length = 0;
1231 break;
1232 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1233 bpp = 16;
1234 var->red.offset = 11;
1235 var->red.length = 5;
1236 var->green.offset = 5;
1237 var->green.length = 6;
1238 var->blue.offset = 0;
1239 var->blue.length = 5;
1240 var->transp.offset = 0;
1241 var->transp.length = 0;
1242 break;
1243 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1244 bpp = 24;
1245 var->red.offset = 16;
1246 var->red.length = 8;
1247 var->green.offset = 8;
1248 var->green.length = 8;
1249 var->blue.offset = 0;
1250 var->blue.length = 8;
1251 var->transp.offset = 0;
1252 var->transp.length = 0;
1253 break;
1254 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1255 bpp = 32;
1256 var->red.offset = 16;
1257 var->red.length = 8;
1258 var->green.offset = 8;
1259 var->green.length = 8;
1260 var->blue.offset = 0;
1261 var->blue.length = 8;
1262 var->transp.offset = 24;
1263 var->transp.length = 8;
1264 break;
1265 default:
1266 PRINTKE("Invalid pixel width\n");
1267 return -EINVAL;
1268 }
1269
1270 /* output */
1271 var->xres = xres;
1272 var->yres = yres;
1273 var->xres_virtual = crtc->vxres;
1274 var->yres_virtual = crtc->vyres;
1275 var->bits_per_pixel = bpp;
1276 var->left_margin = left;
1277 var->right_margin = right;
1278 var->upper_margin = upper;
1279 var->lower_margin = lower;
1280 var->hsync_len = hslen;
1281 var->vsync_len = vslen;
1282 var->sync = sync;
1283 var->vmode = FB_VMODE_NONINTERLACED;
1284 /*
1285 * In double scan mode, the vertical parameters are doubled,
1286 * so we need to halve them to get the right values.
1287 * In interlaced mode the values are already correct,
1288 * so no correction is necessary.
1289 */
1290 if (interlace)
1291 var->vmode = FB_VMODE_INTERLACED;
1292
1293 if (double_scan) {
1294 var->vmode = FB_VMODE_DOUBLE;
1295 var->yres >>= 1;
1296 var->upper_margin >>= 1;
1297 var->lower_margin >>= 1;
1298 var->vsync_len >>= 1;
1299 }
1300
1301 return 0;
1302 }
1303
1304 /* ------------------------------------------------------------------------- */
1305
1306 static int atyfb_set_par(struct fb_info *info)
1307 {
1308 struct atyfb_par *par = (struct atyfb_par *) info->par;
1309 struct fb_var_screeninfo *var = &info->var;
1310 u32 tmp, pixclock;
1311 int err;
1312 #ifdef DEBUG
1313 struct fb_var_screeninfo debug;
1314 u32 pixclock_in_ps;
1315 #endif
1316 if (par->asleep)
1317 return 0;
1318
1319 err = aty_var_to_crtc(info, var, &par->crtc);
1320 if (err)
1321 return err;
1322
1323 pixclock = atyfb_get_pixclock(var, par);
1324
1325 if (pixclock == 0) {
1326 PRINTKE("Invalid pixclock\n");
1327 return -EINVAL;
1328 } else {
1329 err = par->pll_ops->var_to_pll(info, pixclock,
1330 var->bits_per_pixel, &par->pll);
1331 if (err)
1332 return err;
1333 }
1334
1335 par->accel_flags = var->accel_flags; /* hack */
1336
1337 if (var->accel_flags) {
1338 info->fbops->fb_sync = atyfb_sync;
1339 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1340 } else {
1341 info->fbops->fb_sync = NULL;
1342 info->flags |= FBINFO_HWACCEL_DISABLED;
1343 }
1344
1345 if (par->blitter_may_be_busy)
1346 wait_for_idle(par);
1347
1348 aty_set_crtc(par, &par->crtc);
1349 par->dac_ops->set_dac(info, &par->pll,
1350 var->bits_per_pixel, par->accel_flags);
1351 par->pll_ops->set_pll(info, &par->pll);
1352
1353 #ifdef DEBUG
1354 if (par->pll_ops && par->pll_ops->pll_to_var)
1355 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
1356 else
1357 pixclock_in_ps = 0;
1358
1359 if (0 == pixclock_in_ps) {
1360 PRINTKE("ALERT ops->pll_to_var get 0\n");
1361 pixclock_in_ps = pixclock;
1362 }
1363
1364 memset(&debug, 0, sizeof(debug));
1365 if (!aty_crtc_to_var(&par->crtc, &debug)) {
1366 u32 hSync, vRefresh;
1367 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1368 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1369
1370 h_disp = debug.xres;
1371 h_sync_strt = h_disp + debug.right_margin;
1372 h_sync_end = h_sync_strt + debug.hsync_len;
1373 h_total = h_sync_end + debug.left_margin;
1374 v_disp = debug.yres;
1375 v_sync_strt = v_disp + debug.lower_margin;
1376 v_sync_end = v_sync_strt + debug.vsync_len;
1377 v_total = v_sync_end + debug.upper_margin;
1378
1379 hSync = 1000000000 / (pixclock_in_ps * h_total);
1380 vRefresh = (hSync * 1000) / v_total;
1381 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1382 vRefresh *= 2;
1383 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1384 vRefresh /= 2;
1385
1386 DPRINTK("atyfb_set_par\n");
1387 DPRINTK(" Set Visible Mode to %ix%i-%i\n",
1388 var->xres, var->yres, var->bits_per_pixel);
1389 DPRINTK(" Virtual resolution %ix%i, "
1390 "pixclock_in_ps %i (calculated %i)\n",
1391 var->xres_virtual, var->yres_virtual,
1392 pixclock, pixclock_in_ps);
1393 DPRINTK(" Dot clock: %i MHz\n",
1394 1000000 / pixclock_in_ps);
1395 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1396 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1397 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1398 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1399 h_disp, h_sync_strt, h_sync_end, h_total,
1400 v_disp, v_sync_strt, v_sync_end, v_total);
1401 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1402 pixclock_in_ps,
1403 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1404 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1405 }
1406 #endif /* DEBUG */
1407
1408 if (!M64_HAS(INTEGRATED)) {
1409 /* Don't forget MEM_CNTL */
1410 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1411 switch (var->bits_per_pixel) {
1412 case 8:
1413 tmp |= 0x02000000;
1414 break;
1415 case 16:
1416 tmp |= 0x03000000;
1417 break;
1418 case 32:
1419 tmp |= 0x06000000;
1420 break;
1421 }
1422 aty_st_le32(MEM_CNTL, tmp, par);
1423 } else {
1424 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1425 if (!M64_HAS(MAGIC_POSTDIV))
1426 tmp |= par->mem_refresh_rate << 20;
1427 switch (var->bits_per_pixel) {
1428 case 8:
1429 case 24:
1430 tmp |= 0x00000000;
1431 break;
1432 case 16:
1433 tmp |= 0x04000000;
1434 break;
1435 case 32:
1436 tmp |= 0x08000000;
1437 break;
1438 }
1439 if (M64_HAS(CT_BUS)) {
1440 aty_st_le32(DAC_CNTL, 0x87010184, par);
1441 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1442 } else if (M64_HAS(VT_BUS)) {
1443 aty_st_le32(DAC_CNTL, 0x87010184, par);
1444 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1445 } else if (M64_HAS(MOBIL_BUS)) {
1446 aty_st_le32(DAC_CNTL, 0x80010102, par);
1447 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1448 } else {
1449 /* GT */
1450 aty_st_le32(DAC_CNTL, 0x86010102, par);
1451 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1452 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1453 }
1454 aty_st_le32(MEM_CNTL, tmp, par);
1455 }
1456 aty_st_8(DAC_MASK, 0xff, par);
1457
1458 info->fix.line_length = calc_line_length(par, var->xres_virtual,
1459 var->bits_per_pixel);
1460
1461 info->fix.visual = var->bits_per_pixel <= 8 ?
1462 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1463
1464 /* Initialize the graphics engine */
1465 if (par->accel_flags & FB_ACCELF_TEXT)
1466 aty_init_engine(par, info);
1467
1468 #ifdef CONFIG_BOOTX_TEXT
1469 btext_update_display(info->fix.smem_start,
1470 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1471 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1472 var->bits_per_pixel,
1473 par->crtc.vxres * var->bits_per_pixel / 8);
1474 #endif /* CONFIG_BOOTX_TEXT */
1475 #if 0
1476 /* switch to accelerator mode */
1477 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1478 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1479 #endif
1480 #ifdef DEBUG
1481 {
1482 /* dump non shadow CRTC, pll, LCD registers */
1483 int i; u32 base;
1484
1485 /* CRTC registers */
1486 base = 0x2000;
1487 printk("debug atyfb: Mach64 non-shadow register values:");
1488 for (i = 0; i < 256; i = i+4) {
1489 if (i % 16 == 0)
1490 printk("\ndebug atyfb: 0x%04X: ", base + i);
1491 printk(" %08X", aty_ld_le32(i, par));
1492 }
1493 printk("\n\n");
1494
1495 #ifdef CONFIG_FB_ATY_CT
1496 /* PLL registers */
1497 base = 0x00;
1498 printk("debug atyfb: Mach64 PLL register values:");
1499 for (i = 0; i < 64; i++) {
1500 if (i % 16 == 0)
1501 printk("\ndebug atyfb: 0x%02X: ", base + i);
1502 if (i % 4 == 0)
1503 printk(" ");
1504 printk("%02X", aty_ld_pll_ct(i, par));
1505 }
1506 printk("\n\n");
1507 #endif /* CONFIG_FB_ATY_CT */
1508
1509 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1510 if (par->lcd_table != 0) {
1511 /* LCD registers */
1512 base = 0x00;
1513 printk("debug atyfb: LCD register values:");
1514 if (M64_HAS(LT_LCD_REGS)) {
1515 for (i = 0; i <= POWER_MANAGEMENT; i++) {
1516 if (i == EXT_VERT_STRETCH)
1517 continue;
1518 printk("\ndebug atyfb: 0x%04X: ",
1519 lt_lcd_regs[i]);
1520 printk(" %08X", aty_ld_lcd(i, par));
1521 }
1522 } else {
1523 for (i = 0; i < 64; i++) {
1524 if (i % 4 == 0)
1525 printk("\ndebug atyfb: 0x%02X: ",
1526 base + i);
1527 printk(" %08X", aty_ld_lcd(i, par));
1528 }
1529 }
1530 printk("\n\n");
1531 }
1532 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1533 }
1534 #endif /* DEBUG */
1535 return 0;
1536 }
1537
1538 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1539 {
1540 struct atyfb_par *par = (struct atyfb_par *) info->par;
1541 int err;
1542 struct crtc crtc;
1543 union aty_pll pll;
1544 u32 pixclock;
1545
1546 memcpy(&pll, &par->pll, sizeof(pll));
1547
1548 err = aty_var_to_crtc(info, var, &crtc);
1549 if (err)
1550 return err;
1551
1552 pixclock = atyfb_get_pixclock(var, par);
1553
1554 if (pixclock == 0) {
1555 if (!(var->activate & FB_ACTIVATE_TEST))
1556 PRINTKE("Invalid pixclock\n");
1557 return -EINVAL;
1558 } else {
1559 err = par->pll_ops->var_to_pll(info, pixclock,
1560 var->bits_per_pixel, &pll);
1561 if (err)
1562 return err;
1563 }
1564
1565 if (var->accel_flags & FB_ACCELF_TEXT)
1566 info->var.accel_flags = FB_ACCELF_TEXT;
1567 else
1568 info->var.accel_flags = 0;
1569
1570 aty_crtc_to_var(&crtc, var);
1571 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1572 return 0;
1573 }
1574
1575 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1576 {
1577 u32 xoffset = info->var.xoffset;
1578 u32 yoffset = info->var.yoffset;
1579 u32 line_length = info->fix.line_length;
1580 u32 bpp = info->var.bits_per_pixel;
1581
1582 par->crtc.off_pitch =
1583 ((yoffset * line_length + xoffset * bpp / 8) / 8) |
1584 ((line_length / bpp) << 22);
1585 }
1586
1587
1588 /*
1589 * Open/Release the frame buffer device
1590 */
1591
1592 static int atyfb_open(struct fb_info *info, int user)
1593 {
1594 struct atyfb_par *par = (struct atyfb_par *) info->par;
1595
1596 if (user) {
1597 par->open++;
1598 #ifdef __sparc__
1599 par->mmaped = 0;
1600 #endif
1601 }
1602 return 0;
1603 }
1604
1605 static irqreturn_t aty_irq(int irq, void *dev_id)
1606 {
1607 struct atyfb_par *par = dev_id;
1608 int handled = 0;
1609 u32 int_cntl;
1610
1611 spin_lock(&par->int_lock);
1612
1613 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1614
1615 if (int_cntl & CRTC_VBLANK_INT) {
1616 /* clear interrupt */
1617 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) |
1618 CRTC_VBLANK_INT_AK, par);
1619 par->vblank.count++;
1620 if (par->vblank.pan_display) {
1621 par->vblank.pan_display = 0;
1622 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1623 }
1624 wake_up_interruptible(&par->vblank.wait);
1625 handled = 1;
1626 }
1627
1628 spin_unlock(&par->int_lock);
1629
1630 return IRQ_RETVAL(handled);
1631 }
1632
1633 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1634 {
1635 u32 int_cntl;
1636
1637 if (!test_and_set_bit(0, &par->irq_flags)) {
1638 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1639 clear_bit(0, &par->irq_flags);
1640 return -EINVAL;
1641 }
1642 spin_lock_irq(&par->int_lock);
1643 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1644 /* clear interrupt */
1645 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1646 /* enable interrupt */
1647 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1648 spin_unlock_irq(&par->int_lock);
1649 } else if (reenable) {
1650 spin_lock_irq(&par->int_lock);
1651 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1652 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1653 printk("atyfb: someone disabled IRQ [%08x]\n",
1654 int_cntl);
1655 /* re-enable interrupt */
1656 aty_st_le32(CRTC_INT_CNTL, int_cntl |
1657 CRTC_VBLANK_INT_EN, par);
1658 }
1659 spin_unlock_irq(&par->int_lock);
1660 }
1661
1662 return 0;
1663 }
1664
1665 static int aty_disable_irq(struct atyfb_par *par)
1666 {
1667 u32 int_cntl;
1668
1669 if (test_and_clear_bit(0, &par->irq_flags)) {
1670 if (par->vblank.pan_display) {
1671 par->vblank.pan_display = 0;
1672 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1673 }
1674 spin_lock_irq(&par->int_lock);
1675 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1676 /* disable interrupt */
1677 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par);
1678 spin_unlock_irq(&par->int_lock);
1679 free_irq(par->irq, par);
1680 }
1681
1682 return 0;
1683 }
1684
1685 static int atyfb_release(struct fb_info *info, int user)
1686 {
1687 struct atyfb_par *par = (struct atyfb_par *) info->par;
1688 #ifdef __sparc__
1689 int was_mmaped;
1690 #endif
1691
1692 if (!user)
1693 return 0;
1694
1695 par->open--;
1696 mdelay(1);
1697 wait_for_idle(par);
1698
1699 if (par->open)
1700 return 0;
1701
1702 #ifdef __sparc__
1703 was_mmaped = par->mmaped;
1704
1705 par->mmaped = 0;
1706
1707 if (was_mmaped) {
1708 struct fb_var_screeninfo var;
1709
1710 /*
1711 * Now reset the default display config, we have
1712 * no idea what the program(s) which mmap'd the
1713 * chip did to the configuration, nor whether it
1714 * restored it correctly.
1715 */
1716 var = default_var;
1717 if (noaccel)
1718 var.accel_flags &= ~FB_ACCELF_TEXT;
1719 else
1720 var.accel_flags |= FB_ACCELF_TEXT;
1721 if (var.yres == var.yres_virtual) {
1722 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1723 var.yres_virtual =
1724 ((videoram * 8) / var.bits_per_pixel) /
1725 var.xres_virtual;
1726 if (var.yres_virtual < var.yres)
1727 var.yres_virtual = var.yres;
1728 }
1729 }
1730 #endif
1731 aty_disable_irq(par);
1732
1733 return 0;
1734 }
1735
1736 /*
1737 * Pan or Wrap the Display
1738 *
1739 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1740 */
1741
1742 static int atyfb_pan_display(struct fb_var_screeninfo *var,
1743 struct fb_info *info)
1744 {
1745 struct atyfb_par *par = (struct atyfb_par *) info->par;
1746 u32 xres, yres, xoffset, yoffset;
1747
1748 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1749 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1750 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1751 yres >>= 1;
1752 xoffset = (var->xoffset + 7) & ~7;
1753 yoffset = var->yoffset;
1754 if (xoffset + xres > par->crtc.vxres ||
1755 yoffset + yres > par->crtc.vyres)
1756 return -EINVAL;
1757 info->var.xoffset = xoffset;
1758 info->var.yoffset = yoffset;
1759 if (par->asleep)
1760 return 0;
1761
1762 set_off_pitch(par, info);
1763 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1764 par->vblank.pan_display = 1;
1765 } else {
1766 par->vblank.pan_display = 0;
1767 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1768 }
1769
1770 return 0;
1771 }
1772
1773 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1774 {
1775 struct aty_interrupt *vbl;
1776 unsigned int count;
1777 int ret;
1778
1779 switch (crtc) {
1780 case 0:
1781 vbl = &par->vblank;
1782 break;
1783 default:
1784 return -ENODEV;
1785 }
1786
1787 ret = aty_enable_irq(par, 0);
1788 if (ret)
1789 return ret;
1790
1791 count = vbl->count;
1792 ret = wait_event_interruptible_timeout(vbl->wait,
1793 count != vbl->count, HZ/10);
1794 if (ret < 0)
1795 return ret;
1796 if (ret == 0) {
1797 aty_enable_irq(par, 1);
1798 return -ETIMEDOUT;
1799 }
1800
1801 return 0;
1802 }
1803
1804
1805 #ifdef DEBUG
1806 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1807 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1808
1809 struct atyclk {
1810 u32 ref_clk_per;
1811 u8 pll_ref_div;
1812 u8 mclk_fb_div;
1813 u8 mclk_post_div; /* 1,2,3,4,8 */
1814 u8 mclk_fb_mult; /* 2 or 4 */
1815 u8 xclk_post_div; /* 1,2,3,4,8 */
1816 u8 vclk_fb_div;
1817 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1818 u32 dsp_xclks_per_row; /* 0-16383 */
1819 u32 dsp_loop_latency; /* 0-15 */
1820 u32 dsp_precision; /* 0-7 */
1821 u32 dsp_on; /* 0-2047 */
1822 u32 dsp_off; /* 0-2047 */
1823 };
1824
1825 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1826 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1827 #endif
1828
1829 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1830 {
1831 struct atyfb_par *par = (struct atyfb_par *) info->par;
1832 #ifdef __sparc__
1833 struct fbtype fbtyp;
1834 #endif
1835
1836 switch (cmd) {
1837 #ifdef __sparc__
1838 case FBIOGTYPE:
1839 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1840 fbtyp.fb_width = par->crtc.vxres;
1841 fbtyp.fb_height = par->crtc.vyres;
1842 fbtyp.fb_depth = info->var.bits_per_pixel;
1843 fbtyp.fb_cmsize = info->cmap.len;
1844 fbtyp.fb_size = info->fix.smem_len;
1845 if (copy_to_user((struct fbtype __user *) arg, &fbtyp,
1846 sizeof(fbtyp)))
1847 return -EFAULT;
1848 break;
1849 #endif /* __sparc__ */
1850
1851 case FBIO_WAITFORVSYNC:
1852 {
1853 u32 crtc;
1854
1855 if (get_user(crtc, (__u32 __user *) arg))
1856 return -EFAULT;
1857
1858 return aty_waitforvblank(par, crtc);
1859 }
1860
1861 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1862 case ATYIO_CLKR:
1863 if (M64_HAS(INTEGRATED)) {
1864 struct atyclk clk;
1865 union aty_pll *pll = &par->pll;
1866 u32 dsp_config = pll->ct.dsp_config;
1867 u32 dsp_on_off = pll->ct.dsp_on_off;
1868 clk.ref_clk_per = par->ref_clk_per;
1869 clk.pll_ref_div = pll->ct.pll_ref_div;
1870 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1871 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1872 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1873 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1874 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1875 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1876 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1877 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1878 clk.dsp_precision = (dsp_config >> 20) & 7;
1879 clk.dsp_off = dsp_on_off & 0x7ff;
1880 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1881 if (copy_to_user((struct atyclk __user *) arg, &clk,
1882 sizeof(clk)))
1883 return -EFAULT;
1884 } else
1885 return -EINVAL;
1886 break;
1887 case ATYIO_CLKW:
1888 if (M64_HAS(INTEGRATED)) {
1889 struct atyclk clk;
1890 union aty_pll *pll = &par->pll;
1891 if (copy_from_user(&clk, (struct atyclk __user *) arg,
1892 sizeof(clk)))
1893 return -EFAULT;
1894 par->ref_clk_per = clk.ref_clk_per;
1895 pll->ct.pll_ref_div = clk.pll_ref_div;
1896 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1897 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1898 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1899 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1900 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1901 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1902 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1903 ((clk.dsp_loop_latency & 0xf) << 16) |
1904 ((clk.dsp_precision & 7) << 20);
1905 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) |
1906 ((clk.dsp_on & 0x7ff) << 16);
1907 /*aty_calc_pll_ct(info, &pll->ct);*/
1908 aty_set_pll_ct(info, pll);
1909 } else
1910 return -EINVAL;
1911 break;
1912 case ATYIO_FEATR:
1913 if (get_user(par->features, (u32 __user *) arg))
1914 return -EFAULT;
1915 break;
1916 case ATYIO_FEATW:
1917 if (put_user(par->features, (u32 __user *) arg))
1918 return -EFAULT;
1919 break;
1920 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1921 default:
1922 return -EINVAL;
1923 }
1924 return 0;
1925 }
1926
1927 static int atyfb_sync(struct fb_info *info)
1928 {
1929 struct atyfb_par *par = (struct atyfb_par *) info->par;
1930
1931 if (par->blitter_may_be_busy)
1932 wait_for_idle(par);
1933 return 0;
1934 }
1935
1936 #ifdef __sparc__
1937 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1938 {
1939 struct atyfb_par *par = (struct atyfb_par *) info->par;
1940 unsigned int size, page, map_size = 0;
1941 unsigned long map_offset = 0;
1942 unsigned long off;
1943 int i;
1944
1945 if (!par->mmap_map)
1946 return -ENXIO;
1947
1948 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1949 return -EINVAL;
1950
1951 off = vma->vm_pgoff << PAGE_SHIFT;
1952 size = vma->vm_end - vma->vm_start;
1953
1954 /* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by remap_pfn_range() */
1955
1956 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1957 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1958 off += 0x8000000000000000UL;
1959
1960 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1961
1962 /* Each page, see which map applies */
1963 for (page = 0; page < size;) {
1964 map_size = 0;
1965 for (i = 0; par->mmap_map[i].size; i++) {
1966 unsigned long start = par->mmap_map[i].voff;
1967 unsigned long end = start + par->mmap_map[i].size;
1968 unsigned long offset = off + page;
1969
1970 if (start > offset)
1971 continue;
1972 if (offset >= end)
1973 continue;
1974
1975 map_size = par->mmap_map[i].size - (offset - start);
1976 map_offset = par->mmap_map[i].poff + (offset - start);
1977 break;
1978 }
1979 if (!map_size) {
1980 page += PAGE_SIZE;
1981 continue;
1982 }
1983 if (page + map_size > size)
1984 map_size = size - page;
1985
1986 pgprot_val(vma->vm_page_prot) &= ~(par->mmap_map[i].prot_mask);
1987 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1988
1989 if (remap_pfn_range(vma, vma->vm_start + page,
1990 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1991 return -EAGAIN;
1992
1993 page += map_size;
1994 }
1995
1996 if (!map_size)
1997 return -EINVAL;
1998
1999 if (!par->mmaped)
2000 par->mmaped = 1;
2001 return 0;
2002 }
2003 #endif /* __sparc__ */
2004
2005
2006
2007 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
2008
2009 #ifdef CONFIG_PPC_PMAC
2010 /* Power management routines. Those are used for PowerBook sleep.
2011 */
2012 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
2013 {
2014 u32 pm;
2015 int timeout;
2016
2017 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2018 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
2019 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2020 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2021
2022 timeout = 2000;
2023 if (sleep) {
2024 /* Sleep */
2025 pm &= ~PWR_MGT_ON;
2026 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2027 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2028 udelay(10);
2029 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2030 pm |= SUSPEND_NOW;
2031 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2032 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2033 udelay(10);
2034 pm |= PWR_MGT_ON;
2035 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2036 do {
2037 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2038 mdelay(1);
2039 if ((--timeout) == 0)
2040 break;
2041 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2042 } else {
2043 /* Wakeup */
2044 pm &= ~PWR_MGT_ON;
2045 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2046 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2047 udelay(10);
2048 pm &= ~SUSPEND_NOW;
2049 pm |= (PWR_BLON | AUTO_PWR_UP);
2050 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2051 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2052 udelay(10);
2053 pm |= PWR_MGT_ON;
2054 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2055 do {
2056 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2057 mdelay(1);
2058 if ((--timeout) == 0)
2059 break;
2060 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2061 }
2062 mdelay(500);
2063
2064 return timeout ? 0 : -EIO;
2065 }
2066 #endif /* CONFIG_PPC_PMAC */
2067
2068 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2069 {
2070 struct fb_info *info = pci_get_drvdata(pdev);
2071 struct atyfb_par *par = (struct atyfb_par *) info->par;
2072
2073 if (state.event == pdev->dev.power.power_state.event)
2074 return 0;
2075
2076 console_lock();
2077
2078 fb_set_suspend(info, 1);
2079
2080 /* Idle & reset engine */
2081 wait_for_idle(par);
2082 aty_reset_engine(par);
2083
2084 /* Blank display and LCD */
2085 atyfb_blank(FB_BLANK_POWERDOWN, info);
2086
2087 par->asleep = 1;
2088 par->lock_blank = 1;
2089
2090 /*
2091 * Because we may change PCI D state ourselves, we need to
2092 * first save the config space content so the core can
2093 * restore it properly on resume.
2094 */
2095 pci_save_state(pdev);
2096
2097 #ifdef CONFIG_PPC_PMAC
2098 /* Set chip to "suspend" mode */
2099 if (machine_is(powermac) && aty_power_mgmt(1, par)) {
2100 par->asleep = 0;
2101 par->lock_blank = 0;
2102 atyfb_blank(FB_BLANK_UNBLANK, info);
2103 fb_set_suspend(info, 0);
2104 console_unlock();
2105 return -EIO;
2106 }
2107 #else
2108 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2109 #endif
2110
2111 console_unlock();
2112
2113 pdev->dev.power.power_state = state;
2114
2115 return 0;
2116 }
2117
2118 static void aty_resume_chip(struct fb_info *info)
2119 {
2120 struct atyfb_par *par = info->par;
2121
2122 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2123
2124 if (par->pll_ops->resume_pll)
2125 par->pll_ops->resume_pll(info, &par->pll);
2126
2127 if (par->aux_start)
2128 aty_st_le32(BUS_CNTL,
2129 aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2130 }
2131
2132 static int atyfb_pci_resume(struct pci_dev *pdev)
2133 {
2134 struct fb_info *info = pci_get_drvdata(pdev);
2135 struct atyfb_par *par = (struct atyfb_par *) info->par;
2136
2137 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2138 return 0;
2139
2140 console_lock();
2141
2142 /*
2143 * PCI state will have been restored by the core, so
2144 * we should be in D0 now with our config space fully
2145 * restored
2146 */
2147
2148 #ifdef CONFIG_PPC_PMAC
2149 if (machine_is(powermac) &&
2150 pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
2151 aty_power_mgmt(0, par);
2152 #endif
2153
2154 aty_resume_chip(info);
2155
2156 par->asleep = 0;
2157
2158 /* Restore display */
2159 atyfb_set_par(info);
2160
2161 /* Refresh */
2162 fb_set_suspend(info, 0);
2163
2164 /* Unblank */
2165 par->lock_blank = 0;
2166 atyfb_blank(FB_BLANK_UNBLANK, info);
2167
2168 console_unlock();
2169
2170 pdev->dev.power.power_state = PMSG_ON;
2171
2172 return 0;
2173 }
2174
2175 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2176
2177 /* Backlight */
2178 #ifdef CONFIG_FB_ATY_BACKLIGHT
2179 #define MAX_LEVEL 0xFF
2180
2181 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2182 {
2183 struct fb_info *info = pci_get_drvdata(par->pdev);
2184 int atylevel;
2185
2186 /* Get and convert the value */
2187 /* No locking of bl_curve since we read a single value */
2188 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2189
2190 if (atylevel < 0)
2191 atylevel = 0;
2192 else if (atylevel > MAX_LEVEL)
2193 atylevel = MAX_LEVEL;
2194
2195 return atylevel;
2196 }
2197
2198 static int aty_bl_update_status(struct backlight_device *bd)
2199 {
2200 struct atyfb_par *par = bl_get_data(bd);
2201 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2202 int level;
2203
2204 if (bd->props.power != FB_BLANK_UNBLANK ||
2205 bd->props.fb_blank != FB_BLANK_UNBLANK)
2206 level = 0;
2207 else
2208 level = bd->props.brightness;
2209
2210 reg |= (BLMOD_EN | BIASMOD_EN);
2211 if (level > 0) {
2212 reg &= ~BIAS_MOD_LEVEL_MASK;
2213 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2214 } else {
2215 reg &= ~BIAS_MOD_LEVEL_MASK;
2216 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2217 }
2218 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2219
2220 return 0;
2221 }
2222
2223 static const struct backlight_ops aty_bl_data = {
2224 .update_status = aty_bl_update_status,
2225 };
2226
2227 static void aty_bl_init(struct atyfb_par *par)
2228 {
2229 struct backlight_properties props;
2230 struct fb_info *info = pci_get_drvdata(par->pdev);
2231 struct backlight_device *bd;
2232 char name[12];
2233
2234 #ifdef CONFIG_PMAC_BACKLIGHT
2235 if (!pmac_has_backlight_type("ati"))
2236 return;
2237 #endif
2238
2239 snprintf(name, sizeof(name), "atybl%d", info->node);
2240
2241 memset(&props, 0, sizeof(struct backlight_properties));
2242 props.type = BACKLIGHT_RAW;
2243 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2244 bd = backlight_device_register(name, info->dev, par, &aty_bl_data,
2245 &props);
2246 if (IS_ERR(bd)) {
2247 info->bl_dev = NULL;
2248 printk(KERN_WARNING "aty: Backlight registration failed\n");
2249 goto error;
2250 }
2251
2252 info->bl_dev = bd;
2253 fb_bl_default_curve(info, 0,
2254 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2255 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2256
2257 bd->props.brightness = bd->props.max_brightness;
2258 bd->props.power = FB_BLANK_UNBLANK;
2259 backlight_update_status(bd);
2260
2261 printk("aty: Backlight initialized (%s)\n", name);
2262
2263 return;
2264
2265 error:
2266 return;
2267 }
2268
2269 #ifdef CONFIG_PCI
2270 static void aty_bl_exit(struct backlight_device *bd)
2271 {
2272 backlight_device_unregister(bd);
2273 printk("aty: Backlight unloaded\n");
2274 }
2275 #endif /* CONFIG_PCI */
2276
2277 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2278
2279 static void aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2280 {
2281 const int ragepro_tbl[] = {
2282 44, 50, 55, 66, 75, 80, 100
2283 };
2284 const int ragexl_tbl[] = {
2285 50, 66, 75, 83, 90, 95, 100, 105,
2286 110, 115, 120, 125, 133, 143, 166
2287 };
2288 const int *refresh_tbl;
2289 int i, size;
2290
2291 if (M64_HAS(XL_MEM)) {
2292 refresh_tbl = ragexl_tbl;
2293 size = ARRAY_SIZE(ragexl_tbl);
2294 } else {
2295 refresh_tbl = ragepro_tbl;
2296 size = ARRAY_SIZE(ragepro_tbl);
2297 }
2298
2299 for (i = 0; i < size; i++) {
2300 if (xclk < refresh_tbl[i])
2301 break;
2302 }
2303 par->mem_refresh_rate = i;
2304 }
2305
2306 /*
2307 * Initialisation
2308 */
2309
2310 static struct fb_info *fb_list = NULL;
2311
2312 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2313 static int atyfb_get_timings_from_lcd(struct atyfb_par *par,
2314 struct fb_var_screeninfo *var)
2315 {
2316 int ret = -EINVAL;
2317
2318 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2319 *var = default_var;
2320 var->xres = var->xres_virtual = par->lcd_hdisp;
2321 var->right_margin = par->lcd_right_margin;
2322 var->left_margin = par->lcd_hblank_len -
2323 (par->lcd_right_margin + par->lcd_hsync_dly +
2324 par->lcd_hsync_len);
2325 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2326 var->yres = var->yres_virtual = par->lcd_vdisp;
2327 var->lower_margin = par->lcd_lower_margin;
2328 var->upper_margin = par->lcd_vblank_len -
2329 (par->lcd_lower_margin + par->lcd_vsync_len);
2330 var->vsync_len = par->lcd_vsync_len;
2331 var->pixclock = par->lcd_pixclock;
2332 ret = 0;
2333 }
2334
2335 return ret;
2336 }
2337 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2338
2339 static int aty_init(struct fb_info *info)
2340 {
2341 struct atyfb_par *par = (struct atyfb_par *) info->par;
2342 const char *ramname = NULL, *xtal;
2343 int gtb_memsize, has_var = 0;
2344 struct fb_var_screeninfo var;
2345 int ret;
2346
2347 init_waitqueue_head(&par->vblank.wait);
2348 spin_lock_init(&par->int_lock);
2349
2350 #ifdef CONFIG_FB_ATY_GX
2351 if (!M64_HAS(INTEGRATED)) {
2352 u32 stat0;
2353 u8 dac_type, dac_subtype, clk_type;
2354 stat0 = aty_ld_le32(CNFG_STAT0, par);
2355 par->bus_type = (stat0 >> 0) & 0x07;
2356 par->ram_type = (stat0 >> 3) & 0x07;
2357 ramname = aty_gx_ram[par->ram_type];
2358 /* FIXME: clockchip/RAMDAC probing? */
2359 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2360 #ifdef CONFIG_ATARI
2361 clk_type = CLK_ATI18818_1;
2362 dac_type = (stat0 >> 9) & 0x07;
2363 if (dac_type == 0x07)
2364 dac_subtype = DAC_ATT20C408;
2365 else
2366 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2367 #else
2368 dac_type = DAC_IBMRGB514;
2369 dac_subtype = DAC_IBMRGB514;
2370 clk_type = CLK_IBMRGB514;
2371 #endif
2372 switch (dac_subtype) {
2373 case DAC_IBMRGB514:
2374 par->dac_ops = &aty_dac_ibm514;
2375 break;
2376 #ifdef CONFIG_ATARI
2377 case DAC_ATI68860_B:
2378 case DAC_ATI68860_C:
2379 par->dac_ops = &aty_dac_ati68860b;
2380 break;
2381 case DAC_ATT20C408:
2382 case DAC_ATT21C498:
2383 par->dac_ops = &aty_dac_att21c498;
2384 break;
2385 #endif
2386 default:
2387 PRINTKI("aty_init: DAC type not implemented yet!\n");
2388 par->dac_ops = &aty_dac_unsupported;
2389 break;
2390 }
2391 switch (clk_type) {
2392 #ifdef CONFIG_ATARI
2393 case CLK_ATI18818_1:
2394 par->pll_ops = &aty_pll_ati18818_1;
2395 break;
2396 #else
2397 case CLK_IBMRGB514:
2398 par->pll_ops = &aty_pll_ibm514;
2399 break;
2400 #endif
2401 #if 0 /* dead code */
2402 case CLK_STG1703:
2403 par->pll_ops = &aty_pll_stg1703;
2404 break;
2405 case CLK_CH8398:
2406 par->pll_ops = &aty_pll_ch8398;
2407 break;
2408 case CLK_ATT20C408:
2409 par->pll_ops = &aty_pll_att20c408;
2410 break;
2411 #endif
2412 default:
2413 PRINTKI("aty_init: CLK type not implemented yet!");
2414 par->pll_ops = &aty_pll_unsupported;
2415 break;
2416 }
2417 }
2418 #endif /* CONFIG_FB_ATY_GX */
2419 #ifdef CONFIG_FB_ATY_CT
2420 if (M64_HAS(INTEGRATED)) {
2421 par->dac_ops = &aty_dac_ct;
2422 par->pll_ops = &aty_pll_ct;
2423 par->bus_type = PCI;
2424 par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
2425 if (M64_HAS(XL_MEM))
2426 ramname = aty_xl_ram[par->ram_type];
2427 else
2428 ramname = aty_ct_ram[par->ram_type];
2429 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2430 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2431 par->pll_limits.mclk = 63;
2432 /* Mobility + 32bit memory interface need halved XCLK. */
2433 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2434 par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2435 }
2436 #endif
2437 #ifdef CONFIG_PPC_PMAC
2438 /*
2439 * The Apple iBook1 uses non-standard memory frequencies.
2440 * We detect it and set the frequency manually.
2441 */
2442 if (of_machine_is_compatible("PowerBook2,1")) {
2443 par->pll_limits.mclk = 70;
2444 par->pll_limits.xclk = 53;
2445 }
2446 #endif
2447
2448 /* Allow command line to override clocks. */
2449 if (pll)
2450 par->pll_limits.pll_max = pll;
2451 if (mclk)
2452 par->pll_limits.mclk = mclk;
2453 if (xclk)
2454 par->pll_limits.xclk = xclk;
2455
2456 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2457 par->pll_per = 1000000/par->pll_limits.pll_max;
2458 par->mclk_per = 1000000/par->pll_limits.mclk;
2459 par->xclk_per = 1000000/par->pll_limits.xclk;
2460
2461 par->ref_clk_per = 1000000000000ULL / 14318180;
2462 xtal = "14.31818";
2463
2464 #ifdef CONFIG_FB_ATY_CT
2465 if (M64_HAS(GTB_DSP)) {
2466 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2467
2468 if (pll_ref_div) {
2469 int diff1, diff2;
2470 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2471 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2472 if (diff1 < 0)
2473 diff1 = -diff1;
2474 if (diff2 < 0)
2475 diff2 = -diff2;
2476 if (diff2 < diff1) {
2477 par->ref_clk_per = 1000000000000ULL / 29498928;
2478 xtal = "29.498928";
2479 }
2480 }
2481 }
2482 #endif /* CONFIG_FB_ATY_CT */
2483
2484 /* save previous video mode */
2485 aty_get_crtc(par, &par->saved_crtc);
2486 if (par->pll_ops->get_pll)
2487 par->pll_ops->get_pll(info, &par->saved_pll);
2488
2489 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2490 gtb_memsize = M64_HAS(GTB_DSP);
2491 if (gtb_memsize)
2492 /* 0xF used instead of MEM_SIZE_ALIAS */
2493 switch (par->mem_cntl & 0xF) {
2494 case MEM_SIZE_512K:
2495 info->fix.smem_len = 0x80000;
2496 break;
2497 case MEM_SIZE_1M:
2498 info->fix.smem_len = 0x100000;
2499 break;
2500 case MEM_SIZE_2M_GTB:
2501 info->fix.smem_len = 0x200000;
2502 break;
2503 case MEM_SIZE_4M_GTB:
2504 info->fix.smem_len = 0x400000;
2505 break;
2506 case MEM_SIZE_6M_GTB:
2507 info->fix.smem_len = 0x600000;
2508 break;
2509 case MEM_SIZE_8M_GTB:
2510 info->fix.smem_len = 0x800000;
2511 break;
2512 default:
2513 info->fix.smem_len = 0x80000;
2514 } else
2515 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2516 case MEM_SIZE_512K:
2517 info->fix.smem_len = 0x80000;
2518 break;
2519 case MEM_SIZE_1M:
2520 info->fix.smem_len = 0x100000;
2521 break;
2522 case MEM_SIZE_2M:
2523 info->fix.smem_len = 0x200000;
2524 break;
2525 case MEM_SIZE_4M:
2526 info->fix.smem_len = 0x400000;
2527 break;
2528 case MEM_SIZE_6M:
2529 info->fix.smem_len = 0x600000;
2530 break;
2531 case MEM_SIZE_8M:
2532 info->fix.smem_len = 0x800000;
2533 break;
2534 default:
2535 info->fix.smem_len = 0x80000;
2536 }
2537
2538 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2539 if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
2540 info->fix.smem_len += 0x400000;
2541 }
2542
2543 if (vram) {
2544 info->fix.smem_len = vram * 1024;
2545 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2546 if (info->fix.smem_len <= 0x80000)
2547 par->mem_cntl |= MEM_SIZE_512K;
2548 else if (info->fix.smem_len <= 0x100000)
2549 par->mem_cntl |= MEM_SIZE_1M;
2550 else if (info->fix.smem_len <= 0x200000)
2551 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2552 else if (info->fix.smem_len <= 0x400000)
2553 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2554 else if (info->fix.smem_len <= 0x600000)
2555 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2556 else
2557 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2558 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2559 }
2560
2561 /*
2562 * Reg Block 0 (CT-compatible block) is at mmio_start
2563 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2564 */
2565 if (M64_HAS(GX)) {
2566 info->fix.mmio_len = 0x400;
2567 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2568 } else if (M64_HAS(CT)) {
2569 info->fix.mmio_len = 0x400;
2570 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2571 } else if (M64_HAS(VT)) {
2572 info->fix.mmio_start -= 0x400;
2573 info->fix.mmio_len = 0x800;
2574 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2575 } else {/* GT */
2576 info->fix.mmio_start -= 0x400;
2577 info->fix.mmio_len = 0x800;
2578 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2579 }
2580
2581 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2582 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len>>20),
2583 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal,
2584 par->pll_limits.pll_max, par->pll_limits.mclk,
2585 par->pll_limits.xclk);
2586
2587 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2588 if (M64_HAS(INTEGRATED)) {
2589 int i;
2590 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL "
2591 "EXT_MEM_CNTL CRTC_GEN_CNTL DSP_CONFIG "
2592 "DSP_ON_OFF CLOCK_CNTL\n"
2593 "debug atyfb: %08x %08x %08x "
2594 "%08x %08x %08x "
2595 "%08x %08x\n"
2596 "debug atyfb: PLL",
2597 aty_ld_le32(BUS_CNTL, par),
2598 aty_ld_le32(DAC_CNTL, par),
2599 aty_ld_le32(MEM_CNTL, par),
2600 aty_ld_le32(EXT_MEM_CNTL, par),
2601 aty_ld_le32(CRTC_GEN_CNTL, par),
2602 aty_ld_le32(DSP_CONFIG, par),
2603 aty_ld_le32(DSP_ON_OFF, par),
2604 aty_ld_le32(CLOCK_CNTL, par));
2605 for (i = 0; i < 40; i++)
2606 printk(" %02x", aty_ld_pll_ct(i, par));
2607 printk("\n");
2608 }
2609 #endif
2610 if (par->pll_ops->init_pll)
2611 par->pll_ops->init_pll(info, &par->pll);
2612 if (par->pll_ops->resume_pll)
2613 par->pll_ops->resume_pll(info, &par->pll);
2614
2615 aty_fudge_framebuffer_len(info);
2616
2617 /*
2618 * Disable register access through the linear aperture
2619 * if the auxiliary aperture is used so we can access
2620 * the full 8 MB of video RAM on 8 MB boards.
2621 */
2622 if (par->aux_start)
2623 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) |
2624 BUS_APER_REG_DIS, par);
2625
2626 if (!nomtrr)
2627 /*
2628 * Only the ioremap_wc()'d area will get WC here
2629 * since ioremap_uc() was used on the entire PCI BAR.
2630 */
2631 par->wc_cookie = arch_phys_wc_add(par->res_start,
2632 par->res_size);
2633
2634 info->fbops = &atyfb_ops;
2635 info->pseudo_palette = par->pseudo_palette;
2636 info->flags = FBINFO_DEFAULT |
2637 FBINFO_HWACCEL_IMAGEBLIT |
2638 FBINFO_HWACCEL_FILLRECT |
2639 FBINFO_HWACCEL_COPYAREA |
2640 FBINFO_HWACCEL_YPAN |
2641 FBINFO_READS_FAST;
2642
2643 #ifdef CONFIG_PMAC_BACKLIGHT
2644 if (M64_HAS(G3_PB_1_1) && of_machine_is_compatible("PowerBook1,1")) {
2645 /*
2646 * these bits let the 101 powerbook
2647 * wake up from sleep -- paulus
2648 */
2649 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par) |
2650 USE_F32KHZ | TRISTATE_MEM_EN, par);
2651 } else
2652 #endif
2653 if (M64_HAS(MOBIL_BUS) && backlight) {
2654 #ifdef CONFIG_FB_ATY_BACKLIGHT
2655 aty_bl_init(par);
2656 #endif
2657 }
2658
2659 memset(&var, 0, sizeof(var));
2660 #ifdef CONFIG_PPC
2661 if (machine_is(powermac)) {
2662 /*
2663 * FIXME: The NVRAM stuff should be put in a Mac-specific file,
2664 * as it applies to all Mac video cards
2665 */
2666 if (mode) {
2667 if (mac_find_mode(&var, info, mode, 8))
2668 has_var = 1;
2669 } else {
2670 if (default_vmode == VMODE_CHOOSE) {
2671 int sense;
2672 if (M64_HAS(G3_PB_1024x768))
2673 /* G3 PowerBook with 1024x768 LCD */
2674 default_vmode = VMODE_1024_768_60;
2675 else if (of_machine_is_compatible("iMac"))
2676 default_vmode = VMODE_1024_768_75;
2677 else if (of_machine_is_compatible("PowerBook2,1"))
2678 /* iBook with 800x600 LCD */
2679 default_vmode = VMODE_800_600_60;
2680 else
2681 default_vmode = VMODE_640_480_67;
2682 sense = read_aty_sense(par);
2683 PRINTKI("monitor sense=%x, mode %d\n",
2684 sense, mac_map_monitor_sense(sense));
2685 }
2686 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2687 default_vmode = VMODE_640_480_60;
2688 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2689 default_cmode = CMODE_8;
2690 if (!mac_vmode_to_var(default_vmode, default_cmode,
2691 &var))
2692 has_var = 1;
2693 }
2694 }
2695
2696 #endif /* !CONFIG_PPC */
2697
2698 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2699 if (!atyfb_get_timings_from_lcd(par, &var))
2700 has_var = 1;
2701 #endif
2702
2703 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2704 has_var = 1;
2705
2706 if (!has_var)
2707 var = default_var;
2708
2709 if (noaccel)
2710 var.accel_flags &= ~FB_ACCELF_TEXT;
2711 else
2712 var.accel_flags |= FB_ACCELF_TEXT;
2713
2714 if (comp_sync != -1) {
2715 if (!comp_sync)
2716 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2717 else
2718 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2719 }
2720
2721 if (var.yres == var.yres_virtual) {
2722 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2723 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2724 if (var.yres_virtual < var.yres)
2725 var.yres_virtual = var.yres;
2726 }
2727
2728 ret = atyfb_check_var(&var, info);
2729 if (ret) {
2730 PRINTKE("can't set default video mode\n");
2731 goto aty_init_exit;
2732 }
2733
2734 #ifdef CONFIG_FB_ATY_CT
2735 if (!noaccel && M64_HAS(INTEGRATED))
2736 aty_init_cursor(info);
2737 #endif /* CONFIG_FB_ATY_CT */
2738 info->var = var;
2739
2740 ret = fb_alloc_cmap(&info->cmap, 256, 0);
2741 if (ret < 0)
2742 goto aty_init_exit;
2743
2744 ret = register_framebuffer(info);
2745 if (ret < 0) {
2746 fb_dealloc_cmap(&info->cmap);
2747 goto aty_init_exit;
2748 }
2749
2750 fb_list = info;
2751
2752 PRINTKI("fb%d: %s frame buffer device on %s\n",
2753 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2754 return 0;
2755
2756 aty_init_exit:
2757 /* restore video mode */
2758 aty_set_crtc(par, &par->saved_crtc);
2759 par->pll_ops->set_pll(info, &par->saved_pll);
2760 arch_phys_wc_del(par->wc_cookie);
2761
2762 return ret;
2763 }
2764
2765 #if defined(CONFIG_ATARI) && !defined(MODULE)
2766 static int store_video_par(char *video_str, unsigned char m64_num)
2767 {
2768 char *p;
2769 unsigned long vmembase, size, guiregbase;
2770
2771 PRINTKI("store_video_par() '%s' \n", video_str);
2772
2773 if (!(p = strsep(&video_str, ";")) || !*p)
2774 goto mach64_invalid;
2775 vmembase = simple_strtoul(p, NULL, 0);
2776 if (!(p = strsep(&video_str, ";")) || !*p)
2777 goto mach64_invalid;
2778 size = simple_strtoul(p, NULL, 0);
2779 if (!(p = strsep(&video_str, ";")) || !*p)
2780 goto mach64_invalid;
2781 guiregbase = simple_strtoul(p, NULL, 0);
2782
2783 phys_vmembase[m64_num] = vmembase;
2784 phys_size[m64_num] = size;
2785 phys_guiregbase[m64_num] = guiregbase;
2786 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2787 guiregbase);
2788 return 0;
2789
2790 mach64_invalid:
2791 phys_vmembase[m64_num] = 0;
2792 return -1;
2793 }
2794 #endif /* CONFIG_ATARI && !MODULE */
2795
2796 /*
2797 * Blank the display.
2798 */
2799
2800 static int atyfb_blank(int blank, struct fb_info *info)
2801 {
2802 struct atyfb_par *par = (struct atyfb_par *) info->par;
2803 u32 gen_cntl;
2804
2805 if (par->lock_blank || par->asleep)
2806 return 0;
2807
2808 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2809 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2810 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2811 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2812 pm &= ~PWR_BLON;
2813 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2814 }
2815 #endif
2816
2817 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2818 gen_cntl &= ~0x400004c;
2819 switch (blank) {
2820 case FB_BLANK_UNBLANK:
2821 break;
2822 case FB_BLANK_NORMAL:
2823 gen_cntl |= 0x4000040;
2824 break;
2825 case FB_BLANK_VSYNC_SUSPEND:
2826 gen_cntl |= 0x4000048;
2827 break;
2828 case FB_BLANK_HSYNC_SUSPEND:
2829 gen_cntl |= 0x4000044;
2830 break;
2831 case FB_BLANK_POWERDOWN:
2832 gen_cntl |= 0x400004c;
2833 break;
2834 }
2835 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2836
2837 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2838 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2839 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2840 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2841 pm |= PWR_BLON;
2842 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2843 }
2844 #endif
2845
2846 return 0;
2847 }
2848
2849 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2850 const struct atyfb_par *par)
2851 {
2852 aty_st_8(DAC_W_INDEX, regno, par);
2853 aty_st_8(DAC_DATA, red, par);
2854 aty_st_8(DAC_DATA, green, par);
2855 aty_st_8(DAC_DATA, blue, par);
2856 }
2857
2858 /*
2859 * Set a single color register. The values supplied are already
2860 * rounded down to the hardware's capabilities (according to the
2861 * entries in the var structure). Return != 0 for invalid regno.
2862 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2863 */
2864
2865 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2866 u_int transp, struct fb_info *info)
2867 {
2868 struct atyfb_par *par = (struct atyfb_par *) info->par;
2869 int i, depth;
2870 u32 *pal = info->pseudo_palette;
2871
2872 depth = info->var.bits_per_pixel;
2873 if (depth == 16)
2874 depth = (info->var.green.length == 5) ? 15 : 16;
2875
2876 if (par->asleep)
2877 return 0;
2878
2879 if (regno > 255 ||
2880 (depth == 16 && regno > 63) ||
2881 (depth == 15 && regno > 31))
2882 return 1;
2883
2884 red >>= 8;
2885 green >>= 8;
2886 blue >>= 8;
2887
2888 par->palette[regno].red = red;
2889 par->palette[regno].green = green;
2890 par->palette[regno].blue = blue;
2891
2892 if (regno < 16) {
2893 switch (depth) {
2894 case 15:
2895 pal[regno] = (regno << 10) | (regno << 5) | regno;
2896 break;
2897 case 16:
2898 pal[regno] = (regno << 11) | (regno << 5) | regno;
2899 break;
2900 case 24:
2901 pal[regno] = (regno << 16) | (regno << 8) | regno;
2902 break;
2903 case 32:
2904 i = (regno << 8) | regno;
2905 pal[regno] = (i << 16) | i;
2906 break;
2907 }
2908 }
2909
2910 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2911 if (M64_HAS(EXTRA_BRIGHT))
2912 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2913 aty_st_8(DAC_CNTL, i, par);
2914 aty_st_8(DAC_MASK, 0xff, par);
2915
2916 if (M64_HAS(INTEGRATED)) {
2917 if (depth == 16) {
2918 if (regno < 32)
2919 aty_st_pal(regno << 3, red,
2920 par->palette[regno << 1].green,
2921 blue, par);
2922 red = par->palette[regno >> 1].red;
2923 blue = par->palette[regno >> 1].blue;
2924 regno <<= 2;
2925 } else if (depth == 15) {
2926 regno <<= 3;
2927 for (i = 0; i < 8; i++)
2928 aty_st_pal(regno + i, red, green, blue, par);
2929 }
2930 }
2931 aty_st_pal(regno, red, green, blue, par);
2932
2933 return 0;
2934 }
2935
2936 #ifdef CONFIG_PCI
2937
2938 #ifdef __sparc__
2939
2940 static int atyfb_setup_sparc(struct pci_dev *pdev, struct fb_info *info,
2941 unsigned long addr)
2942 {
2943 struct atyfb_par *par = info->par;
2944 struct device_node *dp;
2945 u32 mem, chip_id;
2946 int i, j, ret;
2947
2948 /*
2949 * Map memory-mapped registers.
2950 */
2951 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2952 info->fix.mmio_start = addr + 0x7ffc00UL;
2953
2954 /*
2955 * Map in big-endian aperture.
2956 */
2957 info->screen_base = (char *) (addr + 0x800000UL);
2958 info->fix.smem_start = addr + 0x800000UL;
2959
2960 /*
2961 * Figure mmap addresses from PCI config space.
2962 * Split Framebuffer in big- and little-endian halfs.
2963 */
2964 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2965 /* nothing */ ;
2966 j = i + 4;
2967
2968 par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2969 if (!par->mmap_map) {
2970 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2971 return -ENOMEM;
2972 }
2973
2974 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2975 struct resource *rp = &pdev->resource[i];
2976 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2977 unsigned long base;
2978 u32 size, pbase;
2979
2980 base = rp->start;
2981
2982 io = (rp->flags & IORESOURCE_IO);
2983
2984 size = rp->end - base + 1;
2985
2986 pci_read_config_dword(pdev, breg, &pbase);
2987
2988 if (io)
2989 size &= ~1;
2990
2991 /*
2992 * Map the framebuffer a second time, this time without
2993 * the braindead _PAGE_IE setting. This is used by the
2994 * fixed Xserver, but we need to maintain the old mapping
2995 * to stay compatible with older ones...
2996 */
2997 if (base == addr) {
2998 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2999 par->mmap_map[j].poff = base & PAGE_MASK;
3000 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3001 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3002 par->mmap_map[j].prot_flag = _PAGE_E;
3003 j++;
3004 }
3005
3006 /*
3007 * Here comes the old framebuffer mapping with _PAGE_IE
3008 * set for the big endian half of the framebuffer...
3009 */
3010 if (base == addr) {
3011 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3012 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3013 par->mmap_map[j].size = 0x800000;
3014 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3015 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3016 size -= 0x800000;
3017 j++;
3018 }
3019
3020 par->mmap_map[j].voff = pbase & PAGE_MASK;
3021 par->mmap_map[j].poff = base & PAGE_MASK;
3022 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3023 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3024 par->mmap_map[j].prot_flag = _PAGE_E;
3025 j++;
3026 }
3027
3028 ret = correct_chipset(par);
3029 if (ret)
3030 return ret;
3031
3032 if (IS_XL(pdev->device)) {
3033 /*
3034 * Fix PROMs idea of MEM_CNTL settings...
3035 */
3036 mem = aty_ld_le32(MEM_CNTL, par);
3037 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
3038 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3039 switch (mem & 0x0f) {
3040 case 3:
3041 mem = (mem & ~(0x0f)) | 2;
3042 break;
3043 case 7:
3044 mem = (mem & ~(0x0f)) | 3;
3045 break;
3046 case 9:
3047 mem = (mem & ~(0x0f)) | 4;
3048 break;
3049 case 11:
3050 mem = (mem & ~(0x0f)) | 5;
3051 break;
3052 default:
3053 break;
3054 }
3055 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
3056 mem &= ~(0x00700000);
3057 }
3058 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3059 aty_st_le32(MEM_CNTL, mem, par);
3060 }
3061
3062 dp = pci_device_to_OF_node(pdev);
3063 if (dp == of_console_device) {
3064 struct fb_var_screeninfo *var = &default_var;
3065 unsigned int N, P, Q, M, T, R;
3066 u32 v_total, h_total;
3067 struct crtc crtc;
3068 u8 pll_regs[16];
3069 u8 clock_cntl;
3070
3071 crtc.vxres = of_getintprop_default(dp, "width", 1024);
3072 crtc.vyres = of_getintprop_default(dp, "height", 768);
3073 var->bits_per_pixel = of_getintprop_default(dp, "depth", 8);
3074 var->xoffset = var->yoffset = 0;
3075 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3076 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3077 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3078 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3079 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3080 aty_crtc_to_var(&crtc, var);
3081
3082 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3083 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3084
3085 /*
3086 * Read the PLL to figure actual Refresh Rate.
3087 */
3088 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3089 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3090 for (i = 0; i < 16; i++)
3091 pll_regs[i] = aty_ld_pll_ct(i, par);
3092
3093 /*
3094 * PLL Reference Divider M:
3095 */
3096 M = pll_regs[2];
3097
3098 /*
3099 * PLL Feedback Divider N (Dependent on CLOCK_CNTL):
3100 */
3101 N = pll_regs[7 + (clock_cntl & 3)];
3102
3103 /*
3104 * PLL Post Divider P (Dependent on CLOCK_CNTL):
3105 */
3106 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3107
3108 /*
3109 * PLL Divider Q:
3110 */
3111 Q = N / P;
3112
3113 /*
3114 * Target Frequency:
3115 *
3116 * T * M
3117 * Q = -------
3118 * 2 * R
3119 *
3120 * where R is XTALIN (= 14318 or 29498 kHz).
3121 */
3122 if (IS_XL(pdev->device))
3123 R = 29498;
3124 else
3125 R = 14318;
3126
3127 T = 2 * Q * R / M;
3128
3129 default_var.pixclock = 1000000000 / T;
3130 }
3131
3132 return 0;
3133 }
3134
3135 #else /* __sparc__ */
3136
3137 #ifdef __i386__
3138 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3139 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3140 {
3141 u32 driv_inf_tab, sig;
3142 u16 lcd_ofs;
3143
3144 /*
3145 * To support an LCD panel, we should know it's dimensions and
3146 * it's desired pixel clock.
3147 * There are two ways to do it:
3148 * - Check the startup video mode and calculate the panel
3149 * size from it. This is unreliable.
3150 * - Read it from the driver information table in the video BIOS.
3151 */
3152 /* Address of driver information table is at offset 0x78. */
3153 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3154
3155 /* Check for the driver information table signature. */
3156 sig = *(u32 *)driv_inf_tab;
3157 if ((sig == 0x54504c24) || /* Rage LT pro */
3158 (sig == 0x544d5224) || /* Rage mobility */
3159 (sig == 0x54435824) || /* Rage XC */
3160 (sig == 0x544c5824)) { /* Rage XL */
3161 PRINTKI("BIOS contains driver information table.\n");
3162 lcd_ofs = *(u16 *)(driv_inf_tab + 10);
3163 par->lcd_table = 0;
3164 if (lcd_ofs != 0)
3165 par->lcd_table = bios_base + lcd_ofs;
3166 }
3167
3168 if (par->lcd_table != 0) {
3169 char model[24];
3170 char strbuf[16];
3171 char refresh_rates_buf[100];
3172 int id, tech, f, i, m, default_refresh_rate;
3173 char *txtcolour;
3174 char *txtmonitor;
3175 char *txtdual;
3176 char *txtformat;
3177 u16 width, height, panel_type, refresh_rates;
3178 u16 *lcdmodeptr;
3179 u32 format;
3180 u8 lcd_refresh_rates[16] = { 50, 56, 60, 67, 70, 72, 75, 76, 85,
3181 90, 100, 120, 140, 150, 160, 200 };
3182 /*
3183 * The most important information is the panel size at
3184 * offset 25 and 27, but there's some other nice information
3185 * which we print to the screen.
3186 */
3187 id = *(u8 *)par->lcd_table;
3188 strncpy(model, (char *)par->lcd_table+1, 24);
3189 model[23] = 0;
3190
3191 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3192 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3193 panel_type = *(u16 *)(par->lcd_table+29);
3194 if (panel_type & 1)
3195 txtcolour = "colour";
3196 else
3197 txtcolour = "monochrome";
3198 if (panel_type & 2)
3199 txtdual = "dual (split) ";
3200 else
3201 txtdual = "";
3202 tech = (panel_type >> 2) & 63;
3203 switch (tech) {
3204 case 0:
3205 txtmonitor = "passive matrix";
3206 break;
3207 case 1:
3208 txtmonitor = "active matrix";
3209 break;
3210 case 2:
3211 txtmonitor = "active addressed STN";
3212 break;
3213 case 3:
3214 txtmonitor = "EL";
3215 break;
3216 case 4:
3217 txtmonitor = "plasma";
3218 break;
3219 default:
3220 txtmonitor = "unknown";
3221 }
3222 format = *(u32 *)(par->lcd_table+57);
3223 if (tech == 0 || tech == 2) {
3224 switch (format & 7) {
3225 case 0:
3226 txtformat = "12 bit interface";
3227 break;
3228 case 1:
3229 txtformat = "16 bit interface";
3230 break;
3231 case 2:
3232 txtformat = "24 bit interface";
3233 break;
3234 default:
3235 txtformat = "unknown format";
3236 }
3237 } else {
3238 switch (format & 7) {
3239 case 0:
3240 txtformat = "8 colours";
3241 break;
3242 case 1:
3243 txtformat = "512 colours";
3244 break;
3245 case 2:
3246 txtformat = "4096 colours";
3247 break;
3248 case 4:
3249 txtformat = "262144 colours (LT mode)";
3250 break;
3251 case 5:
3252 txtformat = "16777216 colours";
3253 break;
3254 case 6:
3255 txtformat = "262144 colours (FDPI-2 mode)";
3256 break;
3257 default:
3258 txtformat = "unknown format";
3259 }
3260 }
3261 PRINTKI("%s%s %s monitor detected: %s\n",
3262 txtdual, txtcolour, txtmonitor, model);
3263 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3264 id, width, height, txtformat);
3265 refresh_rates_buf[0] = 0;
3266 refresh_rates = *(u16 *)(par->lcd_table+62);
3267 m = 1;
3268 f = 0;
3269 for (i = 0; i < 16; i++) {
3270 if (refresh_rates & m) {
3271 if (f == 0) {
3272 sprintf(strbuf, "%d",
3273 lcd_refresh_rates[i]);
3274 f++;
3275 } else {
3276 sprintf(strbuf, ",%d",
3277 lcd_refresh_rates[i]);
3278 }
3279 strcat(refresh_rates_buf, strbuf);
3280 }
3281 m = m << 1;
3282 }
3283 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3284 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3285 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3286 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3287 /*
3288 * We now need to determine the crtc parameters for the
3289 * LCD monitor. This is tricky, because they are not stored
3290 * individually in the BIOS. Instead, the BIOS contains a
3291 * table of display modes that work for this monitor.
3292 *
3293 * The idea is that we search for a mode of the same dimensions
3294 * as the dimensions of the LCD monitor. Say our LCD monitor
3295 * is 800x600 pixels, we search for a 800x600 monitor.
3296 * The CRTC parameters we find here are the ones that we need
3297 * to use to simulate other resolutions on the LCD screen.
3298 */
3299 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3300 while (*lcdmodeptr != 0) {
3301 u32 modeptr;
3302 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3303 modeptr = bios_base + *lcdmodeptr;
3304
3305 mwidth = *((u16 *)(modeptr+0));
3306 mheight = *((u16 *)(modeptr+2));
3307
3308 if (mwidth == width && mheight == height) {
3309 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3310 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3311 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3312 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3313 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3314 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3315
3316 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3317 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3318 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3319 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3320
3321 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3322 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3323 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3324 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3325
3326 par->lcd_vtotal++;
3327 par->lcd_vdisp++;
3328 lcd_vsync_start++;
3329
3330 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3331 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3332 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3333 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3334 break;
3335 }
3336
3337 lcdmodeptr++;
3338 }
3339 if (*lcdmodeptr == 0) {
3340 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3341 /* To do: Switch to CRT if possible. */
3342 } else {
3343 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3344 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3345 par->lcd_hdisp,
3346 par->lcd_hdisp + par->lcd_right_margin,
3347 par->lcd_hdisp + par->lcd_right_margin
3348 + par->lcd_hsync_dly + par->lcd_hsync_len,
3349 par->lcd_htotal,
3350 par->lcd_vdisp,
3351 par->lcd_vdisp + par->lcd_lower_margin,
3352 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3353 par->lcd_vtotal);
3354 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3355 par->lcd_pixclock,
3356 par->lcd_hblank_len - (par->lcd_right_margin +
3357 par->lcd_hsync_dly + par->lcd_hsync_len),
3358 par->lcd_hdisp,
3359 par->lcd_right_margin,
3360 par->lcd_hsync_len,
3361 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3362 par->lcd_vdisp,
3363 par->lcd_lower_margin,
3364 par->lcd_vsync_len);
3365 }
3366 }
3367 }
3368 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3369
3370 static int init_from_bios(struct atyfb_par *par)
3371 {
3372 u32 bios_base, rom_addr;
3373 int ret;
3374
3375 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3376 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3377
3378 /* The BIOS starts with 0xaa55. */
3379 if (*((u16 *)bios_base) == 0xaa55) {
3380
3381 u8 *bios_ptr;
3382 u16 rom_table_offset, freq_table_offset;
3383 PLL_BLOCK_MACH64 pll_block;
3384
3385 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3386
3387 /* check for frequncy table */
3388 bios_ptr = (u8*)bios_base;
3389 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3390 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3391 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3392
3393 PRINTKI("BIOS frequency table:\n");
3394 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3395 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3396 pll_block.ref_freq, pll_block.ref_divider);
3397 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3398 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3399 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3400
3401 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3402 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3403 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3404 par->pll_limits.ref_div = pll_block.ref_divider;
3405 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3406 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3407 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3408 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3409 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3410 aty_init_lcd(par, bios_base);
3411 #endif
3412 ret = 0;
3413 } else {
3414 PRINTKE("no BIOS frequency table found, use parameters\n");
3415 ret = -ENXIO;
3416 }
3417 iounmap((void __iomem *)bios_base);
3418
3419 return ret;
3420 }
3421 #endif /* __i386__ */
3422
3423 static int atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info,
3424 unsigned long addr)
3425 {
3426 struct atyfb_par *par = info->par;
3427 u16 tmp;
3428 unsigned long raddr;
3429 struct resource *rrp;
3430 int ret = 0;
3431
3432 raddr = addr + 0x7ff000UL;
3433 rrp = &pdev->resource[2];
3434 if ((rrp->flags & IORESOURCE_MEM) &&
3435 request_mem_region(rrp->start, resource_size(rrp), "atyfb")) {
3436 par->aux_start = rrp->start;
3437 par->aux_size = resource_size(rrp);
3438 raddr = rrp->start;
3439 PRINTKI("using auxiliary register aperture\n");
3440 }
3441
3442 info->fix.mmio_start = raddr;
3443 /*
3444 * By using strong UC we force the MTRR to never have an
3445 * effect on the MMIO region on both non-PAT and PAT systems.
3446 */
3447 par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000);
3448 if (par->ati_regbase == NULL)
3449 return -ENOMEM;
3450
3451 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3452 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3453
3454 /*
3455 * Enable memory-space accesses using config-space
3456 * command register.
3457 */
3458 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3459 if (!(tmp & PCI_COMMAND_MEMORY)) {
3460 tmp |= PCI_COMMAND_MEMORY;
3461 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3462 }
3463 #ifdef __BIG_ENDIAN
3464 /* Use the big-endian aperture */
3465 addr += 0x800000;
3466 #endif
3467
3468 /* Map in frame buffer */
3469 info->fix.smem_start = addr;
3470
3471 /*
3472 * The framebuffer is not always 8 MiB, that's just the size of the
3473 * PCI BAR. We temporarily abuse smem_len here to store the size
3474 * of the BAR. aty_init() will later correct it to match the actual
3475 * framebuffer size.
3476 *
3477 * On devices that don't have the auxiliary register aperture, the
3478 * registers are housed at the top end of the framebuffer PCI BAR.
3479 * aty_fudge_framebuffer_len() is used to reduce smem_len to not
3480 * overlap with the registers.
3481 */
3482 info->fix.smem_len = 0x800000;
3483
3484 aty_fudge_framebuffer_len(info);
3485
3486 info->screen_base = ioremap_wc(info->fix.smem_start,
3487 info->fix.smem_len);
3488 if (info->screen_base == NULL) {
3489 ret = -ENOMEM;
3490 goto atyfb_setup_generic_fail;
3491 }
3492
3493 ret = correct_chipset(par);
3494 if (ret)
3495 goto atyfb_setup_generic_fail;
3496 #ifdef __i386__
3497 ret = init_from_bios(par);
3498 if (ret)
3499 goto atyfb_setup_generic_fail;
3500 #endif
3501 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3502 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3503 else
3504 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3505
3506 /* according to ATI, we should use clock 3 for acelerated mode */
3507 par->clk_wr_offset = 3;
3508
3509 return 0;
3510
3511 atyfb_setup_generic_fail:
3512 iounmap(par->ati_regbase);
3513 par->ati_regbase = NULL;
3514 if (info->screen_base) {
3515 iounmap(info->screen_base);
3516 info->screen_base = NULL;
3517 }
3518 return ret;
3519 }
3520
3521 #endif /* !__sparc__ */
3522
3523 static int atyfb_pci_probe(struct pci_dev *pdev,
3524 const struct pci_device_id *ent)
3525 {
3526 unsigned long addr, res_start, res_size;
3527 struct fb_info *info;
3528 struct resource *rp;
3529 struct atyfb_par *par;
3530 int rc = -ENOMEM;
3531
3532 /* Enable device in PCI config */
3533 if (pci_enable_device(pdev)) {
3534 PRINTKE("Cannot enable PCI device\n");
3535 return -ENXIO;
3536 }
3537
3538 /* Find which resource to use */
3539 rp = &pdev->resource[0];
3540 if (rp->flags & IORESOURCE_IO)
3541 rp = &pdev->resource[1];
3542 addr = rp->start;
3543 if (!addr)
3544 return -ENXIO;
3545
3546 /* Reserve space */
3547 res_start = rp->start;
3548 res_size = resource_size(rp);
3549 if (!request_mem_region(res_start, res_size, "atyfb"))
3550 return -EBUSY;
3551
3552 /* Allocate framebuffer */
3553 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3554 if (!info) {
3555 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3556 return -ENOMEM;
3557 }
3558 par = info->par;
3559 par->bus_type = PCI;
3560 info->fix = atyfb_fix;
3561 info->device = &pdev->dev;
3562 par->pci_id = pdev->device;
3563 par->res_start = res_start;
3564 par->res_size = res_size;
3565 par->irq = pdev->irq;
3566 par->pdev = pdev;
3567
3568 /* Setup "info" structure */
3569 #ifdef __sparc__
3570 rc = atyfb_setup_sparc(pdev, info, addr);
3571 #else
3572 rc = atyfb_setup_generic(pdev, info, addr);
3573 #endif
3574 if (rc)
3575 goto err_release_mem;
3576
3577 pci_set_drvdata(pdev, info);
3578
3579 /* Init chip & register framebuffer */
3580 rc = aty_init(info);
3581 if (rc)
3582 goto err_release_io;
3583
3584 #ifdef __sparc__
3585 /*
3586 * Add /dev/fb mmap values.
3587 */
3588 par->mmap_map[0].voff = 0x8000000000000000UL;
3589 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3590 par->mmap_map[0].size = info->fix.smem_len;
3591 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3592 par->mmap_map[0].prot_flag = _PAGE_E;
3593 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3594 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3595 par->mmap_map[1].size = PAGE_SIZE;
3596 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3597 par->mmap_map[1].prot_flag = _PAGE_E;
3598 #endif /* __sparc__ */
3599
3600 mutex_lock(&reboot_lock);
3601 if (!reboot_info)
3602 reboot_info = info;
3603 mutex_unlock(&reboot_lock);
3604
3605 return 0;
3606
3607 err_release_io:
3608 #ifdef __sparc__
3609 kfree(par->mmap_map);
3610 #else
3611 if (par->ati_regbase)
3612 iounmap(par->ati_regbase);
3613 if (info->screen_base)
3614 iounmap(info->screen_base);
3615 #endif
3616 err_release_mem:
3617 if (par->aux_start)
3618 release_mem_region(par->aux_start, par->aux_size);
3619
3620 release_mem_region(par->res_start, par->res_size);
3621 framebuffer_release(info);
3622
3623 return rc;
3624 }
3625
3626 #endif /* CONFIG_PCI */
3627
3628 #ifdef CONFIG_ATARI
3629
3630 static int __init atyfb_atari_probe(void)
3631 {
3632 struct atyfb_par *par;
3633 struct fb_info *info;
3634 int m64_num;
3635 u32 clock_r;
3636 int num_found = 0;
3637
3638 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3639 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3640 !phys_guiregbase[m64_num]) {
3641 PRINTKI("phys_*[%d] parameters not set => "
3642 "returning early. \n", m64_num);
3643 continue;
3644 }
3645
3646 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3647 if (!info) {
3648 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3649 return -ENOMEM;
3650 }
3651 par = info->par;
3652
3653 info->fix = atyfb_fix;
3654
3655 par->irq = (unsigned int) -1; /* something invalid */
3656
3657 /*
3658 * Map the video memory (physical address given)
3659 * to somewhere in the kernel address space.
3660 */
3661 info->screen_base = ioremap_wc(phys_vmembase[m64_num],
3662 phys_size[m64_num]);
3663 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3664 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3665 0xFC00ul;
3666 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3667
3668 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3669 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3670
3671 switch (clock_r & 0x003F) {
3672 case 0x12:
3673 par->clk_wr_offset = 3; /* */
3674 break;
3675 case 0x34:
3676 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3677 break;
3678 case 0x16:
3679 par->clk_wr_offset = 1; /* */
3680 break;
3681 case 0x38:
3682 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3683 break;
3684 }
3685
3686 /* Fake pci_id for correct_chipset() */
3687 switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3688 case 0x00d7:
3689 par->pci_id = PCI_CHIP_MACH64GX;
3690 break;
3691 case 0x0057:
3692 par->pci_id = PCI_CHIP_MACH64CX;
3693 break;
3694 default:
3695 break;
3696 }
3697
3698 if (correct_chipset(par) || aty_init(info)) {
3699 iounmap(info->screen_base);
3700 iounmap(par->ati_regbase);
3701 framebuffer_release(info);
3702 } else {
3703 num_found++;
3704 }
3705 }
3706
3707 return num_found ? 0 : -ENXIO;
3708 }
3709
3710 #endif /* CONFIG_ATARI */
3711
3712 #ifdef CONFIG_PCI
3713
3714 static void atyfb_remove(struct fb_info *info)
3715 {
3716 struct atyfb_par *par = (struct atyfb_par *) info->par;
3717
3718 /* restore video mode */
3719 aty_set_crtc(par, &par->saved_crtc);
3720 par->pll_ops->set_pll(info, &par->saved_pll);
3721
3722 unregister_framebuffer(info);
3723
3724 #ifdef CONFIG_FB_ATY_BACKLIGHT
3725 if (M64_HAS(MOBIL_BUS))
3726 aty_bl_exit(info->bl_dev);
3727 #endif
3728 arch_phys_wc_del(par->wc_cookie);
3729
3730 #ifndef __sparc__
3731 if (par->ati_regbase)
3732 iounmap(par->ati_regbase);
3733 if (info->screen_base)
3734 iounmap(info->screen_base);
3735 #ifdef __BIG_ENDIAN
3736 if (info->sprite.addr)
3737 iounmap(info->sprite.addr);
3738 #endif
3739 #endif
3740 #ifdef __sparc__
3741 kfree(par->mmap_map);
3742 #endif
3743 if (par->aux_start)
3744 release_mem_region(par->aux_start, par->aux_size);
3745
3746 if (par->res_start)
3747 release_mem_region(par->res_start, par->res_size);
3748
3749 framebuffer_release(info);
3750 }
3751
3752
3753 static void atyfb_pci_remove(struct pci_dev *pdev)
3754 {
3755 struct fb_info *info = pci_get_drvdata(pdev);
3756
3757 mutex_lock(&reboot_lock);
3758 if (reboot_info == info)
3759 reboot_info = NULL;
3760 mutex_unlock(&reboot_lock);
3761
3762 atyfb_remove(info);
3763 }
3764
3765 static struct pci_device_id atyfb_pci_tbl[] = {
3766 #ifdef CONFIG_FB_ATY_GX
3767 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GX) },
3768 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CX) },
3769 #endif /* CONFIG_FB_ATY_GX */
3770
3771 #ifdef CONFIG_FB_ATY_CT
3772 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CT) },
3773 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64ET) },
3774
3775 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LT) },
3776
3777 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VT) },
3778 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GT) },
3779
3780 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VU) },
3781 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GU) },
3782
3783 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LG) },
3784
3785 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VV) },
3786
3787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GV) },
3788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GW) },
3789 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GY) },
3790 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GZ) },
3791
3792 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GB) },
3793 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GD) },
3794 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GI) },
3795 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GP) },
3796 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GQ) },
3797
3798 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LB) },
3799 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LD) },
3800 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LI) },
3801 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LP) },
3802 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LQ) },
3803
3804 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GM) },
3805 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GN) },
3806 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GO) },
3807 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GL) },
3808 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GR) },
3809 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GS) },
3810
3811 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LM) },
3812 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LN) },
3813 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LR) },
3814 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LS) },
3815 #endif /* CONFIG_FB_ATY_CT */
3816 { }
3817 };
3818
3819 MODULE_DEVICE_TABLE(pci, atyfb_pci_tbl);
3820
3821 static struct pci_driver atyfb_driver = {
3822 .name = "atyfb",
3823 .id_table = atyfb_pci_tbl,
3824 .probe = atyfb_pci_probe,
3825 .remove = atyfb_pci_remove,
3826 #ifdef CONFIG_PM
3827 .suspend = atyfb_pci_suspend,
3828 .resume = atyfb_pci_resume,
3829 #endif /* CONFIG_PM */
3830 };
3831
3832 #endif /* CONFIG_PCI */
3833
3834 #ifndef MODULE
3835 static int __init atyfb_setup(char *options)
3836 {
3837 char *this_opt;
3838
3839 if (!options || !*options)
3840 return 0;
3841
3842 while ((this_opt = strsep(&options, ",")) != NULL) {
3843 if (!strncmp(this_opt, "noaccel", 7)) {
3844 noaccel = 1;
3845 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3846 nomtrr = 1;
3847 } else if (!strncmp(this_opt, "vram:", 5))
3848 vram = simple_strtoul(this_opt + 5, NULL, 0);
3849 else if (!strncmp(this_opt, "pll:", 4))
3850 pll = simple_strtoul(this_opt + 4, NULL, 0);
3851 else if (!strncmp(this_opt, "mclk:", 5))
3852 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3853 else if (!strncmp(this_opt, "xclk:", 5))
3854 xclk = simple_strtoul(this_opt+5, NULL, 0);
3855 else if (!strncmp(this_opt, "comp_sync:", 10))
3856 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3857 else if (!strncmp(this_opt, "backlight:", 10))
3858 backlight = simple_strtoul(this_opt+10, NULL, 0);
3859 #ifdef CONFIG_PPC
3860 else if (!strncmp(this_opt, "vmode:", 6)) {
3861 unsigned int vmode =
3862 simple_strtoul(this_opt + 6, NULL, 0);
3863 if (vmode > 0 && vmode <= VMODE_MAX)
3864 default_vmode = vmode;
3865 } else if (!strncmp(this_opt, "cmode:", 6)) {
3866 unsigned int cmode =
3867 simple_strtoul(this_opt + 6, NULL, 0);
3868 switch (cmode) {
3869 case 0:
3870 case 8:
3871 default_cmode = CMODE_8;
3872 break;
3873 case 15:
3874 case 16:
3875 default_cmode = CMODE_16;
3876 break;
3877 case 24:
3878 case 32:
3879 default_cmode = CMODE_32;
3880 break;
3881 }
3882 }
3883 #endif
3884 #ifdef CONFIG_ATARI
3885 /*
3886 * Why do we need this silly Mach64 argument?
3887 * We are already here because of mach64= so its redundant.
3888 */
3889 else if (MACH_IS_ATARI
3890 && (!strncmp(this_opt, "Mach64:", 7))) {
3891 static unsigned char m64_num;
3892 static char mach64_str[80];
3893 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3894 if (!store_video_par(mach64_str, m64_num)) {
3895 m64_num++;
3896 mach64_count = m64_num;
3897 }
3898 }
3899 #endif
3900 else
3901 mode = this_opt;
3902 }
3903 return 0;
3904 }
3905 #endif /* MODULE */
3906
3907 static int atyfb_reboot_notify(struct notifier_block *nb,
3908 unsigned long code, void *unused)
3909 {
3910 struct atyfb_par *par;
3911
3912 if (code != SYS_RESTART)
3913 return NOTIFY_DONE;
3914
3915 mutex_lock(&reboot_lock);
3916
3917 if (!reboot_info)
3918 goto out;
3919
3920 if (!lock_fb_info(reboot_info))
3921 goto out;
3922
3923 par = reboot_info->par;
3924
3925 /*
3926 * HP OmniBook 500's BIOS doesn't like the state of the
3927 * hardware after atyfb has been used. Restore the hardware
3928 * to the original state to allow successful reboots.
3929 */
3930 aty_set_crtc(par, &par->saved_crtc);
3931 par->pll_ops->set_pll(reboot_info, &par->saved_pll);
3932
3933 unlock_fb_info(reboot_info);
3934 out:
3935 mutex_unlock(&reboot_lock);
3936
3937 return NOTIFY_DONE;
3938 }
3939
3940 static struct notifier_block atyfb_reboot_notifier = {
3941 .notifier_call = atyfb_reboot_notify,
3942 };
3943
3944 static const struct dmi_system_id atyfb_reboot_ids[] __initconst = {
3945 {
3946 .ident = "HP OmniBook 500",
3947 .matches = {
3948 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3949 DMI_MATCH(DMI_PRODUCT_NAME, "HP OmniBook PC"),
3950 DMI_MATCH(DMI_PRODUCT_VERSION, "HP OmniBook 500 FA"),
3951 },
3952 },
3953
3954 { }
3955 };
3956 static bool registered_notifier = false;
3957
3958 static int __init atyfb_init(void)
3959 {
3960 int err1 = 1, err2 = 1;
3961 #ifndef MODULE
3962 char *option = NULL;
3963
3964 if (fb_get_options("atyfb", &option))
3965 return -ENODEV;
3966 atyfb_setup(option);
3967 #endif
3968
3969 #ifdef CONFIG_PCI
3970 err1 = pci_register_driver(&atyfb_driver);
3971 #endif
3972 #ifdef CONFIG_ATARI
3973 err2 = atyfb_atari_probe();
3974 #endif
3975
3976 if (err1 && err2)
3977 return -ENODEV;
3978
3979 if (dmi_check_system(atyfb_reboot_ids)) {
3980 register_reboot_notifier(&atyfb_reboot_notifier);
3981 registered_notifier = true;
3982 }
3983
3984 return 0;
3985 }
3986
3987 static void __exit atyfb_exit(void)
3988 {
3989 if (registered_notifier)
3990 unregister_reboot_notifier(&atyfb_reboot_notifier);
3991
3992 #ifdef CONFIG_PCI
3993 pci_unregister_driver(&atyfb_driver);
3994 #endif
3995 }
3996
3997 module_init(atyfb_init);
3998 module_exit(atyfb_exit);
3999
4000 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
4001 MODULE_LICENSE("GPL");
4002 module_param(noaccel, bool, 0);
4003 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
4004 module_param(vram, int, 0);
4005 MODULE_PARM_DESC(vram, "int: override size of video ram");
4006 module_param(pll, int, 0);
4007 MODULE_PARM_DESC(pll, "int: override video clock");
4008 module_param(mclk, int, 0);
4009 MODULE_PARM_DESC(mclk, "int: override memory clock");
4010 module_param(xclk, int, 0);
4011 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
4012 module_param(comp_sync, int, 0);
4013 MODULE_PARM_DESC(comp_sync, "Set composite sync signal to low (0) or high (1)");
4014 module_param(mode, charp, 0);
4015 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
4016 module_param(nomtrr, bool, 0);
4017 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
Linux with added FPC-III support