drivers/video/fbdev/matrox/matroxfb_base.h

   1 /*
   2  *
   3  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
   4  *
   5  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
   6  *
   7  */
   8 #ifndef __MATROXFB_H__
   9 #define __MATROXFB_H__
  10
  11 /* general, but fairly heavy, debugging */
  12 #undef MATROXFB_DEBUG
  13
  14 /* heavy debugging: */
  15 /* -- logs putc[s], so every time a char is displayed, it's logged */
  16 #undef MATROXFB_DEBUG_HEAVY
  17
  18 /* This one _could_ cause infinite loops */
  19 /* It _does_ cause lots and lots of messages during idle loops */
  20 #undef MATROXFB_DEBUG_LOOP
  21
  22 /* Debug register calls, too? */
  23 #undef MATROXFB_DEBUG_REG
  24
  25 /* Guard accelerator accesses with spin_lock_irqsave... */
  26 #undef MATROXFB_USE_SPINLOCKS
  27
  28 #include <linux/module.h>
  29 #include <linux/kernel.h>
  30 #include <linux/errno.h>
  31 #include <linux/string.h>
  32 #include <linux/mm.h>
  33 #include <linux/slab.h>
  34 #include <linux/delay.h>
  35 #include <linux/fb.h>
  36 #include <linux/console.h>
  37 #include <linux/selection.h>
  38 #include <linux/ioport.h>
  39 #include <linux/init.h>
  40 #include <linux/timer.h>
  41 #include <linux/pci.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/kd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/unaligned.h>
  47
  48 #if defined(CONFIG_PPC_PMAC)
  49 #include <asm/prom.h>
  50 #include "../macmodes.h"
  51 #endif
  52
  53 #ifdef MATROXFB_DEBUG
  54
  55 #define DEBUG
  56 #define DBG(x)          printk(KERN_DEBUG "matroxfb: %s\n", (x));
  57
  58 #ifdef MATROXFB_DEBUG_HEAVY
  59 #define DBG_HEAVY(x)    DBG(x)
  60 #else /* MATROXFB_DEBUG_HEAVY */
  61 #define DBG_HEAVY(x)    /* DBG_HEAVY */
  62 #endif /* MATROXFB_DEBUG_HEAVY */
  63
  64 #ifdef MATROXFB_DEBUG_LOOP
  65 #define DBG_LOOP(x)     DBG(x)
  66 #else /* MATROXFB_DEBUG_LOOP */
  67 #define DBG_LOOP(x)     /* DBG_LOOP */
  68 #endif /* MATROXFB_DEBUG_LOOP */
  69
  70 #ifdef MATROXFB_DEBUG_REG
  71 #define DBG_REG(x)      DBG(x)
  72 #else /* MATROXFB_DEBUG_REG */
  73 #define DBG_REG(x)      /* DBG_REG */
  74 #endif /* MATROXFB_DEBUG_REG */
  75
  76 #else /* MATROXFB_DEBUG */
  77
  78 #define DBG(x)          /* DBG */
  79 #define DBG_HEAVY(x)    /* DBG_HEAVY */
  80 #define DBG_REG(x)      /* DBG_REG */
  81 #define DBG_LOOP(x)     /* DBG_LOOP */
  82
  83 #endif /* MATROXFB_DEBUG */
  84
  85 #ifdef DEBUG
  86 #define dprintk(X...)   printk(X)
  87 #else
  88 #define dprintk(X...)
  89 #endif
  90
  91 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
  92 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF        0x110A
  93 #endif
  94 #ifndef PCI_SS_VENDOR_ID_MATROX
  95 #define PCI_SS_VENDOR_ID_MATROX         PCI_VENDOR_ID_MATROX
  96 #endif
  97
  98 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
  99 #define PCI_SS_ID_MATROX_GENERIC                0xFF00
 100 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP    0xFF01
 101 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP      0xFF02
 102 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP     0xFF03
 103 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP        0xFF04
 104 #define PCI_SS_ID_MATROX_MGA_G100_PCI           0xFF05
 105 #define PCI_SS_ID_MATROX_MGA_G100_AGP           0x1001
 106 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP        0x2179
 107 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP          0x001E /* 30 */
 108 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP          0x0032 /* 50 */
 109 #endif
 110
 111 #define MX_VISUAL_TRUECOLOR     FB_VISUAL_DIRECTCOLOR
 112 #define MX_VISUAL_DIRECTCOLOR   FB_VISUAL_TRUECOLOR
 113 #define MX_VISUAL_PSEUDOCOLOR   FB_VISUAL_PSEUDOCOLOR
 114
 115 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 116
 117 /* G-series and Mystique have (almost) same DAC */
 118 #undef NEED_DAC1064
 119 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
 120 #define NEED_DAC1064 1
 121 #endif
 122
 123 typedef struct {
 124         void __iomem*   vaddr;
 125 } vaddr_t;
 126
 127 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
 128         return readb(va.vaddr + offs);
 129 }
 130
 131 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
 132         writeb(value, va.vaddr + offs);
 133 }
 134
 135 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
 136         writew(value, va.vaddr + offs);
 137 }
 138
 139 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
 140         return readl(va.vaddr + offs);
 141 }
 142
 143 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
 144         writel(value, va.vaddr + offs);
 145 }
 146
 147 static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
 148 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
 149         /*
 150          * iowrite32_rep works for us if:
 151          *  (1) Copies data as 32bit quantities, not byte after byte,
 152          *  (2) Performs LE ordered stores, and
 153          *  (3) It copes with unaligned source (destination is guaranteed to be page
 154          *      aligned and length is guaranteed to be multiple of 4).
 155          */
 156         iowrite32_rep(va.vaddr, src, len >> 2);
 157 #else
 158         u_int32_t __iomem* addr = va.vaddr;
 159
 160         if ((unsigned long)src & 3) {
 161                 while (len >= 4) {
 162                         fb_writel(get_unaligned((u32 *)src), addr);
 163                         addr++;
 164                         len -= 4;
 165                         src += 4;
 166                 }
 167         } else {
 168                 while (len >= 4) {
 169                         fb_writel(*(u32 *)src, addr);
 170                         addr++;
 171                         len -= 4;
 172                         src += 4;
 173                 }
 174         }
 175 #endif
 176 }
 177
 178 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
 179         va->vaddr += offs;
 180 }
 181
 182 static inline void __iomem* vaddr_va(vaddr_t va) {
 183         return va.vaddr;
 184 }
 185
 186 struct my_timming {
 187         unsigned int pixclock;
 188         int mnp;
 189         unsigned int crtc;
 190         unsigned int HDisplay;
 191         unsigned int HSyncStart;
 192         unsigned int HSyncEnd;
 193         unsigned int HTotal;
 194         unsigned int VDisplay;
 195         unsigned int VSyncStart;
 196         unsigned int VSyncEnd;
 197         unsigned int VTotal;
 198         unsigned int sync;
 199         int          dblscan;
 200         int          interlaced;
 201         unsigned int delay;     /* CRTC delay */
 202 };
 203
 204 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
 205
 206 struct matrox_pll_cache {
 207         unsigned int    valid;
 208         struct {
 209                 unsigned int    mnp_key;
 210                 unsigned int    mnp_value;
 211                       } data[4];
 212 };
 213
 214 struct matrox_pll_limits {
 215         unsigned int    vcomin;
 216         unsigned int    vcomax;
 217 };
 218
 219 struct matrox_pll_features {
 220         unsigned int    vco_freq_min;
 221         unsigned int    ref_freq;
 222         unsigned int    feed_div_min;
 223         unsigned int    feed_div_max;
 224         unsigned int    in_div_min;
 225         unsigned int    in_div_max;
 226         unsigned int    post_shift_max;
 227 };
 228
 229 struct matroxfb_par
 230 {
 231         unsigned int    final_bppShift;
 232         unsigned int    cmap_len;
 233         struct {
 234                 unsigned int bytes;
 235                 unsigned int pixels;
 236                 unsigned int chunks;
 237                       } ydstorg;
 238 };
 239
 240 struct matrox_fb_info;
 241
 242 struct matrox_DAC1064_features {
 243         u_int8_t        xvrefctrl;
 244         u_int8_t        xmiscctrl;
 245 };
 246
 247 /* current hardware status */
 248 struct mavenregs {
 249         u_int8_t regs[256];
 250         int      mode;
 251         int      vlines;
 252         int      xtal;
 253         int      fv;
 254
 255         u_int16_t htotal;
 256         u_int16_t hcorr;
 257 };
 258
 259 struct matrox_crtc2 {
 260         u_int32_t ctl;
 261 };
 262
 263 struct matrox_hw_state {
 264         u_int32_t       MXoptionReg;
 265         unsigned char   DACclk[6];
 266         unsigned char   DACreg[80];
 267         unsigned char   MiscOutReg;
 268         unsigned char   DACpal[768];
 269         unsigned char   CRTC[25];
 270         unsigned char   CRTCEXT[9];
 271         unsigned char   SEQ[5];
 272         /* unused for MGA mode, but who knows... */
 273         unsigned char   GCTL[9];
 274         /* unused for MGA mode, but who knows... */
 275         unsigned char   ATTR[21];
 276
 277         /* TVOut only */
 278         struct mavenregs        maven;
 279
 280         struct matrox_crtc2     crtc2;
 281 };
 282
 283 struct matrox_accel_data {
 284 #ifdef CONFIG_FB_MATROX_MILLENIUM
 285         unsigned char   ramdac_rev;
 286 #endif
 287         u_int32_t       m_dwg_rect;
 288         u_int32_t       m_opmode;
 289         u_int32_t       m_access;
 290         u_int32_t       m_pitch;
 291 };
 292
 293 struct v4l2_queryctrl;
 294 struct v4l2_control;
 295
 296 struct matrox_altout {
 297         const char      *name;
 298         int             (*compute)(void* altout_dev, struct my_timming* input);
 299         int             (*program)(void* altout_dev);
 300         int             (*start)(void* altout_dev);
 301         int             (*verifymode)(void* altout_dev, u_int32_t mode);
 302         int             (*getqueryctrl)(void* altout_dev,
 303                                         struct v4l2_queryctrl* ctrl);
 304         int             (*getctrl)(void* altout_dev,
 305                                    struct v4l2_control* ctrl);
 306         int             (*setctrl)(void* altout_dev,
 307                                    struct v4l2_control* ctrl);
 308 };
 309
 310 #define MATROXFB_SRC_NONE       0
 311 #define MATROXFB_SRC_CRTC1      1
 312 #define MATROXFB_SRC_CRTC2      2
 313
 314 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
 315
 316 struct matrox_bios {
 317         unsigned int    bios_valid : 1;
 318         unsigned int    pins_len;
 319         unsigned char   pins[128];
 320         struct {
 321                 unsigned char vMaj, vMin, vRev;
 322                       } version;
 323         struct {
 324                 unsigned char state, tvout;
 325                       } output;
 326 };
 327
 328 struct matrox_switch;
 329 struct matroxfb_driver;
 330 struct matroxfb_dh_fb_info;
 331
 332 struct matrox_vsync {
 333         wait_queue_head_t       wait;
 334         unsigned int            cnt;
 335 };
 336
 337 struct matrox_fb_info {
 338         struct fb_info          fbcon;
 339
 340         struct list_head        next_fb;
 341
 342         int                     dead;
 343         int                     initialized;
 344         unsigned int            usecount;
 345
 346         unsigned int            userusecount;
 347         unsigned long           irq_flags;
 348
 349         struct matroxfb_par     curr;
 350         struct matrox_hw_state  hw;
 351
 352         struct matrox_accel_data accel;
 353
 354         struct pci_dev*         pcidev;
 355
 356         struct {
 357                 struct matrox_vsync     vsync;
 358                 unsigned int    pixclock;
 359                 int             mnp;
 360                 int             panpos;
 361                               } crtc1;
 362         struct {
 363                 struct matrox_vsync     vsync;
 364                 unsigned int    pixclock;
 365                 int             mnp;
 366         struct matroxfb_dh_fb_info*     info;
 367         struct rw_semaphore     lock;
 368                               } crtc2;
 369         struct {
 370         struct rw_semaphore     lock;
 371         struct {
 372                 int brightness, contrast, saturation, hue, gamma;
 373                 int testout, deflicker;
 374                                 } tvo_params;
 375                               } altout;
 376 #define MATROXFB_MAX_OUTPUTS            3
 377         struct {
 378         unsigned int            src;
 379         struct matrox_altout*   output;
 380         void*                   data;
 381         unsigned int            mode;
 382         unsigned int            default_src;
 383                               } outputs[MATROXFB_MAX_OUTPUTS];
 384
 385 #define MATROXFB_MAX_FB_DRIVERS         5
 386         struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
 387         void*                   (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
 388         unsigned int            drivers_count;
 389
 390         struct {
 391         unsigned long   base;   /* physical */
 392         vaddr_t         vbase;  /* CPU view */
 393         unsigned int    len;
 394         unsigned int    len_usable;
 395         unsigned int    len_maximum;
 396                       } video;
 397
 398         struct {
 399         unsigned long   base;   /* physical */
 400         vaddr_t         vbase;  /* CPU view */
 401         unsigned int    len;
 402                       } mmio;
 403
 404         unsigned int    max_pixel_clock;
 405         unsigned int    max_pixel_clock_panellink;
 406
 407         struct matrox_switch*   hw_switch;
 408
 409         struct {
 410                 struct matrox_pll_features pll;
 411                 struct matrox_DAC1064_features DAC1064;
 412                               } features;
 413         struct {
 414                 spinlock_t      DAC;
 415                 spinlock_t      accel;
 416                               } lock;
 417
 418         enum mga_chip           chip;
 419
 420         int                     interleave;
 421         int                     millenium;
 422         int                     milleniumII;
 423         struct {
 424                 int             cfb4;
 425                 const int*      vxres;
 426                 int             cross4MB;
 427                 int             text;
 428                 int             plnwt;
 429                 int             srcorg;
 430                               } capable;
 431         int                     wc_cookie;
 432         struct {
 433                 int             precise_width;
 434                 int             mga_24bpp_fix;
 435                 int             novga;
 436                 int             nobios;
 437                 int             nopciretry;
 438                 int             noinit;
 439                 int             sgram;
 440                 int             support32MB;
 441
 442                 int             accelerator;
 443                 int             text_type_aux;
 444                 int             video64bits;
 445                 int             crtc2;
 446                 int             maven_capable;
 447                 unsigned int    vgastep;
 448                 unsigned int    textmode;
 449                 unsigned int    textstep;
 450                 unsigned int    textvram;       /* character cells */
 451                 unsigned int    ydstorg;        /* offset in bytes from video start to usable memory */
 452                                                 /* 0 except for 6MB Millenium */
 453                 int             memtype;
 454                 int             g450dac;
 455                 int             dfp_type;
 456                 int             panellink;      /* G400 DFP possible (not G450/G550) */
 457                 int             dualhead;
 458                 unsigned int    fbResource;
 459                               } devflags;
 460         struct fb_ops           fbops;
 461         struct matrox_bios      bios;
 462         struct {
 463                 struct matrox_pll_limits        pixel;
 464                 struct matrox_pll_limits        system;
 465                 struct matrox_pll_limits        video;
 466                               } limits;
 467         struct {
 468                 struct matrox_pll_cache pixel;
 469                 struct matrox_pll_cache system;
 470                 struct matrox_pll_cache video;
 471                                       } cache;
 472         struct {
 473                 struct {
 474                         unsigned int    video;
 475                         unsigned int    system;
 476                                       } pll;
 477                 struct {
 478                         u_int32_t       opt;
 479                         u_int32_t       opt2;
 480                         u_int32_t       opt3;
 481                         u_int32_t       mctlwtst;
 482                         u_int32_t       mctlwtst_core;
 483                         u_int32_t       memmisc;
 484                         u_int32_t       memrdbk;
 485                         u_int32_t       maccess;
 486                                       } reg;
 487                 struct {
 488                         unsigned int    ddr:1,
 489                                         emrswen:1,
 490                                         dll:1;
 491                                       } memory;
 492                               } values;
 493         u_int32_t cmap[16];
 494 };
 495
 496 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
 497
 498 struct matrox_switch {
 499         int     (*preinit)(struct matrox_fb_info *minfo);
 500         void    (*reset)(struct matrox_fb_info *minfo);
 501         int     (*init)(struct matrox_fb_info *minfo, struct my_timming*);
 502         void    (*restore)(struct matrox_fb_info *minfo);
 503 };
 504
 505 struct matroxfb_driver {
 506         struct list_head        node;
 507         char*                   name;
 508         void*                   (*probe)(struct matrox_fb_info* info);
 509         void                    (*remove)(struct matrox_fb_info* info, void* data);
 510 };
 511
 512 int matroxfb_register_driver(struct matroxfb_driver* drv);
 513 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
 514
 515 #define PCI_OPTION_REG  0x40
 516 #define   PCI_OPTION_ENABLE_ROM         0x40000000
 517
 518 #define PCI_MGA_INDEX   0x44
 519 #define PCI_MGA_DATA    0x48
 520 #define PCI_OPTION2_REG 0x50
 521 #define PCI_OPTION3_REG 0x54
 522 #define PCI_MEMMISC_REG 0x58
 523
 524 #define M_DWGCTL        0x1C00
 525 #define M_MACCESS       0x1C04
 526 #define M_CTLWTST       0x1C08
 527
 528 #define M_PLNWT         0x1C1C
 529
 530 #define M_BCOL          0x1C20
 531 #define M_FCOL          0x1C24
 532
 533 #define M_SGN           0x1C58
 534 #define M_LEN           0x1C5C
 535 #define M_AR0           0x1C60
 536 #define M_AR1           0x1C64
 537 #define M_AR2           0x1C68
 538 #define M_AR3           0x1C6C
 539 #define M_AR4           0x1C70
 540 #define M_AR5           0x1C74
 541 #define M_AR6           0x1C78
 542
 543 #define M_CXBNDRY       0x1C80
 544 #define M_FXBNDRY       0x1C84
 545 #define M_YDSTLEN       0x1C88
 546 #define M_PITCH         0x1C8C
 547 #define M_YDST          0x1C90
 548 #define M_YDSTORG       0x1C94
 549 #define M_YTOP          0x1C98
 550 #define M_YBOT          0x1C9C
 551
 552 /* mystique only */
 553 #define M_CACHEFLUSH    0x1FFF
 554
 555 #define M_EXEC          0x0100
 556
 557 #define M_DWG_TRAP      0x04
 558 #define M_DWG_BITBLT    0x08
 559 #define M_DWG_ILOAD     0x09
 560
 561 #define M_DWG_LINEAR    0x0080
 562 #define M_DWG_SOLID     0x0800
 563 #define M_DWG_ARZERO    0x1000
 564 #define M_DWG_SGNZERO   0x2000
 565 #define M_DWG_SHIFTZERO 0x4000
 566
 567 #define M_DWG_REPLACE   0x000C0000
 568 #define M_DWG_REPLACE2  (M_DWG_REPLACE | 0x40)
 569 #define M_DWG_XOR       0x00060010
 570
 571 #define M_DWG_BFCOL     0x04000000
 572 #define M_DWG_BMONOWF   0x08000000
 573
 574 #define M_DWG_TRANSC    0x40000000
 575
 576 #define M_FIFOSTATUS    0x1E10
 577 #define M_STATUS        0x1E14
 578 #define M_ICLEAR        0x1E18
 579 #define M_IEN           0x1E1C
 580
 581 #define M_VCOUNT        0x1E20
 582
 583 #define M_RESET         0x1E40
 584 #define M_MEMRDBK       0x1E44
 585
 586 #define M_AGP2PLL       0x1E4C
 587
 588 #define M_OPMODE        0x1E54
 589 #define     M_OPMODE_DMA_GEN_WRITE      0x00
 590 #define     M_OPMODE_DMA_BLIT           0x04
 591 #define     M_OPMODE_DMA_VECTOR_WRITE   0x08
 592 #define     M_OPMODE_DMA_LE             0x0000          /* little endian - no transformation */
 593 #define     M_OPMODE_DMA_BE_8BPP        0x0000
 594 #define     M_OPMODE_DMA_BE_16BPP       0x0100
 595 #define     M_OPMODE_DMA_BE_32BPP       0x0200
 596 #define     M_OPMODE_DIR_LE             0x000000        /* little endian - no transformation */
 597 #define     M_OPMODE_DIR_BE_8BPP        0x000000
 598 #define     M_OPMODE_DIR_BE_16BPP       0x010000
 599 #define     M_OPMODE_DIR_BE_32BPP       0x020000
 600
 601 #define M_ATTR_INDEX    0x1FC0
 602 #define M_ATTR_DATA     0x1FC1
 603
 604 #define M_MISC_REG      0x1FC2
 605 #define M_3C2_RD        0x1FC2
 606
 607 #define M_SEQ_INDEX     0x1FC4
 608 #define M_SEQ_DATA      0x1FC5
 609 #define     M_SEQ1              0x01
 610 #define        M_SEQ1_SCROFF            0x20
 611
 612 #define M_MISC_REG_READ 0x1FCC
 613
 614 #define M_GRAPHICS_INDEX 0x1FCE
 615 #define M_GRAPHICS_DATA 0x1FCF
 616
 617 #define M_CRTC_INDEX    0x1FD4
 618
 619 #define M_ATTR_RESET    0x1FDA
 620 #define M_3DA_WR        0x1FDA
 621 #define M_INSTS1        0x1FDA
 622
 623 #define M_EXTVGA_INDEX  0x1FDE
 624 #define M_EXTVGA_DATA   0x1FDF
 625
 626 /* G200 only */
 627 #define M_SRCORG        0x2CB4
 628 #define M_DSTORG        0x2CB8
 629
 630 #define M_RAMDAC_BASE   0x3C00
 631
 632 /* fortunately, same on TVP3026 and MGA1064 */
 633 #define M_DAC_REG       (M_RAMDAC_BASE+0)
 634 #define M_DAC_VAL       (M_RAMDAC_BASE+1)
 635 #define M_PALETTE_MASK  (M_RAMDAC_BASE+2)
 636
 637 #define M_X_INDEX       0x00
 638 #define M_X_DATAREG     0x0A
 639
 640 #define DAC_XGENIOCTRL          0x2A
 641 #define DAC_XGENIODATA          0x2B
 642
 643 #define M_C2CTL         0x3C10
 644
 645 #define MX_OPTION_BSWAP         0x00000000
 646
 647 #ifdef __LITTLE_ENDIAN
 648 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 649 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 650 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 651 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 652 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 653 #else
 654 #ifdef __BIG_ENDIAN
 655 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE       | M_OPMODE_DMA_BLIT)   /* TODO */
 656 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)
 657 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
 658 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)   /* TODO, ?32 */
 659 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
 660 #else
 661 #error "Byte ordering have to be defined. Cannot continue."
 662 #endif
 663 #endif
 664
 665 #define mga_inb(addr)           mga_readb(minfo->mmio.vbase, (addr))
 666 #define mga_inl(addr)           mga_readl(minfo->mmio.vbase, (addr))
 667 #define mga_outb(addr,val)      mga_writeb(minfo->mmio.vbase, (addr), (val))
 668 #define mga_outw(addr,val)      mga_writew(minfo->mmio.vbase, (addr), (val))
 669 #define mga_outl(addr,val)      mga_writel(minfo->mmio.vbase, (addr), (val))
 670 #define mga_readr(port,idx)     (mga_outb((port),(idx)), mga_inb((port)+1))
 671 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
 672
 673 #define mga_fifo(n)     do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
 674
 675 #define WaitTillIdle()  do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0)
 676
 677 /* code speedup */
 678 #ifdef CONFIG_FB_MATROX_MILLENIUM
 679 #define isInterleave(x)  (x->interleave)
 680 #define isMillenium(x)   (x->millenium)
 681 #define isMilleniumII(x) (x->milleniumII)
 682 #else
 683 #define isInterleave(x)  (0)
 684 #define isMillenium(x)   (0)
 685 #define isMilleniumII(x) (0)
 686 #endif
 687
 688 #define matroxfb_DAC_lock()                   spin_lock(&minfo->lock.DAC)
 689 #define matroxfb_DAC_unlock()                 spin_unlock(&minfo->lock.DAC)
 690 #define matroxfb_DAC_lock_irqsave(flags)      spin_lock_irqsave(&minfo->lock.DAC, flags)
 691 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
 692 extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg,
 693                              int val);
 694 extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg);
 695 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
 696 extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc);
 697 extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable);
 698
 699 #ifdef MATROXFB_USE_SPINLOCKS
 700 #define CRITBEGIN  spin_lock_irqsave(&minfo->lock.accel, critflags);
 701 #define CRITEND    spin_unlock_irqrestore(&minfo->lock.accel, critflags);
 702 #define CRITFLAGS  unsigned long critflags;
 703 #else
 704 #define CRITBEGIN
 705 #define CRITEND
 706 #define CRITFLAGS
 707 #endif
 708
 709 #endif  /* __MATROXFB_H__ */