drivers/video/fbdev/savage/savagefb.h

   1 /*
   2  * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
   3  *
   4  * Copyright (c) 2001  Denis Oliver Kropp <dok@convergence.de>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General
   7  * Public License.  See the file COPYING in the main directory of this
   8  * archive for more details.
   9  */
  10
  11
  12 #ifndef __SAVAGEFB_H__
  13 #define __SAVAGEFB_H__
  14
  15 #include <linux/i2c.h>
  16 #include <linux/i2c-algo-bit.h>
  17 #include <linux/mutex.h>
  18 #include <video/vga.h>
  19 #include "../edid.h"
  20
  21 #ifdef SAVAGEFB_DEBUG
  22 # define DBG(x)         printk (KERN_DEBUG "savagefb: %s\n", (x));
  23 #else
  24 # define DBG(x)
  25 # define SavagePrintRegs(...)
  26 #endif
  27
  28
  29 #define PCI_CHIP_SAVAGE4      0x8a22
  30 #define PCI_CHIP_SAVAGE3D     0x8a20
  31 #define PCI_CHIP_SAVAGE3D_MV  0x8a21
  32 #define PCI_CHIP_SAVAGE2000   0x9102
  33 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
  34 #define PCI_CHIP_SAVAGE_MX    0x8c11
  35 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
  36 #define PCI_CHIP_SAVAGE_IX    0x8c13
  37 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
  38 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
  39 #define PCI_CHIP_S3TWISTER_P  0x8d01
  40 #define PCI_CHIP_S3TWISTER_K  0x8d02
  41 #define PCI_CHIP_PROSAVAGE_DDR          0x8d03
  42 #define PCI_CHIP_PROSAVAGE_DDRK         0x8d04
  43 #define PCI_CHIP_SUPSAV_MX128           0x8c22
  44 #define PCI_CHIP_SUPSAV_MX64            0x8c24
  45 #define PCI_CHIP_SUPSAV_MX64C           0x8c26
  46 #define PCI_CHIP_SUPSAV_IX128SDR        0x8c2a
  47 #define PCI_CHIP_SUPSAV_IX128DDR        0x8c2b
  48 #define PCI_CHIP_SUPSAV_IX64SDR         0x8c2c
  49 #define PCI_CHIP_SUPSAV_IX64DDR         0x8c2d
  50 #define PCI_CHIP_SUPSAV_IXCSDR          0x8c2e
  51 #define PCI_CHIP_SUPSAV_IXCDDR          0x8c2f
  52
  53
  54 #define S3_SAVAGE_SERIES(chip)    ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
  55
  56 #define S3_SAVAGE3D_SERIES(chip)  ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
  57
  58 #define S3_SAVAGE4_SERIES(chip)   ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
  59
  60 #define S3_SAVAGE_MOBILE_SERIES(chip)  ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
  61
  62 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
  63
  64 /* Chip tags.  These are used to group the adapters into
  65  * related families.
  66  */
  67
  68 typedef enum {
  69   S3_UNKNOWN = 0,
  70   S3_SAVAGE3D,
  71   S3_SAVAGE_MX,
  72   S3_SAVAGE4,
  73   S3_PROSAVAGE,
  74   S3_TWISTER,
  75   S3_PROSAVAGEDDR,
  76   S3_SUPERSAVAGE,
  77   S3_SAVAGE2000,
  78   S3_LAST
  79 } savage_chipset;
  80
  81 #define BIOS_BSIZE                   1024
  82 #define BIOS_BASE                    0xc0000
  83
  84 #define SAVAGE_NEWMMIO_REGBASE_S3    0x1000000  /* 16MB */
  85 #define SAVAGE_NEWMMIO_REGBASE_S4    0x0000000
  86 #define SAVAGE_NEWMMIO_REGSIZE       0x0080000  /* 512kb */
  87 #define SAVAGE_NEWMMIO_VGABASE       0x8000
  88
  89 #define BASE_FREQ                    14318
  90 #define HALF_BASE_FREQ               7159
  91
  92 #define FIFO_CONTROL_REG             0x8200
  93 #define MIU_CONTROL_REG              0x8204
  94 #define STREAMS_TIMEOUT_REG          0x8208
  95 #define MISC_TIMEOUT_REG             0x820c
  96
  97 #define MONO_PAT_0                   0xa4e8
  98 #define MONO_PAT_1                   0xa4ec
  99
 100 #define MAXFIFO                      0x7f00
 101
 102 #define BCI_CMD_NOP                  0x40000000
 103 #define BCI_CMD_SETREG               0x96000000
 104 #define BCI_CMD_RECT                 0x48000000
 105 #define BCI_CMD_RECT_XP              0x01000000
 106 #define BCI_CMD_RECT_YP              0x02000000
 107 #define BCI_CMD_SEND_COLOR           0x00008000
 108 #define BCI_CMD_DEST_GBD             0x00000000
 109 #define BCI_CMD_SRC_GBD              0x00000020
 110 #define BCI_CMD_SRC_SOLID            0x00000000
 111 #define BCI_CMD_SRC_MONO             0x00000060
 112 #define BCI_CMD_CLIP_NEW             0x00006000
 113 #define BCI_CMD_CLIP_LR              0x00004000
 114
 115 #define BCI_CLIP_LR(l, r)            ((((r) << 16) | (l)) & 0x0FFF0FFF)
 116 #define BCI_CLIP_TL(t, l)            ((((t) << 16) | (l)) & 0x0FFF0FFF)
 117 #define BCI_CLIP_BR(b, r)            ((((b) << 16) | (r)) & 0x0FFF0FFF)
 118 #define BCI_W_H(w, h)                (((h) << 16) | ((w) & 0xFFF))
 119 #define BCI_X_Y(x, y)                (((y) << 16) | ((x) & 0xFFF))
 120
 121 #define BCI_GBD1                     0xE0
 122 #define BCI_GBD2                     0xE1
 123
 124 #define BCI_BUFFER_OFFSET            0x10000
 125 #define BCI_SIZE                     0x4000
 126
 127 #define BCI_SEND(dw)                 writel(dw, par->bci_base + par->bci_ptr++)
 128
 129 #define BCI_CMD_GET_ROP(cmd)         (((cmd) >> 16) & 0xFF)
 130 #define BCI_CMD_SET_ROP(cmd, rop)    ((cmd) |= ((rop & 0xFF) << 16))
 131 #define BCI_CMD_SEND_COLOR           0x00008000
 132
 133 #define DISP_CRT     1
 134 #define DISP_LCD     2
 135 #define DISP_DFP     3
 136
 137 struct xtimings {
 138         unsigned int Clock;
 139         unsigned int HDisplay;
 140         unsigned int HSyncStart;
 141         unsigned int HSyncEnd;
 142         unsigned int HTotal;
 143         unsigned int HAdjusted;
 144         unsigned int VDisplay;
 145         unsigned int VSyncStart;
 146         unsigned int VSyncEnd;
 147         unsigned int VTotal;
 148         unsigned int sync;
 149         int            dblscan;
 150         int            interlaced;
 151 };
 152
 153 struct savage_reg {
 154         unsigned char MiscOutReg;     /* Misc */
 155         unsigned char CRTC[25];       /* Crtc Controller */
 156         unsigned char Sequencer[5];   /* Video Sequencer */
 157         unsigned char Graphics[9];    /* Video Graphics */
 158         unsigned char Attribute[21];  /* Video Attribute */
 159
 160         unsigned int mode, refresh;
 161         unsigned char SR08, SR0E, SR0F;
 162         unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
 163         unsigned char SR54[8];
 164         unsigned char Clock;
 165         unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
 166         unsigned char CR40, CR41, CR42, CR43, CR45;
 167         unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
 168         unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
 169         unsigned char CR86, CR88;
 170         unsigned char CR90, CR91, CRB0;
 171         unsigned int  STREAMS[22];      /* yuck, streams regs */
 172         unsigned int  MMPR0, MMPR1, MMPR2, MMPR3;
 173 };
 174 /* --------------------------------------------------------------------- */
 175
 176 #define NR_PALETTE      256
 177
 178
 179 struct savagefb_par;
 180
 181 struct savagefb_i2c_chan {
 182         struct savagefb_par *par;
 183         struct i2c_adapter adapter;
 184         struct i2c_algo_bit_data algo;
 185         volatile u8 __iomem *ioaddr;
 186         u32   reg;
 187 };
 188
 189 struct savagefb_par {
 190         struct pci_dev *pcidev;
 191         savage_chipset  chip;
 192         struct savagefb_i2c_chan chan;
 193         struct savage_reg state;
 194         struct savage_reg save;
 195         struct savage_reg initial;
 196         struct vgastate vgastate;
 197         struct mutex open_lock;
 198         unsigned char   *edid;
 199         u32 pseudo_palette[16];
 200         u32 open_count;
 201         int paletteEnabled;
 202         int pm_state;
 203         int display_type;
 204         int dvi;
 205         int crtonly;
 206         int dacSpeedBpp;
 207         int maxClock;
 208         int minClock;
 209         int numClocks;
 210         int clock[4];
 211         int MCLK, REFCLK, LCDclk;
 212         struct {
 213                 void   __iomem *vbase;
 214                 u32    pbase;
 215                 u32    len;
 216                 int    wc_cookie;
 217         } video;
 218
 219         struct {
 220                 void  __iomem *vbase;
 221                 u32           pbase;
 222                 u32           len;
 223         } mmio;
 224
 225         volatile u32  __iomem *bci_base;
 226         unsigned int  bci_ptr;
 227         u32           cob_offset;
 228         u32           cob_size;
 229         int           cob_index;
 230
 231         void (*SavageWaitIdle) (struct savagefb_par *par);
 232         void (*SavageWaitFifo) (struct savagefb_par *par, int space);
 233
 234         int HorizScaleFactor;
 235
 236         /* Panels size */
 237         int SavagePanelWidth;
 238         int SavagePanelHeight;
 239
 240         struct {
 241                 u16 red, green, blue, transp;
 242         } palette[NR_PALETTE];
 243
 244         int depth;
 245         int vwidth;
 246 };
 247
 248 #define BCI_BD_BW_DISABLE            0x10000000
 249 #define BCI_BD_SET_BPP(bd, bpp)      ((bd) |= (((bpp) & 0xFF) << 16))
 250 #define BCI_BD_SET_STRIDE(bd, st)    ((bd) |= ((st) & 0xFFFF))
 251
 252
 253 /* IO functions */
 254 static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
 255 {
 256         return readb(par->mmio.vbase + addr);
 257 }
 258
 259 static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
 260 {
 261         return readw(par->mmio.vbase + addr);
 262 }
 263
 264 static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
 265 {
 266         return readl(par->mmio.vbase + addr);
 267 }
 268
 269 static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
 270 {
 271         writeb(val, par->mmio.vbase + addr);
 272 }
 273
 274 static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
 275 {
 276         writew(val, par->mmio.vbase + addr);
 277 }
 278
 279 static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
 280 {
 281         writel(val, par->mmio.vbase + addr);
 282 }
 283
 284 static inline u8 vga_in8(int addr, struct savagefb_par *par)
 285 {
 286         return savage_in8(0x8000 + addr, par);
 287 }
 288
 289 static inline u16 vga_in16(int addr, struct savagefb_par *par)
 290 {
 291         return savage_in16(0x8000 + addr, par);
 292 }
 293
 294 static inline u8 vga_in32(int addr, struct savagefb_par *par)
 295 {
 296         return savage_in32(0x8000 + addr, par);
 297 }
 298
 299 static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
 300 {
 301         savage_out8(0x8000 + addr, val, par);
 302 }
 303
 304 static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
 305 {
 306         savage_out16(0x8000 + addr, val, par);
 307 }
 308
 309 static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
 310 {
 311         savage_out32(0x8000 + addr, val, par);
 312 }
 313
 314 static inline u8 VGArCR (u8 index, struct savagefb_par *par)
 315 {
 316         vga_out8(0x3d4, index,  par);
 317         return vga_in8(0x3d5, par);
 318 }
 319
 320 static inline u8 VGArGR (u8 index, struct savagefb_par *par)
 321 {
 322         vga_out8(0x3ce, index, par);
 323         return vga_in8(0x3cf, par);
 324 }
 325
 326 static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
 327 {
 328         vga_out8(0x3c4, index, par);
 329         return vga_in8(0x3c5, par);
 330 }
 331
 332 static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
 333 {
 334         vga_out8(0x3d4, index, par);
 335         vga_out8(0x3d5, val, par);
 336 }
 337
 338 static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
 339 {
 340         vga_out8(0x3ce, index, par);
 341         vga_out8(0x3cf, val, par);
 342 }
 343
 344 static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
 345 {
 346         vga_out8(0x3c4, index, par);
 347         vga_out8 (0x3c5, val, par);
 348 }
 349
 350 static inline void VGAenablePalette(struct savagefb_par *par)
 351 {
 352         vga_in8(0x3da, par);
 353         vga_out8(0x3c0, 0x00, par);
 354         par->paletteEnabled = 1;
 355 }
 356
 357 static inline void VGAdisablePalette(struct savagefb_par *par)
 358 {
 359         vga_in8(0x3da, par);
 360         vga_out8(0x3c0, 0x20, par);
 361         par->paletteEnabled = 0;
 362 }
 363
 364 static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
 365 {
 366         if (par->paletteEnabled)
 367                 index &= ~0x20;
 368         else
 369                 index |= 0x20;
 370
 371         vga_in8(0x3da, par);
 372         vga_out8(0x3c0, index, par);
 373         vga_out8 (0x3c0, value, par);
 374 }
 375
 376 static inline void VGAwMISC(u8 value, struct savagefb_par *par)
 377 {
 378         vga_out8(0x3c2, value, par);
 379 }
 380
 381 #ifndef CONFIG_FB_SAVAGE_ACCEL
 382 #define savagefb_set_clip(x)
 383 #endif
 384
 385 static inline void VerticalRetraceWait(struct savagefb_par *par)
 386 {
 387         vga_out8(0x3d4, 0x17, par);
 388         if (vga_in8(0x3d5, par) & 0x80) {
 389                 while ((vga_in8(0x3da, par) & 0x08) == 0x08);
 390                 while ((vga_in8(0x3da, par) & 0x08) == 0x00);
 391         }
 392 }
 393
 394 extern int savagefb_probe_i2c_connector(struct fb_info *info,
 395                                         u8 **out_edid);
 396 extern void savagefb_create_i2c_busses(struct fb_info *info);
 397 extern void savagefb_delete_i2c_busses(struct fb_info *info);
 398 extern int  savagefb_sync(struct fb_info *info);
 399 extern void savagefb_copyarea(struct fb_info *info,
 400                               const struct fb_copyarea *region);
 401 extern void savagefb_fillrect(struct fb_info *info,
 402                               const struct fb_fillrect *rect);
 403 extern void savagefb_imageblit(struct fb_info *info,
 404                                const struct fb_image *image);
 405
 406
 407 #endif /* __SAVAGEFB_H__ */