sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / video / fbdev / valkyriefb.h
blobd787441e5a42a489c9075900f846afd37597716a
1 /*
2 * valkyriefb.h: Constants of all sorts for valkyriefb
4 * Created 8 August 1998 by
5 * Martin Costabel <costabel@wanadoo.fr> and Kevin Schoedel
7 * Vmode-switching changes and vmode 15/17 modifications created 29 August
8 * 1998 by Barry K. Nathan <barryn@pobox.com>.
9 *
10 * vmode 10 changed by Steven Borley <sjb@salix.demon.co.uk>, 14 mai 2000
12 * Ported to 68k Macintosh by David Huggins-Daines <dhd@debian.org>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
19 * Based directly on:
21 * controlfb.h: Constants of all sorts for controlfb
22 * Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
24 * pmc-valkyrie.h: Console support for PowerMac "control" display adaptor.
25 * Copyright (C) 1997 Paul Mackerras.
27 * pmc-valkyrie.c: Console support for PowerMac "control" display adaptor.
28 * Copyright (C) 1997 Paul Mackerras.
30 * and indirectly from:
32 * pmc-control.h: Console support for PowerMac "control" display adaptor.
33 * Copyright (C) 1997 Paul Mackerras.
35 * pmc-control.c: Console support for PowerMac "control" display adaptor.
36 * Copyright (C) 1996 Paul Mackerras.
38 * platinumfb.c: Console support for PowerMac "platinum" display adaptor.
39 * Copyright (C) 1998 Jon Howell
42 #ifdef CONFIG_MAC
43 /* Valkyrie registers are word-aligned on m68k */
44 #define VALKYRIE_REG_PADSIZE 3
45 #else
46 #define VALKYRIE_REG_PADSIZE 7
47 #endif
50 * Structure of the registers for the Valkyrie colormap registers.
52 struct cmap_regs {
53 unsigned char addr;
54 char pad1[VALKYRIE_REG_PADSIZE];
55 unsigned char lut;
59 * Structure of the registers for the "valkyrie" display adaptor.
62 struct vpreg { /* padded register */
63 unsigned char r;
64 char pad[VALKYRIE_REG_PADSIZE];
68 struct valkyrie_regs {
69 struct vpreg mode;
70 struct vpreg depth;
71 struct vpreg status;
72 struct vpreg reg3;
73 struct vpreg intr;
74 struct vpreg reg5;
75 struct vpreg intr_enb;
76 struct vpreg msense;
80 * Register initialization tables for the valkyrie display.
82 * Dot clock rate is
83 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
85 struct valkyrie_regvals {
86 unsigned char mode;
87 unsigned char clock_params[3];
88 int pitch[2]; /* bytes/line, indexed by color_mode */
89 int hres;
90 int vres;
93 #ifndef CONFIG_MAC
94 /* Register values for 1024x768, 75Hz mode (17) */
95 /* I'm not sure which mode this is (16 or 17), so I'm defining it as 17,
96 * since the equivalent mode in controlfb (which I adapted this from) is
97 * also 17. Just because MacOS can't do this on Valkyrie doesn't mean we
98 * can't! :)
100 * I was going to use 12, 31, 3, which I found by myself, but instead I'm
101 * using 11, 28, 3 like controlfb, for consistency's sake.
104 static struct valkyrie_regvals valkyrie_reg_init_17 = {
105 15,
106 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
107 { 1024, 0 },
108 1024, 768
111 /* Register values for 1024x768, 72Hz mode (15) */
112 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
113 * that didn't match MacOS in the same video mode on this chip, and it also
114 * caused the 15" Apple Studio Display to not work in this mode. While this
115 * mode still doesn't match MacOS exactly (as far as I can tell), it's a lot
116 * closer now, and it works with the Apple Studio Display.
118 * Yes, even though MacOS calls it "72Hz", in reality it's about 70Hz.
120 static struct valkyrie_regvals valkyrie_reg_init_15 = {
122 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
123 /* I interpolated the V=69.71 from the vmode 14 and old 15
124 * numbers. Is this result correct?
126 { 1024, 0 },
127 1024, 768
130 /* Register values for 1024x768, 60Hz mode (14) */
131 static struct valkyrie_regvals valkyrie_reg_init_14 = {
133 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
134 { 1024, 0 },
135 1024, 768
137 #endif /* !defined CONFIG_MAC */
139 /* Register values for 832x624, 75Hz mode (13) */
140 static struct valkyrie_regvals valkyrie_reg_init_13 = {
142 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
143 { 832, 0 },
144 832, 624
147 /* Register values for 800x600, 72Hz mode (11) */
148 static struct valkyrie_regvals valkyrie_reg_init_11 = {
150 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
151 { 800, 0 },
152 800, 600
155 /* Register values for 800x600, 60Hz mode (10) */
156 static struct valkyrie_regvals valkyrie_reg_init_10 = {
158 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
159 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
160 { 800, 1600 },
161 800, 600
164 /* Register values for 640x480, 67Hz mode (6) */
165 static struct valkyrie_regvals valkyrie_reg_init_6 = {
167 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
168 { 640, 1280 },
169 640, 480
172 /* Register values for 640x480, 60Hz mode (5) */
173 static struct valkyrie_regvals valkyrie_reg_init_5 = {
175 { 23, 37, 2 }, /* pixel clock = 25.14MHz for V=59.85Hz */
176 { 640, 1280 },
177 640, 480
180 static struct valkyrie_regvals *valkyrie_reg_init[VMODE_MAX] = {
181 NULL,
182 NULL,
183 NULL,
184 NULL,
185 &valkyrie_reg_init_5,
186 &valkyrie_reg_init_6,
187 NULL,
188 NULL,
189 NULL,
190 &valkyrie_reg_init_10,
191 &valkyrie_reg_init_11,
192 NULL,
193 &valkyrie_reg_init_13,
194 #ifndef CONFIG_MAC
195 &valkyrie_reg_init_14,
196 &valkyrie_reg_init_15,
197 NULL,
198 &valkyrie_reg_init_17,
199 #endif