| blob | 27b044f84c816f5b4f15efa9782b7c4fbd1a217d |
1 #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
2 #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
4 /*
5 * DICE device interface definitions
6 */
8 /*
9 * Generally, all registers can be read like memory, i.e., with quadlet read or
10 * block read transactions with at least quadlet-aligned offset and length.
11 * Writes are not allowed except where noted; quadlet-sized registers must be
12 * written with a quadlet write transaction.
13 *
14 * All values are in big endian. The DICE firmware runs on a little-endian CPU
15 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
16 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
17 */
19 /*
20 * Streaming is handled by the "DICE driver" interface. Its registers are
21 * located in this private address space.
22 */
23 #define DICE_PRIVATE_SPACE 0xffffe0000000uLL
25 /*
26 * The registers are organized in several sections, which are organized
27 * separately to allow them to be extended individually. Whether a register is
28 * supported can be detected by checking its offset against its section's size.
29 *
30 * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/
31 * size values are measured in quadlets. Read-only.
32 */
33 #define DICE_GLOBAL_OFFSET 0x00
34 #define DICE_GLOBAL_SIZE 0x04
35 #define DICE_TX_OFFSET 0x08
36 #define DICE_TX_SIZE 0x0c
37 #define DICE_RX_OFFSET 0x10
38 #define DICE_RX_SIZE 0x14
39 #define DICE_EXT_SYNC_OFFSET 0x18
40 #define DICE_EXT_SYNC_SIZE 0x1c
41 #define DICE_UNUSED2_OFFSET 0x20
42 #define DICE_UNUSED2_SIZE 0x24
44 /*
45 * Global settings.
46 */
48 /*
49 * Stores the full 64-bit address (node ID and offset in the node's address
50 * space) where the device will send notifications. Must be changed with
51 * a compare/swap transaction by the owner. This register is automatically
52 * cleared on a bus reset.
53 */
54 #define GLOBAL_OWNER 0x000
55 #define OWNER_NO_OWNER 0xffff000000000000uLL
56 #define OWNER_NODE_SHIFT 48
58 /*
59 * A bitmask with asynchronous events; read-only. When any event(s) happen,
60 * the bits of previous events are cleared, and the value of this register is
61 * also written to the address stored in the owner register.
62 */
63 #define GLOBAL_NOTIFICATION 0x008
64 /* Some registers in the Rx/Tx sections may have changed. */
65 #define NOTIFY_RX_CFG_CHG 0x00000001
66 #define NOTIFY_TX_CFG_CHG 0x00000002
67 /* Lock status of the current clock source may have changed. */
68 #define NOTIFY_LOCK_CHG 0x00000010
69 /* Write to the clock select register has been finished. */
70 #define NOTIFY_CLOCK_ACCEPTED 0x00000020
71 /* Lock status of some clock source has changed. */
72 #define NOTIFY_EXT_STATUS 0x00000040
73 /* Other bits may be used for device-specific events. */
75 /*
76 * A name that can be customized for each device; read/write. Padded with zero
77 * bytes. Quadlets are byte-swapped. The encoding is whatever the host driver
78 * happens to be using.
79 */
80 #define GLOBAL_NICK_NAME 0x00c
81 #define NICK_NAME_SIZE 64
83 /*
84 * The current sample rate and clock source; read/write. Whether a clock
85 * source or sample rate is supported is device-specific; the internal clock
86 * source is always available. Low/mid/high = up to 48/96/192 kHz. This
87 * register can be changed even while streams are running.
88 */
89 #define GLOBAL_CLOCK_SELECT 0x04c
90 #define CLOCK_SOURCE_MASK 0x000000ff
91 #define CLOCK_SOURCE_AES1 0x00000000
92 #define CLOCK_SOURCE_AES2 0x00000001
93 #define CLOCK_SOURCE_AES3 0x00000002
94 #define CLOCK_SOURCE_AES4 0x00000003
95 #define CLOCK_SOURCE_AES_ANY 0x00000004
96 #define CLOCK_SOURCE_ADAT 0x00000005
97 #define CLOCK_SOURCE_TDIF 0x00000006
98 #define CLOCK_SOURCE_WC 0x00000007
99 #define CLOCK_SOURCE_ARX1 0x00000008
100 #define CLOCK_SOURCE_ARX2 0x00000009
101 #define CLOCK_SOURCE_ARX3 0x0000000a
102 #define CLOCK_SOURCE_ARX4 0x0000000b
103 #define CLOCK_SOURCE_INTERNAL 0x0000000c
104 #define CLOCK_RATE_MASK 0x0000ff00
105 #define CLOCK_RATE_32000 0x00000000
106 #define CLOCK_RATE_44100 0x00000100
107 #define CLOCK_RATE_48000 0x00000200
108 #define CLOCK_RATE_88200 0x00000300
109 #define CLOCK_RATE_96000 0x00000400
110 #define CLOCK_RATE_176400 0x00000500
111 #define CLOCK_RATE_192000 0x00000600
112 #define CLOCK_RATE_ANY_LOW 0x00000700
113 #define CLOCK_RATE_ANY_MID 0x00000800
114 #define CLOCK_RATE_ANY_HIGH 0x00000900
115 #define CLOCK_RATE_NONE 0x00000a00
116 #define CLOCK_RATE_SHIFT 8
118 /*
119 * Enable streaming; read/write. Writing a non-zero value (re)starts all
120 * streams that have a valid iso channel set; zero stops all streams. The
121 * streams' parameters must be configured before starting. This register is
122 * automatically cleared on a bus reset.
123 */
124 #define GLOBAL_ENABLE 0x050
126 /*
127 * Status of the sample clock; read-only.
128 */
129 #define GLOBAL_STATUS 0x054
130 /* The current clock source is locked. */
131 #define STATUS_SOURCE_LOCKED 0x00000001
132 /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */
133 #define STATUS_NOMINAL_RATE_MASK 0x0000ff00
135 /*
136 * Status of all clock sources; read-only.
137 */
138 #define GLOBAL_EXTENDED_STATUS 0x058
139 /*
140 * The _LOCKED bits always show the current status; any change generates
141 * a notification.
142 */
143 #define EXT_STATUS_AES1_LOCKED 0x00000001
144 #define EXT_STATUS_AES2_LOCKED 0x00000002
145 #define EXT_STATUS_AES3_LOCKED 0x00000004
146 #define EXT_STATUS_AES4_LOCKED 0x00000008
147 #define EXT_STATUS_ADAT_LOCKED 0x00000010
148 #define EXT_STATUS_TDIF_LOCKED 0x00000020
149 #define EXT_STATUS_ARX1_LOCKED 0x00000040
150 #define EXT_STATUS_ARX2_LOCKED 0x00000080
151 #define EXT_STATUS_ARX3_LOCKED 0x00000100
152 #define EXT_STATUS_ARX4_LOCKED 0x00000200
153 #define EXT_STATUS_WC_LOCKED 0x00000400
154 /*
155 * The _SLIP bits do not generate notifications; a set bit indicates that an
156 * error occurred since the last time when this register was read with
157 * a quadlet read transaction.
158 */
159 #define EXT_STATUS_AES1_SLIP 0x00010000
160 #define EXT_STATUS_AES2_SLIP 0x00020000
161 #define EXT_STATUS_AES3_SLIP 0x00040000
162 #define EXT_STATUS_AES4_SLIP 0x00080000
163 #define EXT_STATUS_ADAT_SLIP 0x00100000
164 #define EXT_STATUS_TDIF_SLIP 0x00200000
165 #define EXT_STATUS_ARX1_SLIP 0x00400000
166 #define EXT_STATUS_ARX2_SLIP 0x00800000
167 #define EXT_STATUS_ARX3_SLIP 0x01000000
168 #define EXT_STATUS_ARX4_SLIP 0x02000000
169 #define EXT_STATUS_WC_SLIP 0x04000000
171 /*
172 * The measured rate of the current clock source, in Hz; read-only.
173 */
174 #define GLOBAL_SAMPLE_RATE 0x05c
176 /*
177 * The version of the DICE driver specification that this device conforms to;
178 * read-only.
179 */
180 #define GLOBAL_VERSION 0x060
182 /* Some old firmware versions do not have the following global registers: */
184 /*
185 * Supported sample rates and clock sources; read-only.
186 */
187 #define GLOBAL_CLOCK_CAPABILITIES 0x064
188 #define CLOCK_CAP_RATE_32000 0x00000001
189 #define CLOCK_CAP_RATE_44100 0x00000002
190 #define CLOCK_CAP_RATE_48000 0x00000004
191 #define CLOCK_CAP_RATE_88200 0x00000008
192 #define CLOCK_CAP_RATE_96000 0x00000010
193 #define CLOCK_CAP_RATE_176400 0x00000020
194 #define CLOCK_CAP_RATE_192000 0x00000040
195 #define CLOCK_CAP_SOURCE_AES1 0x00010000
196 #define CLOCK_CAP_SOURCE_AES2 0x00020000
197 #define CLOCK_CAP_SOURCE_AES3 0x00040000
198 #define CLOCK_CAP_SOURCE_AES4 0x00080000
199 #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
200 #define CLOCK_CAP_SOURCE_ADAT 0x00200000
201 #define CLOCK_CAP_SOURCE_TDIF 0x00400000
202 #define CLOCK_CAP_SOURCE_WC 0x00800000
203 #define CLOCK_CAP_SOURCE_ARX1 0x01000000
204 #define CLOCK_CAP_SOURCE_ARX2 0x02000000
205 #define CLOCK_CAP_SOURCE_ARX3 0x04000000
206 #define CLOCK_CAP_SOURCE_ARX4 0x08000000
207 #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
209 /*
210 * Names of all clock sources; read-only. Quadlets are byte-swapped. Names
211 * are separated with one backslash, the list is terminated with two
212 * backslashes. Unused clock sources are included.
213 */
214 #define GLOBAL_CLOCK_SOURCE_NAMES 0x068
215 #define CLOCK_SOURCE_NAMES_SIZE 256
217 /*
218 * Capture stream settings. This section includes the number/size registers
219 * and the registers of all streams.
220 */
222 /*
223 * The number of supported capture streams; read-only.
224 */
225 #define TX_NUMBER 0x000
227 /*
228 * The size of one stream's register block, in quadlets; read-only. The
229 * registers of the first stream follow immediately afterwards; the registers
230 * of the following streams are offset by this register's value.
231 */
232 #define TX_SIZE 0x004
234 /*
235 * The isochronous channel number on which packets are sent, or -1 if the
236 * stream is not to be used; read/write.
237 */
238 #define TX_ISOCHRONOUS 0x008
240 /*
241 * The number of audio channels; read-only. There will be one quadlet per
242 * channel; the first channel is the first quadlet in a data block.
243 */
244 #define TX_NUMBER_AUDIO 0x00c
246 /*
247 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
248 * additional quadlet in each data block, following the audio quadlets.
249 */
250 #define TX_NUMBER_MIDI 0x010
252 /*
253 * The speed at which the packets are sent, SCODE_100-_400; read/write.
254 */
255 #define TX_SPEED 0x014
257 /*
258 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
259 * are separated with one backslash, the list is terminated with two
260 * backslashes.
261 */
262 #define TX_NAMES 0x018
263 #define TX_NAMES_SIZE 256
265 /*
266 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
267 * channel.
268 */
269 #define TX_AC3_CAPABILITIES 0x118
271 /*
272 * Send audio data with IEC60958 label; read/write. Bitmask with one bit per
273 * audio channel. This register can be changed even while the stream is
274 * running.
275 */
276 #define TX_AC3_ENABLE 0x11c
278 /*
279 * Playback stream settings. This section includes the number/size registers
280 * and the registers of all streams.
281 */
283 /*
284 * The number of supported playback streams; read-only.
285 */
286 #define RX_NUMBER 0x000
288 /*
289 * The size of one stream's register block, in quadlets; read-only. The
290 * registers of the first stream follow immediately afterwards; the registers
291 * of the following streams are offset by this register's value.
292 */
293 #define RX_SIZE 0x004
295 /*
296 * The isochronous channel number on which packets are received, or -1 if the
297 * stream is not to be used; read/write.
298 */
299 #define RX_ISOCHRONOUS 0x008
301 /*
302 * Index of first quadlet to be interpreted; read/write. If > 0, that many
303 * quadlets at the beginning of each data block will be ignored, and all the
304 * audio and MIDI quadlets will follow.
305 */
306 #define RX_SEQ_START 0x00c
308 /*
309 * The number of audio channels; read-only. There will be one quadlet per
310 * channel.
311 */
312 #define RX_NUMBER_AUDIO 0x010
314 /*
315 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
316 * additional quadlet in each data block, following the audio quadlets.
317 */
318 #define RX_NUMBER_MIDI 0x014
320 /*
321 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
322 * are separated with one backslash, the list is terminated with two
323 * backslashes.
324 */
325 #define RX_NAMES 0x018
326 #define RX_NAMES_SIZE 256
328 /*
329 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
330 * channel.
331 */
332 #define RX_AC3_CAPABILITIES 0x118
334 /*
335 * Receive audio data with IEC60958 label; read/write. Bitmask with one bit
336 * per audio channel. This register can be changed even while the stream is
337 * running.
338 */
339 #define RX_AC3_ENABLE 0x11c
341 /*
342 * Extended synchronization information.
343 * This section can be read completely with a block read request.
344 */
346 /*
347 * Current clock source; read-only.
348 */
349 #define EXT_SYNC_CLOCK_SOURCE 0x000
351 /*
352 * Clock source is locked (boolean); read-only.
353 */
354 #define EXT_SYNC_LOCKED 0x004
356 /*
357 * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or
358 * _NONE; read-only.
359 */
360 #define EXT_SYNC_RATE 0x008
362 /*
363 * ADAT user data bits; read-only.
364 */
365 #define EXT_SYNC_ADAT_USER_DATA 0x00c
366 /* The data bits, if available. */
367 #define ADAT_USER_DATA_MASK 0x0f
368 /* The data bits are not available. */
369 #define ADAT_USER_DATA_NO_DATA 0x10
371 #endif