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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / codecs / lm49453.c
blob8d413c2677ccad5287d06a41d33c586296056985
1 /*
2 * lm49453.c - LM49453 ALSA Soc Audio driver
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * Initially based on sound/soc/codecs/wm8350.c
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/tlv.h>
28 #include <sound/jack.h>
29 #include <sound/initval.h>
30 #include <asm/div64.h>
31 #include "lm49453.h"
32
33 static const struct reg_default lm49453_reg_defs[] = {
34 { 0, 0x00 },
35 { 1, 0x00 },
36 { 2, 0x00 },
37 { 3, 0x00 },
38 { 4, 0x00 },
39 { 5, 0x00 },
40 { 6, 0x00 },
41 { 7, 0x00 },
42 { 8, 0x00 },
43 { 9, 0x00 },
44 { 10, 0x00 },
45 { 11, 0x00 },
46 { 12, 0x00 },
47 { 13, 0x00 },
48 { 14, 0x00 },
49 { 15, 0x00 },
50 { 16, 0x00 },
51 { 17, 0x00 },
52 { 18, 0x00 },
53 { 19, 0x00 },
54 { 20, 0x00 },
55 { 21, 0x00 },
56 { 22, 0x00 },
57 { 23, 0x00 },
58 { 32, 0x00 },
59 { 33, 0x00 },
60 { 35, 0x00 },
61 { 36, 0x00 },
62 { 37, 0x00 },
63 { 46, 0x00 },
64 { 48, 0x00 },
65 { 49, 0x00 },
66 { 51, 0x00 },
67 { 56, 0x00 },
68 { 58, 0x00 },
69 { 59, 0x00 },
70 { 60, 0x00 },
71 { 61, 0x00 },
72 { 62, 0x00 },
73 { 63, 0x00 },
74 { 64, 0x00 },
75 { 65, 0x00 },
76 { 66, 0x00 },
77 { 67, 0x00 },
78 { 68, 0x00 },
79 { 69, 0x00 },
80 { 70, 0x00 },
81 { 71, 0x00 },
82 { 72, 0x00 },
83 { 73, 0x00 },
84 { 74, 0x00 },
85 { 75, 0x00 },
86 { 76, 0x00 },
87 { 77, 0x00 },
88 { 78, 0x00 },
89 { 79, 0x00 },
90 { 80, 0x00 },
91 { 81, 0x00 },
92 { 82, 0x00 },
93 { 83, 0x00 },
94 { 85, 0x00 },
95 { 85, 0x00 },
96 { 86, 0x00 },
97 { 87, 0x00 },
98 { 88, 0x00 },
99 { 89, 0x00 },
100 { 90, 0x00 },
101 { 91, 0x00 },
102 { 92, 0x00 },
103 { 93, 0x00 },
104 { 94, 0x00 },
105 { 95, 0x00 },
106 { 96, 0x01 },
107 { 97, 0x00 },
108 { 98, 0x00 },
109 { 99, 0x00 },
110 { 100, 0x00 },
111 { 101, 0x00 },
112 { 102, 0x00 },
113 { 103, 0x01 },
114 { 104, 0x01 },
115 { 105, 0x00 },
116 { 106, 0x01 },
117 { 107, 0x00 },
118 { 108, 0x00 },
119 { 109, 0x00 },
120 { 110, 0x00 },
121 { 111, 0x02 },
122 { 112, 0x02 },
123 { 113, 0x00 },
124 { 121, 0x80 },
125 { 122, 0xBB },
126 { 123, 0x80 },
127 { 124, 0xBB },
128 { 128, 0x00 },
129 { 130, 0x00 },
130 { 131, 0x00 },
131 { 132, 0x00 },
132 { 133, 0x0A },
133 { 134, 0x0A },
134 { 135, 0x0A },
135 { 136, 0x0F },
136 { 137, 0x00 },
137 { 138, 0x73 },
138 { 139, 0x33 },
139 { 140, 0x73 },
140 { 141, 0x33 },
141 { 142, 0x73 },
142 { 143, 0x33 },
143 { 144, 0x73 },
144 { 145, 0x33 },
145 { 146, 0x73 },
146 { 147, 0x33 },
147 { 148, 0x73 },
148 { 149, 0x33 },
149 { 150, 0x73 },
150 { 151, 0x33 },
151 { 152, 0x00 },
152 { 153, 0x00 },
153 { 154, 0x00 },
154 { 155, 0x00 },
155 { 176, 0x00 },
156 { 177, 0x00 },
157 { 178, 0x00 },
158 { 179, 0x00 },
159 { 180, 0x00 },
160 { 181, 0x00 },
161 { 182, 0x00 },
162 { 183, 0x00 },
163 { 184, 0x00 },
164 { 185, 0x00 },
165 { 186, 0x00 },
166 { 187, 0x00 },
167 { 188, 0x00 },
168 { 189, 0x00 },
169 { 208, 0x06 },
170 { 209, 0x00 },
171 { 210, 0x08 },
172 { 211, 0x54 },
173 { 212, 0x14 },
174 { 213, 0x0d },
175 { 214, 0x0d },
176 { 215, 0x14 },
177 { 216, 0x60 },
178 { 221, 0x00 },
179 { 222, 0x00 },
180 { 223, 0x00 },
181 { 224, 0x00 },
182 { 248, 0x00 },
183 { 249, 0x00 },
184 { 250, 0x00 },
185 { 255, 0x00 },
186 };
187
188 /* codec private data */
189 struct lm49453_priv {
190 struct regmap *regmap;
191 };
192
193 /* capture path controls */
194
195 static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
196
197 static SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
198 lm49453_mic2mode_text);
199
200 static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
201
202 static SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
203 LM49453_P0_DIGITAL_MIC1_CONFIG_REG, 7,
204 lm49453_dmic_cfg_text);
205
206 static SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
207 LM49453_P0_DIGITAL_MIC2_CONFIG_REG, 7,
208 lm49453_dmic_cfg_text);
209
210 /* MUX Controls */
211 static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
212
213 static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
214
215 static SOC_ENUM_SINGLE_DECL(lm49453_adcl_enum,
216 LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
217 lm49453_adcl_mux_text);
218
219 static SOC_ENUM_SINGLE_DECL(lm49453_adcr_enum,
220 LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
221 lm49453_adcr_mux_text);
222
223 static const struct snd_kcontrol_new lm49453_adcl_mux_control =
224 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
225
226 static const struct snd_kcontrol_new lm49453_adcr_mux_control =
227 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
228
229 static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
230 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
231 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
232 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
233 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
234 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
235 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
236 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
237 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
238 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
239 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
240 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
241 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
242 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
243 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
244 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
245 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
246 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
247 };
248
249 static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
250 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
251 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
252 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
253 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
254 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
255 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
256 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
257 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
258 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
259 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
260 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
261 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
262 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
263 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
264 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
265 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
266 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
267 };
268
269 static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
270 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
271 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
272 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
273 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
274 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
275 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
276 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
277 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
278 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
279 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
280 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
281 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
282 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
283 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
284 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
285 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
286 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
287 };
288
289 static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
290 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
291 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
292 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
293 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
294 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
295 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
296 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
297 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
298 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
299 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
300 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
301 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
302 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
303 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
304 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
305 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
306 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
307 };
308
309 static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
310 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
311 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
312 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
313 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
314 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
315 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
316 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
317 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
318 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
319 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
320 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
321 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
322 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
323 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
324 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
325 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
326 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
327 };
328
329 static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
330 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
331 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
332 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
333 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
334 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
335 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
336 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
337 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
338 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
339 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
340 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
341 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
342 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
343 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
344 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
345 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
346 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
347 };
348
349 static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
350 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
351 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
352 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
353 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
354 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
355 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
356 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
357 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
358 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
359 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
360 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
361 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
362 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
363 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
364 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
365 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
366 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
367 };
368
369 static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
370 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
371 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
372 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
373 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
374 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
375 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
376 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
377 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
378 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
379 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
380 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
381 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
382 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
383 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
384 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
385 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
386 SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
387 };
388
389 static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
390 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
391 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
392 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
393 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
394 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
395 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
396 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
397 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
398 };
399
400 static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
401 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
402 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
403 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
404 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
405 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
406 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
407 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
408 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
409 };
410
411 static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
412 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
413 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
414 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
415 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
416 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
417 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
418 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
419 };
420
421 static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
422 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
423 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
424 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
425 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
426 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
427 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
428 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
429 };
430
431 static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
432 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
433 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
434 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
435 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
436 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
437 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
438 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
439 };
440
441 static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
442 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
443 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
444 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
445 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
446 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
447 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
448 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
449 };
450
451 static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
452 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
453 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
454 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
455 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
456 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
457 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
458 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
459 };
460
461 static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
462 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
463 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
464 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
465 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
466 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
467 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
468 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
469 };
470
471 static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
472 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
473 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
474 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
475 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
476 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
477 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
478 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
479 SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
480 };
481
482 static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
483 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
484 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
485 SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
486 SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
487 SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
488 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
489 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
490 SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
491 };
492
493 /* TLV Declarations */
494 static const DECLARE_TLV_DB_SCALE(adc_dac_tlv, -7650, 150, 1);
495 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 200, 1);
496 static const DECLARE_TLV_DB_SCALE(port_tlv, -1800, 600, 0);
497 static const DECLARE_TLV_DB_SCALE(stn_tlv, -7200, 150, 0);
498
499 static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
500 /* Sidetone supports mono only */
501 SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
502 0, 0x3F, 0, stn_tlv),
503 SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
504 0, 0x3F, 0, stn_tlv),
505 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
506 0, 0x3F, 0, stn_tlv),
507 SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
508 0, 0x3F, 0, stn_tlv),
509 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
510 0, 0x3F, 0, stn_tlv),
511 SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
512 0, 0x3F, 0, stn_tlv),
513 };
514
515 static const struct snd_kcontrol_new lm49453_snd_controls[] = {
516 /* mic1 and mic2 supports mono only */
517 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_MICL_REG, 0, 15, 0, mic_tlv),
518 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_MICR_REG, 0, 15, 0, mic_tlv),
519
520 SOC_SINGLE_TLV("ADCL Volume", LM49453_P0_ADC_LEVELL_REG, 0, 63,
521 0, adc_dac_tlv),
522 SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
523 0, adc_dac_tlv),
524
525 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
526 LM49453_P0_DMIC1_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
527 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
528 LM49453_P0_DMIC2_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
529
530 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
531 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
532 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
533
534 /* Capture path filter enable */
535 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
536 0, 1, 0),
537 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
538 1, 1, 0),
539 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
540 2, 1, 0),
541
542 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
543 LM49453_P0_DAC_HP_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
544 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
545 LM49453_P0_DAC_LO_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
546 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
547 LM49453_P0_DAC_LS_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
548 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
549 LM49453_P0_DAC_HA_LEVELR_REG, 0, 63, 0, adc_dac_tlv),
550
551 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
552 0, 63, 0, adc_dac_tlv),
553
554 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
555 0, 3, 0, port_tlv),
556 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
557 2, 3, 0, port_tlv),
558 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
559 4, 3, 0, port_tlv),
560 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
561 6, 3, 0, port_tlv),
562 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
563 0, 3, 0, port_tlv),
564 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
565 2, 3, 0, port_tlv),
566 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
567 4, 3, 0, port_tlv),
568 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
569 6, 3, 0, port_tlv),
570
571 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
572 0, 3, 0, port_tlv),
573 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
574 2, 3, 0, port_tlv),
575
576 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
577 1, 1, 0),
578 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
579 1, 1, 0),
580 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
581 2, 1, 0),
582 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
583 2, 1, 0)
584
585 };
586
587 /* DAPM widgets */
588 static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
589
590 /* All end points HP,EP, LS, Lineout and Haptic */
591 SND_SOC_DAPM_OUTPUT("HPOUTL"),
592 SND_SOC_DAPM_OUTPUT("HPOUTR"),
593 SND_SOC_DAPM_OUTPUT("EPOUT"),
594 SND_SOC_DAPM_OUTPUT("LSOUTL"),
595 SND_SOC_DAPM_OUTPUT("LSOUTR"),
596 SND_SOC_DAPM_OUTPUT("LOOUTR"),
597 SND_SOC_DAPM_OUTPUT("LOOUTL"),
598 SND_SOC_DAPM_OUTPUT("HAOUTL"),
599 SND_SOC_DAPM_OUTPUT("HAOUTR"),
600
601 SND_SOC_DAPM_INPUT("AMIC1"),
602 SND_SOC_DAPM_INPUT("AMIC2"),
603 SND_SOC_DAPM_INPUT("DMIC1DAT"),
604 SND_SOC_DAPM_INPUT("DMIC2DAT"),
605 SND_SOC_DAPM_INPUT("AUXL"),
606 SND_SOC_DAPM_INPUT("AUXR"),
607
608 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
609 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
610 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
611 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
612 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
613 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
614 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
615 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
616 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
617 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
618
619 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
620 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
621
622 /* playback path driver enables */
623 SND_SOC_DAPM_OUT_DRV("Headset Switch",
624 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
625 SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
626 LM49453_P0_EP_REG, 0, 0, NULL, 0),
627 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
628 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
629 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
630 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
631 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
632 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
633 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
634 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
635
636 /* DAC */
637 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
638 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
639 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
640 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
641 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
642 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
643 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
644 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
645
646
647 SND_SOC_DAPM_PGA("AUXL Input",
648 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
649 SND_SOC_DAPM_PGA("AUXR Input",
650 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
651
652 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
653
654 /* ADC */
655 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
656 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
657 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
658 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
659
660 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
661 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
662
663 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
664 &lm49453_adcl_mux_control),
665 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
666 &lm49453_adcr_mux_control),
667
668 SND_SOC_DAPM_MUX("Mic1 Input",
669 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
670
671 SND_SOC_DAPM_MUX("Mic2 Input",
672 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
673
674 /* AIF */
675 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
676 LM49453_P0_PULL_CONFIG1_REG, 2, 0),
677 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
678 LM49453_P0_PULL_CONFIG1_REG, 6, 0),
679
680 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
681 LM49453_P0_PULL_CONFIG1_REG, 3, 0),
682 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
683 LM49453_P0_PULL_CONFIG1_REG, 7, 0),
684
685 /* Port1 TX controls */
686 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
687 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
688 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
689 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
690 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
691 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
692 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
693 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
694
695 /* Port2 TX controls */
696 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
697 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
698
699 /* Sidetone Mixer */
700 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
701 lm49453_sidetone_mixer_controls,
702 ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
703
704 /* DAC MIXERS */
705 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
706 lm49453_headset_left_mixer,
707 ARRAY_SIZE(lm49453_headset_left_mixer)),
708 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
709 lm49453_headset_right_mixer,
710 ARRAY_SIZE(lm49453_headset_right_mixer)),
711 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
712 lm49453_lineout_left_mixer,
713 ARRAY_SIZE(lm49453_lineout_left_mixer)),
714 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
715 lm49453_lineout_right_mixer,
716 ARRAY_SIZE(lm49453_lineout_right_mixer)),
717 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
718 lm49453_speaker_left_mixer,
719 ARRAY_SIZE(lm49453_speaker_left_mixer)),
720 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
721 lm49453_speaker_right_mixer,
722 ARRAY_SIZE(lm49453_speaker_right_mixer)),
723 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
724 lm49453_haptic_left_mixer,
725 ARRAY_SIZE(lm49453_haptic_left_mixer)),
726 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
727 lm49453_haptic_right_mixer,
728 ARRAY_SIZE(lm49453_haptic_right_mixer)),
729
730 /* Capture Mixer */
731 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
732 lm49453_port1_tx1_mixer,
733 ARRAY_SIZE(lm49453_port1_tx1_mixer)),
734 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
735 lm49453_port1_tx2_mixer,
736 ARRAY_SIZE(lm49453_port1_tx2_mixer)),
737 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
738 lm49453_port1_tx3_mixer,
739 ARRAY_SIZE(lm49453_port1_tx3_mixer)),
740 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
741 lm49453_port1_tx4_mixer,
742 ARRAY_SIZE(lm49453_port1_tx4_mixer)),
743 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
744 lm49453_port1_tx5_mixer,
745 ARRAY_SIZE(lm49453_port1_tx5_mixer)),
746 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
747 lm49453_port1_tx6_mixer,
748 ARRAY_SIZE(lm49453_port1_tx6_mixer)),
749 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
750 lm49453_port1_tx7_mixer,
751 ARRAY_SIZE(lm49453_port1_tx7_mixer)),
752 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
753 lm49453_port1_tx8_mixer,
754 ARRAY_SIZE(lm49453_port1_tx8_mixer)),
755
756 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
757 lm49453_port2_tx1_mixer,
758 ARRAY_SIZE(lm49453_port2_tx1_mixer)),
759 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
760 lm49453_port2_tx2_mixer,
761 ARRAY_SIZE(lm49453_port2_tx2_mixer)),
762 };
763
764 static const struct snd_soc_dapm_route lm49453_audio_map[] = {
765 /* Port SDI mapping */
766 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
767 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
768 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
769 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
770 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
771 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
772 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
773 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
774
775 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
776 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
777
778 /* HP mapping */
779 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
780 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
781 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
782 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
783 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
784 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
785 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
786 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
787
788 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
789 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
790
791 { "HPL Mixer", "ADCL Switch", "ADC Left" },
792 { "HPL Mixer", "ADCR Switch", "ADC Right" },
793 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
794 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
795 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
796 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
797 { "HPL Mixer", "Sidetone Switch", "Sidetone" },
798
799 { "HPL DAC", NULL, "HPL Mixer" },
800
801 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
802 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
803 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
804 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
805 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
806 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
807 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
808 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
809
810 /* Port 2 */
811 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
812 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
813
814 { "HPR Mixer", "ADCL Switch", "ADC Left" },
815 { "HPR Mixer", "ADCR Switch", "ADC Right" },
816 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
817 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
818 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
819 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
820 { "HPR Mixer", "Sidetone Switch", "Sidetone" },
821
822 { "HPR DAC", NULL, "HPR Mixer" },
823
824 { "HPOUTL", "Headset Switch", "HPL DAC"},
825 { "HPOUTR", "Headset Switch", "HPR DAC"},
826
827 /* EP map */
828 { "EPOUT", "Earpiece Switch", "HPL DAC" },
829
830 /* Speaker map */
831 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
832 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
833 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
834 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
835 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
836 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
837 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
838 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
839
840 /* Port 2 */
841 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
842 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
843
844 { "LSL Mixer", "ADCL Switch", "ADC Left" },
845 { "LSL Mixer", "ADCR Switch", "ADC Right" },
846 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
847 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
848 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
849 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
850 { "LSL Mixer", "Sidetone Switch", "Sidetone" },
851
852 { "LSL DAC", NULL, "LSL Mixer" },
853
854 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
855 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
856 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
857 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
858 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
859 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
860 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
861 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
862
863 /* Port 2 */
864 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
865 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
866
867 { "LSR Mixer", "ADCL Switch", "ADC Left" },
868 { "LSR Mixer", "ADCR Switch", "ADC Right" },
869 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
870 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
871 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
872 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
873 { "LSR Mixer", "Sidetone Switch", "Sidetone" },
874
875 { "LSR DAC", NULL, "LSR Mixer" },
876
877 { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
878 { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
879
880 /* Haptic map */
881 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
882 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
883 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
884 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
885 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
886 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
887 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
888 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
889
890 /* Port 2 */
891 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
892 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
893
894 { "HAL Mixer", "ADCL Switch", "ADC Left" },
895 { "HAL Mixer", "ADCR Switch", "ADC Right" },
896 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
897 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
898 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
899 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
900 { "HAL Mixer", "Sidetone Switch", "Sidetone" },
901
902 { "HAL DAC", NULL, "HAL Mixer" },
903
904 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
905 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
906 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
907 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
908 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
909 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
910 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
911 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
912
913 /* Port 2 */
914 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
915 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
916
917 { "HAR Mixer", "ADCL Switch", "ADC Left" },
918 { "HAR Mixer", "ADCR Switch", "ADC Right" },
919 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
920 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
921 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
922 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
923 { "HAR Mixer", "Sideton Switch", "Sidetone" },
924
925 { "HAR DAC", NULL, "HAR Mixer" },
926
927 { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
928 { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
929
930 /* Lineout map */
931 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
932 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
933 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
934 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
935 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
936 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
937 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
938 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
939
940 /* Port 2 */
941 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
942 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
943
944 { "LOL Mixer", "ADCL Switch", "ADC Left" },
945 { "LOL Mixer", "ADCR Switch", "ADC Right" },
946 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
947 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
948 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
949 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
950 { "LOL Mixer", "Sidetone Switch", "Sidetone" },
951
952 { "LOL DAC", NULL, "LOL Mixer" },
953
954 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
955 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
956 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
957 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
958 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
959 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
960 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
961 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
962
963 /* Port 2 */
964 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
965 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
966
967 { "LOR Mixer", "ADCL Switch", "ADC Left" },
968 { "LOR Mixer", "ADCR Switch", "ADC Right" },
969 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
970 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
971 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
972 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
973 { "LOR Mixer", "Sidetone Switch", "Sidetone" },
974
975 { "LOR DAC", NULL, "LOR Mixer" },
976
977 { "LOOUTL", NULL, "LOL DAC" },
978 { "LOOUTR", NULL, "LOR DAC" },
979
980 /* TX map */
981 /* Port1 mappings */
982 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
983 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
984 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
985 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
986 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
987 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
988
989 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
990 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
991 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
992 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
993 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
994 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
995
996 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
997 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
998 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
999 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1000 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1001 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1002
1003 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1004 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1005 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1006 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1007 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1008 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1009
1010 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1011 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1012 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1013 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1014 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1015 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1016
1017 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1018 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1019 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1020 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1021 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1022 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1023
1024 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1025 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1026 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1027 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1028 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1029 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1030
1031 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1032 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1033 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1034 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1035 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1036 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1037
1038 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1039 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1040 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1041 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1042 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1043 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1044
1045 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1046 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1047 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1048 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1049 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1050 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1051
1052 { "P1_1_TX", NULL, "Port1_1 Mixer" },
1053 { "P1_2_TX", NULL, "Port1_2 Mixer" },
1054 { "P1_3_TX", NULL, "Port1_3 Mixer" },
1055 { "P1_4_TX", NULL, "Port1_4 Mixer" },
1056 { "P1_5_TX", NULL, "Port1_5 Mixer" },
1057 { "P1_6_TX", NULL, "Port1_6 Mixer" },
1058 { "P1_7_TX", NULL, "Port1_7 Mixer" },
1059 { "P1_8_TX", NULL, "Port1_8 Mixer" },
1060
1061 { "P2_1_TX", NULL, "Port2_1 Mixer" },
1062 { "P2_2_TX", NULL, "Port2_2 Mixer" },
1063
1064 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1065 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1066 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1067 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1068 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1069 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1070 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1071 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1072
1073 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1074 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1075
1076 { "Mic1 Input", NULL, "AMIC1" },
1077 { "Mic2 Input", NULL, "AMIC2" },
1078
1079 { "AUXL Input", NULL, "AUXL" },
1080 { "AUXR Input", NULL, "AUXR" },
1081
1082 /* AUX connections */
1083 { "ADCL Mux", "Aux_L", "AUXL Input" },
1084 { "ADCL Mux", "MIC1", "Mic1 Input" },
1085
1086 { "ADCR Mux", "Aux_R", "AUXR Input" },
1087 { "ADCR Mux", "MIC2", "Mic2 Input" },
1088
1089 /* ADC connection */
1090 { "ADC Left", NULL, "ADCL Mux"},
1091 { "ADC Right", NULL, "ADCR Mux"},
1092
1093 { "DMIC1 Left", NULL, "DMIC1DAT"},
1094 { "DMIC1 Right", NULL, "DMIC1DAT"},
1095 { "DMIC2 Left", NULL, "DMIC2DAT"},
1096 { "DMIC2 Right", NULL, "DMIC2DAT"},
1097
1098 /* Sidetone map */
1099 { "Sidetone Mixer", NULL, "ADC Left" },
1100 { "Sidetone Mixer", NULL, "ADC Right" },
1101 { "Sidetone Mixer", NULL, "DMIC1 Left" },
1102 { "Sidetone Mixer", NULL, "DMIC1 Right" },
1103 { "Sidetone Mixer", NULL, "DMIC2 Left" },
1104 { "Sidetone Mixer", NULL, "DMIC2 Right" },
1105
1106 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1107 };
1108
1109 static int lm49453_hw_params(struct snd_pcm_substream *substream,
1110 struct snd_pcm_hw_params *params,
1111 struct snd_soc_dai *dai)
1112 {
1113 struct snd_soc_codec *codec = dai->codec;
1114 u16 clk_div = 0;
1115
1116 /* Setting DAC clock dividers based on substream sample rate. */
1117 switch (params_rate(params)) {
1118 case 8000:
1119 case 16000:
1120 case 32000:
1121 case 24000:
1122 case 48000:
1123 clk_div = 256;
1124 break;
1125 case 11025:
1126 case 22050:
1127 case 44100:
1128 clk_div = 216;
1129 break;
1130 case 96000:
1131 clk_div = 127;
1132 break;
1133 default:
1134 return -EINVAL;
1135 }
1136
1137 snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1138 snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1139
1140 return 0;
1141 }
1142
1143 static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1144 {
1145 struct snd_soc_codec *codec = codec_dai->codec;
1146
1147 u16 aif_val;
1148 int mode = 0;
1149 int clk_phase = 0;
1150 int clk_shift = 0;
1151
1152 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1153 case SND_SOC_DAIFMT_CBS_CFS:
1154 aif_val = 0;
1155 break;
1156 case SND_SOC_DAIFMT_CBS_CFM:
1157 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1158 break;
1159 case SND_SOC_DAIFMT_CBM_CFS:
1160 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
1161 break;
1162 case SND_SOC_DAIFMT_CBM_CFM:
1163 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1164 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170
1171 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1172 case SND_SOC_DAIFMT_I2S:
1173 break;
1174 case SND_SOC_DAIFMT_DSP_A:
1175 mode = 1;
1176 clk_phase = (1 << 5);
1177 clk_shift = 1;
1178 break;
1179 case SND_SOC_DAIFMT_DSP_B:
1180 mode = 1;
1181 clk_phase = (1 << 5);
1182 clk_shift = 0;
1183 break;
1184 default:
1185 return -EINVAL;
1186 }
1187
1188 snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1189 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(0)|BIT(5),
1190 (aif_val | mode | clk_phase));
1191
1192 snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1193
1194 return 0;
1195 }
1196
1197 static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1198 unsigned int freq, int dir)
1199 {
1200 struct snd_soc_codec *codec = dai->codec;
1201 u16 pll_clk = 0;
1202
1203 switch (freq) {
1204 case 12288000:
1205 case 26000000:
1206 case 19200000:
1207 /* pll clk slection */
1208 pll_clk = 0;
1209 break;
1210 case 48000:
1211 case 32576:
1212 /* fll clk slection */
1213 pll_clk = BIT(4);
1214 return 0;
1215 default:
1216 return -EINVAL;
1217 }
1218
1219 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1220
1221 return 0;
1222 }
1223
1224 static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1225 {
1226 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1227 (mute ? (BIT(1)|BIT(0)) : 0));
1228 return 0;
1229 }
1230
1231 static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1232 {
1233 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1234 (mute ? (BIT(3)|BIT(2)) : 0));
1235 return 0;
1236 }
1237
1238 static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1239 {
1240 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1241 (mute ? (BIT(5)|BIT(4)) : 0));
1242 return 0;
1243 }
1244
1245 static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1246 {
1247 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1248 (mute ? BIT(4) : 0));
1249 return 0;
1250 }
1251
1252 static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1253 {
1254 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1255 (mute ? (BIT(7)|BIT(6)) : 0));
1256 return 0;
1257 }
1258
1259 static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1260 enum snd_soc_bias_level level)
1261 {
1262 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1263
1264 switch (level) {
1265 case SND_SOC_BIAS_ON:
1266 case SND_SOC_BIAS_PREPARE:
1267 break;
1268
1269 case SND_SOC_BIAS_STANDBY:
1270 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
1271 regcache_sync(lm49453->regmap);
1272
1273 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1274 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1275 break;
1276
1277 case SND_SOC_BIAS_OFF:
1278 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1279 LM49453_PMC_SETUP_CHIP_EN, 0);
1280 break;
1281 }
1282
1283 return 0;
1284 }
1285
1286 /* Formates supported by LM49453 driver. */
1287 #define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1288 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1289
1290 static const struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1291 .hw_params = lm49453_hw_params,
1292 .set_sysclk = lm49453_set_dai_sysclk,
1293 .set_fmt = lm49453_set_dai_fmt,
1294 .digital_mute = lm49453_hp_mute,
1295 };
1296
1297 static const struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1298 .hw_params = lm49453_hw_params,
1299 .set_sysclk = lm49453_set_dai_sysclk,
1300 .set_fmt = lm49453_set_dai_fmt,
1301 .digital_mute = lm49453_ls_mute,
1302 };
1303
1304 static const struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1305 .hw_params = lm49453_hw_params,
1306 .set_sysclk = lm49453_set_dai_sysclk,
1307 .set_fmt = lm49453_set_dai_fmt,
1308 .digital_mute = lm49453_ha_mute,
1309 };
1310
1311 static const struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1312 .hw_params = lm49453_hw_params,
1313 .set_sysclk = lm49453_set_dai_sysclk,
1314 .set_fmt = lm49453_set_dai_fmt,
1315 .digital_mute = lm49453_ep_mute,
1316 };
1317
1318 static const struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1319 .hw_params = lm49453_hw_params,
1320 .set_sysclk = lm49453_set_dai_sysclk,
1321 .set_fmt = lm49453_set_dai_fmt,
1322 .digital_mute = lm49453_lo_mute,
1323 };
1324
1325 /* LM49453 dai structure. */
1326 static struct snd_soc_dai_driver lm49453_dai[] = {
1327 {
1328 .name = "LM49453 Headset",
1329 .playback = {
1330 .stream_name = "Headset",
1331 .channels_min = 2,
1332 .channels_max = 2,
1333 .rates = SNDRV_PCM_RATE_8000_192000,
1334 .formats = LM49453_FORMATS,
1335 },
1336 .capture = {
1337 .stream_name = "Capture",
1338 .channels_min = 1,
1339 .channels_max = 5,
1340 .rates = SNDRV_PCM_RATE_8000_192000,
1341 .formats = LM49453_FORMATS,
1342 },
1343 .ops = &lm49453_headset_dai_ops,
1344 .symmetric_rates = 1,
1345 },
1346 {
1347 .name = "LM49453 Speaker",
1348 .playback = {
1349 .stream_name = "Speaker",
1350 .channels_min = 2,
1351 .channels_max = 2,
1352 .rates = SNDRV_PCM_RATE_8000_192000,
1353 .formats = LM49453_FORMATS,
1354 },
1355 .ops = &lm49453_speaker_dai_ops,
1356 },
1357 {
1358 .name = "LM49453 Haptic",
1359 .playback = {
1360 .stream_name = "Haptic",
1361 .channels_min = 2,
1362 .channels_max = 2,
1363 .rates = SNDRV_PCM_RATE_8000_192000,
1364 .formats = LM49453_FORMATS,
1365 },
1366 .ops = &lm49453_haptic_dai_ops,
1367 },
1368 {
1369 .name = "LM49453 Earpiece",
1370 .playback = {
1371 .stream_name = "Earpiece",
1372 .channels_min = 1,
1373 .channels_max = 1,
1374 .rates = SNDRV_PCM_RATE_8000_192000,
1375 .formats = LM49453_FORMATS,
1376 },
1377 .ops = &lm49453_ep_dai_ops,
1378 },
1379 {
1380 .name = "LM49453 line out",
1381 .playback = {
1382 .stream_name = "Lineout",
1383 .channels_min = 2,
1384 .channels_max = 2,
1385 .rates = SNDRV_PCM_RATE_8000_192000,
1386 .formats = LM49453_FORMATS,
1387 },
1388 .ops = &lm49453_lineout_dai_ops,
1389 },
1390 };
1391
1392 static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1393 .set_bias_level = lm49453_set_bias_level,
1394 .component_driver = {
1395 .controls = lm49453_snd_controls,
1396 .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1397 .dapm_widgets = lm49453_dapm_widgets,
1398 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1399 .dapm_routes = lm49453_audio_map,
1400 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1401 },
1402 .idle_bias_off = true,
1403 };
1404
1405 static const struct regmap_config lm49453_regmap_config = {
1406 .reg_bits = 8,
1407 .val_bits = 8,
1408
1409 .max_register = LM49453_MAX_REGISTER,
1410 .reg_defaults = lm49453_reg_defs,
1411 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1412 .cache_type = REGCACHE_RBTREE,
1413 };
1414
1415 static int lm49453_i2c_probe(struct i2c_client *i2c,
1416 const struct i2c_device_id *id)
1417 {
1418 struct lm49453_priv *lm49453;
1419 int ret = 0;
1420
1421 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1422 GFP_KERNEL);
1423
1424 if (lm49453 == NULL)
1425 return -ENOMEM;
1426
1427 i2c_set_clientdata(i2c, lm49453);
1428
1429 lm49453->regmap = devm_regmap_init_i2c(i2c, &lm49453_regmap_config);
1430 if (IS_ERR(lm49453->regmap)) {
1431 ret = PTR_ERR(lm49453->regmap);
1432 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1433 ret);
1434 return ret;
1435 }
1436
1437 ret = snd_soc_register_codec(&i2c->dev,
1438 &soc_codec_dev_lm49453,
1439 lm49453_dai, ARRAY_SIZE(lm49453_dai));
1440 if (ret < 0)
1441 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1442
1443 return ret;
1444 }
1445
1446 static int lm49453_i2c_remove(struct i2c_client *client)
1447 {
1448 snd_soc_unregister_codec(&client->dev);
1449 return 0;
1450 }
1451
1452 static const struct i2c_device_id lm49453_i2c_id[] = {
1453 { "lm49453", 0 },
1454 { }
1455 };
1456 MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1457
1458 static struct i2c_driver lm49453_i2c_driver = {
1459 .driver = {
1460 .name = "lm49453",
1461 },
1462 .probe = lm49453_i2c_probe,
1463 .remove = lm49453_i2c_remove,
1464 .id_table = lm49453_i2c_id,
1465 };
1466
1467 module_i2c_driver(lm49453_i2c_driver);
1468
1469 MODULE_DESCRIPTION("ASoC LM49453 driver");
1470 MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
1471 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support