sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic23.h
blob3a7235a04a8966ea28a6cf31983ac2af892f5e17
1 /*
2 * ALSA SoC TLV320AIC23 codec driver
4 * Author: Arun KS, <arunks@mistralsolutions.com>
5 * Copyright: (C) 2008 Mistral Solutions Pvt Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef _TLV320AIC23_H
13 #define _TLV320AIC23_H
15 struct device;
16 struct regmap_config;
18 extern const struct regmap_config tlv320aic23_regmap;
19 int tlv320aic23_probe(struct device *dev, struct regmap *regmap);
21 /* Codec TLV320AIC23 */
22 #define TLV320AIC23_LINVOL 0x00
23 #define TLV320AIC23_RINVOL 0x01
24 #define TLV320AIC23_LCHNVOL 0x02
25 #define TLV320AIC23_RCHNVOL 0x03
26 #define TLV320AIC23_ANLG 0x04
27 #define TLV320AIC23_DIGT 0x05
28 #define TLV320AIC23_PWR 0x06
29 #define TLV320AIC23_DIGT_FMT 0x07
30 #define TLV320AIC23_SRATE 0x08
31 #define TLV320AIC23_ACTIVE 0x09
32 #define TLV320AIC23_RESET 0x0F
34 /* Left (right) line input volume control register */
35 #define TLV320AIC23_LRS_ENABLED 0x0100
36 #define TLV320AIC23_LIM_MUTED 0x0080
37 #define TLV320AIC23_LIV_DEFAULT 0x0017
38 #define TLV320AIC23_LIV_MAX 0x001f
39 #define TLV320AIC23_LIV_MIN 0x0000
41 /* Left (right) channel headphone volume control register */
42 #define TLV320AIC23_LZC_ON 0x0080
43 #define TLV320AIC23_LHV_DEFAULT 0x0079
44 #define TLV320AIC23_LHV_MAX 0x007f
45 #define TLV320AIC23_LHV_MIN 0x0000
47 /* Analog audio path control register */
48 #define TLV320AIC23_STA_REG(x) ((x)<<6)
49 #define TLV320AIC23_STE_ENABLED 0x0020
50 #define TLV320AIC23_DAC_SELECTED 0x0010
51 #define TLV320AIC23_BYPASS_ON 0x0008
52 #define TLV320AIC23_INSEL_MIC 0x0004
53 #define TLV320AIC23_MICM_MUTED 0x0002
54 #define TLV320AIC23_MICB_20DB 0x0001
56 /* Digital audio path control register */
57 #define TLV320AIC23_DACM_MUTE 0x0008
58 #define TLV320AIC23_DEEMP_32K 0x0002
59 #define TLV320AIC23_DEEMP_44K 0x0004
60 #define TLV320AIC23_DEEMP_48K 0x0006
61 #define TLV320AIC23_ADCHP_ON 0x0001
63 /* Power control down register */
64 #define TLV320AIC23_DEVICE_PWR_OFF 0x0080
65 #define TLV320AIC23_CLK_OFF 0x0040
66 #define TLV320AIC23_OSC_OFF 0x0020
67 #define TLV320AIC23_OUT_OFF 0x0010
68 #define TLV320AIC23_DAC_OFF 0x0008
69 #define TLV320AIC23_ADC_OFF 0x0004
70 #define TLV320AIC23_MIC_OFF 0x0002
71 #define TLV320AIC23_LINE_OFF 0x0001
73 /* Digital audio interface register */
74 #define TLV320AIC23_MS_MASTER 0x0040
75 #define TLV320AIC23_LRSWAP_ON 0x0020
76 #define TLV320AIC23_LRP_ON 0x0010
77 #define TLV320AIC23_IWL_16 0x0000
78 #define TLV320AIC23_IWL_20 0x0004
79 #define TLV320AIC23_IWL_24 0x0008
80 #define TLV320AIC23_IWL_32 0x000C
81 #define TLV320AIC23_FOR_I2S 0x0002
82 #define TLV320AIC23_FOR_DSP 0x0003
83 #define TLV320AIC23_FOR_LJUST 0x0001
85 /* Sample rate control register */
86 #define TLV320AIC23_CLKOUT_HALF 0x0080
87 #define TLV320AIC23_CLKIN_HALF 0x0040
88 #define TLV320AIC23_BOSR_384fs 0x0002 /* BOSR_272fs in USB mode */
89 #define TLV320AIC23_USB_CLK_ON 0x0001
90 #define TLV320AIC23_SR_MASK 0xf
91 #define TLV320AIC23_CLKOUT_SHIFT 7
92 #define TLV320AIC23_CLKIN_SHIFT 6
93 #define TLV320AIC23_SR_SHIFT 2
94 #define TLV320AIC23_BOSR_SHIFT 1
96 /* Digital interface register */
97 #define TLV320AIC23_ACT_ON 0x0001
100 * AUDIO related MACROS
103 #define TLV320AIC23_DEFAULT_OUT_VOL 0x70
104 #define TLV320AIC23_DEFAULT_IN_VOLUME 0x10
106 #define TLV320AIC23_OUT_VOL_MIN TLV320AIC23_LHV_MIN
107 #define TLV320AIC23_OUT_VOL_MAX TLV320AIC23_LHV_MAX
108 #define TLV320AIC23_OUT_VO_RANGE (TLV320AIC23_OUT_VOL_MAX - \
109 TLV320AIC23_OUT_VOL_MIN)
110 #define TLV320AIC23_OUT_VOL_MASK TLV320AIC23_OUT_VOL_MAX
112 #define TLV320AIC23_IN_VOL_MIN TLV320AIC23_LIV_MIN
113 #define TLV320AIC23_IN_VOL_MAX TLV320AIC23_LIV_MAX
114 #define TLV320AIC23_IN_VOL_RANGE (TLV320AIC23_IN_VOL_MAX - \
115 TLV320AIC23_IN_VOL_MIN)
116 #define TLV320AIC23_IN_VOL_MASK TLV320AIC23_IN_VOL_MAX
118 #define TLV320AIC23_SIDETONE_MASK 0x1c0
119 #define TLV320AIC23_SIDETONE_0 0x100
120 #define TLV320AIC23_SIDETONE_6 0x000
121 #define TLV320AIC23_SIDETONE_9 0x040
122 #define TLV320AIC23_SIDETONE_12 0x080
123 #define TLV320AIC23_SIDETONE_18 0x0c0
125 #endif /* _TLV320AIC23_H */