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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / codecs / wm8955.c
blob1edc7b1df31de2a845fb1a5e06669a3b09bdd2c4
1 /*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/wm8955.h>
29
30 #include "wm8955.h"
31
32 #define WM8955_NUM_SUPPLIES 4
33 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
34 "DCVDD",
35 "DBVDD",
36 "HPVDD",
37 "AVDD",
38 };
39
40 /* codec private data */
41 struct wm8955_priv {
42 struct regmap *regmap;
43
44 unsigned int mclk_rate;
45
46 int deemph;
47 int fs;
48
49 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
50 };
51
52 static const struct reg_default wm8955_reg_defaults[] = {
53 { 2, 0x0079 }, /* R2 - LOUT1 volume */
54 { 3, 0x0079 }, /* R3 - ROUT1 volume */
55 { 5, 0x0008 }, /* R5 - DAC Control */
56 { 7, 0x000A }, /* R7 - Audio Interface */
57 { 8, 0x0000 }, /* R8 - Sample Rate */
58 { 10, 0x00FF }, /* R10 - Left DAC volume */
59 { 11, 0x00FF }, /* R11 - Right DAC volume */
60 { 12, 0x000F }, /* R12 - Bass control */
61 { 13, 0x000F }, /* R13 - Treble control */
62 { 23, 0x00C1 }, /* R23 - Additional control (1) */
63 { 24, 0x0000 }, /* R24 - Additional control (2) */
64 { 25, 0x0000 }, /* R25 - Power Management (1) */
65 { 26, 0x0000 }, /* R26 - Power Management (2) */
66 { 27, 0x0000 }, /* R27 - Additional Control (3) */
67 { 34, 0x0050 }, /* R34 - Left out Mix (1) */
68 { 35, 0x0050 }, /* R35 - Left out Mix (2) */
69 { 36, 0x0050 }, /* R36 - Right out Mix (1) */
70 { 37, 0x0050 }, /* R37 - Right Out Mix (2) */
71 { 38, 0x0050 }, /* R38 - Mono out Mix (1) */
72 { 39, 0x0050 }, /* R39 - Mono out Mix (2) */
73 { 40, 0x0079 }, /* R40 - LOUT2 volume */
74 { 41, 0x0079 }, /* R41 - ROUT2 volume */
75 { 42, 0x0079 }, /* R42 - MONOOUT volume */
76 { 43, 0x0000 }, /* R43 - Clocking / PLL */
77 { 44, 0x0103 }, /* R44 - PLL Control 1 */
78 { 45, 0x0024 }, /* R45 - PLL Control 2 */
79 { 46, 0x01BA }, /* R46 - PLL Control 3 */
80 { 59, 0x0000 }, /* R59 - PLL Control 4 */
81 };
82
83 static bool wm8955_writeable(struct device *dev, unsigned int reg)
84 {
85 switch (reg) {
86 case WM8955_LOUT1_VOLUME:
87 case WM8955_ROUT1_VOLUME:
88 case WM8955_DAC_CONTROL:
89 case WM8955_AUDIO_INTERFACE:
90 case WM8955_SAMPLE_RATE:
91 case WM8955_LEFT_DAC_VOLUME:
92 case WM8955_RIGHT_DAC_VOLUME:
93 case WM8955_BASS_CONTROL:
94 case WM8955_TREBLE_CONTROL:
95 case WM8955_RESET:
96 case WM8955_ADDITIONAL_CONTROL_1:
97 case WM8955_ADDITIONAL_CONTROL_2:
98 case WM8955_POWER_MANAGEMENT_1:
99 case WM8955_POWER_MANAGEMENT_2:
100 case WM8955_ADDITIONAL_CONTROL_3:
101 case WM8955_LEFT_OUT_MIX_1:
102 case WM8955_LEFT_OUT_MIX_2:
103 case WM8955_RIGHT_OUT_MIX_1:
104 case WM8955_RIGHT_OUT_MIX_2:
105 case WM8955_MONO_OUT_MIX_1:
106 case WM8955_MONO_OUT_MIX_2:
107 case WM8955_LOUT2_VOLUME:
108 case WM8955_ROUT2_VOLUME:
109 case WM8955_MONOOUT_VOLUME:
110 case WM8955_CLOCKING_PLL:
111 case WM8955_PLL_CONTROL_1:
112 case WM8955_PLL_CONTROL_2:
113 case WM8955_PLL_CONTROL_3:
114 case WM8955_PLL_CONTROL_4:
115 return true;
116 default:
117 return false;
118 }
119 }
120
121 static bool wm8955_volatile(struct device *dev, unsigned int reg)
122 {
123 switch (reg) {
124 case WM8955_RESET:
125 return true;
126 default:
127 return false;
128 }
129 }
130
131 static int wm8955_reset(struct snd_soc_codec *codec)
132 {
133 return snd_soc_write(codec, WM8955_RESET, 0);
134 }
135
136 struct pll_factors {
137 int n;
138 int k;
139 int outdiv;
140 };
141
142 /* The size in bits of the FLL divide multiplied by 10
143 * to allow rounding later */
144 #define FIXED_FLL_SIZE ((1 << 22) * 10)
145
146 static int wm8995_pll_factors(struct device *dev,
147 int Fref, int Fout, struct pll_factors *pll)
148 {
149 u64 Kpart;
150 unsigned int K, Ndiv, Nmod, target;
151
152 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
153
154 /* The oscilator should run at should be 90-100MHz, and
155 * there's a divide by 4 plus an optional divide by 2 in the
156 * output path to generate the system clock. The clock table
157 * is sortd so we should always generate a suitable target. */
158 target = Fout * 4;
159 if (target < 90000000) {
160 pll->outdiv = 1;
161 target *= 2;
162 } else {
163 pll->outdiv = 0;
164 }
165
166 WARN_ON(target < 90000000 || target > 100000000);
167
168 dev_dbg(dev, "Fvco=%dHz\n", target);
169
170 /* Now, calculate N.K */
171 Ndiv = target / Fref;
172
173 pll->n = Ndiv;
174 Nmod = target % Fref;
175 dev_dbg(dev, "Nmod=%d\n", Nmod);
176
177 /* Calculate fractional part - scale up so we can round. */
178 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
179
180 do_div(Kpart, Fref);
181
182 K = Kpart & 0xFFFFFFFF;
183
184 if ((K % 10) >= 5)
185 K += 5;
186
187 /* Move down to proper range now rounding is done */
188 pll->k = K / 10;
189
190 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
191
192 return 0;
193 }
194
195 /* Lookup table specifying SRATE (table 25 in datasheet); some of the
196 * output frequencies have been rounded to the standard frequencies
197 * they are intended to match where the error is slight. */
198 static struct {
199 int mclk;
200 int fs;
201 int usb;
202 int sr;
203 } clock_cfgs[] = {
204 { 18432000, 8000, 0, 3, },
205 { 18432000, 12000, 0, 9, },
206 { 18432000, 16000, 0, 11, },
207 { 18432000, 24000, 0, 29, },
208 { 18432000, 32000, 0, 13, },
209 { 18432000, 48000, 0, 1, },
210 { 18432000, 96000, 0, 15, },
211
212 { 16934400, 8018, 0, 19, },
213 { 16934400, 11025, 0, 25, },
214 { 16934400, 22050, 0, 27, },
215 { 16934400, 44100, 0, 17, },
216 { 16934400, 88200, 0, 31, },
217
218 { 12000000, 8000, 1, 2, },
219 { 12000000, 11025, 1, 25, },
220 { 12000000, 12000, 1, 8, },
221 { 12000000, 16000, 1, 10, },
222 { 12000000, 22050, 1, 27, },
223 { 12000000, 24000, 1, 28, },
224 { 12000000, 32000, 1, 12, },
225 { 12000000, 44100, 1, 17, },
226 { 12000000, 48000, 1, 0, },
227 { 12000000, 88200, 1, 31, },
228 { 12000000, 96000, 1, 14, },
229
230 { 12288000, 8000, 0, 2, },
231 { 12288000, 12000, 0, 8, },
232 { 12288000, 16000, 0, 10, },
233 { 12288000, 24000, 0, 28, },
234 { 12288000, 32000, 0, 12, },
235 { 12288000, 48000, 0, 0, },
236 { 12288000, 96000, 0, 14, },
237
238 { 12289600, 8018, 0, 18, },
239 { 12289600, 11025, 0, 24, },
240 { 12289600, 22050, 0, 26, },
241 { 11289600, 44100, 0, 16, },
242 { 11289600, 88200, 0, 31, },
243 };
244
245 static int wm8955_configure_clocking(struct snd_soc_codec *codec)
246 {
247 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
248 int i, ret, val;
249 int clocking = 0;
250 int srate = 0;
251 int sr = -1;
252 struct pll_factors pll;
253
254 /* If we're not running a sample rate currently just pick one */
255 if (wm8955->fs == 0)
256 wm8955->fs = 8000;
257
258 /* Can we generate an exact output? */
259 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
260 if (wm8955->fs != clock_cfgs[i].fs)
261 continue;
262 sr = i;
263
264 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
265 break;
266 }
267
268 /* We should never get here with an unsupported sample rate */
269 if (sr == -1) {
270 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
271 wm8955->fs);
272 WARN_ON(sr == -1);
273 return -EINVAL;
274 }
275
276 if (i == ARRAY_SIZE(clock_cfgs)) {
277 /* If we can't generate the right clock from MCLK then
278 * we should configure the PLL to supply us with an
279 * appropriate clock.
280 */
281 clocking |= WM8955_MCLKSEL;
282
283 /* Use the last divider configuration we saw for the
284 * sample rate. */
285 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
286 clock_cfgs[sr].mclk, &pll);
287 if (ret != 0) {
288 dev_err(codec->dev,
289 "Unable to generate %dHz from %dHz MCLK\n",
290 wm8955->fs, wm8955->mclk_rate);
291 return -EINVAL;
292 }
293
294 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
295 WM8955_N_MASK | WM8955_K_21_18_MASK,
296 (pll.n << WM8955_N_SHIFT) |
297 pll.k >> 18);
298 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
299 WM8955_K_17_9_MASK,
300 (pll.k >> 9) & WM8955_K_17_9_MASK);
301 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_3,
302 WM8955_K_8_0_MASK,
303 pll.k & WM8955_K_8_0_MASK);
304 if (pll.k)
305 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
306 WM8955_KEN, WM8955_KEN);
307 else
308 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
309 WM8955_KEN, 0);
310
311 if (pll.outdiv)
312 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
313 else
314 val = WM8955_PLL_RB;
315
316 /* Now start the PLL running */
317 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
318 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
319 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
320 WM8955_PLLEN, WM8955_PLLEN);
321 }
322
323 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
324
325 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
326 WM8955_USB | WM8955_SR_MASK, srate);
327 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
328 WM8955_MCLKSEL, clocking);
329
330 return 0;
331 }
332
333 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
334 struct snd_kcontrol *kcontrol, int event)
335 {
336 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
337 int ret = 0;
338
339 /* Always disable the clocks - if we're doing reconfiguration this
340 * avoids misclocking.
341 */
342 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
343 WM8955_DIGENB, 0);
344 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
345 WM8955_PLL_RB | WM8955_PLLEN, 0);
346
347 switch (event) {
348 case SND_SOC_DAPM_POST_PMD:
349 break;
350 case SND_SOC_DAPM_PRE_PMU:
351 ret = wm8955_configure_clocking(codec);
352 break;
353 default:
354 ret = -EINVAL;
355 break;
356 }
357
358 return ret;
359 }
360
361 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
362
363 static int wm8955_set_deemph(struct snd_soc_codec *codec)
364 {
365 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
366 int val, i, best;
367
368 /* If we're using deemphasis select the nearest available sample
369 * rate.
370 */
371 if (wm8955->deemph) {
372 best = 1;
373 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
374 if (abs(deemph_settings[i] - wm8955->fs) <
375 abs(deemph_settings[best] - wm8955->fs))
376 best = i;
377 }
378
379 val = best << WM8955_DEEMPH_SHIFT;
380 } else {
381 val = 0;
382 }
383
384 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
385
386 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
387 WM8955_DEEMPH_MASK, val);
388 }
389
390 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
391 struct snd_ctl_elem_value *ucontrol)
392 {
393 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
394 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
395
396 ucontrol->value.integer.value[0] = wm8955->deemph;
397 return 0;
398 }
399
400 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_value *ucontrol)
402 {
403 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
404 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
405 unsigned int deemph = ucontrol->value.integer.value[0];
406
407 if (deemph > 1)
408 return -EINVAL;
409
410 wm8955->deemph = deemph;
411
412 return wm8955_set_deemph(codec);
413 }
414
415 static const char *bass_mode_text[] = {
416 "Linear", "Adaptive",
417 };
418
419 static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text);
420
421 static const char *bass_cutoff_text[] = {
422 "Low", "High"
423 };
424
425 static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6,
426 bass_cutoff_text);
427
428 static const char *treble_cutoff_text[] = {
429 "High", "Low"
430 };
431
432 static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2,
433 treble_cutoff_text);
434
435 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
436 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
437 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
438 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
439 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
440 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
441
442 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
443 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
444 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
445 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
446 atten_tlv),
447 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
448 wm8955_get_deemph, wm8955_put_deemph),
449
450 SOC_ENUM("Bass Mode", bass_mode),
451 SOC_ENUM("Bass Cutoff", bass_cutoff),
452 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
453
454 SOC_ENUM("Treble Cutoff", treble_cutoff),
455 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
456
457 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
458 bypass_tlv),
459 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
460 bypass_tlv),
461
462 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
463 bypass_tlv),
464 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
465 bypass_tlv),
466
467 /* Not a stereo pair so they line up with the DAPM switches */
468 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
469 mono_tlv),
470 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
471 mono_tlv),
472
473 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
474 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
475 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
476 WM8955_ROUT1_VOLUME, 7, 1, 0),
477
478 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
479 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
480 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
481 WM8955_ROUT2_VOLUME, 7, 1, 0),
482
483 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
484 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
485 };
486
487 static const struct snd_kcontrol_new lmixer[] = {
488 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
489 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
490 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
491 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
492 };
493
494 static const struct snd_kcontrol_new rmixer[] = {
495 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
496 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
497 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
498 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
499 };
500
501 static const struct snd_kcontrol_new mmixer[] = {
502 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
503 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
504 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
505 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
506 };
507
508 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
509 SND_SOC_DAPM_INPUT("MONOIN-"),
510 SND_SOC_DAPM_INPUT("MONOIN+"),
511 SND_SOC_DAPM_INPUT("LINEINR"),
512 SND_SOC_DAPM_INPUT("LINEINL"),
513
514 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
515
516 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
518 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
519
520 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
521 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
522
523 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
524 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
525 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
526 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
527 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
528 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
529
530 /* The names are chosen to make the control names nice */
531 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
532 lmixer, ARRAY_SIZE(lmixer)),
533 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
534 rmixer, ARRAY_SIZE(rmixer)),
535 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
536 mmixer, ARRAY_SIZE(mmixer)),
537
538 SND_SOC_DAPM_OUTPUT("LOUT1"),
539 SND_SOC_DAPM_OUTPUT("ROUT1"),
540 SND_SOC_DAPM_OUTPUT("LOUT2"),
541 SND_SOC_DAPM_OUTPUT("ROUT2"),
542 SND_SOC_DAPM_OUTPUT("MONOOUT"),
543 SND_SOC_DAPM_OUTPUT("OUT3"),
544 };
545
546 static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
547 { "DACL", NULL, "SYSCLK" },
548 { "DACR", NULL, "SYSCLK" },
549
550 { "Mono Input", NULL, "MONOIN-" },
551 { "Mono Input", NULL, "MONOIN+" },
552
553 { "Left", "Playback Switch", "DACL" },
554 { "Left", "Right Playback Switch", "DACR" },
555 { "Left", "Bypass Switch", "LINEINL" },
556 { "Left", "Mono Switch", "Mono Input" },
557
558 { "Right", "Playback Switch", "DACR" },
559 { "Right", "Left Playback Switch", "DACL" },
560 { "Right", "Bypass Switch", "LINEINR" },
561 { "Right", "Mono Switch", "Mono Input" },
562
563 { "Mono", "Left Playback Switch", "DACL" },
564 { "Mono", "Right Playback Switch", "DACR" },
565 { "Mono", "Left Bypass Switch", "LINEINL" },
566 { "Mono", "Right Bypass Switch", "LINEINR" },
567
568 { "LOUT1 PGA", NULL, "Left" },
569 { "LOUT1", NULL, "TSDEN" },
570 { "LOUT1", NULL, "LOUT1 PGA" },
571
572 { "ROUT1 PGA", NULL, "Right" },
573 { "ROUT1", NULL, "TSDEN" },
574 { "ROUT1", NULL, "ROUT1 PGA" },
575
576 { "LOUT2 PGA", NULL, "Left" },
577 { "LOUT2", NULL, "TSDEN" },
578 { "LOUT2", NULL, "LOUT2 PGA" },
579
580 { "ROUT2 PGA", NULL, "Right" },
581 { "ROUT2", NULL, "TSDEN" },
582 { "ROUT2", NULL, "ROUT2 PGA" },
583
584 { "MOUT PGA", NULL, "Mono" },
585 { "MONOOUT", NULL, "MOUT PGA" },
586
587 /* OUT3 not currently implemented */
588 { "OUT3", NULL, "OUT3 PGA" },
589 };
590
591 static int wm8955_hw_params(struct snd_pcm_substream *substream,
592 struct snd_pcm_hw_params *params,
593 struct snd_soc_dai *dai)
594 {
595 struct snd_soc_codec *codec = dai->codec;
596 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
597 int ret;
598 int wl;
599
600 switch (params_width(params)) {
601 case 16:
602 wl = 0;
603 break;
604 case 20:
605 wl = 0x4;
606 break;
607 case 24:
608 wl = 0x8;
609 break;
610 case 32:
611 wl = 0xc;
612 break;
613 default:
614 return -EINVAL;
615 }
616 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
617 WM8955_WL_MASK, wl);
618
619 wm8955->fs = params_rate(params);
620 wm8955_set_deemph(codec);
621
622 /* If the chip is clocked then disable the clocks and force a
623 * reconfiguration, otherwise DAPM will power up the
624 * clocks for us later. */
625 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
626 if (ret < 0)
627 return ret;
628 if (ret & WM8955_DIGENB) {
629 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
630 WM8955_DIGENB, 0);
631 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
632 WM8955_PLL_RB | WM8955_PLLEN, 0);
633
634 wm8955_configure_clocking(codec);
635 }
636
637 return 0;
638 }
639
640
641 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
642 unsigned int freq, int dir)
643 {
644 struct snd_soc_codec *codec = dai->codec;
645 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
646 int div;
647
648 switch (clk_id) {
649 case WM8955_CLK_MCLK:
650 if (freq > 15000000) {
651 priv->mclk_rate = freq /= 2;
652 div = WM8955_MCLKDIV2;
653 } else {
654 priv->mclk_rate = freq;
655 div = 0;
656 }
657
658 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
659 WM8955_MCLKDIV2, div);
660 break;
661
662 default:
663 return -EINVAL;
664 }
665
666 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
667
668 return 0;
669 }
670
671 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
672 {
673 struct snd_soc_codec *codec = dai->codec;
674 u16 aif = 0;
675
676 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
677 case SND_SOC_DAIFMT_CBS_CFS:
678 break;
679 case SND_SOC_DAIFMT_CBM_CFM:
680 aif |= WM8955_MS;
681 break;
682 default:
683 return -EINVAL;
684 }
685
686 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
687 case SND_SOC_DAIFMT_DSP_B:
688 aif |= WM8955_LRP;
689 case SND_SOC_DAIFMT_DSP_A:
690 aif |= 0x3;
691 break;
692 case SND_SOC_DAIFMT_I2S:
693 aif |= 0x2;
694 break;
695 case SND_SOC_DAIFMT_RIGHT_J:
696 break;
697 case SND_SOC_DAIFMT_LEFT_J:
698 aif |= 0x1;
699 break;
700 default:
701 return -EINVAL;
702 }
703
704 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
705 case SND_SOC_DAIFMT_DSP_A:
706 case SND_SOC_DAIFMT_DSP_B:
707 /* frame inversion not valid for DSP modes */
708 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
709 case SND_SOC_DAIFMT_NB_NF:
710 break;
711 case SND_SOC_DAIFMT_IB_NF:
712 aif |= WM8955_BCLKINV;
713 break;
714 default:
715 return -EINVAL;
716 }
717 break;
718
719 case SND_SOC_DAIFMT_I2S:
720 case SND_SOC_DAIFMT_RIGHT_J:
721 case SND_SOC_DAIFMT_LEFT_J:
722 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
723 case SND_SOC_DAIFMT_NB_NF:
724 break;
725 case SND_SOC_DAIFMT_IB_IF:
726 aif |= WM8955_BCLKINV | WM8955_LRP;
727 break;
728 case SND_SOC_DAIFMT_IB_NF:
729 aif |= WM8955_BCLKINV;
730 break;
731 case SND_SOC_DAIFMT_NB_IF:
732 aif |= WM8955_LRP;
733 break;
734 default:
735 return -EINVAL;
736 }
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
743 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
744 WM8955_LRP, aif);
745
746 return 0;
747 }
748
749
750 static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
751 {
752 struct snd_soc_codec *codec = codec_dai->codec;
753 int val;
754
755 if (mute)
756 val = WM8955_DACMU;
757 else
758 val = 0;
759
760 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
761
762 return 0;
763 }
764
765 static int wm8955_set_bias_level(struct snd_soc_codec *codec,
766 enum snd_soc_bias_level level)
767 {
768 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
769 int ret;
770
771 switch (level) {
772 case SND_SOC_BIAS_ON:
773 break;
774
775 case SND_SOC_BIAS_PREPARE:
776 /* VMID resistance 2*50k */
777 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
778 WM8955_VMIDSEL_MASK,
779 0x1 << WM8955_VMIDSEL_SHIFT);
780
781 /* Default bias current */
782 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
783 WM8955_VSEL_MASK,
784 0x2 << WM8955_VSEL_SHIFT);
785 break;
786
787 case SND_SOC_BIAS_STANDBY:
788 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
789 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
790 wm8955->supplies);
791 if (ret != 0) {
792 dev_err(codec->dev,
793 "Failed to enable supplies: %d\n",
794 ret);
795 return ret;
796 }
797
798 regcache_sync(wm8955->regmap);
799
800 /* Enable VREF and VMID */
801 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
802 WM8955_VREF |
803 WM8955_VMIDSEL_MASK,
804 WM8955_VREF |
805 0x3 << WM8955_VREF_SHIFT);
806
807 /* Let VMID ramp */
808 msleep(500);
809
810 /* High resistance VROI to maintain outputs */
811 snd_soc_update_bits(codec,
812 WM8955_ADDITIONAL_CONTROL_3,
813 WM8955_VROI, WM8955_VROI);
814 }
815
816 /* Maintain VMID with 2*250k */
817 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
818 WM8955_VMIDSEL_MASK,
819 0x2 << WM8955_VMIDSEL_SHIFT);
820
821 /* Minimum bias current */
822 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
823 WM8955_VSEL_MASK, 0);
824 break;
825
826 case SND_SOC_BIAS_OFF:
827 /* Low resistance VROI to help discharge */
828 snd_soc_update_bits(codec,
829 WM8955_ADDITIONAL_CONTROL_3,
830 WM8955_VROI, 0);
831
832 /* Turn off VMID and VREF */
833 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
834 WM8955_VREF |
835 WM8955_VMIDSEL_MASK, 0);
836
837 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
838 wm8955->supplies);
839 break;
840 }
841 return 0;
842 }
843
844 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
845
846 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
847 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
848
849 static const struct snd_soc_dai_ops wm8955_dai_ops = {
850 .set_sysclk = wm8955_set_sysclk,
851 .set_fmt = wm8955_set_fmt,
852 .hw_params = wm8955_hw_params,
853 .digital_mute = wm8955_digital_mute,
854 };
855
856 static struct snd_soc_dai_driver wm8955_dai = {
857 .name = "wm8955-hifi",
858 .playback = {
859 .stream_name = "Playback",
860 .channels_min = 2,
861 .channels_max = 2,
862 .rates = WM8955_RATES,
863 .formats = WM8955_FORMATS,
864 },
865 .ops = &wm8955_dai_ops,
866 };
867
868 static int wm8955_probe(struct snd_soc_codec *codec)
869 {
870 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
871 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
872 int ret, i;
873
874 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
875 wm8955->supplies[i].supply = wm8955_supply_names[i];
876
877 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
878 wm8955->supplies);
879 if (ret != 0) {
880 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
881 return ret;
882 }
883
884 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
885 wm8955->supplies);
886 if (ret != 0) {
887 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
888 return ret;
889 }
890
891 ret = wm8955_reset(codec);
892 if (ret < 0) {
893 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
894 goto err_enable;
895 }
896
897 /* Change some default settings - latch VU and enable ZC */
898 snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
899 WM8955_LDVU, WM8955_LDVU);
900 snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
901 WM8955_RDVU, WM8955_RDVU);
902 snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
903 WM8955_LO1VU | WM8955_LO1ZC,
904 WM8955_LO1VU | WM8955_LO1ZC);
905 snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
906 WM8955_RO1VU | WM8955_RO1ZC,
907 WM8955_RO1VU | WM8955_RO1ZC);
908 snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
909 WM8955_LO2VU | WM8955_LO2ZC,
910 WM8955_LO2VU | WM8955_LO2ZC);
911 snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
912 WM8955_RO2VU | WM8955_RO2ZC,
913 WM8955_RO2VU | WM8955_RO2ZC);
914 snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
915 WM8955_MOZC, WM8955_MOZC);
916
917 /* Also enable adaptive bass boost by default */
918 snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
919
920 /* Set platform data values */
921 if (pdata) {
922 if (pdata->out2_speaker)
923 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_2,
924 WM8955_ROUT2INV, WM8955_ROUT2INV);
925
926 if (pdata->monoin_diff)
927 snd_soc_update_bits(codec, WM8955_MONO_OUT_MIX_1,
928 WM8955_DMEN, WM8955_DMEN);
929 }
930
931 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
932
933 /* Bias level configuration will have done an extra enable */
934 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
935
936 return 0;
937
938 err_enable:
939 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
940 return ret;
941 }
942
943 static const struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
944 .probe = wm8955_probe,
945 .set_bias_level = wm8955_set_bias_level,
946 .suspend_bias_off = true,
947
948 .component_driver = {
949 .controls = wm8955_snd_controls,
950 .num_controls = ARRAY_SIZE(wm8955_snd_controls),
951 .dapm_widgets = wm8955_dapm_widgets,
952 .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets),
953 .dapm_routes = wm8955_dapm_routes,
954 .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes),
955 },
956 };
957
958 static const struct regmap_config wm8955_regmap = {
959 .reg_bits = 7,
960 .val_bits = 9,
961
962 .max_register = WM8955_MAX_REGISTER,
963 .volatile_reg = wm8955_volatile,
964 .writeable_reg = wm8955_writeable,
965
966 .cache_type = REGCACHE_RBTREE,
967 .reg_defaults = wm8955_reg_defaults,
968 .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
969 };
970
971 static int wm8955_i2c_probe(struct i2c_client *i2c,
972 const struct i2c_device_id *id)
973 {
974 struct wm8955_priv *wm8955;
975 int ret;
976
977 wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
978 GFP_KERNEL);
979 if (wm8955 == NULL)
980 return -ENOMEM;
981
982 wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap);
983 if (IS_ERR(wm8955->regmap)) {
984 ret = PTR_ERR(wm8955->regmap);
985 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
986 ret);
987 return ret;
988 }
989
990 i2c_set_clientdata(i2c, wm8955);
991
992 ret = snd_soc_register_codec(&i2c->dev,
993 &soc_codec_dev_wm8955, &wm8955_dai, 1);
994
995 return ret;
996 }
997
998 static int wm8955_i2c_remove(struct i2c_client *client)
999 {
1000 snd_soc_unregister_codec(&client->dev);
1001
1002 return 0;
1003 }
1004
1005 static const struct i2c_device_id wm8955_i2c_id[] = {
1006 { "wm8955", 0 },
1007 { }
1008 };
1009 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1010
1011 static struct i2c_driver wm8955_i2c_driver = {
1012 .driver = {
1013 .name = "wm8955",
1014 },
1015 .probe = wm8955_i2c_probe,
1016 .remove = wm8955_i2c_remove,
1017 .id_table = wm8955_i2c_id,
1018 };
1019
1020 module_i2c_driver(wm8955_i2c_driver);
1021
1022 MODULE_DESCRIPTION("ASoC WM8955 driver");
1023 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1024 MODULE_LICENSE("GPL");
Linux with added FPC-III support