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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / codecs / wm8983.c
blobbfdbe72ee687daf17bbb3bd9fe5cc6f5ab7026af
1 /*
2 * wm8983.c -- WM8983 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28
29 #include "wm8983.h"
30
31 static const struct reg_default wm8983_defaults[] = {
32 { 0x01, 0x0000 }, /* R1 - Power management 1 */
33 { 0x02, 0x0000 }, /* R2 - Power management 2 */
34 { 0x03, 0x0000 }, /* R3 - Power management 3 */
35 { 0x04, 0x0050 }, /* R4 - Audio Interface */
36 { 0x05, 0x0000 }, /* R5 - Companding control */
37 { 0x06, 0x0140 }, /* R6 - Clock Gen control */
38 { 0x07, 0x0000 }, /* R7 - Additional control */
39 { 0x08, 0x0000 }, /* R8 - GPIO Control */
40 { 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */
41 { 0x0A, 0x0000 }, /* R10 - DAC Control */
42 { 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */
43 { 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */
44 { 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */
45 { 0x0E, 0x0100 }, /* R14 - ADC Control */
46 { 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */
47 { 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */
48 { 0x12, 0x012C }, /* R18 - EQ1 - low shelf */
49 { 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */
50 { 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */
51 { 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */
52 { 0x16, 0x002C }, /* R22 - EQ5 - high shelf */
53 { 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */
54 { 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */
55 { 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */
56 { 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */
57 { 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */
58 { 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */
59 { 0x20, 0x0038 }, /* R32 - ALC control 1 */
60 { 0x21, 0x000B }, /* R33 - ALC control 2 */
61 { 0x22, 0x0032 }, /* R34 - ALC control 3 */
62 { 0x23, 0x0000 }, /* R35 - Noise Gate */
63 { 0x24, 0x0008 }, /* R36 - PLL N */
64 { 0x25, 0x000C }, /* R37 - PLL K 1 */
65 { 0x26, 0x0093 }, /* R38 - PLL K 2 */
66 { 0x27, 0x00E9 }, /* R39 - PLL K 3 */
67 { 0x29, 0x0000 }, /* R41 - 3D control */
68 { 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */
69 { 0x2B, 0x0000 }, /* R43 - Beep control */
70 { 0x2C, 0x0033 }, /* R44 - Input ctrl */
71 { 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
72 { 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
73 { 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
74 { 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
75 { 0x31, 0x0002 }, /* R49 - Output ctrl */
76 { 0x32, 0x0001 }, /* R50 - Left mixer ctrl */
77 { 0x33, 0x0001 }, /* R51 - Right mixer ctrl */
78 { 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
79 { 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
80 { 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
81 { 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
82 { 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */
83 { 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
84 { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
85 };
86
87 /* vol/gain update regs */
88 static const int vol_update_regs[] = {
89 WM8983_LEFT_DAC_DIGITAL_VOL,
90 WM8983_RIGHT_DAC_DIGITAL_VOL,
91 WM8983_LEFT_ADC_DIGITAL_VOL,
92 WM8983_RIGHT_ADC_DIGITAL_VOL,
93 WM8983_LOUT1_HP_VOLUME_CTRL,
94 WM8983_ROUT1_HP_VOLUME_CTRL,
95 WM8983_LOUT2_SPK_VOLUME_CTRL,
96 WM8983_ROUT2_SPK_VOLUME_CTRL,
97 WM8983_LEFT_INP_PGA_GAIN_CTRL,
98 WM8983_RIGHT_INP_PGA_GAIN_CTRL
99 };
100
101 struct wm8983_priv {
102 struct regmap *regmap;
103 u32 sysclk;
104 u32 bclk;
105 };
106
107 static const struct {
108 int div;
109 int ratio;
110 } fs_ratios[] = {
111 { 10, 128 },
112 { 15, 192 },
113 { 20, 256 },
114 { 30, 384 },
115 { 40, 512 },
116 { 60, 768 },
117 { 80, 1024 },
118 { 120, 1536 }
119 };
120
121 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
122
123 static const int bclk_divs[] = {
124 1, 2, 4, 8, 16, 32
125 };
126
127 static int eqmode_get(struct snd_kcontrol *kcontrol,
128 struct snd_ctl_elem_value *ucontrol);
129 static int eqmode_put(struct snd_kcontrol *kcontrol,
130 struct snd_ctl_elem_value *ucontrol);
131
132 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
133 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
134 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
135 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
136 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
137 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
138 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
139 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
140 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
141 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
142 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
143 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
144 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
145 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
146
147 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
148 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text);
149
150 static const char *alc_mode_text[] = { "ALC", "Limiter" };
151 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text);
152
153 static const char *filter_mode_text[] = { "Audio", "Application" };
154 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
155 filter_mode_text);
156
157 static const char *eq_bw_text[] = { "Narrow", "Wide" };
158 static const char *eqmode_text[] = { "Capture", "Playback" };
159 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
160
161 static const char *eq1_cutoff_text[] = {
162 "80Hz", "105Hz", "135Hz", "175Hz"
163 };
164 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
165 eq1_cutoff_text);
166 static const char *eq2_cutoff_text[] = {
167 "230Hz", "300Hz", "385Hz", "500Hz"
168 };
169 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
170 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text);
171 static const char *eq3_cutoff_text[] = {
172 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
173 };
174 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
175 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text);
176 static const char *eq4_cutoff_text[] = {
177 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
178 };
179 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
180 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text);
181 static const char *eq5_cutoff_text[] = {
182 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
183 };
184 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
185 eq5_cutoff_text);
186
187 static const char *depth_3d_text[] = {
188 "Off",
189 "6.67%",
190 "13.3%",
191 "20%",
192 "26.7%",
193 "33.3%",
194 "40%",
195 "46.6%",
196 "53.3%",
197 "60%",
198 "66.7%",
199 "73.3%",
200 "80%",
201 "86.7%",
202 "93.3%",
203 "100%"
204 };
205 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
206 depth_3d_text);
207
208 static const struct snd_kcontrol_new wm8983_snd_controls[] = {
209 SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
210 0, 1, 0),
211
212 SOC_ENUM("ALC Capture Function", alc_sel),
213 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
214 3, 7, 0, alc_max_tlv),
215 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
216 0, 7, 0, alc_min_tlv),
217 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
218 0, 15, 0, alc_tar_tlv),
219 SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
220 SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
221 SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
222 SOC_ENUM("ALC Mode", alc_mode),
223 SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
224 3, 1, 0),
225 SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
226 0, 7, 1),
227
228 SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
229 WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
230 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
231 WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
232 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
233 WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
234
235 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
236 WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
237 8, 1, 0, pga_boost_tlv),
238
239 SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
240 SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
241
242 SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
243 WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
244
245 SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
246 SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
247 SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
248 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
249 4, 7, 1, lim_thresh_tlv),
250 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
251 0, 12, 0, lim_boost_tlv),
252 SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
253 SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
254 SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
255
256 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
257 WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
258 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
259 WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
260 SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
261 WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
262
263 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
264 WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
265 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
266 WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
267 SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
268 WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
269
270 SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
271 6, 1, 1),
272
273 SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
274 6, 1, 1),
275
276 SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
277 SOC_ENUM("High Pass Filter Mode", filter_mode),
278 SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
279
280 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
281 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
282 aux_tlv),
283
284 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
285 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
286 bypass_tlv),
287
288 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
289 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
290 SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
291 SOC_ENUM("EQ2 Bandwidth", eq2_bw),
292 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
293 SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
294 SOC_ENUM("EQ3 Bandwidth", eq3_bw),
295 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
296 SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
297 SOC_ENUM("EQ4 Bandwidth", eq4_bw),
298 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
299 SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
300 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
301 SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
302
303 SOC_ENUM("3D Depth", depth_3d),
304 };
305
306 static const struct snd_kcontrol_new left_out_mixer[] = {
307 SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
308 SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
309 SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
310 };
311
312 static const struct snd_kcontrol_new right_out_mixer[] = {
313 SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
314 SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
315 SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
316 };
317
318 static const struct snd_kcontrol_new left_input_mixer[] = {
319 SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
320 SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
321 SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
322 };
323
324 static const struct snd_kcontrol_new right_input_mixer[] = {
325 SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
326 SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
327 SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
328 };
329
330 static const struct snd_kcontrol_new left_boost_mixer[] = {
331 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
332 4, 7, 0, boost_tlv),
333 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
334 0, 7, 0, boost_tlv)
335 };
336
337 static const struct snd_kcontrol_new out3_mixer[] = {
338 SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
339 1, 1, 0),
340 SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
341 0, 1, 0),
342 };
343
344 static const struct snd_kcontrol_new out4_mixer[] = {
345 SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
346 4, 1, 0),
347 SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
348 1, 1, 0),
349 SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
350 3, 1, 0),
351 SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
352 0, 1, 0),
353 };
354
355 static const struct snd_kcontrol_new right_boost_mixer[] = {
356 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
357 4, 7, 0, boost_tlv),
358 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
359 0, 7, 0, boost_tlv)
360 };
361
362 static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
363 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
364 0, 0),
365 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
366 1, 0),
367 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
368 0, 0),
369 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
370 1, 0),
371
372 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
373 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
374 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
375 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
376
377 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
378 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
379 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
380 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
381
382 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
383 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
384 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
385 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
386
387 SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
388 6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
389
390 SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
391 7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
392
393 SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
394 6, 1, NULL, 0),
395 SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
396 6, 1, NULL, 0),
397
398 SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
399 7, 0, NULL, 0),
400 SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
401 8, 0, NULL, 0),
402
403 SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
404 5, 0, NULL, 0),
405 SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
406 6, 0, NULL, 0),
407
408 SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
409 7, 0, NULL, 0),
410
411 SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
412 8, 0, NULL, 0),
413
414 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
415 NULL, 0),
416
417 SND_SOC_DAPM_INPUT("LIN"),
418 SND_SOC_DAPM_INPUT("LIP"),
419 SND_SOC_DAPM_INPUT("RIN"),
420 SND_SOC_DAPM_INPUT("RIP"),
421 SND_SOC_DAPM_INPUT("AUXL"),
422 SND_SOC_DAPM_INPUT("AUXR"),
423 SND_SOC_DAPM_INPUT("L2"),
424 SND_SOC_DAPM_INPUT("R2"),
425 SND_SOC_DAPM_OUTPUT("HPL"),
426 SND_SOC_DAPM_OUTPUT("HPR"),
427 SND_SOC_DAPM_OUTPUT("SPKL"),
428 SND_SOC_DAPM_OUTPUT("SPKR"),
429 SND_SOC_DAPM_OUTPUT("OUT3"),
430 SND_SOC_DAPM_OUTPUT("OUT4")
431 };
432
433 static const struct snd_soc_dapm_route wm8983_audio_map[] = {
434 { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
435 { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
436
437 { "OUT3 Out", NULL, "OUT3 Mixer" },
438 { "OUT3", NULL, "OUT3 Out" },
439
440 { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
441 { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
442 { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
443 { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
444
445 { "OUT4 Out", NULL, "OUT4 Mixer" },
446 { "OUT4", NULL, "OUT4 Out" },
447
448 { "Right Output Mixer", "PCM Switch", "Right DAC" },
449 { "Right Output Mixer", "Aux Switch", "AUXR" },
450 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
451
452 { "Left Output Mixer", "PCM Switch", "Left DAC" },
453 { "Left Output Mixer", "Aux Switch", "AUXL" },
454 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
455
456 { "Right Headphone Out", NULL, "Right Output Mixer" },
457 { "HPR", NULL, "Right Headphone Out" },
458
459 { "Left Headphone Out", NULL, "Left Output Mixer" },
460 { "HPL", NULL, "Left Headphone Out" },
461
462 { "Right Speaker Out", NULL, "Right Output Mixer" },
463 { "SPKR", NULL, "Right Speaker Out" },
464
465 { "Left Speaker Out", NULL, "Left Output Mixer" },
466 { "SPKL", NULL, "Left Speaker Out" },
467
468 { "Right ADC", NULL, "Right Boost Mixer" },
469
470 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
471 { "Right Boost Mixer", NULL, "Right Capture PGA" },
472 { "Right Boost Mixer", "R2 Volume", "R2" },
473
474 { "Left ADC", NULL, "Left Boost Mixer" },
475
476 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
477 { "Left Boost Mixer", NULL, "Left Capture PGA" },
478 { "Left Boost Mixer", "L2 Volume", "L2" },
479
480 { "Right Capture PGA", NULL, "Right Input Mixer" },
481 { "Left Capture PGA", NULL, "Left Input Mixer" },
482
483 { "Right Input Mixer", "R2 Switch", "R2" },
484 { "Right Input Mixer", "MicN Switch", "RIN" },
485 { "Right Input Mixer", "MicP Switch", "RIP" },
486
487 { "Left Input Mixer", "L2 Switch", "L2" },
488 { "Left Input Mixer", "MicN Switch", "LIN" },
489 { "Left Input Mixer", "MicP Switch", "LIP" },
490 };
491
492 static int eqmode_get(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494 {
495 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
496 unsigned int reg;
497
498 reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
499 if (reg & WM8983_EQ3DMODE)
500 ucontrol->value.enumerated.item[0] = 1;
501 else
502 ucontrol->value.enumerated.item[0] = 0;
503
504 return 0;
505 }
506
507 static int eqmode_put(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol)
509 {
510 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
511 unsigned int regpwr2, regpwr3;
512 unsigned int reg_eq;
513
514 if (ucontrol->value.enumerated.item[0] != 0
515 && ucontrol->value.enumerated.item[0] != 1)
516 return -EINVAL;
517
518 reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
519 switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
520 case 0:
521 if (!ucontrol->value.enumerated.item[0])
522 return 0;
523 break;
524 case 1:
525 if (ucontrol->value.enumerated.item[0])
526 return 0;
527 break;
528 }
529
530 regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2);
531 regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3);
532 /* disable the DACs and ADCs */
533 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2,
534 WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
535 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3,
536 WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
537 /* set the desired eqmode */
538 snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF,
539 WM8983_EQ3DMODE_MASK,
540 ucontrol->value.enumerated.item[0]
541 << WM8983_EQ3DMODE_SHIFT);
542 /* restore DAC/ADC configuration */
543 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2);
544 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3);
545 return 0;
546 }
547
548 static bool wm8983_writeable(struct device *dev, unsigned int reg)
549 {
550 switch (reg) {
551 case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
552 case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
553 case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
554 case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
555 case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
556 case WM8983_BIAS_CTRL:
557 return true;
558 default:
559 return false;
560 }
561 }
562
563 static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
564 {
565 struct snd_soc_codec *codec = dai->codec;
566
567 return snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
568 WM8983_SOFTMUTE_MASK,
569 !!mute << WM8983_SOFTMUTE_SHIFT);
570 }
571
572 static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
573 {
574 struct snd_soc_codec *codec = dai->codec;
575 u16 format, master, bcp, lrp;
576
577 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
578 case SND_SOC_DAIFMT_I2S:
579 format = 0x2;
580 break;
581 case SND_SOC_DAIFMT_RIGHT_J:
582 format = 0x0;
583 break;
584 case SND_SOC_DAIFMT_LEFT_J:
585 format = 0x1;
586 break;
587 case SND_SOC_DAIFMT_DSP_A:
588 case SND_SOC_DAIFMT_DSP_B:
589 format = 0x3;
590 break;
591 default:
592 dev_err(dai->dev, "Unknown dai format\n");
593 return -EINVAL;
594 }
595
596 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
597 WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
598
599 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
600 case SND_SOC_DAIFMT_CBM_CFM:
601 master = 1;
602 break;
603 case SND_SOC_DAIFMT_CBS_CFS:
604 master = 0;
605 break;
606 default:
607 dev_err(dai->dev, "Unknown master/slave configuration\n");
608 return -EINVAL;
609 }
610
611 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
612 WM8983_MS_MASK, master << WM8983_MS_SHIFT);
613
614 /* FIXME: We don't currently support DSP A/B modes */
615 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
616 case SND_SOC_DAIFMT_DSP_A:
617 case SND_SOC_DAIFMT_DSP_B:
618 dev_err(dai->dev, "DSP A/B modes are not supported\n");
619 return -EINVAL;
620 default:
621 break;
622 }
623
624 bcp = lrp = 0;
625 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
626 case SND_SOC_DAIFMT_NB_NF:
627 break;
628 case SND_SOC_DAIFMT_IB_IF:
629 bcp = lrp = 1;
630 break;
631 case SND_SOC_DAIFMT_IB_NF:
632 bcp = 1;
633 break;
634 case SND_SOC_DAIFMT_NB_IF:
635 lrp = 1;
636 break;
637 default:
638 dev_err(dai->dev, "Unknown polarity configuration\n");
639 return -EINVAL;
640 }
641
642 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
643 WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
644 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
645 WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
646 return 0;
647 }
648
649 static int wm8983_hw_params(struct snd_pcm_substream *substream,
650 struct snd_pcm_hw_params *params,
651 struct snd_soc_dai *dai)
652 {
653 int i;
654 struct snd_soc_codec *codec = dai->codec;
655 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
656 u16 blen, srate_idx;
657 u32 tmp;
658 int srate_best;
659 int ret;
660
661 ret = snd_soc_params_to_bclk(params);
662 if (ret < 0) {
663 dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret);
664 return ret;
665 }
666
667 wm8983->bclk = ret;
668
669 switch (params_width(params)) {
670 case 16:
671 blen = 0x0;
672 break;
673 case 20:
674 blen = 0x1;
675 break;
676 case 24:
677 blen = 0x2;
678 break;
679 case 32:
680 blen = 0x3;
681 break;
682 default:
683 dev_err(dai->dev, "Unsupported word length %u\n",
684 params_width(params));
685 return -EINVAL;
686 }
687
688 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
689 WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
690
691 /*
692 * match to the nearest possible sample rate and rely
693 * on the array index to configure the SR register
694 */
695 srate_idx = 0;
696 srate_best = abs(srates[0] - params_rate(params));
697 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
698 if (abs(srates[i] - params_rate(params)) >= srate_best)
699 continue;
700 srate_idx = i;
701 srate_best = abs(srates[i] - params_rate(params));
702 }
703
704 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
705 snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL,
706 WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
707
708 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
709 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
710
711 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
712 if (wm8983->sysclk / params_rate(params)
713 == fs_ratios[i].ratio)
714 break;
715 }
716
717 if (i == ARRAY_SIZE(fs_ratios)) {
718 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
719 wm8983->sysclk, params_rate(params));
720 return -EINVAL;
721 }
722
723 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
724 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
725 WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
726
727 /* select the appropriate bclk divider */
728 tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
729 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
730 if (wm8983->bclk == tmp / bclk_divs[i])
731 break;
732 }
733
734 if (i == ARRAY_SIZE(bclk_divs)) {
735 dev_err(dai->dev, "No matching BCLK divider found\n");
736 return -EINVAL;
737 }
738
739 dev_dbg(dai->dev, "BCLK div = %d\n", i);
740 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
741 WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
742
743 return 0;
744 }
745
746 struct pll_div {
747 u32 div2:1;
748 u32 n:4;
749 u32 k:24;
750 };
751
752 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
753 static int pll_factors(struct pll_div *pll_div, unsigned int target,
754 unsigned int source)
755 {
756 u64 Kpart;
757 unsigned long int K, Ndiv, Nmod;
758
759 pll_div->div2 = 0;
760 Ndiv = target / source;
761 if (Ndiv < 6) {
762 source >>= 1;
763 pll_div->div2 = 1;
764 Ndiv = target / source;
765 }
766
767 if (Ndiv < 6 || Ndiv > 12) {
768 printk(KERN_ERR "%s: WM8983 N value is not within"
769 " the recommended range: %lu\n", __func__, Ndiv);
770 return -EINVAL;
771 }
772 pll_div->n = Ndiv;
773
774 Nmod = target % source;
775 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
776
777 do_div(Kpart, source);
778
779 K = Kpart & 0xffffffff;
780 if ((K % 10) >= 5)
781 K += 5;
782 K /= 10;
783 pll_div->k = K;
784 return 0;
785 }
786
787 static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
788 int source, unsigned int freq_in,
789 unsigned int freq_out)
790 {
791 int ret;
792 struct snd_soc_codec *codec;
793 struct pll_div pll_div;
794
795 codec = dai->codec;
796 if (!freq_in || !freq_out) {
797 /* disable the PLL */
798 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
799 WM8983_PLLEN_MASK, 0);
800 return 0;
801 } else {
802 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
803 if (ret)
804 return ret;
805
806 /* disable the PLL before re-programming it */
807 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
808 WM8983_PLLEN_MASK, 0);
809
810 /* set PLLN and PRESCALE */
811 snd_soc_write(codec, WM8983_PLL_N,
812 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
813 | pll_div.n);
814 /* set PLLK */
815 snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
816 snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
817 snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
818 /* enable the PLL */
819 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
820 WM8983_PLLEN_MASK, WM8983_PLLEN);
821 }
822
823 return 0;
824 }
825
826 static int wm8983_set_sysclk(struct snd_soc_dai *dai,
827 int clk_id, unsigned int freq, int dir)
828 {
829 struct snd_soc_codec *codec = dai->codec;
830 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
831
832 switch (clk_id) {
833 case WM8983_CLKSRC_MCLK:
834 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
835 WM8983_CLKSEL_MASK, 0);
836 break;
837 case WM8983_CLKSRC_PLL:
838 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
839 WM8983_CLKSEL_MASK, WM8983_CLKSEL);
840 break;
841 default:
842 dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
843 return -EINVAL;
844 }
845
846 wm8983->sysclk = freq;
847 return 0;
848 }
849
850 static int wm8983_set_bias_level(struct snd_soc_codec *codec,
851 enum snd_soc_bias_level level)
852 {
853 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
854 int ret;
855
856 switch (level) {
857 case SND_SOC_BIAS_ON:
858 case SND_SOC_BIAS_PREPARE:
859 /* VMID at 100k */
860 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
861 WM8983_VMIDSEL_MASK,
862 1 << WM8983_VMIDSEL_SHIFT);
863 break;
864 case SND_SOC_BIAS_STANDBY:
865 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
866 ret = regcache_sync(wm8983->regmap);
867 if (ret < 0) {
868 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
869 return ret;
870 }
871 /* enable anti-pop features */
872 snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
873 WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
874 WM8983_POBCTRL | WM8983_DELEN);
875 /* enable thermal shutdown */
876 snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
877 WM8983_TSDEN_MASK, WM8983_TSDEN);
878 /* enable BIASEN */
879 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
880 WM8983_BIASEN_MASK, WM8983_BIASEN);
881 /* VMID at 100k */
882 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
883 WM8983_VMIDSEL_MASK,
884 1 << WM8983_VMIDSEL_SHIFT);
885 msleep(250);
886 /* disable anti-pop features */
887 snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
888 WM8983_POBCTRL_MASK |
889 WM8983_DELEN_MASK, 0);
890 }
891
892 /* VMID at 500k */
893 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
894 WM8983_VMIDSEL_MASK,
895 2 << WM8983_VMIDSEL_SHIFT);
896 break;
897 case SND_SOC_BIAS_OFF:
898 /* disable thermal shutdown */
899 snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
900 WM8983_TSDEN_MASK, 0);
901 /* disable VMIDSEL and BIASEN */
902 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
903 WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
904 0);
905 /* wait for VMID to discharge */
906 msleep(100);
907 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0);
908 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0);
909 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0);
910 break;
911 }
912
913 return 0;
914 }
915
916 static int wm8983_probe(struct snd_soc_codec *codec)
917 {
918 int ret;
919 int i;
920
921 ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0);
922 if (ret < 0) {
923 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
924 return ret;
925 }
926
927 /* set the vol/gain update bits */
928 for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
929 snd_soc_update_bits(codec, vol_update_regs[i],
930 0x100, 0x100);
931
932 /* mute all outputs and set PGAs to minimum gain */
933 for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
934 i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
935 snd_soc_update_bits(codec, i, 0x40, 0x40);
936
937 /* enable soft mute */
938 snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
939 WM8983_SOFTMUTE_MASK,
940 WM8983_SOFTMUTE);
941
942 /* enable BIASCUT */
943 snd_soc_update_bits(codec, WM8983_BIAS_CTRL,
944 WM8983_BIASCUT, WM8983_BIASCUT);
945 return 0;
946 }
947
948 static const struct snd_soc_dai_ops wm8983_dai_ops = {
949 .digital_mute = wm8983_dac_mute,
950 .hw_params = wm8983_hw_params,
951 .set_fmt = wm8983_set_fmt,
952 .set_sysclk = wm8983_set_sysclk,
953 .set_pll = wm8983_set_pll
954 };
955
956 #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
957 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
958
959 static struct snd_soc_dai_driver wm8983_dai = {
960 .name = "wm8983-hifi",
961 .playback = {
962 .stream_name = "Playback",
963 .channels_min = 2,
964 .channels_max = 2,
965 .rates = SNDRV_PCM_RATE_8000_48000,
966 .formats = WM8983_FORMATS,
967 },
968 .capture = {
969 .stream_name = "Capture",
970 .channels_min = 2,
971 .channels_max = 2,
972 .rates = SNDRV_PCM_RATE_8000_48000,
973 .formats = WM8983_FORMATS,
974 },
975 .ops = &wm8983_dai_ops,
976 .symmetric_rates = 1
977 };
978
979 static const struct snd_soc_codec_driver soc_codec_dev_wm8983 = {
980 .probe = wm8983_probe,
981 .set_bias_level = wm8983_set_bias_level,
982 .suspend_bias_off = true,
983 .component_driver = {
984 .controls = wm8983_snd_controls,
985 .num_controls = ARRAY_SIZE(wm8983_snd_controls),
986 .dapm_widgets = wm8983_dapm_widgets,
987 .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
988 .dapm_routes = wm8983_audio_map,
989 .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
990 },
991 };
992
993 static const struct regmap_config wm8983_regmap = {
994 .reg_bits = 7,
995 .val_bits = 9,
996
997 .reg_defaults = wm8983_defaults,
998 .num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
999 .cache_type = REGCACHE_RBTREE,
1000 .max_register = WM8983_MAX_REGISTER,
1001
1002 .writeable_reg = wm8983_writeable,
1003 };
1004
1005 #if defined(CONFIG_SPI_MASTER)
1006 static int wm8983_spi_probe(struct spi_device *spi)
1007 {
1008 struct wm8983_priv *wm8983;
1009 int ret;
1010
1011 wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
1012 if (!wm8983)
1013 return -ENOMEM;
1014
1015 wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
1016 if (IS_ERR(wm8983->regmap)) {
1017 ret = PTR_ERR(wm8983->regmap);
1018 dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
1019 return ret;
1020 }
1021
1022 spi_set_drvdata(spi, wm8983);
1023
1024 ret = snd_soc_register_codec(&spi->dev,
1025 &soc_codec_dev_wm8983, &wm8983_dai, 1);
1026 return ret;
1027 }
1028
1029 static int wm8983_spi_remove(struct spi_device *spi)
1030 {
1031 snd_soc_unregister_codec(&spi->dev);
1032 return 0;
1033 }
1034
1035 static struct spi_driver wm8983_spi_driver = {
1036 .driver = {
1037 .name = "wm8983",
1038 },
1039 .probe = wm8983_spi_probe,
1040 .remove = wm8983_spi_remove
1041 };
1042 #endif
1043
1044 #if IS_ENABLED(CONFIG_I2C)
1045 static int wm8983_i2c_probe(struct i2c_client *i2c,
1046 const struct i2c_device_id *id)
1047 {
1048 struct wm8983_priv *wm8983;
1049 int ret;
1050
1051 wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
1052 if (!wm8983)
1053 return -ENOMEM;
1054
1055 wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
1056 if (IS_ERR(wm8983->regmap)) {
1057 ret = PTR_ERR(wm8983->regmap);
1058 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1059 return ret;
1060 }
1061
1062 i2c_set_clientdata(i2c, wm8983);
1063
1064 ret = snd_soc_register_codec(&i2c->dev,
1065 &soc_codec_dev_wm8983, &wm8983_dai, 1);
1066
1067 return ret;
1068 }
1069
1070 static int wm8983_i2c_remove(struct i2c_client *client)
1071 {
1072 snd_soc_unregister_codec(&client->dev);
1073 return 0;
1074 }
1075
1076 static const struct i2c_device_id wm8983_i2c_id[] = {
1077 { "wm8983", 0 },
1078 { }
1079 };
1080 MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
1081
1082 static struct i2c_driver wm8983_i2c_driver = {
1083 .driver = {
1084 .name = "wm8983",
1085 },
1086 .probe = wm8983_i2c_probe,
1087 .remove = wm8983_i2c_remove,
1088 .id_table = wm8983_i2c_id
1089 };
1090 #endif
1091
1092 static int __init wm8983_modinit(void)
1093 {
1094 int ret = 0;
1095
1096 #if IS_ENABLED(CONFIG_I2C)
1097 ret = i2c_add_driver(&wm8983_i2c_driver);
1098 if (ret) {
1099 printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
1100 ret);
1101 }
1102 #endif
1103 #if defined(CONFIG_SPI_MASTER)
1104 ret = spi_register_driver(&wm8983_spi_driver);
1105 if (ret != 0) {
1106 printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
1107 ret);
1108 }
1109 #endif
1110 return ret;
1111 }
1112 module_init(wm8983_modinit);
1113
1114 static void __exit wm8983_exit(void)
1115 {
1116 #if IS_ENABLED(CONFIG_I2C)
1117 i2c_del_driver(&wm8983_i2c_driver);
1118 #endif
1119 #if defined(CONFIG_SPI_MASTER)
1120 spi_unregister_driver(&wm8983_spi_driver);
1121 #endif
1122 }
1123 module_exit(wm8983_exit);
1124
1125 MODULE_DESCRIPTION("ASoC WM8983 driver");
1126 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1127 MODULE_LICENSE("GPL");
Linux with added FPC-III support