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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / intel / skylake / skl-pcm.c
blob84b5101e6ca691df0e0896b59a95e07a55e3b5e7
1 /*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include "skl.h"
27 #include "skl-topology.h"
28 #include "skl-sst-dsp.h"
29 #include "skl-sst-ipc.h"
30
31 #define HDA_MONO 1
32 #define HDA_STEREO 2
33 #define HDA_QUAD 4
34
35 static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
41 SNDRV_PCM_INFO_RESUME |
42 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
44 SNDRV_PCM_INFO_HAS_LINK_ATIME |
45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
46 .formats = SNDRV_PCM_FMTBIT_S16_LE |
47 SNDRV_PCM_FMTBIT_S32_LE |
48 SNDRV_PCM_FMTBIT_S24_LE,
49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
50 SNDRV_PCM_RATE_8000,
51 .rate_min = 8000,
52 .rate_max = 48000,
53 .channels_min = 1,
54 .channels_max = 8,
55 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
56 .period_bytes_min = 128,
57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
58 .periods_min = 2,
59 .periods_max = AZX_MAX_FRAG,
60 .fifo_size = 0,
61 };
62
63 static inline
64 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
65 {
66 return substream->runtime->private_data;
67 }
68
69 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
70 {
71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
72 struct hdac_stream *hstream = hdac_stream(stream);
73 struct hdac_bus *bus = hstream->bus;
74
75 return hbus_to_ebus(bus);
76 }
77
78 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81 {
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89 }
90
91 static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93 {
94 return snd_pcm_lib_free_pages(substream);
95 }
96
97 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
98 struct snd_pcm_runtime *runtime)
99 {
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105 }
106
107 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
108 {
109 if ((ebus_to_hbus(ebus))->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113 }
114
115 /*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
122 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124 {
125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = ebus_to_skl(ebus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138 }
139
140 static int skl_pcm_open(struct snd_pcm_substream *substream,
141 struct snd_soc_dai *dai)
142 {
143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
144 struct hdac_ext_stream *stream;
145 struct snd_pcm_runtime *runtime = substream->runtime;
146 struct skl_dma_params *dma_params;
147 struct skl *skl = get_skl_ctx(dai->dev);
148 struct skl_module_cfg *mconfig;
149
150 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
151
152 stream = snd_hdac_ext_stream_assign(ebus, substream,
153 skl_get_host_stream_type(ebus));
154 if (stream == NULL)
155 return -EBUSY;
156
157 skl_set_pcm_constrains(ebus, runtime);
158
159 /*
160 * disable WALLCLOCK timestamps for capture streams
161 * until we figure out how to handle digital inputs
162 */
163 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
164 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
165 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
166 }
167
168 runtime->private_data = stream;
169
170 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
171 if (!dma_params)
172 return -ENOMEM;
173
174 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
175 snd_soc_dai_set_dma_data(dai, substream, dma_params);
176
177 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
178 dma_params->stream_tag);
179 skl_set_suspend_active(substream, dai, true);
180 snd_pcm_set_sync(substream);
181
182 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
183 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
184
185 return 0;
186 }
187
188 static int skl_get_format(struct snd_pcm_substream *substream,
189 struct snd_soc_dai *dai)
190 {
191 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
192 struct skl_dma_params *dma_params;
193 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
194 int format_val = 0;
195
196 if ((ebus_to_hbus(ebus))->ppcap) {
197 struct snd_pcm_runtime *runtime = substream->runtime;
198
199 format_val = snd_hdac_calc_stream_format(runtime->rate,
200 runtime->channels,
201 runtime->format,
202 32, 0);
203 } else {
204 struct snd_soc_dai *codec_dai = rtd->codec_dai;
205
206 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
207 if (dma_params)
208 format_val = dma_params->format;
209 }
210
211 return format_val;
212 }
213
214 static int skl_be_prepare(struct snd_pcm_substream *substream,
215 struct snd_soc_dai *dai)
216 {
217 struct skl *skl = get_skl_ctx(dai->dev);
218 struct skl_sst *ctx = skl->skl_sst;
219 struct skl_module_cfg *mconfig;
220
221 if (dai->playback_widget->power || dai->capture_widget->power)
222 return 0;
223
224 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
225 if (mconfig == NULL)
226 return -EINVAL;
227
228 return skl_dsp_set_dma_control(ctx, mconfig);
229 }
230
231 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
232 struct snd_soc_dai *dai)
233 {
234 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
235 struct skl *skl = get_skl_ctx(dai->dev);
236 unsigned int format_val;
237 int err;
238 struct skl_module_cfg *mconfig;
239
240 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
241
242 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
243
244 format_val = skl_get_format(substream, dai);
245 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
246 hdac_stream(stream)->stream_tag, format_val);
247 snd_hdac_stream_reset(hdac_stream(stream));
248
249 /* In case of XRUN recovery, reset the FW pipe to clean state */
250 if (mconfig && (substream->runtime->status->state ==
251 SNDRV_PCM_STATE_XRUN))
252 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
253
254 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
255 if (err < 0)
256 return err;
257
258 err = snd_hdac_stream_setup(hdac_stream(stream));
259 if (err < 0)
260 return err;
261
262 hdac_stream(stream)->prepared = 1;
263
264 return err;
265 }
266
267 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
268 struct snd_pcm_hw_params *params,
269 struct snd_soc_dai *dai)
270 {
271 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
272 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
273 struct snd_pcm_runtime *runtime = substream->runtime;
274 struct skl_pipe_params p_params = {0};
275 struct skl_module_cfg *m_cfg;
276 int ret, dma_id;
277
278 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
279 ret = skl_substream_alloc_pages(ebus, substream,
280 params_buffer_bytes(params));
281 if (ret < 0)
282 return ret;
283
284 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
285 runtime->rate, runtime->channels, runtime->format);
286
287 dma_id = hdac_stream(stream)->stream_tag - 1;
288 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
289
290 p_params.s_fmt = snd_pcm_format_width(params_format(params));
291 p_params.ch = params_channels(params);
292 p_params.s_freq = params_rate(params);
293 p_params.host_dma_id = dma_id;
294 p_params.stream = substream->stream;
295
296 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
297 if (m_cfg)
298 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
299
300 return 0;
301 }
302
303 static void skl_pcm_close(struct snd_pcm_substream *substream,
304 struct snd_soc_dai *dai)
305 {
306 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
307 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
308 struct skl_dma_params *dma_params = NULL;
309 struct skl *skl = ebus_to_skl(ebus);
310 struct skl_module_cfg *mconfig;
311
312 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
313
314 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
315
316 dma_params = snd_soc_dai_get_dma_data(dai, substream);
317 /*
318 * now we should set this to NULL as we are freeing by the
319 * dma_params
320 */
321 snd_soc_dai_set_dma_data(dai, substream, NULL);
322 skl_set_suspend_active(substream, dai, false);
323
324 /*
325 * check if close is for "Reference Pin" and set back the
326 * CGCTL.MISCBDCGE if disabled by driver
327 */
328 if (!strncmp(dai->name, "Reference Pin", 13) &&
329 skl->skl_sst->miscbdcg_disabled) {
330 skl->skl_sst->enable_miscbdcge(dai->dev, true);
331 skl->skl_sst->miscbdcg_disabled = false;
332 }
333
334 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
335 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
336
337 kfree(dma_params);
338 }
339
340 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
341 struct snd_soc_dai *dai)
342 {
343 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
344 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
345
346 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
347
348 snd_hdac_stream_cleanup(hdac_stream(stream));
349 hdac_stream(stream)->prepared = 0;
350
351 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
352 }
353
354 static int skl_be_hw_params(struct snd_pcm_substream *substream,
355 struct snd_pcm_hw_params *params,
356 struct snd_soc_dai *dai)
357 {
358 struct skl_pipe_params p_params = {0};
359
360 p_params.s_fmt = snd_pcm_format_width(params_format(params));
361 p_params.ch = params_channels(params);
362 p_params.s_freq = params_rate(params);
363 p_params.stream = substream->stream;
364
365 return skl_tplg_be_update_params(dai, &p_params);
366 }
367
368 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
369 int cmd)
370 {
371 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
372 struct hdac_bus *bus = ebus_to_hbus(ebus);
373 struct hdac_ext_stream *stream;
374 int start;
375 unsigned long cookie;
376 struct hdac_stream *hstr;
377
378 stream = get_hdac_ext_stream(substream);
379 hstr = hdac_stream(stream);
380
381 if (!hstr->prepared)
382 return -EPIPE;
383
384 switch (cmd) {
385 case SNDRV_PCM_TRIGGER_START:
386 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
387 case SNDRV_PCM_TRIGGER_RESUME:
388 start = 1;
389 break;
390
391 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
392 case SNDRV_PCM_TRIGGER_SUSPEND:
393 case SNDRV_PCM_TRIGGER_STOP:
394 start = 0;
395 break;
396
397 default:
398 return -EINVAL;
399 }
400
401 spin_lock_irqsave(&bus->reg_lock, cookie);
402
403 if (start) {
404 snd_hdac_stream_start(hdac_stream(stream), true);
405 snd_hdac_stream_timecounter_init(hstr, 0);
406 } else {
407 snd_hdac_stream_stop(hdac_stream(stream));
408 }
409
410 spin_unlock_irqrestore(&bus->reg_lock, cookie);
411
412 return 0;
413 }
414
415 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
416 struct snd_soc_dai *dai)
417 {
418 struct skl *skl = get_skl_ctx(dai->dev);
419 struct skl_sst *ctx = skl->skl_sst;
420 struct skl_module_cfg *mconfig;
421 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
422 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
423 struct snd_soc_dapm_widget *w;
424 int ret;
425
426 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
427 if (!mconfig)
428 return -EIO;
429
430 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
431 w = dai->playback_widget;
432 else
433 w = dai->capture_widget;
434
435 switch (cmd) {
436 case SNDRV_PCM_TRIGGER_RESUME:
437 if (!w->ignore_suspend) {
438 skl_pcm_prepare(substream, dai);
439 /*
440 * enable DMA Resume enable bit for the stream, set the
441 * dpib & lpib position to resume before starting the
442 * DMA
443 */
444 snd_hdac_ext_stream_drsm_enable(ebus, true,
445 hdac_stream(stream)->index);
446 snd_hdac_ext_stream_set_dpibr(ebus, stream,
447 stream->dpib);
448 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
449 }
450
451 case SNDRV_PCM_TRIGGER_START:
452 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
453 /*
454 * Start HOST DMA and Start FE Pipe.This is to make sure that
455 * there are no underrun/overrun in the case when the FE
456 * pipeline is started but there is a delay in starting the
457 * DMA channel on the host.
458 */
459 snd_hdac_ext_stream_decouple(ebus, stream, true);
460 ret = skl_decoupled_trigger(substream, cmd);
461 if (ret < 0)
462 return ret;
463 return skl_run_pipe(ctx, mconfig->pipe);
464 break;
465
466 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
467 case SNDRV_PCM_TRIGGER_SUSPEND:
468 case SNDRV_PCM_TRIGGER_STOP:
469 /*
470 * Stop FE Pipe first and stop DMA. This is to make sure that
471 * there are no underrun/overrun in the case if there is a delay
472 * between the two operations.
473 */
474 ret = skl_stop_pipe(ctx, mconfig->pipe);
475 if (ret < 0)
476 return ret;
477
478 ret = skl_decoupled_trigger(substream, cmd);
479 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
480 /* save the dpib and lpib positions */
481 stream->dpib = readl(ebus->bus.remap_addr +
482 AZX_REG_VS_SDXDPIB_XBASE +
483 (AZX_REG_VS_SDXDPIB_XINTERVAL *
484 hdac_stream(stream)->index));
485
486 stream->lpib = snd_hdac_stream_get_pos_lpib(
487 hdac_stream(stream));
488 snd_hdac_ext_stream_decouple(ebus, stream, false);
489 }
490 break;
491
492 default:
493 return -EINVAL;
494 }
495
496 return 0;
497 }
498
499 static int skl_link_hw_params(struct snd_pcm_substream *substream,
500 struct snd_pcm_hw_params *params,
501 struct snd_soc_dai *dai)
502 {
503 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
504 struct hdac_ext_stream *link_dev;
505 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
506 struct hdac_ext_dma_params *dma_params;
507 struct snd_soc_dai *codec_dai = rtd->codec_dai;
508 struct skl_pipe_params p_params = {0};
509
510 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
511 HDAC_EXT_STREAM_TYPE_LINK);
512 if (!link_dev)
513 return -EBUSY;
514
515 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
516
517 /* set the stream tag in the codec dai dma params */
518 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
519 if (dma_params)
520 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
521
522 p_params.s_fmt = snd_pcm_format_width(params_format(params));
523 p_params.ch = params_channels(params);
524 p_params.s_freq = params_rate(params);
525 p_params.stream = substream->stream;
526 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
527
528 return skl_tplg_be_update_params(dai, &p_params);
529 }
530
531 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
532 struct snd_soc_dai *dai)
533 {
534 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
535 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
536 struct hdac_ext_stream *link_dev =
537 snd_soc_dai_get_dma_data(dai, substream);
538 unsigned int format_val = 0;
539 struct skl_dma_params *dma_params;
540 struct snd_soc_dai *codec_dai = rtd->codec_dai;
541 struct hdac_ext_link *link;
542 struct skl *skl = get_skl_ctx(dai->dev);
543 struct skl_module_cfg *mconfig = NULL;
544
545 dma_params = (struct skl_dma_params *)
546 snd_soc_dai_get_dma_data(codec_dai, substream);
547 if (dma_params)
548 format_val = dma_params->format;
549 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
550 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
551
552 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
553 if (!link)
554 return -EINVAL;
555
556 snd_hdac_ext_link_stream_reset(link_dev);
557
558 /* In case of XRUN recovery, reset the FW pipe to clean state */
559 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
560 if (mconfig && (substream->runtime->status->state ==
561 SNDRV_PCM_STATE_XRUN))
562 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
563
564 snd_hdac_ext_link_stream_setup(link_dev, format_val);
565
566 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
567 link_dev->link_prepared = 1;
568
569 return 0;
570 }
571
572 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
573 int cmd, struct snd_soc_dai *dai)
574 {
575 struct hdac_ext_stream *link_dev =
576 snd_soc_dai_get_dma_data(dai, substream);
577 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
578 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
579
580 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
581 switch (cmd) {
582 case SNDRV_PCM_TRIGGER_RESUME:
583 skl_link_pcm_prepare(substream, dai);
584 case SNDRV_PCM_TRIGGER_START:
585 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
586 snd_hdac_ext_stream_decouple(ebus, stream, true);
587 snd_hdac_ext_link_stream_start(link_dev);
588 break;
589
590 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
591 case SNDRV_PCM_TRIGGER_SUSPEND:
592 case SNDRV_PCM_TRIGGER_STOP:
593 snd_hdac_ext_link_stream_clear(link_dev);
594 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
595 snd_hdac_ext_stream_decouple(ebus, stream, false);
596 break;
597
598 default:
599 return -EINVAL;
600 }
601 return 0;
602 }
603
604 static int skl_link_hw_free(struct snd_pcm_substream *substream,
605 struct snd_soc_dai *dai)
606 {
607 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
608 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
609 struct hdac_ext_stream *link_dev =
610 snd_soc_dai_get_dma_data(dai, substream);
611 struct hdac_ext_link *link;
612
613 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
614
615 link_dev->link_prepared = 0;
616
617 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
618 if (!link)
619 return -EINVAL;
620
621 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
622 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
623 return 0;
624 }
625
626 static struct snd_soc_dai_ops skl_pcm_dai_ops = {
627 .startup = skl_pcm_open,
628 .shutdown = skl_pcm_close,
629 .prepare = skl_pcm_prepare,
630 .hw_params = skl_pcm_hw_params,
631 .hw_free = skl_pcm_hw_free,
632 .trigger = skl_pcm_trigger,
633 };
634
635 static struct snd_soc_dai_ops skl_dmic_dai_ops = {
636 .hw_params = skl_be_hw_params,
637 };
638
639 static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
640 .hw_params = skl_be_hw_params,
641 .prepare = skl_be_prepare,
642 };
643
644 static struct snd_soc_dai_ops skl_link_dai_ops = {
645 .prepare = skl_link_pcm_prepare,
646 .hw_params = skl_link_hw_params,
647 .hw_free = skl_link_hw_free,
648 .trigger = skl_link_pcm_trigger,
649 };
650
651 static struct snd_soc_dai_driver skl_platform_dai[] = {
652 {
653 .name = "System Pin",
654 .ops = &skl_pcm_dai_ops,
655 .playback = {
656 .stream_name = "System Playback",
657 .channels_min = HDA_MONO,
658 .channels_max = HDA_STEREO,
659 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
660 .formats = SNDRV_PCM_FMTBIT_S16_LE |
661 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
662 },
663 .capture = {
664 .stream_name = "System Capture",
665 .channels_min = HDA_MONO,
666 .channels_max = HDA_STEREO,
667 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
668 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
669 },
670 },
671 {
672 .name = "Reference Pin",
673 .ops = &skl_pcm_dai_ops,
674 .capture = {
675 .stream_name = "Reference Capture",
676 .channels_min = HDA_MONO,
677 .channels_max = HDA_QUAD,
678 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
679 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
680 },
681 },
682 {
683 .name = "Deepbuffer Pin",
684 .ops = &skl_pcm_dai_ops,
685 .playback = {
686 .stream_name = "Deepbuffer Playback",
687 .channels_min = HDA_STEREO,
688 .channels_max = HDA_STEREO,
689 .rates = SNDRV_PCM_RATE_48000,
690 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
691 },
692 },
693 {
694 .name = "LowLatency Pin",
695 .ops = &skl_pcm_dai_ops,
696 .playback = {
697 .stream_name = "Low Latency Playback",
698 .channels_min = HDA_STEREO,
699 .channels_max = HDA_STEREO,
700 .rates = SNDRV_PCM_RATE_48000,
701 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
702 },
703 },
704 {
705 .name = "DMIC Pin",
706 .ops = &skl_pcm_dai_ops,
707 .capture = {
708 .stream_name = "DMIC Capture",
709 .channels_min = HDA_MONO,
710 .channels_max = HDA_QUAD,
711 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
712 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
713 },
714 },
715 {
716 .name = "HDMI1 Pin",
717 .ops = &skl_pcm_dai_ops,
718 .playback = {
719 .stream_name = "HDMI1 Playback",
720 .channels_min = HDA_STEREO,
721 .channels_max = 8,
722 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
723 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
724 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
725 SNDRV_PCM_RATE_192000,
726 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
727 SNDRV_PCM_FMTBIT_S32_LE,
728 },
729 },
730 {
731 .name = "HDMI2 Pin",
732 .ops = &skl_pcm_dai_ops,
733 .playback = {
734 .stream_name = "HDMI2 Playback",
735 .channels_min = HDA_STEREO,
736 .channels_max = 8,
737 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
738 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
739 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
740 SNDRV_PCM_RATE_192000,
741 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
742 SNDRV_PCM_FMTBIT_S32_LE,
743 },
744 },
745 {
746 .name = "HDMI3 Pin",
747 .ops = &skl_pcm_dai_ops,
748 .playback = {
749 .stream_name = "HDMI3 Playback",
750 .channels_min = HDA_STEREO,
751 .channels_max = 8,
752 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
753 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
754 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
755 SNDRV_PCM_RATE_192000,
756 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
757 SNDRV_PCM_FMTBIT_S32_LE,
758 },
759 },
760
761 /* BE CPU Dais */
762 {
763 .name = "SSP0 Pin",
764 .ops = &skl_be_ssp_dai_ops,
765 .playback = {
766 .stream_name = "ssp0 Tx",
767 .channels_min = HDA_STEREO,
768 .channels_max = HDA_STEREO,
769 .rates = SNDRV_PCM_RATE_48000,
770 .formats = SNDRV_PCM_FMTBIT_S16_LE,
771 },
772 .capture = {
773 .stream_name = "ssp0 Rx",
774 .channels_min = HDA_STEREO,
775 .channels_max = HDA_STEREO,
776 .rates = SNDRV_PCM_RATE_48000,
777 .formats = SNDRV_PCM_FMTBIT_S16_LE,
778 },
779 },
780 {
781 .name = "SSP1 Pin",
782 .ops = &skl_be_ssp_dai_ops,
783 .playback = {
784 .stream_name = "ssp1 Tx",
785 .channels_min = HDA_STEREO,
786 .channels_max = HDA_STEREO,
787 .rates = SNDRV_PCM_RATE_48000,
788 .formats = SNDRV_PCM_FMTBIT_S16_LE,
789 },
790 .capture = {
791 .stream_name = "ssp1 Rx",
792 .channels_min = HDA_STEREO,
793 .channels_max = HDA_STEREO,
794 .rates = SNDRV_PCM_RATE_48000,
795 .formats = SNDRV_PCM_FMTBIT_S16_LE,
796 },
797 },
798 {
799 .name = "SSP2 Pin",
800 .ops = &skl_be_ssp_dai_ops,
801 .playback = {
802 .stream_name = "ssp2 Tx",
803 .channels_min = HDA_STEREO,
804 .channels_max = HDA_STEREO,
805 .rates = SNDRV_PCM_RATE_48000,
806 .formats = SNDRV_PCM_FMTBIT_S16_LE,
807 },
808 .capture = {
809 .stream_name = "ssp2 Rx",
810 .channels_min = HDA_STEREO,
811 .channels_max = HDA_STEREO,
812 .rates = SNDRV_PCM_RATE_48000,
813 .formats = SNDRV_PCM_FMTBIT_S16_LE,
814 },
815 },
816 {
817 .name = "SSP3 Pin",
818 .ops = &skl_be_ssp_dai_ops,
819 .playback = {
820 .stream_name = "ssp3 Tx",
821 .channels_min = HDA_STEREO,
822 .channels_max = HDA_STEREO,
823 .rates = SNDRV_PCM_RATE_48000,
824 .formats = SNDRV_PCM_FMTBIT_S16_LE,
825 },
826 .capture = {
827 .stream_name = "ssp3 Rx",
828 .channels_min = HDA_STEREO,
829 .channels_max = HDA_STEREO,
830 .rates = SNDRV_PCM_RATE_48000,
831 .formats = SNDRV_PCM_FMTBIT_S16_LE,
832 },
833 },
834 {
835 .name = "SSP4 Pin",
836 .ops = &skl_be_ssp_dai_ops,
837 .playback = {
838 .stream_name = "ssp4 Tx",
839 .channels_min = HDA_STEREO,
840 .channels_max = HDA_STEREO,
841 .rates = SNDRV_PCM_RATE_48000,
842 .formats = SNDRV_PCM_FMTBIT_S16_LE,
843 },
844 .capture = {
845 .stream_name = "ssp4 Rx",
846 .channels_min = HDA_STEREO,
847 .channels_max = HDA_STEREO,
848 .rates = SNDRV_PCM_RATE_48000,
849 .formats = SNDRV_PCM_FMTBIT_S16_LE,
850 },
851 },
852 {
853 .name = "SSP5 Pin",
854 .ops = &skl_be_ssp_dai_ops,
855 .playback = {
856 .stream_name = "ssp5 Tx",
857 .channels_min = HDA_STEREO,
858 .channels_max = HDA_STEREO,
859 .rates = SNDRV_PCM_RATE_48000,
860 .formats = SNDRV_PCM_FMTBIT_S16_LE,
861 },
862 .capture = {
863 .stream_name = "ssp5 Rx",
864 .channels_min = HDA_STEREO,
865 .channels_max = HDA_STEREO,
866 .rates = SNDRV_PCM_RATE_48000,
867 .formats = SNDRV_PCM_FMTBIT_S16_LE,
868 },
869 },
870 {
871 .name = "iDisp1 Pin",
872 .ops = &skl_link_dai_ops,
873 .playback = {
874 .stream_name = "iDisp1 Tx",
875 .channels_min = HDA_STEREO,
876 .channels_max = 8,
877 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
878 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
879 SNDRV_PCM_FMTBIT_S24_LE,
880 },
881 },
882 {
883 .name = "iDisp2 Pin",
884 .ops = &skl_link_dai_ops,
885 .playback = {
886 .stream_name = "iDisp2 Tx",
887 .channels_min = HDA_STEREO,
888 .channels_max = 8,
889 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
890 SNDRV_PCM_RATE_48000,
891 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
892 SNDRV_PCM_FMTBIT_S24_LE,
893 },
894 },
895 {
896 .name = "iDisp3 Pin",
897 .ops = &skl_link_dai_ops,
898 .playback = {
899 .stream_name = "iDisp3 Tx",
900 .channels_min = HDA_STEREO,
901 .channels_max = 8,
902 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
903 SNDRV_PCM_RATE_48000,
904 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
905 SNDRV_PCM_FMTBIT_S24_LE,
906 },
907 },
908 {
909 .name = "DMIC01 Pin",
910 .ops = &skl_dmic_dai_ops,
911 .capture = {
912 .stream_name = "DMIC01 Rx",
913 .channels_min = HDA_MONO,
914 .channels_max = HDA_QUAD,
915 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
916 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
917 },
918 },
919 {
920 .name = "HD-Codec Pin",
921 .ops = &skl_link_dai_ops,
922 .playback = {
923 .stream_name = "HD-Codec Tx",
924 .channels_min = HDA_STEREO,
925 .channels_max = HDA_STEREO,
926 .rates = SNDRV_PCM_RATE_48000,
927 .formats = SNDRV_PCM_FMTBIT_S16_LE,
928 },
929 .capture = {
930 .stream_name = "HD-Codec Rx",
931 .channels_min = HDA_STEREO,
932 .channels_max = HDA_STEREO,
933 .rates = SNDRV_PCM_RATE_48000,
934 .formats = SNDRV_PCM_FMTBIT_S16_LE,
935 },
936 },
937 };
938
939 static int skl_platform_open(struct snd_pcm_substream *substream)
940 {
941 struct snd_pcm_runtime *runtime;
942 struct snd_soc_pcm_runtime *rtd = substream->private_data;
943 struct snd_soc_dai_link *dai_link = rtd->dai_link;
944
945 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
946 dai_link->cpu_dai_name);
947
948 runtime = substream->runtime;
949 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
950
951 return 0;
952 }
953
954 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
955 int cmd)
956 {
957 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
958 struct hdac_bus *bus = ebus_to_hbus(ebus);
959 struct hdac_ext_stream *stream;
960 struct snd_pcm_substream *s;
961 bool start;
962 int sbits = 0;
963 unsigned long cookie;
964 struct hdac_stream *hstr;
965
966 stream = get_hdac_ext_stream(substream);
967 hstr = hdac_stream(stream);
968
969 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
970
971 if (!hstr->prepared)
972 return -EPIPE;
973
974 switch (cmd) {
975 case SNDRV_PCM_TRIGGER_START:
976 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
977 case SNDRV_PCM_TRIGGER_RESUME:
978 start = true;
979 break;
980
981 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
982 case SNDRV_PCM_TRIGGER_SUSPEND:
983 case SNDRV_PCM_TRIGGER_STOP:
984 start = false;
985 break;
986
987 default:
988 return -EINVAL;
989 }
990
991 snd_pcm_group_for_each_entry(s, substream) {
992 if (s->pcm->card != substream->pcm->card)
993 continue;
994 stream = get_hdac_ext_stream(s);
995 sbits |= 1 << hdac_stream(stream)->index;
996 snd_pcm_trigger_done(s, substream);
997 }
998
999 spin_lock_irqsave(&bus->reg_lock, cookie);
1000
1001 /* first, set SYNC bits of corresponding streams */
1002 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1003
1004 snd_pcm_group_for_each_entry(s, substream) {
1005 if (s->pcm->card != substream->pcm->card)
1006 continue;
1007 stream = get_hdac_ext_stream(s);
1008 if (start)
1009 snd_hdac_stream_start(hdac_stream(stream), true);
1010 else
1011 snd_hdac_stream_stop(hdac_stream(stream));
1012 }
1013 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1014
1015 snd_hdac_stream_sync(hstr, start, sbits);
1016
1017 spin_lock_irqsave(&bus->reg_lock, cookie);
1018
1019 /* reset SYNC bits */
1020 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1021 if (start)
1022 snd_hdac_stream_timecounter_init(hstr, sbits);
1023 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1024
1025 return 0;
1026 }
1027
1028 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1029 int cmd)
1030 {
1031 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1032
1033 if (!(ebus_to_hbus(ebus))->ppcap)
1034 return skl_coupled_trigger(substream, cmd);
1035
1036 return 0;
1037 }
1038
1039 static snd_pcm_uframes_t skl_platform_pcm_pointer
1040 (struct snd_pcm_substream *substream)
1041 {
1042 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1043 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1044 unsigned int pos;
1045
1046 /*
1047 * Use DPIB for Playback stream as the periodic DMA Position-in-
1048 * Buffer Writes may be scheduled at the same time or later than
1049 * the MSI and does not guarantee to reflect the Position of the
1050 * last buffer that was transferred. Whereas DPIB register in
1051 * HAD space reflects the actual data that is transferred.
1052 * Use the position buffer for capture, as DPIB write gets
1053 * completed earlier than the actual data written to the DDR.
1054 */
1055 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1056 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1057 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1058 hdac_stream(hstream)->index));
1059 else
1060 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1061
1062 if (pos >= hdac_stream(hstream)->bufsize)
1063 pos = 0;
1064
1065 return bytes_to_frames(substream->runtime, pos);
1066 }
1067
1068 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1069 u64 nsec)
1070 {
1071 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1072 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1073 u64 codec_frames, codec_nsecs;
1074
1075 if (!codec_dai->driver->ops->delay)
1076 return nsec;
1077
1078 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1079 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1080 substream->runtime->rate);
1081
1082 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1083 return nsec + codec_nsecs;
1084
1085 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1086 }
1087
1088 static int skl_get_time_info(struct snd_pcm_substream *substream,
1089 struct timespec *system_ts, struct timespec *audio_ts,
1090 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1091 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1092 {
1093 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1094 struct hdac_stream *hstr = hdac_stream(sstream);
1095 u64 nsec;
1096
1097 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1098 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1099
1100 snd_pcm_gettime(substream->runtime, system_ts);
1101
1102 nsec = timecounter_read(&hstr->tc);
1103 nsec = div_u64(nsec, 3); /* can be optimized */
1104 if (audio_tstamp_config->report_delay)
1105 nsec = skl_adjust_codec_delay(substream, nsec);
1106
1107 *audio_ts = ns_to_timespec(nsec);
1108
1109 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1110 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1111 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1112
1113 } else {
1114 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1115 }
1116
1117 return 0;
1118 }
1119
1120 static const struct snd_pcm_ops skl_platform_ops = {
1121 .open = skl_platform_open,
1122 .ioctl = snd_pcm_lib_ioctl,
1123 .trigger = skl_platform_pcm_trigger,
1124 .pointer = skl_platform_pcm_pointer,
1125 .get_time_info = skl_get_time_info,
1126 .mmap = snd_pcm_lib_default_mmap,
1127 .page = snd_pcm_sgbuf_ops_page,
1128 };
1129
1130 static void skl_pcm_free(struct snd_pcm *pcm)
1131 {
1132 snd_pcm_lib_preallocate_free_for_all(pcm);
1133 }
1134
1135 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1136
1137 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1138 {
1139 struct snd_soc_dai *dai = rtd->cpu_dai;
1140 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1141 struct snd_pcm *pcm = rtd->pcm;
1142 unsigned int size;
1143 int retval = 0;
1144 struct skl *skl = ebus_to_skl(ebus);
1145
1146 if (dai->driver->playback.channels_min ||
1147 dai->driver->capture.channels_min) {
1148 /* buffer pre-allocation */
1149 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1150 if (size > MAX_PREALLOC_SIZE)
1151 size = MAX_PREALLOC_SIZE;
1152 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1153 SNDRV_DMA_TYPE_DEV_SG,
1154 snd_dma_pci_data(skl->pci),
1155 size, MAX_PREALLOC_SIZE);
1156 if (retval) {
1157 dev_err(dai->dev, "dma buffer allocationf fail\n");
1158 return retval;
1159 }
1160 }
1161
1162 return retval;
1163 }
1164
1165 static int skl_populate_modules(struct skl *skl)
1166 {
1167 struct skl_pipeline *p;
1168 struct skl_pipe_module *m;
1169 struct snd_soc_dapm_widget *w;
1170 struct skl_module_cfg *mconfig;
1171 int ret;
1172
1173 list_for_each_entry(p, &skl->ppl_list, node) {
1174 list_for_each_entry(m, &p->pipe->w_list, node) {
1175
1176 w = m->w;
1177 mconfig = w->priv;
1178
1179 ret = snd_skl_get_module_info(skl->skl_sst, mconfig);
1180 if (ret < 0) {
1181 dev_err(skl->skl_sst->dev,
1182 "query module info failed:%d\n", ret);
1183 goto err;
1184 }
1185 }
1186 }
1187 err:
1188 return ret;
1189 }
1190
1191 static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1192 {
1193 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1194 struct skl *skl = ebus_to_skl(ebus);
1195 const struct skl_dsp_ops *ops;
1196 int ret;
1197
1198 pm_runtime_get_sync(platform->dev);
1199 if ((ebus_to_hbus(ebus))->ppcap) {
1200 ret = skl_tplg_init(platform, ebus);
1201 if (ret < 0) {
1202 dev_err(platform->dev, "Failed to init topology!\n");
1203 return ret;
1204 }
1205 skl->platform = platform;
1206
1207 /* load the firmwares, since all is set */
1208 ops = skl_get_dsp_ops(skl->pci->device);
1209 if (!ops)
1210 return -EIO;
1211
1212 if (skl->skl_sst->is_first_boot == false) {
1213 dev_err(platform->dev, "DSP reports first boot done!!!\n");
1214 return -EIO;
1215 }
1216
1217 ret = ops->init_fw(platform->dev, skl->skl_sst);
1218 if (ret < 0) {
1219 dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);
1220 return ret;
1221 }
1222 skl_populate_modules(skl);
1223 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1224 }
1225 pm_runtime_mark_last_busy(platform->dev);
1226 pm_runtime_put_autosuspend(platform->dev);
1227
1228 return 0;
1229 }
1230 static struct snd_soc_platform_driver skl_platform_drv = {
1231 .probe = skl_platform_soc_probe,
1232 .ops = &skl_platform_ops,
1233 .pcm_new = skl_pcm_new,
1234 .pcm_free = skl_pcm_free,
1235 };
1236
1237 static const struct snd_soc_component_driver skl_component = {
1238 .name = "pcm",
1239 };
1240
1241 int skl_platform_register(struct device *dev)
1242 {
1243 int ret;
1244 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1245 struct skl *skl = ebus_to_skl(ebus);
1246
1247 INIT_LIST_HEAD(&skl->ppl_list);
1248
1249 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1250 if (ret) {
1251 dev_err(dev, "soc platform registration failed %d\n", ret);
1252 return ret;
1253 }
1254 ret = snd_soc_register_component(dev, &skl_component,
1255 skl_platform_dai,
1256 ARRAY_SIZE(skl_platform_dai));
1257 if (ret) {
1258 dev_err(dev, "soc component registration failed %d\n", ret);
1259 snd_soc_unregister_platform(dev);
1260 }
1261
1262 return ret;
1263
1264 }
1265
1266 int skl_platform_unregister(struct device *dev)
1267 {
1268 snd_soc_unregister_component(dev);
1269 snd_soc_unregister_platform(dev);
1270 return 0;
1271 }
Linux with added FPC-III support