sound/soc/intel/skylake/skl-topology.h

   1 /*
   2  *  skl_topology.h - Intel HDA Platform topology header file
   3  *
   4  *  Copyright (C) 2014-15 Intel Corp
   5  *  Author: Jeeja KP <jeeja.kp@intel.com>
   6  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; version 2 of the License.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but
  13  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  *  General Public License for more details.
  16  *
  17  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  18  *
  19  */
  20
  21 #ifndef __SKL_TOPOLOGY_H__
  22 #define __SKL_TOPOLOGY_H__
  23
  24 #include <linux/types.h>
  25
  26 #include <sound/hdaudio_ext.h>
  27 #include <sound/soc.h>
  28 #include "skl.h"
  29 #include "skl-tplg-interface.h"
  30
  31 #define BITS_PER_BYTE 8
  32 #define MAX_TS_GROUPS 8
  33 #define MAX_DMIC_TS_GROUPS 4
  34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
  35
  36 /* Maximum number of coefficients up down mixer module */
  37 #define UP_DOWN_MIXER_MAX_COEFF         6
  38
  39 #define MODULE_MAX_IN_PINS      8
  40 #define MODULE_MAX_OUT_PINS     8
  41
  42 enum skl_channel_index {
  43         SKL_CHANNEL_LEFT = 0,
  44         SKL_CHANNEL_RIGHT = 1,
  45         SKL_CHANNEL_CENTER = 2,
  46         SKL_CHANNEL_LEFT_SURROUND = 3,
  47         SKL_CHANNEL_CENTER_SURROUND = 3,
  48         SKL_CHANNEL_RIGHT_SURROUND = 4,
  49         SKL_CHANNEL_LFE = 7,
  50         SKL_CHANNEL_INVALID = 0xF,
  51 };
  52
  53 enum skl_bitdepth {
  54         SKL_DEPTH_8BIT = 8,
  55         SKL_DEPTH_16BIT = 16,
  56         SKL_DEPTH_24BIT = 24,
  57         SKL_DEPTH_32BIT = 32,
  58         SKL_DEPTH_INVALID
  59 };
  60
  61
  62 enum skl_s_freq {
  63         SKL_FS_8000 = 8000,
  64         SKL_FS_11025 = 11025,
  65         SKL_FS_12000 = 12000,
  66         SKL_FS_16000 = 16000,
  67         SKL_FS_22050 = 22050,
  68         SKL_FS_24000 = 24000,
  69         SKL_FS_32000 = 32000,
  70         SKL_FS_44100 = 44100,
  71         SKL_FS_48000 = 48000,
  72         SKL_FS_64000 = 64000,
  73         SKL_FS_88200 = 88200,
  74         SKL_FS_96000 = 96000,
  75         SKL_FS_128000 = 128000,
  76         SKL_FS_176400 = 176400,
  77         SKL_FS_192000 = 192000,
  78         SKL_FS_INVALID
  79 };
  80
  81 enum skl_widget_type {
  82         SKL_WIDGET_VMIXER = 1,
  83         SKL_WIDGET_MIXER = 2,
  84         SKL_WIDGET_PGA = 3,
  85         SKL_WIDGET_MUX = 4
  86 };
  87
  88 struct skl_audio_data_format {
  89         enum skl_s_freq s_freq;
  90         enum skl_bitdepth bit_depth;
  91         u32 channel_map;
  92         enum skl_ch_cfg ch_cfg;
  93         enum skl_interleaving interleaving;
  94         u8 number_of_channels;
  95         u8 valid_bit_depth;
  96         u8 sample_type;
  97         u8 reserved[1];
  98 } __packed;
  99
 100 struct skl_base_cfg {
 101         u32 cps;
 102         u32 ibs;
 103         u32 obs;
 104         u32 is_pages;
 105         struct skl_audio_data_format audio_fmt;
 106 };
 107
 108 struct skl_cpr_gtw_cfg {
 109         u32 node_id;
 110         u32 dma_buffer_size;
 111         u32 config_length;
 112         /* not mandatory; required only for DMIC/I2S */
 113         u32 config_data[1];
 114 } __packed;
 115
 116 struct skl_dma_control {
 117         u32 node_id;
 118         u32 config_length;
 119         u32 config_data[0];
 120 } __packed;
 121
 122 struct skl_cpr_cfg {
 123         struct skl_base_cfg base_cfg;
 124         struct skl_audio_data_format out_fmt;
 125         u32 cpr_feature_mask;
 126         struct skl_cpr_gtw_cfg gtw_cfg;
 127 } __packed;
 128
 129
 130 struct skl_src_module_cfg {
 131         struct skl_base_cfg base_cfg;
 132         enum skl_s_freq src_cfg;
 133 } __packed;
 134
 135 struct notification_mask {
 136         u32 notify;
 137         u32 enable;
 138 } __packed;
 139
 140 struct skl_up_down_mixer_cfg {
 141         struct skl_base_cfg base_cfg;
 142         enum skl_ch_cfg out_ch_cfg;
 143         /* This should be set to 1 if user coefficients are required */
 144         u32 coeff_sel;
 145         /* Pass the user coeff in this array */
 146         s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
 147 } __packed;
 148
 149 struct skl_algo_cfg {
 150         struct skl_base_cfg  base_cfg;
 151         char params[0];
 152 } __packed;
 153
 154 struct skl_base_outfmt_cfg {
 155         struct skl_base_cfg base_cfg;
 156         struct skl_audio_data_format out_fmt;
 157 } __packed;
 158
 159 enum skl_dma_type {
 160         SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
 161         SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
 162         SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
 163         SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
 164         SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
 165         SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
 166         SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
 167         SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
 168         SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
 169 };
 170
 171 union skl_ssp_dma_node {
 172         u8 val;
 173         struct {
 174                 u8 time_slot_index:4;
 175                 u8 i2s_instance:4;
 176         } dma_node;
 177 };
 178
 179 union skl_connector_node_id {
 180         u32 val;
 181         struct {
 182                 u32 vindex:8;
 183                 u32 dma_type:4;
 184                 u32 rsvd:20;
 185         } node;
 186 };
 187
 188 struct skl_module_fmt {
 189         u32 channels;
 190         u32 s_freq;
 191         u32 bit_depth;
 192         u32 valid_bit_depth;
 193         u32 ch_cfg;
 194         u32 interleaving_style;
 195         u32 sample_type;
 196         u32 ch_map;
 197 };
 198
 199 struct skl_module_cfg;
 200
 201 struct skl_mod_inst_map {
 202         u16 mod_id;
 203         u16 inst_id;
 204 };
 205
 206 struct skl_kpb_params {
 207         u32 num_modules;
 208         struct skl_mod_inst_map map[0];
 209 };
 210
 211 struct skl_module_inst_id {
 212         int module_id;
 213         u32 instance_id;
 214         int pvt_id;
 215 };
 216
 217 enum skl_module_pin_state {
 218         SKL_PIN_UNBIND = 0,
 219         SKL_PIN_BIND_DONE = 1,
 220 };
 221
 222 struct skl_module_pin {
 223         struct skl_module_inst_id id;
 224         bool is_dynamic;
 225         bool in_use;
 226         enum skl_module_pin_state pin_state;
 227         struct skl_module_cfg *tgt_mcfg;
 228 };
 229
 230 struct skl_specific_cfg {
 231         u32 set_params;
 232         u32 param_id;
 233         u32 caps_size;
 234         u32 *caps;
 235 };
 236
 237 enum skl_pipe_state {
 238         SKL_PIPE_INVALID = 0,
 239         SKL_PIPE_CREATED = 1,
 240         SKL_PIPE_PAUSED = 2,
 241         SKL_PIPE_STARTED = 3,
 242         SKL_PIPE_RESET = 4
 243 };
 244
 245 struct skl_pipe_module {
 246         struct snd_soc_dapm_widget *w;
 247         struct list_head node;
 248 };
 249
 250 struct skl_pipe_params {
 251         u8 host_dma_id;
 252         u8 link_dma_id;
 253         u32 ch;
 254         u32 s_freq;
 255         u32 s_fmt;
 256         u8 linktype;
 257         int stream;
 258 };
 259
 260 struct skl_pipe {
 261         u8 ppl_id;
 262         u8 pipe_priority;
 263         u16 conn_type;
 264         u32 memory_pages;
 265         u8 lp_mode;
 266         struct skl_pipe_params *p_params;
 267         enum skl_pipe_state state;
 268         struct list_head w_list;
 269         bool passthru;
 270 };
 271
 272 enum skl_module_state {
 273         SKL_MODULE_UNINIT = 0,
 274         SKL_MODULE_LOADED = 1,
 275         SKL_MODULE_INIT_DONE = 2,
 276         SKL_MODULE_BIND_DONE = 3,
 277         SKL_MODULE_UNLOADED = 4,
 278 };
 279
 280 enum d0i3_capability {
 281         SKL_D0I3_NONE = 0,
 282         SKL_D0I3_STREAMING = 1,
 283         SKL_D0I3_NON_STREAMING = 2,
 284 };
 285
 286 struct skl_module_cfg {
 287         u8 guid[16];
 288         struct skl_module_inst_id id;
 289         u8 domain;
 290         bool homogenous_inputs;
 291         bool homogenous_outputs;
 292         struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
 293         struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
 294         u8 max_in_queue;
 295         u8 max_out_queue;
 296         u8 in_queue_mask;
 297         u8 out_queue_mask;
 298         u8 in_queue;
 299         u8 out_queue;
 300         u32 mcps;
 301         u32 ibs;
 302         u32 obs;
 303         u8 is_loadable;
 304         u8 core_id;
 305         u8 dev_type;
 306         u8 dma_id;
 307         u8 time_slot;
 308         u32 params_fixup;
 309         u32 converter;
 310         u32 vbus_id;
 311         u32 mem_pages;
 312         enum d0i3_capability d0i3_caps;
 313         struct skl_module_pin *m_in_pin;
 314         struct skl_module_pin *m_out_pin;
 315         enum skl_module_type m_type;
 316         enum skl_hw_conn_type  hw_conn_type;
 317         enum skl_module_state m_state;
 318         struct skl_pipe *pipe;
 319         struct skl_specific_cfg formats_config;
 320 };
 321
 322 struct skl_algo_data {
 323         u32 param_id;
 324         u32 set_params;
 325         u32 max;
 326         u32 size;
 327         char *params;
 328 };
 329
 330 struct skl_pipeline {
 331         struct skl_pipe *pipe;
 332         struct list_head node;
 333 };
 334
 335 static inline struct skl *get_skl_ctx(struct device *dev)
 336 {
 337         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
 338
 339         return ebus_to_skl(ebus);
 340 }
 341
 342 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
 343         struct skl_pipe_params *params);
 344 int skl_dsp_set_dma_control(struct skl_sst *ctx,
 345                 struct skl_module_cfg *mconfig);
 346 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
 347         struct skl_pipe_params *params, int stream);
 348 int skl_tplg_init(struct snd_soc_platform *platform,
 349                                 struct hdac_ext_bus *ebus);
 350 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
 351                 struct snd_soc_dai *dai, int stream);
 352 int skl_tplg_update_pipe_params(struct device *dev,
 353                 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
 354
 355 void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps);
 356 void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps);
 357
 358 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
 359
 360 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 361
 362 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 363
 364 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 365
 366 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 367
 368 int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 369
 370 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
 371
 372 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
 373         *src_module, struct skl_module_cfg *dst_module);
 374
 375 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
 376         *src_module, struct skl_module_cfg *dst_module);
 377
 378 int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
 379                         u32 param_id, struct skl_module_cfg *mcfg);
 380 int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
 381                           u32 param_id, struct skl_module_cfg *mcfg);
 382
 383 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
 384                                                                 int stream);
 385 enum skl_bitdepth skl_get_bit_depth(int params);
 386 #endif