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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / sound / soc / mediatek / mt2701 / mt2701-afe-clock-ctrl.c
blobb815ecc6bbf6b39eb279d08fdb9ee5384bdda48f
1 /*
2 * mt2701-afe-clock-ctrl.c -- Mediatek 2701 afe clock ctrl
3 *
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <sound/soc.h>
18 #include <linux/regmap.h>
19 #include <linux/pm_runtime.h>
20
21 #include "mt2701-afe-common.h"
22 #include "mt2701-afe-clock-ctrl.h"
23
24 static const char *aud_clks[MT2701_CLOCK_NUM] = {
25 [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
26 [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
27 [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
28 [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
29 [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
30 [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
31 [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
32 [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
33 [MT2701_AUD_APLL_SEL] = "top_apll_sel",
34 [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
35 [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
36 [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
37 [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
38 [MT2701_AUD_AUDPLL] = "top_audpll",
39 [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
40 [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
41 [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
42 [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
43 [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
44 [MT2701_AUD_CLK_26M] = "clk_26m",
45 [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
46 [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
47 [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
48 [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
49 [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
50 [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
51 [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
52 [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
53 [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
54 [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
55 [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
56 [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
57 [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
58 [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
59 [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
60 [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
61 [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
62 [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
63 [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
64 [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
65 [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
66 [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
67 [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
68 [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
69 };
70
71 int mt2701_init_clock(struct mtk_base_afe *afe)
72 {
73 struct mt2701_afe_private *afe_priv = afe->platform_priv;
74 int i = 0;
75
76 for (i = 0; i < MT2701_CLOCK_NUM; i++) {
77 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
78 if (IS_ERR(aud_clks[i])) {
79 dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
80 __func__, aud_clks[i]);
81 return PTR_ERR(aud_clks[i]);
82 }
83 }
84
85 return 0;
86 }
87
88 int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
89 {
90 int ret = 0;
91
92 ret = mt2701_turn_on_a1sys_clock(afe);
93 if (ret) {
94 dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
95 __func__, ret);
96 return ret;
97 }
98
99 ret = mt2701_turn_on_a2sys_clock(afe);
100 if (ret) {
101 dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n",
102 __func__, ret);
103 mt2701_turn_off_a1sys_clock(afe);
104 return ret;
105 }
106
107 ret = mt2701_turn_on_afe_clock(afe);
108 if (ret) {
109 dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
110 __func__, ret);
111 mt2701_turn_off_a1sys_clock(afe);
112 mt2701_turn_off_a2sys_clock(afe);
113 return ret;
114 }
115
116 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
117 AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
118 AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
119 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
120 AFE_DAC_CON0_AFE_ON,
121 AFE_DAC_CON0_AFE_ON);
122 regmap_write(afe->regmap, PWR2_TOP_CON,
123 PWR2_TOP_CON_INIT_VAL);
124 regmap_write(afe->regmap, PWR1_ASM_CON1,
125 PWR1_ASM_CON1_INIT_VAL);
126 regmap_write(afe->regmap, PWR2_ASM_CON1,
127 PWR2_ASM_CON1_INIT_VAL);
128
129 return 0;
130 }
131
132 void mt2701_afe_disable_clock(struct mtk_base_afe *afe)
133 {
134 mt2701_turn_off_afe_clock(afe);
135 mt2701_turn_off_a1sys_clock(afe);
136 mt2701_turn_off_a2sys_clock(afe);
137 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
138 AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
139 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
140 AFE_DAC_CON0_AFE_ON, 0);
141 }
142
143 int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe)
144 {
145 struct mt2701_afe_private *afe_priv = afe->platform_priv;
146 int ret = 0;
147
148 /* Set Mux */
149 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
150 if (ret) {
151 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
152 __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
153 goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
154 }
155
156 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
157 afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
158 if (ret) {
159 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
160 aud_clks[MT2701_AUD_AUD_MUX1_SEL],
161 aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
162 goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
163 }
164
165 /* Set Divider */
166 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
167 if (ret) {
168 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
169 __func__,
170 aud_clks[MT2701_AUD_AUD_MUX1_DIV],
171 ret);
172 goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
173 }
174
175 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
176 MT2701_AUD_AUD_MUX1_DIV_RATE);
177 if (ret) {
178 dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
179 aud_clks[MT2701_AUD_AUD_MUX1_DIV],
180 MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
181 goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
182 }
183
184 /* Enable clock gate */
185 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
186 if (ret) {
187 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
188 __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
189 goto A1SYS_CLK_AUD_48K_ERR;
190 }
191
192 /* Enable infra audio */
193 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
194 if (ret) {
195 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
196 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
197 goto A1SYS_CLK_INFRA_ERR;
198 }
199
200 return 0;
201
202 A1SYS_CLK_INFRA_ERR:
203 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
204 A1SYS_CLK_AUD_48K_ERR:
205 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
206 A1SYS_CLK_AUD_MUX1_DIV_ERR:
207 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
208 A1SYS_CLK_AUD_MUX1_SEL_ERR:
209 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
210
211 return ret;
212 }
213
214 void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe)
215 {
216 struct mt2701_afe_private *afe_priv = afe->platform_priv;
217
218 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
219 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
220 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
221 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
222 }
223
224 int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe)
225 {
226 struct mt2701_afe_private *afe_priv = afe->platform_priv;
227 int ret = 0;
228
229 /* Set Mux */
230 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
231 if (ret) {
232 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
233 __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
234 goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
235 }
236
237 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL],
238 afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]);
239 if (ret) {
240 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
241 aud_clks[MT2701_AUD_AUD_MUX2_SEL],
242 aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
243 goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
244 }
245
246 /* Set Divider */
247 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
248 if (ret) {
249 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
250 __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
251 goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
252 }
253
254 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV],
255 MT2701_AUD_AUD_MUX2_DIV_RATE);
256 if (ret) {
257 dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
258 aud_clks[MT2701_AUD_AUD_MUX2_DIV],
259 MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
260 goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
261 }
262
263 /* Enable clock gate */
264 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
265 if (ret) {
266 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
267 __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
268 goto A2SYS_CLK_AUD_44K_ERR;
269 }
270
271 /* Enable infra audio */
272 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
273 if (ret) {
274 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
275 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
276 goto A2SYS_CLK_INFRA_ERR;
277 }
278
279 return 0;
280
281 A2SYS_CLK_INFRA_ERR:
282 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
283 A2SYS_CLK_AUD_44K_ERR:
284 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
285 A2SYS_CLK_AUD_MUX2_DIV_ERR:
286 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
287 A2SYS_CLK_AUD_MUX2_SEL_ERR:
288 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
289
290 return ret;
291 }
292
293 void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe)
294 {
295 struct mt2701_afe_private *afe_priv = afe->platform_priv;
296
297 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
298 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
299 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
300 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
301 }
302
303 int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe)
304 {
305 struct mt2701_afe_private *afe_priv = afe->platform_priv;
306 int ret;
307
308 /* enable INFRA_SYS */
309 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
310 if (ret) {
311 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
312 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
313 goto AFE_AUD_INFRA_ERR;
314 }
315
316 /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
317 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
318 if (ret) {
319 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
320 __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
321 goto AFE_AUD_AUDINTBUS_ERR;
322 }
323
324 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
325 afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
326 if (ret) {
327 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
328 aud_clks[MT2701_AUD_AUDINTBUS],
329 aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
330 goto AFE_AUD_AUDINTBUS_ERR;
331 }
332
333 /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
334 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
335 if (ret) {
336 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
337 __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret);
338 goto AFE_AUD_ASM_H_ERR;
339 }
340
341 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
342 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
343 if (ret) {
344 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
345 aud_clks[MT2701_AUD_ASM_H_SEL],
346 aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
347 goto AFE_AUD_ASM_H_ERR;
348 }
349
350 /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
351 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
352 if (ret) {
353 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
354 __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
355 goto AFE_AUD_ASM_M_ERR;
356 }
357
358 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL],
359 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]);
360 if (ret) {
361 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
362 aud_clks[MT2701_AUD_ASM_M_SEL],
363 aud_clks[MT2701_AUD_UNIVPLL2_D4], ret);
364 goto AFE_AUD_ASM_M_ERR;
365 }
366
367 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
368 AUDIO_TOP_CON0_PDN_AFE, 0);
369 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
370 AUDIO_TOP_CON0_PDN_APLL_CK, 0);
371 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
372 AUDIO_TOP_CON4_PDN_A1SYS, 0);
373 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
374 AUDIO_TOP_CON4_PDN_A2SYS, 0);
375 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
376 AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
377
378 return 0;
379
380 AFE_AUD_ASM_M_ERR:
381 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
382 AFE_AUD_ASM_H_ERR:
383 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
384 AFE_AUD_AUDINTBUS_ERR:
385 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
386 AFE_AUD_INFRA_ERR:
387 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
388
389 return ret;
390 }
391
392 void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe)
393 {
394 struct mt2701_afe_private *afe_priv = afe->platform_priv;
395
396 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
397
398 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
399 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
400 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
401
402 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
403 AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
404 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
405 AUDIO_TOP_CON0_PDN_APLL_CK,
406 AUDIO_TOP_CON0_PDN_APLL_CK);
407 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
408 AUDIO_TOP_CON4_PDN_A1SYS,
409 AUDIO_TOP_CON4_PDN_A1SYS);
410 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
411 AUDIO_TOP_CON4_PDN_A2SYS,
412 AUDIO_TOP_CON4_PDN_A2SYS);
413 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
414 AUDIO_TOP_CON4_PDN_AFE_CONN,
415 AUDIO_TOP_CON4_PDN_AFE_CONN);
416 }
417
418 void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
419 int mclk)
420 {
421 struct mt2701_afe_private *afe_priv = afe->platform_priv;
422 int ret;
423 int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
424 int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
425
426 /* Set MCLK Kx_SRC_SEL(domain) */
427 ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]);
428 if (ret)
429 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
430 __func__, aud_clks[aud_src_clk_id], ret);
431
432 if (domain == 0) {
433 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
434 afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
435 if (ret)
436 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
437 __func__, aud_clks[aud_src_clk_id],
438 aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
439 } else {
440 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
441 afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
442 if (ret)
443 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
444 __func__, aud_clks[aud_src_clk_id],
445 aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
446 }
447 clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
448
449 /* Set MCLK Kx_SRC_DIV(divider) */
450 ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
451 if (ret)
452 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
453 __func__, aud_clks[aud_src_div_id], ret);
454
455 ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk);
456 if (ret)
457 dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__,
458 aud_clks[aud_src_div_id], mclk, ret);
459 clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
460 }
461
462 MODULE_DESCRIPTION("MT2701 afe clock control");
463 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
464 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support