sound/soc/omap/mcbsp.c

   1 /*
   2  * sound/soc/omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Multichannel mode not supported.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27 #include <linux/pm_runtime.h>
  28
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30
  31 #include "mcbsp.h"
  32
  33 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  34 {
  35         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  36
  37         if (mcbsp->pdata->reg_size == 2) {
  38                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  39                 writew_relaxed((u16)val, addr);
  40         } else {
  41                 ((u32 *)mcbsp->reg_cache)[reg] = val;
  42                 writel_relaxed(val, addr);
  43         }
  44 }
  45
  46 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  47 {
  48         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  49
  50         if (mcbsp->pdata->reg_size == 2) {
  51                 return !from_cache ? readw_relaxed(addr) :
  52                                      ((u16 *)mcbsp->reg_cache)[reg];
  53         } else {
  54                 return !from_cache ? readl_relaxed(addr) :
  55                                      ((u32 *)mcbsp->reg_cache)[reg];
  56         }
  57 }
  58
  59 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  60 {
  61         writel_relaxed(val, mcbsp->st_data->io_base_st + reg);
  62 }
  63
  64 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  65 {
  66         return readl_relaxed(mcbsp->st_data->io_base_st + reg);
  67 }
  68
  69 #define MCBSP_READ(mcbsp, reg) \
  70                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  71 #define MCBSP_WRITE(mcbsp, reg, val) \
  72                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  73 #define MCBSP_READ_CACHE(mcbsp, reg) \
  74                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  75
  76 #define MCBSP_ST_READ(mcbsp, reg) \
  77                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  78 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  79                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  80
  81 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  82 {
  83         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  84         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  85                         MCBSP_READ(mcbsp, DRR2));
  86         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  87                         MCBSP_READ(mcbsp, DRR1));
  88         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  89                         MCBSP_READ(mcbsp, DXR2));
  90         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  91                         MCBSP_READ(mcbsp, DXR1));
  92         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  93                         MCBSP_READ(mcbsp, SPCR2));
  94         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  95                         MCBSP_READ(mcbsp, SPCR1));
  96         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  97                         MCBSP_READ(mcbsp, RCR2));
  98         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  99                         MCBSP_READ(mcbsp, RCR1));
 100         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 101                         MCBSP_READ(mcbsp, XCR2));
 102         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 103                         MCBSP_READ(mcbsp, XCR1));
 104         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 105                         MCBSP_READ(mcbsp, SRGR2));
 106         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 107                         MCBSP_READ(mcbsp, SRGR1));
 108         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 109                         MCBSP_READ(mcbsp, PCR0));
 110         dev_dbg(mcbsp->dev, "***********************\n");
 111 }
 112
 113 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
 114 {
 115         struct omap_mcbsp *mcbsp = dev_id;
 116         u16 irqst;
 117
 118         irqst = MCBSP_READ(mcbsp, IRQST);
 119         dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
 120
 121         if (irqst & RSYNCERREN)
 122                 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 123         if (irqst & RFSREN)
 124                 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 125         if (irqst & REOFEN)
 126                 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 127         if (irqst & RRDYEN)
 128                 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 129         if (irqst & RUNDFLEN)
 130                 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 131         if (irqst & ROVFLEN)
 132                 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 133
 134         if (irqst & XSYNCERREN)
 135                 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 136         if (irqst & XFSXEN)
 137                 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 138         if (irqst & XEOFEN)
 139                 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 140         if (irqst & XRDYEN)
 141                 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 142         if (irqst & XUNDFLEN)
 143                 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 144         if (irqst & XOVFLEN)
 145                 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 146         if (irqst & XEMPTYEOFEN)
 147                 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 148
 149         MCBSP_WRITE(mcbsp, IRQST, irqst);
 150
 151         return IRQ_HANDLED;
 152 }
 153
 154 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 155 {
 156         struct omap_mcbsp *mcbsp_tx = dev_id;
 157         u16 irqst_spcr2;
 158
 159         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 160         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 161
 162         if (irqst_spcr2 & XSYNC_ERR) {
 163                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 164                         irqst_spcr2);
 165                 /* Writing zero to XSYNC_ERR clears the IRQ */
 166                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 167         }
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 173 {
 174         struct omap_mcbsp *mcbsp_rx = dev_id;
 175         u16 irqst_spcr1;
 176
 177         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 178         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 179
 180         if (irqst_spcr1 & RSYNC_ERR) {
 181                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 182                         irqst_spcr1);
 183                 /* Writing zero to RSYNC_ERR clears the IRQ */
 184                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 185         }
 186
 187         return IRQ_HANDLED;
 188 }
 189
 190 /*
 191  * omap_mcbsp_config simply write a config to the
 192  * appropriate McBSP.
 193  * You either call this function or set the McBSP registers
 194  * by yourself before calling omap_mcbsp_start().
 195  */
 196 void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 197                        const struct omap_mcbsp_reg_cfg *config)
 198 {
 199         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 200                         mcbsp->id, mcbsp->phys_base);
 201
 202         /* We write the given config */
 203         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 204         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 205         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 206         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 207         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 208         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 209         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 210         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 211         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 212         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 213         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 214         if (mcbsp->pdata->has_ccr) {
 215                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 216                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 217         }
 218         /* Enable wakeup behavior */
 219         if (mcbsp->pdata->has_wakeup)
 220                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 221
 222         /* Enable TX/RX sync error interrupts by default */
 223         if (mcbsp->irq)
 224                 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
 225                             RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
 226 }
 227
 228 /**
 229  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 230  * @id - mcbsp id
 231  * @stream - indicates the direction of data flow (rx or tx)
 232  *
 233  * Returns the address of mcbsp data transmit register or data receive register
 234  * to be used by DMA for transferring/receiving data based on the value of
 235  * @stream for the requested mcbsp given by @id
 236  */
 237 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 238                                      unsigned int stream)
 239 {
 240         int data_reg;
 241
 242         if (mcbsp->pdata->reg_size == 2) {
 243                 if (stream)
 244                         data_reg = OMAP_MCBSP_REG_DRR1;
 245                 else
 246                         data_reg = OMAP_MCBSP_REG_DXR1;
 247         } else {
 248                 if (stream)
 249                         data_reg = OMAP_MCBSP_REG_DRR;
 250                 else
 251                         data_reg = OMAP_MCBSP_REG_DXR;
 252         }
 253
 254         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 255 }
 256
 257 static void omap_st_on(struct omap_mcbsp *mcbsp)
 258 {
 259         unsigned int w;
 260
 261         if (mcbsp->pdata->force_ick_on)
 262                 mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, true);
 263
 264         /* Disable Sidetone clock auto-gating for normal operation */
 265         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 266         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 267
 268         /* Enable McBSP Sidetone */
 269         w = MCBSP_READ(mcbsp, SSELCR);
 270         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 271
 272         /* Enable Sidetone from Sidetone Core */
 273         w = MCBSP_ST_READ(mcbsp, SSELCR);
 274         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 275 }
 276
 277 static void omap_st_off(struct omap_mcbsp *mcbsp)
 278 {
 279         unsigned int w;
 280
 281         w = MCBSP_ST_READ(mcbsp, SSELCR);
 282         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 283
 284         w = MCBSP_READ(mcbsp, SSELCR);
 285         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 286
 287         /* Enable Sidetone clock auto-gating to reduce power consumption */
 288         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 289         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 290
 291         if (mcbsp->pdata->force_ick_on)
 292                 mcbsp->pdata->force_ick_on(mcbsp->st_data->mcbsp_iclk, false);
 293 }
 294
 295 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 296 {
 297         u16 val, i;
 298
 299         val = MCBSP_ST_READ(mcbsp, SSELCR);
 300
 301         if (val & ST_COEFFWREN)
 302                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 303
 304         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 305
 306         for (i = 0; i < 128; i++)
 307                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 308
 309         i = 0;
 310
 311         val = MCBSP_ST_READ(mcbsp, SSELCR);
 312         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 313                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 314
 315         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 316
 317         if (i == 1000)
 318                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 319 }
 320
 321 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 322 {
 323         u16 w;
 324         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 325
 326         w = MCBSP_ST_READ(mcbsp, SSELCR);
 327
 328         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 329                       ST_CH1GAIN(st_data->ch1gain));
 330 }
 331
 332 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
 333 {
 334         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 335         int ret = 0;
 336
 337         if (!st_data)
 338                 return -ENOENT;
 339
 340         spin_lock_irq(&mcbsp->lock);
 341         if (channel == 0)
 342                 st_data->ch0gain = chgain;
 343         else if (channel == 1)
 344                 st_data->ch1gain = chgain;
 345         else
 346                 ret = -EINVAL;
 347
 348         if (st_data->enabled)
 349                 omap_st_chgain(mcbsp);
 350         spin_unlock_irq(&mcbsp->lock);
 351
 352         return ret;
 353 }
 354
 355 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
 356 {
 357         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 358         int ret = 0;
 359
 360         if (!st_data)
 361                 return -ENOENT;
 362
 363         spin_lock_irq(&mcbsp->lock);
 364         if (channel == 0)
 365                 *chgain = st_data->ch0gain;
 366         else if (channel == 1)
 367                 *chgain = st_data->ch1gain;
 368         else
 369                 ret = -EINVAL;
 370         spin_unlock_irq(&mcbsp->lock);
 371
 372         return ret;
 373 }
 374
 375 static int omap_st_start(struct omap_mcbsp *mcbsp)
 376 {
 377         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 378
 379         if (st_data->enabled && !st_data->running) {
 380                 omap_st_fir_write(mcbsp, st_data->taps);
 381                 omap_st_chgain(mcbsp);
 382
 383                 if (!mcbsp->free) {
 384                         omap_st_on(mcbsp);
 385                         st_data->running = 1;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 int omap_st_enable(struct omap_mcbsp *mcbsp)
 393 {
 394         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 395
 396         if (!st_data)
 397                 return -ENODEV;
 398
 399         spin_lock_irq(&mcbsp->lock);
 400         st_data->enabled = 1;
 401         omap_st_start(mcbsp);
 402         spin_unlock_irq(&mcbsp->lock);
 403
 404         return 0;
 405 }
 406
 407 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 408 {
 409         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 410
 411         if (st_data->running) {
 412                 if (!mcbsp->free) {
 413                         omap_st_off(mcbsp);
 414                         st_data->running = 0;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 int omap_st_disable(struct omap_mcbsp *mcbsp)
 422 {
 423         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 424         int ret = 0;
 425
 426         if (!st_data)
 427                 return -ENODEV;
 428
 429         spin_lock_irq(&mcbsp->lock);
 430         omap_st_stop(mcbsp);
 431         st_data->enabled = 0;
 432         spin_unlock_irq(&mcbsp->lock);
 433
 434         return ret;
 435 }
 436
 437 int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
 438 {
 439         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 440
 441         if (!st_data)
 442                 return -ENODEV;
 443
 444         return st_data->enabled;
 445 }
 446
 447 /*
 448  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 449  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 450  * for the THRSH2 register.
 451  */
 452 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 453 {
 454         if (mcbsp->pdata->buffer_size == 0)
 455                 return;
 456
 457         if (threshold && threshold <= mcbsp->max_tx_thres)
 458                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 459 }
 460
 461 /*
 462  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 463  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 464  * for the THRSH1 register.
 465  */
 466 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 467 {
 468         if (mcbsp->pdata->buffer_size == 0)
 469                 return;
 470
 471         if (threshold && threshold <= mcbsp->max_rx_thres)
 472                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 473 }
 474
 475 /*
 476  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 477  */
 478 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 479 {
 480         u16 buffstat;
 481
 482         if (mcbsp->pdata->buffer_size == 0)
 483                 return 0;
 484
 485         /* Returns the number of free locations in the buffer */
 486         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 487
 488         /* Number of slots are different in McBSP ports */
 489         return mcbsp->pdata->buffer_size - buffstat;
 490 }
 491
 492 /*
 493  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 494  * to reach the threshold value (when the DMA will be triggered to read it)
 495  */
 496 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 497 {
 498         u16 buffstat, threshold;
 499
 500         if (mcbsp->pdata->buffer_size == 0)
 501                 return 0;
 502
 503         /* Returns the number of used locations in the buffer */
 504         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 505         /* RX threshold */
 506         threshold = MCBSP_READ(mcbsp, THRSH1);
 507
 508         /* Return the number of location till we reach the threshold limit */
 509         if (threshold <= buffstat)
 510                 return 0;
 511         else
 512                 return threshold - buffstat;
 513 }
 514
 515 int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 516 {
 517         void *reg_cache;
 518         int err;
 519
 520         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 521         if (!reg_cache) {
 522                 return -ENOMEM;
 523         }
 524
 525         spin_lock(&mcbsp->lock);
 526         if (!mcbsp->free) {
 527                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 528                         mcbsp->id);
 529                 err = -EBUSY;
 530                 goto err_kfree;
 531         }
 532
 533         mcbsp->free = false;
 534         mcbsp->reg_cache = reg_cache;
 535         spin_unlock(&mcbsp->lock);
 536
 537         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 538                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 539
 540         /*
 541          * Make sure that transmitter, receiver and sample-rate generator are
 542          * not running before activating IRQs.
 543          */
 544         MCBSP_WRITE(mcbsp, SPCR1, 0);
 545         MCBSP_WRITE(mcbsp, SPCR2, 0);
 546
 547         if (mcbsp->irq) {
 548                 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 549                                   "McBSP", (void *)mcbsp);
 550                 if (err != 0) {
 551                         dev_err(mcbsp->dev, "Unable to request IRQ\n");
 552                         goto err_clk_disable;
 553                 }
 554         } else {
 555                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 556                                   "McBSP TX", (void *)mcbsp);
 557                 if (err != 0) {
 558                         dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 559                         goto err_clk_disable;
 560                 }
 561
 562                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 563                                   "McBSP RX", (void *)mcbsp);
 564                 if (err != 0) {
 565                         dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 566                         goto err_free_irq;
 567                 }
 568         }
 569
 570         return 0;
 571 err_free_irq:
 572         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 573 err_clk_disable:
 574         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 575                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 576
 577         /* Disable wakeup behavior */
 578         if (mcbsp->pdata->has_wakeup)
 579                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 580
 581         spin_lock(&mcbsp->lock);
 582         mcbsp->free = true;
 583         mcbsp->reg_cache = NULL;
 584 err_kfree:
 585         spin_unlock(&mcbsp->lock);
 586         kfree(reg_cache);
 587
 588         return err;
 589 }
 590
 591 void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 592 {
 593         void *reg_cache;
 594
 595         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 596                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 597
 598         /* Disable wakeup behavior */
 599         if (mcbsp->pdata->has_wakeup)
 600                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 601
 602         /* Disable interrupt requests */
 603         if (mcbsp->irq)
 604                 MCBSP_WRITE(mcbsp, IRQEN, 0);
 605
 606         if (mcbsp->irq) {
 607                 free_irq(mcbsp->irq, (void *)mcbsp);
 608         } else {
 609                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 610                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 611         }
 612
 613         reg_cache = mcbsp->reg_cache;
 614
 615         /*
 616          * Select CLKS source from internal source unconditionally before
 617          * marking the McBSP port as free.
 618          * If the external clock source via MCBSP_CLKS pin has been selected the
 619          * system will refuse to enter idle if the CLKS pin source is not reset
 620          * back to internal source.
 621          */
 622         if (!mcbsp_omap1())
 623                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 624
 625         spin_lock(&mcbsp->lock);
 626         if (mcbsp->free)
 627                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 628         else
 629                 mcbsp->free = true;
 630         mcbsp->reg_cache = NULL;
 631         spin_unlock(&mcbsp->lock);
 632
 633         kfree(reg_cache);
 634 }
 635
 636 /*
 637  * Here we start the McBSP, by enabling transmitter, receiver or both.
 638  * If no transmitter or receiver is active prior calling, then sample-rate
 639  * generator and frame sync are started.
 640  */
 641 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
 642 {
 643         int enable_srg = 0;
 644         u16 w;
 645
 646         if (mcbsp->st_data)
 647                 omap_st_start(mcbsp);
 648
 649         /* Only enable SRG, if McBSP is master */
 650         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 651         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 652                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 653                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 654
 655         if (enable_srg) {
 656                 /* Start the sample generator */
 657                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 658                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 659         }
 660
 661         /* Enable transmitter and receiver */
 662         tx &= 1;
 663         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 664         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 665
 666         rx &= 1;
 667         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 668         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 669
 670         /*
 671          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 672          * REVISIT: 100us may give enough time for two CLKSRG, however
 673          * due to some unknown PM related, clock gating etc. reason it
 674          * is now at 500us.
 675          */
 676         udelay(500);
 677
 678         if (enable_srg) {
 679                 /* Start frame sync */
 680                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 681                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 682         }
 683
 684         if (mcbsp->pdata->has_ccr) {
 685                 /* Release the transmitter and receiver */
 686                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 687                 w &= ~(tx ? XDISABLE : 0);
 688                 MCBSP_WRITE(mcbsp, XCCR, w);
 689                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 690                 w &= ~(rx ? RDISABLE : 0);
 691                 MCBSP_WRITE(mcbsp, RCCR, w);
 692         }
 693
 694         /* Dump McBSP Regs */
 695         omap_mcbsp_dump_reg(mcbsp);
 696 }
 697
 698 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 699 {
 700         int idle;
 701         u16 w;
 702
 703         /* Reset transmitter */
 704         tx &= 1;
 705         if (mcbsp->pdata->has_ccr) {
 706                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 707                 w |= (tx ? XDISABLE : 0);
 708                 MCBSP_WRITE(mcbsp, XCCR, w);
 709         }
 710         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 711         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 712
 713         /* Reset receiver */
 714         rx &= 1;
 715         if (mcbsp->pdata->has_ccr) {
 716                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 717                 w |= (rx ? RDISABLE : 0);
 718                 MCBSP_WRITE(mcbsp, RCCR, w);
 719         }
 720         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 721         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 722
 723         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 724                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 725
 726         if (idle) {
 727                 /* Reset the sample rate generator */
 728                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 729                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 730         }
 731
 732         if (mcbsp->st_data)
 733                 omap_st_stop(mcbsp);
 734 }
 735
 736 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 737 {
 738         struct clk *fck_src;
 739         const char *src;
 740         int r;
 741
 742         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
 743                 src = "pad_fck";
 744         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
 745                 src = "prcm_fck";
 746         else
 747                 return -EINVAL;
 748
 749         fck_src = clk_get(mcbsp->dev, src);
 750         if (IS_ERR(fck_src)) {
 751                 dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
 752                 return -EINVAL;
 753         }
 754
 755         pm_runtime_put_sync(mcbsp->dev);
 756
 757         r = clk_set_parent(mcbsp->fclk, fck_src);
 758         if (r) {
 759                 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
 760                         src);
 761                 clk_put(fck_src);
 762                 return r;
 763         }
 764
 765         pm_runtime_get_sync(mcbsp->dev);
 766
 767         clk_put(fck_src);
 768
 769         return 0;
 770
 771 }
 772
 773 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 774 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 775 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 776 static ssize_t prop##_show(struct device *dev,                          \
 777                         struct device_attribute *attr, char *buf)       \
 778 {                                                                       \
 779         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 780                                                                         \
 781         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 782 }                                                                       \
 783                                                                         \
 784 static ssize_t prop##_store(struct device *dev,                         \
 785                                 struct device_attribute *attr,          \
 786                                 const char *buf, size_t size)           \
 787 {                                                                       \
 788         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 789         unsigned long val;                                              \
 790         int status;                                                     \
 791                                                                         \
 792         status = kstrtoul(buf, 0, &val);                                \
 793         if (status)                                                     \
 794                 return status;                                          \
 795                                                                         \
 796         if (!valid_threshold(mcbsp, val))                               \
 797                 return -EDOM;                                           \
 798                                                                         \
 799         mcbsp->prop = val;                                              \
 800         return size;                                                    \
 801 }                                                                       \
 802                                                                         \
 803 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
 804
 805 THRESHOLD_PROP_BUILDER(max_tx_thres);
 806 THRESHOLD_PROP_BUILDER(max_rx_thres);
 807
 808 static const char *dma_op_modes[] = {
 809         "element", "threshold",
 810 };
 811
 812 static ssize_t dma_op_mode_show(struct device *dev,
 813                         struct device_attribute *attr, char *buf)
 814 {
 815         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 816         int dma_op_mode, i = 0;
 817         ssize_t len = 0;
 818         const char * const *s;
 819
 820         dma_op_mode = mcbsp->dma_op_mode;
 821
 822         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 823                 if (dma_op_mode == i)
 824                         len += sprintf(buf + len, "[%s] ", *s);
 825                 else
 826                         len += sprintf(buf + len, "%s ", *s);
 827         }
 828         len += sprintf(buf + len, "\n");
 829
 830         return len;
 831 }
 832
 833 static ssize_t dma_op_mode_store(struct device *dev,
 834                                 struct device_attribute *attr,
 835                                 const char *buf, size_t size)
 836 {
 837         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 838         const char * const *s;
 839         int i = 0;
 840
 841         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
 842                 if (sysfs_streq(buf, *s))
 843                         break;
 844
 845         if (i == ARRAY_SIZE(dma_op_modes))
 846                 return -EINVAL;
 847
 848         spin_lock_irq(&mcbsp->lock);
 849         if (!mcbsp->free) {
 850                 size = -EBUSY;
 851                 goto unlock;
 852         }
 853         mcbsp->dma_op_mode = i;
 854
 855 unlock:
 856         spin_unlock_irq(&mcbsp->lock);
 857
 858         return size;
 859 }
 860
 861 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 862
 863 static const struct attribute *additional_attrs[] = {
 864         &dev_attr_max_tx_thres.attr,
 865         &dev_attr_max_rx_thres.attr,
 866         &dev_attr_dma_op_mode.attr,
 867         NULL,
 868 };
 869
 870 static const struct attribute_group additional_attr_group = {
 871         .attrs = (struct attribute **)additional_attrs,
 872 };
 873
 874 static ssize_t st_taps_show(struct device *dev,
 875                             struct device_attribute *attr, char *buf)
 876 {
 877         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 878         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 879         ssize_t status = 0;
 880         int i;
 881
 882         spin_lock_irq(&mcbsp->lock);
 883         for (i = 0; i < st_data->nr_taps; i++)
 884                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
 885                                   st_data->taps[i]);
 886         if (i)
 887                 status += sprintf(&buf[status], "\n");
 888         spin_unlock_irq(&mcbsp->lock);
 889
 890         return status;
 891 }
 892
 893 static ssize_t st_taps_store(struct device *dev,
 894                              struct device_attribute *attr,
 895                              const char *buf, size_t size)
 896 {
 897         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 898         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 899         int val, tmp, status, i = 0;
 900
 901         spin_lock_irq(&mcbsp->lock);
 902         memset(st_data->taps, 0, sizeof(st_data->taps));
 903         st_data->nr_taps = 0;
 904
 905         do {
 906                 status = sscanf(buf, "%d%n", &val, &tmp);
 907                 if (status < 0 || status == 0) {
 908                         size = -EINVAL;
 909                         goto out;
 910                 }
 911                 if (val < -32768 || val > 32767) {
 912                         size = -EINVAL;
 913                         goto out;
 914                 }
 915                 st_data->taps[i++] = val;
 916                 buf += tmp;
 917                 if (*buf != ',')
 918                         break;
 919                 buf++;
 920         } while (1);
 921
 922         st_data->nr_taps = i;
 923
 924 out:
 925         spin_unlock_irq(&mcbsp->lock);
 926
 927         return size;
 928 }
 929
 930 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
 931
 932 static const struct attribute *sidetone_attrs[] = {
 933         &dev_attr_st_taps.attr,
 934         NULL,
 935 };
 936
 937 static const struct attribute_group sidetone_attr_group = {
 938         .attrs = (struct attribute **)sidetone_attrs,
 939 };
 940
 941 static int omap_st_add(struct omap_mcbsp *mcbsp, struct resource *res)
 942 {
 943         struct omap_mcbsp_st_data *st_data;
 944         int err;
 945
 946         st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
 947         if (!st_data)
 948                 return -ENOMEM;
 949
 950         st_data->mcbsp_iclk = clk_get(mcbsp->dev, "ick");
 951         if (IS_ERR(st_data->mcbsp_iclk)) {
 952                 dev_warn(mcbsp->dev,
 953                          "Failed to get ick, sidetone might be broken\n");
 954                 st_data->mcbsp_iclk = NULL;
 955         }
 956
 957         st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
 958                                            resource_size(res));
 959         if (!st_data->io_base_st)
 960                 return -ENOMEM;
 961
 962         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
 963         if (err)
 964                 return err;
 965
 966         mcbsp->st_data = st_data;
 967         return 0;
 968 }
 969
 970 /*
 971  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 972  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 973  */
 974 int omap_mcbsp_init(struct platform_device *pdev)
 975 {
 976         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 977         struct resource *res;
 978         int ret = 0;
 979
 980         spin_lock_init(&mcbsp->lock);
 981         mcbsp->free = true;
 982
 983         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 984         if (!res)
 985                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 986
 987         mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
 988         if (IS_ERR(mcbsp->io_base))
 989                 return PTR_ERR(mcbsp->io_base);
 990
 991         mcbsp->phys_base = res->start;
 992         mcbsp->reg_cache_size = resource_size(res);
 993
 994         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 995         if (!res)
 996                 mcbsp->phys_dma_base = mcbsp->phys_base;
 997         else
 998                 mcbsp->phys_dma_base = res->start;
 999
1000         /*
1001          * OMAP1, 2 uses two interrupt lines: TX, RX
1002          * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1003          * OMAP4 and newer SoC only have the combined IRQ line.
1004          * Use the combined IRQ if available since it gives better debugging
1005          * possibilities.
1006          */
1007         mcbsp->irq = platform_get_irq_byname(pdev, "common");
1008         if (mcbsp->irq == -ENXIO) {
1009                 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1010
1011                 if (mcbsp->tx_irq == -ENXIO) {
1012                         mcbsp->irq = platform_get_irq(pdev, 0);
1013                         mcbsp->tx_irq = 0;
1014                 } else {
1015                         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1016                         mcbsp->irq = 0;
1017                 }
1018         }
1019
1020         if (!pdev->dev.of_node) {
1021                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1022                 if (!res) {
1023                         dev_err(&pdev->dev, "invalid tx DMA channel\n");
1024                         return -ENODEV;
1025                 }
1026                 mcbsp->dma_req[0] = res->start;
1027                 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
1028
1029                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1030                 if (!res) {
1031                         dev_err(&pdev->dev, "invalid rx DMA channel\n");
1032                         return -ENODEV;
1033                 }
1034                 mcbsp->dma_req[1] = res->start;
1035                 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
1036         } else {
1037                 mcbsp->dma_data[0].filter_data = "tx";
1038                 mcbsp->dma_data[1].filter_data = "rx";
1039         }
1040
1041         mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1042         mcbsp->dma_data[0].maxburst = 4;
1043
1044         mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1045         mcbsp->dma_data[1].maxburst = 4;
1046
1047         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1048         if (IS_ERR(mcbsp->fclk)) {
1049                 ret = PTR_ERR(mcbsp->fclk);
1050                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1051                 return ret;
1052         }
1053
1054         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1055         if (mcbsp->pdata->buffer_size) {
1056                 /*
1057                  * Initially configure the maximum thresholds to a safe value.
1058                  * The McBSP FIFO usage with these values should not go under
1059                  * 16 locations.
1060                  * If the whole FIFO without safety buffer is used, than there
1061                  * is a possibility that the DMA will be not able to push the
1062                  * new data on time, causing channel shifts in runtime.
1063                  */
1064                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1065                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1066
1067                 ret = sysfs_create_group(&mcbsp->dev->kobj,
1068                                          &additional_attr_group);
1069                 if (ret) {
1070                         dev_err(mcbsp->dev,
1071                                 "Unable to create additional controls\n");
1072                         goto err_thres;
1073                 }
1074         } else {
1075                 mcbsp->max_tx_thres = -EINVAL;
1076                 mcbsp->max_rx_thres = -EINVAL;
1077         }
1078
1079         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1080         if (res) {
1081                 ret = omap_st_add(mcbsp, res);
1082                 if (ret) {
1083                         dev_err(mcbsp->dev,
1084                                 "Unable to create sidetone controls\n");
1085                         goto err_st;
1086                 }
1087         }
1088
1089         return 0;
1090
1091 err_st:
1092         if (mcbsp->pdata->buffer_size)
1093                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1094 err_thres:
1095         clk_put(mcbsp->fclk);
1096         return ret;
1097 }
1098
1099 void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp)
1100 {
1101         if (mcbsp->pdata->buffer_size)
1102                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1103
1104         if (mcbsp->st_data) {
1105                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1106                 clk_put(mcbsp->st_data->mcbsp_iclk);
1107         }
1108 }