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tracing: Fix trace_pipe behavior for instance traces
[linux/fpc-iii.git] / drivers / spi / spi-rspi.c
bloba816f07e168e84b0192224dcaadb99cb377ac9ed
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sh_dma.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/rspi.h>
35
36 #define RSPI_SPCR 0x00 /* Control Register */
37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
38 #define RSPI_SPPCR 0x02 /* Pin Control Register */
39 #define RSPI_SPSR 0x03 /* Status Register */
40 #define RSPI_SPDR 0x04 /* Data Register */
41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
43 #define RSPI_SPBR 0x0a /* Bit Rate Register */
44 #define RSPI_SPDCR 0x0b /* Data Control Register */
45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
58 #define RSPI_NUM_SPCMD 8
59 #define RSPI_RZ_NUM_SPCMD 4
60 #define QSPI_NUM_SPCMD 4
61
62 /* RSPI on RZ only */
63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
65
66 /* QSPI only */
67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
74
75 /* SPCR - Control Register */
76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
77 #define SPCR_SPE 0x40 /* Function Enable */
78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
82 /* RSPI on SH only */
83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
85 /* QSPI on R-Car Gen2 only */
86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
88
89 /* SSLP - Slave Select Polarity Register */
90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
92
93 /* SPPCR - Pin Control Register */
94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
96 #define SPPCR_SPOM 0x04
97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
99
100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
102
103 /* SPSR - Status Register */
104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
105 #define SPSR_TEND 0x40 /* Transmit End */
106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
107 #define SPSR_PERF 0x08 /* Parity Error Flag */
108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
111
112 /* SPSCR - Sequence Control Register */
113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
114
115 /* SPSSR - Sequence Status Register */
116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
118
119 /* SPDCR - Data Control Register */
120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
124 #define SPDCR_SPLWORD SPDCR_SPLW1
125 #define SPDCR_SPLBYTE SPDCR_SPLW0
126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
128 #define SPDCR_SLSEL1 0x08
129 #define SPDCR_SLSEL0 0x04
130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
131 #define SPDCR_SPFC1 0x02
132 #define SPDCR_SPFC0 0x01
133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
134
135 /* SPCKD - Clock Delay Register */
136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
137
138 /* SSLND - Slave Select Negation Delay Register */
139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
140
141 /* SPND - Next-Access Delay Register */
142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
143
144 /* SPCR2 - Control Register 2 */
145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
148 #define SPCR2_SPPE 0x01 /* Parity Enable */
149
150 /* SPCMDn - Command Registers */
151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
154 #define SPCMD_LSBF 0x1000 /* LSB First */
155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
158 #define SPCMD_SPB_16BIT 0x0100
159 #define SPCMD_SPB_20BIT 0x0000
160 #define SPCMD_SPB_24BIT 0x0100
161 #define SPCMD_SPB_32BIT 0x0200
162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
164 #define SPCMD_SPIMOD1 0x0040
165 #define SPCMD_SPIMOD0 0x0020
166 #define SPCMD_SPIMOD_SINGLE 0
167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
174
175 /* SPBFCR - Buffer Control Register */
176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
180 /* QSPI on R-Car Gen2 */
181 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
182 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
183 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
184 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
185
186 #define QSPI_BUFFER_SIZE 32u
187
188 struct rspi_data {
189 void __iomem *addr;
190 u32 max_speed_hz;
191 struct spi_master *master;
192 wait_queue_head_t wait;
193 struct clk *clk;
194 u16 spcmd;
195 u8 spsr;
196 u8 sppcr;
197 int rx_irq, tx_irq;
198 const struct spi_ops *ops;
199
200 unsigned dma_callbacked:1;
201 unsigned byte_access:1;
202 };
203
204 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
205 {
206 iowrite8(data, rspi->addr + offset);
207 }
208
209 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
210 {
211 iowrite16(data, rspi->addr + offset);
212 }
213
214 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
215 {
216 iowrite32(data, rspi->addr + offset);
217 }
218
219 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
220 {
221 return ioread8(rspi->addr + offset);
222 }
223
224 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
225 {
226 return ioread16(rspi->addr + offset);
227 }
228
229 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
230 {
231 if (rspi->byte_access)
232 rspi_write8(rspi, data, RSPI_SPDR);
233 else /* 16 bit */
234 rspi_write16(rspi, data, RSPI_SPDR);
235 }
236
237 static u16 rspi_read_data(const struct rspi_data *rspi)
238 {
239 if (rspi->byte_access)
240 return rspi_read8(rspi, RSPI_SPDR);
241 else /* 16 bit */
242 return rspi_read16(rspi, RSPI_SPDR);
243 }
244
245 /* optional functions */
246 struct spi_ops {
247 int (*set_config_register)(struct rspi_data *rspi, int access_size);
248 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
249 struct spi_transfer *xfer);
250 u16 mode_bits;
251 u16 flags;
252 u16 fifo_size;
253 };
254
255 /*
256 * functions for RSPI on legacy SH
257 */
258 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
259 {
260 int spbr;
261
262 /* Sets output mode, MOSI signal, and (optionally) loopback */
263 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
264
265 /* Sets transfer bit rate */
266 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
267 2 * rspi->max_speed_hz) - 1;
268 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
269
270 /* Disable dummy transmission, set 16-bit word access, 1 frame */
271 rspi_write8(rspi, 0, RSPI_SPDCR);
272 rspi->byte_access = 0;
273
274 /* Sets RSPCK, SSL, next-access delay value */
275 rspi_write8(rspi, 0x00, RSPI_SPCKD);
276 rspi_write8(rspi, 0x00, RSPI_SSLND);
277 rspi_write8(rspi, 0x00, RSPI_SPND);
278
279 /* Sets parity, interrupt mask */
280 rspi_write8(rspi, 0x00, RSPI_SPCR2);
281
282 /* Sets SPCMD */
283 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
284 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
285
286 /* Sets RSPI mode */
287 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
288
289 return 0;
290 }
291
292 /*
293 * functions for RSPI on RZ
294 */
295 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
296 {
297 int spbr;
298 int div = 0;
299 unsigned long clksrc;
300
301 /* Sets output mode, MOSI signal, and (optionally) loopback */
302 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
303
304 clksrc = clk_get_rate(rspi->clk);
305 while (div < 3) {
306 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
307 break;
308 div++;
309 clksrc /= 2;
310 }
311
312 /* Sets transfer bit rate */
313 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
314 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
315 rspi->spcmd |= div << 2;
316
317 /* Disable dummy transmission, set byte access */
318 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
319 rspi->byte_access = 1;
320
321 /* Sets RSPCK, SSL, next-access delay value */
322 rspi_write8(rspi, 0x00, RSPI_SPCKD);
323 rspi_write8(rspi, 0x00, RSPI_SSLND);
324 rspi_write8(rspi, 0x00, RSPI_SPND);
325
326 /* Sets SPCMD */
327 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
328 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
329
330 /* Sets RSPI mode */
331 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
332
333 return 0;
334 }
335
336 /*
337 * functions for QSPI
338 */
339 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
340 {
341 int spbr;
342
343 /* Sets output mode, MOSI signal, and (optionally) loopback */
344 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
345
346 /* Sets transfer bit rate */
347 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
348 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
349
350 /* Disable dummy transmission, set byte access */
351 rspi_write8(rspi, 0, RSPI_SPDCR);
352 rspi->byte_access = 1;
353
354 /* Sets RSPCK, SSL, next-access delay value */
355 rspi_write8(rspi, 0x00, RSPI_SPCKD);
356 rspi_write8(rspi, 0x00, RSPI_SSLND);
357 rspi_write8(rspi, 0x00, RSPI_SPND);
358
359 /* Data Length Setting */
360 if (access_size == 8)
361 rspi->spcmd |= SPCMD_SPB_8BIT;
362 else if (access_size == 16)
363 rspi->spcmd |= SPCMD_SPB_16BIT;
364 else
365 rspi->spcmd |= SPCMD_SPB_32BIT;
366
367 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
368
369 /* Resets transfer data length */
370 rspi_write32(rspi, 0, QSPI_SPBMUL0);
371
372 /* Resets transmit and receive buffer */
373 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
374 /* Sets buffer to allow normal operation */
375 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
376
377 /* Sets SPCMD */
378 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
379
380 /* Enables SPI function in master mode */
381 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
382
383 return 0;
384 }
385
386 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
387 {
388 u8 data;
389
390 data = rspi_read8(rspi, reg);
391 data &= ~mask;
392 data |= (val & mask);
393 rspi_write8(rspi, data, reg);
394 }
395
396 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
397 unsigned int len)
398 {
399 unsigned int n;
400
401 n = min(len, QSPI_BUFFER_SIZE);
402
403 if (len >= QSPI_BUFFER_SIZE) {
404 /* sets triggering number to 32 bytes */
405 qspi_update(rspi, SPBFCR_TXTRG_MASK,
406 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
407 } else {
408 /* sets triggering number to 1 byte */
409 qspi_update(rspi, SPBFCR_TXTRG_MASK,
410 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
411 }
412
413 return n;
414 }
415
416 static void qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
417 {
418 unsigned int n;
419
420 n = min(len, QSPI_BUFFER_SIZE);
421
422 if (len >= QSPI_BUFFER_SIZE) {
423 /* sets triggering number to 32 bytes */
424 qspi_update(rspi, SPBFCR_RXTRG_MASK,
425 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
426 } else {
427 /* sets triggering number to 1 byte */
428 qspi_update(rspi, SPBFCR_RXTRG_MASK,
429 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
430 }
431 }
432
433 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
434
435 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
436 {
437 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
438 }
439
440 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
441 {
442 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
443 }
444
445 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
446 u8 enable_bit)
447 {
448 int ret;
449
450 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
451 if (rspi->spsr & wait_mask)
452 return 0;
453
454 rspi_enable_irq(rspi, enable_bit);
455 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
456 if (ret == 0 && !(rspi->spsr & wait_mask))
457 return -ETIMEDOUT;
458
459 return 0;
460 }
461
462 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
463 {
464 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
465 }
466
467 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
468 {
469 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
470 }
471
472 static int rspi_data_out(struct rspi_data *rspi, u8 data)
473 {
474 int error = rspi_wait_for_tx_empty(rspi);
475 if (error < 0) {
476 dev_err(&rspi->master->dev, "transmit timeout\n");
477 return error;
478 }
479 rspi_write_data(rspi, data);
480 return 0;
481 }
482
483 static int rspi_data_in(struct rspi_data *rspi)
484 {
485 int error;
486 u8 data;
487
488 error = rspi_wait_for_rx_full(rspi);
489 if (error < 0) {
490 dev_err(&rspi->master->dev, "receive timeout\n");
491 return error;
492 }
493 data = rspi_read_data(rspi);
494 return data;
495 }
496
497 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
498 unsigned int n)
499 {
500 while (n-- > 0) {
501 if (tx) {
502 int ret = rspi_data_out(rspi, *tx++);
503 if (ret < 0)
504 return ret;
505 }
506 if (rx) {
507 int ret = rspi_data_in(rspi);
508 if (ret < 0)
509 return ret;
510 *rx++ = ret;
511 }
512 }
513
514 return 0;
515 }
516
517 static void rspi_dma_complete(void *arg)
518 {
519 struct rspi_data *rspi = arg;
520
521 rspi->dma_callbacked = 1;
522 wake_up_interruptible(&rspi->wait);
523 }
524
525 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
526 struct sg_table *rx)
527 {
528 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
529 u8 irq_mask = 0;
530 unsigned int other_irq = 0;
531 dma_cookie_t cookie;
532 int ret;
533
534 /* First prepare and submit the DMA request(s), as this may fail */
535 if (rx) {
536 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx,
537 rx->sgl, rx->nents, DMA_FROM_DEVICE,
538 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
539 if (!desc_rx) {
540 ret = -EAGAIN;
541 goto no_dma_rx;
542 }
543
544 desc_rx->callback = rspi_dma_complete;
545 desc_rx->callback_param = rspi;
546 cookie = dmaengine_submit(desc_rx);
547 if (dma_submit_error(cookie)) {
548 ret = cookie;
549 goto no_dma_rx;
550 }
551
552 irq_mask |= SPCR_SPRIE;
553 }
554
555 if (tx) {
556 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx,
557 tx->sgl, tx->nents, DMA_TO_DEVICE,
558 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
559 if (!desc_tx) {
560 ret = -EAGAIN;
561 goto no_dma_tx;
562 }
563
564 if (rx) {
565 /* No callback */
566 desc_tx->callback = NULL;
567 } else {
568 desc_tx->callback = rspi_dma_complete;
569 desc_tx->callback_param = rspi;
570 }
571 cookie = dmaengine_submit(desc_tx);
572 if (dma_submit_error(cookie)) {
573 ret = cookie;
574 goto no_dma_tx;
575 }
576
577 irq_mask |= SPCR_SPTIE;
578 }
579
580 /*
581 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
582 * called. So, this driver disables the IRQ while DMA transfer.
583 */
584 if (tx)
585 disable_irq(other_irq = rspi->tx_irq);
586 if (rx && rspi->rx_irq != other_irq)
587 disable_irq(rspi->rx_irq);
588
589 rspi_enable_irq(rspi, irq_mask);
590 rspi->dma_callbacked = 0;
591
592 /* Now start DMA */
593 if (rx)
594 dma_async_issue_pending(rspi->master->dma_rx);
595 if (tx)
596 dma_async_issue_pending(rspi->master->dma_tx);
597
598 ret = wait_event_interruptible_timeout(rspi->wait,
599 rspi->dma_callbacked, HZ);
600 if (ret > 0 && rspi->dma_callbacked)
601 ret = 0;
602 else if (!ret) {
603 dev_err(&rspi->master->dev, "DMA timeout\n");
604 ret = -ETIMEDOUT;
605 if (tx)
606 dmaengine_terminate_all(rspi->master->dma_tx);
607 if (rx)
608 dmaengine_terminate_all(rspi->master->dma_rx);
609 }
610
611 rspi_disable_irq(rspi, irq_mask);
612
613 if (tx)
614 enable_irq(rspi->tx_irq);
615 if (rx && rspi->rx_irq != other_irq)
616 enable_irq(rspi->rx_irq);
617
618 return ret;
619
620 no_dma_tx:
621 if (rx)
622 dmaengine_terminate_all(rspi->master->dma_rx);
623 no_dma_rx:
624 if (ret == -EAGAIN) {
625 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
626 dev_driver_string(&rspi->master->dev),
627 dev_name(&rspi->master->dev));
628 }
629 return ret;
630 }
631
632 static void rspi_receive_init(const struct rspi_data *rspi)
633 {
634 u8 spsr;
635
636 spsr = rspi_read8(rspi, RSPI_SPSR);
637 if (spsr & SPSR_SPRF)
638 rspi_read_data(rspi); /* dummy read */
639 if (spsr & SPSR_OVRF)
640 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
641 RSPI_SPSR);
642 }
643
644 static void rspi_rz_receive_init(const struct rspi_data *rspi)
645 {
646 rspi_receive_init(rspi);
647 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
648 rspi_write8(rspi, 0, RSPI_SPBFCR);
649 }
650
651 static void qspi_receive_init(const struct rspi_data *rspi)
652 {
653 u8 spsr;
654
655 spsr = rspi_read8(rspi, RSPI_SPSR);
656 if (spsr & SPSR_SPRF)
657 rspi_read_data(rspi); /* dummy read */
658 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
659 rspi_write8(rspi, 0, QSPI_SPBFCR);
660 }
661
662 static bool __rspi_can_dma(const struct rspi_data *rspi,
663 const struct spi_transfer *xfer)
664 {
665 return xfer->len > rspi->ops->fifo_size;
666 }
667
668 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi,
669 struct spi_transfer *xfer)
670 {
671 struct rspi_data *rspi = spi_master_get_devdata(master);
672
673 return __rspi_can_dma(rspi, xfer);
674 }
675
676 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
677 struct spi_transfer *xfer)
678 {
679 if (!rspi->master->can_dma || !__rspi_can_dma(rspi, xfer))
680 return -EAGAIN;
681
682 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
683 return rspi_dma_transfer(rspi, &xfer->tx_sg,
684 xfer->rx_buf ? &xfer->rx_sg : NULL);
685 }
686
687 static int rspi_common_transfer(struct rspi_data *rspi,
688 struct spi_transfer *xfer)
689 {
690 int ret;
691
692 ret = rspi_dma_check_then_transfer(rspi, xfer);
693 if (ret != -EAGAIN)
694 return ret;
695
696 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
697 if (ret < 0)
698 return ret;
699
700 /* Wait for the last transmission */
701 rspi_wait_for_tx_empty(rspi);
702
703 return 0;
704 }
705
706 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
707 struct spi_transfer *xfer)
708 {
709 struct rspi_data *rspi = spi_master_get_devdata(master);
710 u8 spcr;
711
712 spcr = rspi_read8(rspi, RSPI_SPCR);
713 if (xfer->rx_buf) {
714 rspi_receive_init(rspi);
715 spcr &= ~SPCR_TXMD;
716 } else {
717 spcr |= SPCR_TXMD;
718 }
719 rspi_write8(rspi, spcr, RSPI_SPCR);
720
721 return rspi_common_transfer(rspi, xfer);
722 }
723
724 static int rspi_rz_transfer_one(struct spi_master *master,
725 struct spi_device *spi,
726 struct spi_transfer *xfer)
727 {
728 struct rspi_data *rspi = spi_master_get_devdata(master);
729
730 rspi_rz_receive_init(rspi);
731
732 return rspi_common_transfer(rspi, xfer);
733 }
734
735 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
736 u8 *rx, unsigned int len)
737 {
738 unsigned int i, n;
739 int ret;
740
741 while (len > 0) {
742 n = qspi_set_send_trigger(rspi, len);
743 qspi_set_receive_trigger(rspi, len);
744 if (n == QSPI_BUFFER_SIZE) {
745 ret = rspi_wait_for_tx_empty(rspi);
746 if (ret < 0) {
747 dev_err(&rspi->master->dev, "transmit timeout\n");
748 return ret;
749 }
750 for (i = 0; i < n; i++)
751 rspi_write_data(rspi, *tx++);
752
753 ret = rspi_wait_for_rx_full(rspi);
754 if (ret < 0) {
755 dev_err(&rspi->master->dev, "receive timeout\n");
756 return ret;
757 }
758 for (i = 0; i < n; i++)
759 *rx++ = rspi_read_data(rspi);
760 } else {
761 ret = rspi_pio_transfer(rspi, tx, rx, n);
762 if (ret < 0)
763 return ret;
764 }
765 len -= n;
766 }
767
768 return 0;
769 }
770
771 static int qspi_transfer_out_in(struct rspi_data *rspi,
772 struct spi_transfer *xfer)
773 {
774 int ret;
775
776 qspi_receive_init(rspi);
777
778 ret = rspi_dma_check_then_transfer(rspi, xfer);
779 if (ret != -EAGAIN)
780 return ret;
781
782 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
783 xfer->rx_buf, xfer->len);
784 }
785
786 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
787 {
788 int ret;
789
790 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
791 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
792 if (ret != -EAGAIN)
793 return ret;
794 }
795
796 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
797 if (ret < 0)
798 return ret;
799
800 /* Wait for the last transmission */
801 rspi_wait_for_tx_empty(rspi);
802
803 return 0;
804 }
805
806 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
807 {
808 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) {
809 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
810 if (ret != -EAGAIN)
811 return ret;
812 }
813
814 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
815 }
816
817 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
818 struct spi_transfer *xfer)
819 {
820 struct rspi_data *rspi = spi_master_get_devdata(master);
821
822 if (spi->mode & SPI_LOOP) {
823 return qspi_transfer_out_in(rspi, xfer);
824 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
825 /* Quad or Dual SPI Write */
826 return qspi_transfer_out(rspi, xfer);
827 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
828 /* Quad or Dual SPI Read */
829 return qspi_transfer_in(rspi, xfer);
830 } else {
831 /* Single SPI Transfer */
832 return qspi_transfer_out_in(rspi, xfer);
833 }
834 }
835
836 static int rspi_setup(struct spi_device *spi)
837 {
838 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
839
840 rspi->max_speed_hz = spi->max_speed_hz;
841
842 rspi->spcmd = SPCMD_SSLKP;
843 if (spi->mode & SPI_CPOL)
844 rspi->spcmd |= SPCMD_CPOL;
845 if (spi->mode & SPI_CPHA)
846 rspi->spcmd |= SPCMD_CPHA;
847
848 /* CMOS output mode and MOSI signal from previous transfer */
849 rspi->sppcr = 0;
850 if (spi->mode & SPI_LOOP)
851 rspi->sppcr |= SPPCR_SPLP;
852
853 set_config_register(rspi, 8);
854
855 return 0;
856 }
857
858 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
859 {
860 if (xfer->tx_buf)
861 switch (xfer->tx_nbits) {
862 case SPI_NBITS_QUAD:
863 return SPCMD_SPIMOD_QUAD;
864 case SPI_NBITS_DUAL:
865 return SPCMD_SPIMOD_DUAL;
866 default:
867 return 0;
868 }
869 if (xfer->rx_buf)
870 switch (xfer->rx_nbits) {
871 case SPI_NBITS_QUAD:
872 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
873 case SPI_NBITS_DUAL:
874 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
875 default:
876 return 0;
877 }
878
879 return 0;
880 }
881
882 static int qspi_setup_sequencer(struct rspi_data *rspi,
883 const struct spi_message *msg)
884 {
885 const struct spi_transfer *xfer;
886 unsigned int i = 0, len = 0;
887 u16 current_mode = 0xffff, mode;
888
889 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
890 mode = qspi_transfer_mode(xfer);
891 if (mode == current_mode) {
892 len += xfer->len;
893 continue;
894 }
895
896 /* Transfer mode change */
897 if (i) {
898 /* Set transfer data length of previous transfer */
899 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
900 }
901
902 if (i >= QSPI_NUM_SPCMD) {
903 dev_err(&msg->spi->dev,
904 "Too many different transfer modes");
905 return -EINVAL;
906 }
907
908 /* Program transfer mode for this transfer */
909 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
910 current_mode = mode;
911 len = xfer->len;
912 i++;
913 }
914 if (i) {
915 /* Set final transfer data length and sequence length */
916 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
917 rspi_write8(rspi, i - 1, RSPI_SPSCR);
918 }
919
920 return 0;
921 }
922
923 static int rspi_prepare_message(struct spi_master *master,
924 struct spi_message *msg)
925 {
926 struct rspi_data *rspi = spi_master_get_devdata(master);
927 int ret;
928
929 if (msg->spi->mode &
930 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
931 /* Setup sequencer for messages with multiple transfer modes */
932 ret = qspi_setup_sequencer(rspi, msg);
933 if (ret < 0)
934 return ret;
935 }
936
937 /* Enable SPI function in master mode */
938 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
939 return 0;
940 }
941
942 static int rspi_unprepare_message(struct spi_master *master,
943 struct spi_message *msg)
944 {
945 struct rspi_data *rspi = spi_master_get_devdata(master);
946
947 /* Disable SPI function */
948 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
949
950 /* Reset sequencer for Single SPI Transfers */
951 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
952 rspi_write8(rspi, 0, RSPI_SPSCR);
953 return 0;
954 }
955
956 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
957 {
958 struct rspi_data *rspi = _sr;
959 u8 spsr;
960 irqreturn_t ret = IRQ_NONE;
961 u8 disable_irq = 0;
962
963 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
964 if (spsr & SPSR_SPRF)
965 disable_irq |= SPCR_SPRIE;
966 if (spsr & SPSR_SPTEF)
967 disable_irq |= SPCR_SPTIE;
968
969 if (disable_irq) {
970 ret = IRQ_HANDLED;
971 rspi_disable_irq(rspi, disable_irq);
972 wake_up(&rspi->wait);
973 }
974
975 return ret;
976 }
977
978 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
979 {
980 struct rspi_data *rspi = _sr;
981 u8 spsr;
982
983 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
984 if (spsr & SPSR_SPRF) {
985 rspi_disable_irq(rspi, SPCR_SPRIE);
986 wake_up(&rspi->wait);
987 return IRQ_HANDLED;
988 }
989
990 return 0;
991 }
992
993 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
994 {
995 struct rspi_data *rspi = _sr;
996 u8 spsr;
997
998 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
999 if (spsr & SPSR_SPTEF) {
1000 rspi_disable_irq(rspi, SPCR_SPTIE);
1001 wake_up(&rspi->wait);
1002 return IRQ_HANDLED;
1003 }
1004
1005 return 0;
1006 }
1007
1008 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1009 enum dma_transfer_direction dir,
1010 unsigned int id,
1011 dma_addr_t port_addr)
1012 {
1013 dma_cap_mask_t mask;
1014 struct dma_chan *chan;
1015 struct dma_slave_config cfg;
1016 int ret;
1017
1018 dma_cap_zero(mask);
1019 dma_cap_set(DMA_SLAVE, mask);
1020
1021 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1022 (void *)(unsigned long)id, dev,
1023 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1024 if (!chan) {
1025 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1026 return NULL;
1027 }
1028
1029 memset(&cfg, 0, sizeof(cfg));
1030 cfg.direction = dir;
1031 if (dir == DMA_MEM_TO_DEV) {
1032 cfg.dst_addr = port_addr;
1033 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1034 } else {
1035 cfg.src_addr = port_addr;
1036 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1037 }
1038
1039 ret = dmaengine_slave_config(chan, &cfg);
1040 if (ret) {
1041 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1042 dma_release_channel(chan);
1043 return NULL;
1044 }
1045
1046 return chan;
1047 }
1048
1049 static int rspi_request_dma(struct device *dev, struct spi_master *master,
1050 const struct resource *res)
1051 {
1052 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1053 unsigned int dma_tx_id, dma_rx_id;
1054
1055 if (dev->of_node) {
1056 /* In the OF case we will get the slave IDs from the DT */
1057 dma_tx_id = 0;
1058 dma_rx_id = 0;
1059 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1060 dma_tx_id = rspi_pd->dma_tx_id;
1061 dma_rx_id = rspi_pd->dma_rx_id;
1062 } else {
1063 /* The driver assumes no error. */
1064 return 0;
1065 }
1066
1067 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1068 res->start + RSPI_SPDR);
1069 if (!master->dma_tx)
1070 return -ENODEV;
1071
1072 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1073 res->start + RSPI_SPDR);
1074 if (!master->dma_rx) {
1075 dma_release_channel(master->dma_tx);
1076 master->dma_tx = NULL;
1077 return -ENODEV;
1078 }
1079
1080 master->can_dma = rspi_can_dma;
1081 dev_info(dev, "DMA available");
1082 return 0;
1083 }
1084
1085 static void rspi_release_dma(struct spi_master *master)
1086 {
1087 if (master->dma_tx)
1088 dma_release_channel(master->dma_tx);
1089 if (master->dma_rx)
1090 dma_release_channel(master->dma_rx);
1091 }
1092
1093 static int rspi_remove(struct platform_device *pdev)
1094 {
1095 struct rspi_data *rspi = platform_get_drvdata(pdev);
1096
1097 rspi_release_dma(rspi->master);
1098 pm_runtime_disable(&pdev->dev);
1099
1100 return 0;
1101 }
1102
1103 static const struct spi_ops rspi_ops = {
1104 .set_config_register = rspi_set_config_register,
1105 .transfer_one = rspi_transfer_one,
1106 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1107 .flags = SPI_MASTER_MUST_TX,
1108 .fifo_size = 8,
1109 };
1110
1111 static const struct spi_ops rspi_rz_ops = {
1112 .set_config_register = rspi_rz_set_config_register,
1113 .transfer_one = rspi_rz_transfer_one,
1114 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1115 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1116 .fifo_size = 8, /* 8 for TX, 32 for RX */
1117 };
1118
1119 static const struct spi_ops qspi_ops = {
1120 .set_config_register = qspi_set_config_register,
1121 .transfer_one = qspi_transfer_one,
1122 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1123 SPI_TX_DUAL | SPI_TX_QUAD |
1124 SPI_RX_DUAL | SPI_RX_QUAD,
1125 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1126 .fifo_size = 32,
1127 };
1128
1129 #ifdef CONFIG_OF
1130 static const struct of_device_id rspi_of_match[] = {
1131 /* RSPI on legacy SH */
1132 { .compatible = "renesas,rspi", .data = &rspi_ops },
1133 /* RSPI on RZ/A1H */
1134 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1135 /* QSPI on R-Car Gen2 */
1136 { .compatible = "renesas,qspi", .data = &qspi_ops },
1137 { /* sentinel */ }
1138 };
1139
1140 MODULE_DEVICE_TABLE(of, rspi_of_match);
1141
1142 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1143 {
1144 u32 num_cs;
1145 int error;
1146
1147 /* Parse DT properties */
1148 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1149 if (error) {
1150 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1151 return error;
1152 }
1153
1154 master->num_chipselect = num_cs;
1155 return 0;
1156 }
1157 #else
1158 #define rspi_of_match NULL
1159 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1160 {
1161 return -EINVAL;
1162 }
1163 #endif /* CONFIG_OF */
1164
1165 static int rspi_request_irq(struct device *dev, unsigned int irq,
1166 irq_handler_t handler, const char *suffix,
1167 void *dev_id)
1168 {
1169 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1170 dev_name(dev), suffix);
1171 if (!name)
1172 return -ENOMEM;
1173
1174 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1175 }
1176
1177 static int rspi_probe(struct platform_device *pdev)
1178 {
1179 struct resource *res;
1180 struct spi_master *master;
1181 struct rspi_data *rspi;
1182 int ret;
1183 const struct of_device_id *of_id;
1184 const struct rspi_plat_data *rspi_pd;
1185 const struct spi_ops *ops;
1186
1187 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1188 if (master == NULL) {
1189 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1190 return -ENOMEM;
1191 }
1192
1193 of_id = of_match_device(rspi_of_match, &pdev->dev);
1194 if (of_id) {
1195 ops = of_id->data;
1196 ret = rspi_parse_dt(&pdev->dev, master);
1197 if (ret)
1198 goto error1;
1199 } else {
1200 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1201 rspi_pd = dev_get_platdata(&pdev->dev);
1202 if (rspi_pd && rspi_pd->num_chipselect)
1203 master->num_chipselect = rspi_pd->num_chipselect;
1204 else
1205 master->num_chipselect = 2; /* default */
1206 }
1207
1208 /* ops parameter check */
1209 if (!ops->set_config_register) {
1210 dev_err(&pdev->dev, "there is no set_config_register\n");
1211 ret = -ENODEV;
1212 goto error1;
1213 }
1214
1215 rspi = spi_master_get_devdata(master);
1216 platform_set_drvdata(pdev, rspi);
1217 rspi->ops = ops;
1218 rspi->master = master;
1219
1220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1221 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1222 if (IS_ERR(rspi->addr)) {
1223 ret = PTR_ERR(rspi->addr);
1224 goto error1;
1225 }
1226
1227 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1228 if (IS_ERR(rspi->clk)) {
1229 dev_err(&pdev->dev, "cannot get clock\n");
1230 ret = PTR_ERR(rspi->clk);
1231 goto error1;
1232 }
1233
1234 pm_runtime_enable(&pdev->dev);
1235
1236 init_waitqueue_head(&rspi->wait);
1237
1238 master->bus_num = pdev->id;
1239 master->setup = rspi_setup;
1240 master->auto_runtime_pm = true;
1241 master->transfer_one = ops->transfer_one;
1242 master->prepare_message = rspi_prepare_message;
1243 master->unprepare_message = rspi_unprepare_message;
1244 master->mode_bits = ops->mode_bits;
1245 master->flags = ops->flags;
1246 master->dev.of_node = pdev->dev.of_node;
1247
1248 ret = platform_get_irq_byname(pdev, "rx");
1249 if (ret < 0) {
1250 ret = platform_get_irq_byname(pdev, "mux");
1251 if (ret < 0)
1252 ret = platform_get_irq(pdev, 0);
1253 if (ret >= 0)
1254 rspi->rx_irq = rspi->tx_irq = ret;
1255 } else {
1256 rspi->rx_irq = ret;
1257 ret = platform_get_irq_byname(pdev, "tx");
1258 if (ret >= 0)
1259 rspi->tx_irq = ret;
1260 }
1261 if (ret < 0) {
1262 dev_err(&pdev->dev, "platform_get_irq error\n");
1263 goto error2;
1264 }
1265
1266 if (rspi->rx_irq == rspi->tx_irq) {
1267 /* Single multiplexed interrupt */
1268 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1269 "mux", rspi);
1270 } else {
1271 /* Multi-interrupt mode, only SPRI and SPTI are used */
1272 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1273 "rx", rspi);
1274 if (!ret)
1275 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1276 rspi_irq_tx, "tx", rspi);
1277 }
1278 if (ret < 0) {
1279 dev_err(&pdev->dev, "request_irq error\n");
1280 goto error2;
1281 }
1282
1283 ret = rspi_request_dma(&pdev->dev, master, res);
1284 if (ret < 0)
1285 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1286
1287 ret = devm_spi_register_master(&pdev->dev, master);
1288 if (ret < 0) {
1289 dev_err(&pdev->dev, "spi_register_master error.\n");
1290 goto error3;
1291 }
1292
1293 dev_info(&pdev->dev, "probed\n");
1294
1295 return 0;
1296
1297 error3:
1298 rspi_release_dma(master);
1299 error2:
1300 pm_runtime_disable(&pdev->dev);
1301 error1:
1302 spi_master_put(master);
1303
1304 return ret;
1305 }
1306
1307 static const struct platform_device_id spi_driver_ids[] = {
1308 { "rspi", (kernel_ulong_t)&rspi_ops },
1309 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1310 { "qspi", (kernel_ulong_t)&qspi_ops },
1311 {},
1312 };
1313
1314 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1315
1316 static struct platform_driver rspi_driver = {
1317 .probe = rspi_probe,
1318 .remove = rspi_remove,
1319 .id_table = spi_driver_ids,
1320 .driver = {
1321 .name = "renesas_spi",
1322 .of_match_table = of_match_ptr(rspi_of_match),
1323 },
1324 };
1325 module_platform_driver(rspi_driver);
1326
1327 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1328 MODULE_LICENSE("GPL v2");
1329 MODULE_AUTHOR("Yoshihiro Shimoda");
1330 MODULE_ALIAS("platform:rspi");
Linux with added FPC-III support