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Linux 4.14.171
[linux/fpc-iii.git] / sound / oss / ad1848.c
blob2421f59cf27996cb560f27fb90c6823ed69b67f0
1 /*
2 * sound/oss/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 * Christoph Hellwig : adapted to module_init/module_exit
30 * Aki Laukkanen : added power management support
31 * Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
32 * Miguel Freitas : added ISA PnP support
33 * Alan Cox : Added CS4236->4239 identification
34 * Daniel T. Cobra : Alernate config/mixer for later chips
35 * Alan Cox : Merged chip idents and config code
36 *
37 * TODO
38 * APM save restore assist code on IBM thinkpad
39 *
40 * Status:
41 * Tested. Believed fully functional.
42 */
43
44 #include <linux/init.h>
45 #include <linux/interrupt.h>
46 #include <linux/module.h>
47 #include <linux/stddef.h>
48 #include <linux/slab.h>
49 #include <linux/isapnp.h>
50 #include <linux/pnp.h>
51 #include <linux/spinlock.h>
52
53 #include "sound_config.h"
54
55 #include "ad1848.h"
56 #include "ad1848_mixer.h"
57
58 typedef struct
59 {
60 spinlock_t lock;
61 int base;
62 int irq;
63 int dma1, dma2;
64 int dual_dma; /* 1, when two DMA channels allocated */
65 int subtype;
66 unsigned char MCE_bit;
67 unsigned char saved_regs[64]; /* Includes extended register space */
68 int debug_flag;
69
70 int audio_flags;
71 int record_dev, playback_dev;
72
73 int xfer_count;
74 int audio_mode;
75 int open_mode;
76 int intr_active;
77 char *chip_name, *name;
78 int model;
79 #define MD_1848 1
80 #define MD_4231 2
81 #define MD_4231A 3
82 #define MD_1845 4
83 #define MD_4232 5
84 #define MD_C930 6
85 #define MD_IWAVE 7
86 #define MD_4235 8 /* Crystal Audio CS4235 */
87 #define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
88 #define MD_4236 10 /* 4236 and higher */
89 #define MD_42xB 11 /* CS 42xB */
90 #define MD_4239 12 /* CS4239 */
91
92 /* Mixer parameters */
93 int recmask;
94 int supported_devices, orig_devices;
95 int supported_rec_devices, orig_rec_devices;
96 int *levels;
97 short mixer_reroute[32];
98 int dev_no;
99 volatile unsigned long timer_ticks;
100 int timer_running;
101 int irq_ok;
102 mixer_ents *mix_devices;
103 int mixer_output_port;
104 } ad1848_info;
105
106 typedef struct ad1848_port_info
107 {
108 int open_mode;
109 int speed;
110 unsigned char speed_bits;
111 int channels;
112 int audio_format;
113 unsigned char format_bits;
114 }
115 ad1848_port_info;
116
117 static struct address_info cfg;
118 static int nr_ad1848_devs;
119
120 static bool deskpro_xl;
121 static bool deskpro_m;
122 static bool soundpro;
123
124 #ifndef EXCLUDE_TIMERS
125 static int timer_installed = -1;
126 #endif
127
128 static int loaded;
129
130 static int ad_format_mask[13 /*devc->model */ ] =
131 {
132 0,
133 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
134 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
135 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
136 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
137 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
138 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
139 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
140 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
141 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
142 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
143 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
144 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
145 };
146
147 static ad1848_info adev_info[MAX_AUDIO_DEV];
148
149 #define io_Index_Addr(d) ((d)->base)
150 #define io_Indexed_Data(d) ((d)->base+1)
151 #define io_Status(d) ((d)->base+2)
152 #define io_Polled_IO(d) ((d)->base+3)
153
154 static struct {
155 unsigned char flags;
156 #define CAP_F_TIMER 0x01
157 } capabilities [10 /*devc->model */ ] = {
158 {0}
159 ,{0} /* MD_1848 */
160 ,{CAP_F_TIMER} /* MD_4231 */
161 ,{CAP_F_TIMER} /* MD_4231A */
162 ,{CAP_F_TIMER} /* MD_1845 */
163 ,{CAP_F_TIMER} /* MD_4232 */
164 ,{0} /* MD_C930 */
165 ,{CAP_F_TIMER} /* MD_IWAVE */
166 ,{0} /* MD_4235 */
167 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
168 };
169
170 #ifdef CONFIG_PNP
171 static int isapnp = 1;
172 static int isapnpjump;
173 static bool reverse;
174
175 static int audio_activated;
176 #else
177 static int isapnp;
178 #endif
179
180
181
182 static int ad1848_open(int dev, int mode);
183 static void ad1848_close(int dev);
184 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
185 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
186 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
187 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
188 static void ad1848_halt(int dev);
189 static void ad1848_halt_input(int dev);
190 static void ad1848_halt_output(int dev);
191 static void ad1848_trigger(int dev, int bits);
192 static irqreturn_t adintr(int irq, void *dev_id);
193
194 #ifndef EXCLUDE_TIMERS
195 static int ad1848_tmr_install(int dev);
196 static void ad1848_tmr_reprogram(int dev);
197 #endif
198
199 static int ad_read(ad1848_info * devc, int reg)
200 {
201 int x;
202 int timeout = 900000;
203
204 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
205 timeout--;
206
207 if(reg < 32)
208 {
209 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
210 x = inb(io_Indexed_Data(devc));
211 }
212 else
213 {
214 int xreg, xra;
215
216 xreg = (reg & 0xff) - 32;
217 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
218 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
219 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
220 x = inb(io_Indexed_Data(devc));
221 }
222
223 return x;
224 }
225
226 static void ad_write(ad1848_info * devc, int reg, int data)
227 {
228 int timeout = 900000;
229
230 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
231 timeout--;
232
233 if(reg < 32)
234 {
235 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
236 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
237 }
238 else
239 {
240 int xreg, xra;
241
242 xreg = (reg & 0xff) - 32;
243 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
244 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
245 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
246 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
247 }
248 }
249
250 static void wait_for_calibration(ad1848_info * devc)
251 {
252 int timeout;
253
254 /*
255 * Wait until the auto calibration process has finished.
256 *
257 * 1) Wait until the chip becomes ready (reads don't return 0x80).
258 * 2) Wait until the ACI bit of I11 gets on and then off.
259 */
260
261 timeout = 100000;
262 while (timeout > 0 && inb(devc->base) == 0x80)
263 timeout--;
264 if (inb(devc->base) & 0x80)
265 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
266
267 timeout = 100;
268 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
269 timeout--;
270 if (!(ad_read(devc, 11) & 0x20))
271 return;
272
273 timeout = 80000;
274 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
275 timeout--;
276 if (ad_read(devc, 11) & 0x20)
277 if ((devc->model != MD_1845) && (devc->model != MD_1845_SSCAPE))
278 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
279 }
280
281 static void ad_mute(ad1848_info * devc)
282 {
283 int i;
284 unsigned char prev;
285
286 /*
287 * Save old register settings and mute output channels
288 */
289
290 for (i = 6; i < 8; i++)
291 {
292 prev = devc->saved_regs[i] = ad_read(devc, i);
293 }
294
295 }
296
297 static void ad_unmute(ad1848_info * devc)
298 {
299 }
300
301 static void ad_enter_MCE(ad1848_info * devc)
302 {
303 int timeout = 1000;
304 unsigned short prev;
305
306 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
307 timeout--;
308
309 devc->MCE_bit = 0x40;
310 prev = inb(io_Index_Addr(devc));
311 if (prev & 0x40)
312 {
313 return;
314 }
315 outb((devc->MCE_bit), io_Index_Addr(devc));
316 }
317
318 static void ad_leave_MCE(ad1848_info * devc)
319 {
320 unsigned char prev, acal;
321 int timeout = 1000;
322
323 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
324 timeout--;
325
326 acal = ad_read(devc, 9);
327
328 devc->MCE_bit = 0x00;
329 prev = inb(io_Index_Addr(devc));
330 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
331
332 if ((prev & 0x40) == 0) /* Not in MCE mode */
333 {
334 return;
335 }
336 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
337 if (acal & 0x08) /* Auto calibration is enabled */
338 wait_for_calibration(devc);
339 }
340
341 static int ad1848_set_recmask(ad1848_info * devc, int mask)
342 {
343 unsigned char recdev;
344 int i, n;
345 unsigned long flags;
346
347 mask &= devc->supported_rec_devices;
348
349 /* Rename the mixer bits if necessary */
350 for (i = 0; i < 32; i++)
351 {
352 if (devc->mixer_reroute[i] != i)
353 {
354 if (mask & (1 << i))
355 {
356 mask &= ~(1 << i);
357 mask |= (1 << devc->mixer_reroute[i]);
358 }
359 }
360 }
361
362 n = 0;
363 for (i = 0; i < 32; i++) /* Count selected device bits */
364 if (mask & (1 << i))
365 n++;
366
367 spin_lock_irqsave(&devc->lock,flags);
368 if (!soundpro) {
369 if (n == 0)
370 mask = SOUND_MASK_MIC;
371 else if (n != 1) { /* Too many devices selected */
372 mask &= ~devc->recmask; /* Filter out active settings */
373
374 n = 0;
375 for (i = 0; i < 32; i++) /* Count selected device bits */
376 if (mask & (1 << i))
377 n++;
378
379 if (n != 1)
380 mask = SOUND_MASK_MIC;
381 }
382 switch (mask) {
383 case SOUND_MASK_MIC:
384 recdev = 2;
385 break;
386
387 case SOUND_MASK_LINE:
388 case SOUND_MASK_LINE3:
389 recdev = 0;
390 break;
391
392 case SOUND_MASK_CD:
393 case SOUND_MASK_LINE1:
394 recdev = 1;
395 break;
396
397 case SOUND_MASK_IMIX:
398 recdev = 3;
399 break;
400
401 default:
402 mask = SOUND_MASK_MIC;
403 recdev = 2;
404 }
405
406 recdev <<= 6;
407 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
408 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
409 } else { /* soundpro */
410 unsigned char val;
411 int set_rec_bit;
412 int j;
413
414 for (i = 0; i < 32; i++) { /* For each bit */
415 if ((devc->supported_rec_devices & (1 << i)) == 0)
416 continue; /* Device not supported */
417
418 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
419 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
420 continue;
421
422 /*
423 * This is tricky:
424 * set_rec_bit becomes 1 if the corresponding bit in mask is set
425 * then it gets flipped if the polarity is inverse
426 */
427 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
428
429 val = ad_read(devc, devc->mix_devices[i][j].recreg);
430 val &= ~(1 << devc->mix_devices[i][j].recpos);
431 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
432 ad_write(devc, devc->mix_devices[i][j].recreg, val);
433 }
434 }
435 }
436 spin_unlock_irqrestore(&devc->lock,flags);
437
438 /* Rename the mixer bits back if necessary */
439 for (i = 0; i < 32; i++)
440 {
441 if (devc->mixer_reroute[i] != i)
442 {
443 if (mask & (1 << devc->mixer_reroute[i]))
444 {
445 mask &= ~(1 << devc->mixer_reroute[i]);
446 mask |= (1 << i);
447 }
448 }
449 }
450 devc->recmask = mask;
451 return mask;
452 }
453
454 static void oss_change_bits(ad1848_info *devc, unsigned char *regval,
455 unsigned char *muteval, int dev, int chn, int newval)
456 {
457 unsigned char mask;
458 int shift;
459 int mute;
460 int mutemask;
461 int set_mute_bit;
462
463 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
464
465 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
466 newval = 100 - newval;
467
468 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
469 shift = devc->mix_devices[dev][chn].bitpos;
470
471 if (devc->mix_devices[dev][chn].mutepos == 8)
472 { /* if there is no mute bit */
473 mute = 0; /* No mute bit; do nothing special */
474 mutemask = ~0; /* No mute bit; do nothing special */
475 }
476 else
477 {
478 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
479 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
480 }
481
482 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
483 *regval &= ~(mask << shift); /* Clear bits */
484 *regval |= (newval & mask) << shift; /* Set new value */
485
486 *muteval &= mutemask;
487 *muteval |= mute;
488 }
489
490 static int ad1848_mixer_get(ad1848_info * devc, int dev)
491 {
492 if (!((1 << dev) & devc->supported_devices))
493 return -EINVAL;
494
495 dev = devc->mixer_reroute[dev];
496
497 return devc->levels[dev];
498 }
499
500 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
501 {
502 int regoffs, muteregoffs;
503 unsigned char val, muteval;
504 unsigned long flags;
505
506 regoffs = devc->mix_devices[dev][channel].regno;
507 muteregoffs = devc->mix_devices[dev][channel].mutereg;
508 val = ad_read(devc, regoffs);
509
510 if (muteregoffs != regoffs) {
511 muteval = ad_read(devc, muteregoffs);
512 oss_change_bits(devc, &val, &muteval, dev, channel, value);
513 }
514 else
515 oss_change_bits(devc, &val, &val, dev, channel, value);
516
517 spin_lock_irqsave(&devc->lock,flags);
518 ad_write(devc, regoffs, val);
519 devc->saved_regs[regoffs] = val;
520 if (muteregoffs != regoffs) {
521 ad_write(devc, muteregoffs, muteval);
522 devc->saved_regs[muteregoffs] = muteval;
523 }
524 spin_unlock_irqrestore(&devc->lock,flags);
525 }
526
527 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
528 {
529 int left = value & 0x000000ff;
530 int right = (value & 0x0000ff00) >> 8;
531 int retvol;
532
533 if (dev > 31)
534 return -EINVAL;
535
536 if (!(devc->supported_devices & (1 << dev)))
537 return -EINVAL;
538
539 dev = devc->mixer_reroute[dev];
540
541 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
542 return -EINVAL;
543
544 if (left > 100)
545 left = 100;
546 if (right > 100)
547 right = 100;
548
549 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
550 right = left;
551
552 retvol = left | (right << 8);
553
554 /* Scale volumes */
555 left = mix_cvt[left];
556 right = mix_cvt[right];
557
558 devc->levels[dev] = retvol;
559
560 /*
561 * Set the left channel
562 */
563 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
564
565 /*
566 * Set the right channel
567 */
568 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
569 goto out;
570 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
571
572 out:
573 return retvol;
574 }
575
576 static void ad1848_mixer_reset(ad1848_info * devc)
577 {
578 int i;
579 char name[32];
580 unsigned long flags;
581
582 devc->mix_devices = &(ad1848_mix_devices[0]);
583
584 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
585
586 for (i = 0; i < 32; i++)
587 devc->mixer_reroute[i] = i;
588
589 devc->supported_rec_devices = MODE1_REC_DEVICES;
590
591 switch (devc->model)
592 {
593 case MD_4231:
594 case MD_4231A:
595 case MD_1845:
596 case MD_1845_SSCAPE:
597 devc->supported_devices = MODE2_MIXER_DEVICES;
598 break;
599
600 case MD_C930:
601 devc->supported_devices = C930_MIXER_DEVICES;
602 devc->mix_devices = &(c930_mix_devices[0]);
603 break;
604
605 case MD_IWAVE:
606 devc->supported_devices = MODE3_MIXER_DEVICES;
607 devc->mix_devices = &(iwave_mix_devices[0]);
608 break;
609
610 case MD_42xB:
611 case MD_4239:
612 devc->mix_devices = &(cs42xb_mix_devices[0]);
613 devc->supported_devices = MODE3_MIXER_DEVICES;
614 break;
615 case MD_4232:
616 case MD_4235:
617 case MD_4236:
618 devc->supported_devices = MODE3_MIXER_DEVICES;
619 break;
620
621 case MD_1848:
622 if (soundpro) {
623 devc->supported_devices = SPRO_MIXER_DEVICES;
624 devc->supported_rec_devices = SPRO_REC_DEVICES;
625 devc->mix_devices = &(spro_mix_devices[0]);
626 break;
627 }
628
629 default:
630 devc->supported_devices = MODE1_MIXER_DEVICES;
631 }
632
633 devc->orig_devices = devc->supported_devices;
634 devc->orig_rec_devices = devc->supported_rec_devices;
635
636 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
637
638 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
639 {
640 if (devc->supported_devices & (1 << i))
641 ad1848_mixer_set(devc, i, devc->levels[i]);
642 }
643
644 ad1848_set_recmask(devc, SOUND_MASK_MIC);
645
646 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
647
648 spin_lock_irqsave(&devc->lock,flags);
649 if (!soundpro) {
650 if (devc->mixer_output_port & AUDIO_SPEAKER)
651 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
652 else
653 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
654 } else {
655 /*
656 * From the "wouldn't it be nice if the mixer API had (better)
657 * support for custom stuff" category
658 */
659 /* Enable surround mode and SB16 mixer */
660 ad_write(devc, 16, 0x60);
661 }
662 spin_unlock_irqrestore(&devc->lock,flags);
663 }
664
665 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
666 {
667 ad1848_info *devc = mixer_devs[dev]->devc;
668 int val;
669
670 if (cmd == SOUND_MIXER_PRIVATE1)
671 {
672 if (get_user(val, (int __user *)arg))
673 return -EFAULT;
674
675 if (val != 0xffff)
676 {
677 unsigned long flags;
678 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
679 devc->mixer_output_port = val;
680 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
681 devc->mixer_output_port = val;
682 spin_lock_irqsave(&devc->lock,flags);
683 if (val & AUDIO_SPEAKER)
684 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
685 else
686 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
687 spin_unlock_irqrestore(&devc->lock,flags);
688 }
689 val = devc->mixer_output_port;
690 return put_user(val, (int __user *)arg);
691 }
692 if (cmd == SOUND_MIXER_PRIVATE2)
693 {
694 if (get_user(val, (int __user *)arg))
695 return -EFAULT;
696 return(ad1848_control(AD1848_MIXER_REROUTE, val));
697 }
698 if (((cmd >> 8) & 0xff) == 'M')
699 {
700 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
701 {
702 switch (cmd & 0xff)
703 {
704 case SOUND_MIXER_RECSRC:
705 if (get_user(val, (int __user *)arg))
706 return -EFAULT;
707 val = ad1848_set_recmask(devc, val);
708 break;
709
710 default:
711 if (get_user(val, (int __user *)arg))
712 return -EFAULT;
713 val = ad1848_mixer_set(devc, cmd & 0xff, val);
714 break;
715 }
716 return put_user(val, (int __user *)arg);
717 }
718 else
719 {
720 switch (cmd & 0xff)
721 {
722 /*
723 * Return parameters
724 */
725
726 case SOUND_MIXER_RECSRC:
727 val = devc->recmask;
728 break;
729
730 case SOUND_MIXER_DEVMASK:
731 val = devc->supported_devices;
732 break;
733
734 case SOUND_MIXER_STEREODEVS:
735 val = devc->supported_devices;
736 if (devc->model != MD_C930)
737 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
738 break;
739
740 case SOUND_MIXER_RECMASK:
741 val = devc->supported_rec_devices;
742 break;
743
744 case SOUND_MIXER_CAPS:
745 val=SOUND_CAP_EXCL_INPUT;
746 break;
747
748 default:
749 val = ad1848_mixer_get(devc, cmd & 0xff);
750 break;
751 }
752 return put_user(val, (int __user *)arg);
753 }
754 }
755 else
756 return -EINVAL;
757 }
758
759 static int ad1848_set_speed(int dev, int arg)
760 {
761 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
762 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
763
764 /*
765 * The sampling speed is encoded in the least significant nibble of I8. The
766 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
767 * three bits select the divisor (indirectly):
768 *
769 * The available speeds are in the following table. Keep the speeds in
770 * the increasing order.
771 */
772 typedef struct
773 {
774 int speed;
775 unsigned char bits;
776 }
777 speed_struct;
778
779 static speed_struct speed_table[] =
780 {
781 {5510, (0 << 1) | 1},
782 {5510, (0 << 1) | 1},
783 {6620, (7 << 1) | 1},
784 {8000, (0 << 1) | 0},
785 {9600, (7 << 1) | 0},
786 {11025, (1 << 1) | 1},
787 {16000, (1 << 1) | 0},
788 {18900, (2 << 1) | 1},
789 {22050, (3 << 1) | 1},
790 {27420, (2 << 1) | 0},
791 {32000, (3 << 1) | 0},
792 {33075, (6 << 1) | 1},
793 {37800, (4 << 1) | 1},
794 {44100, (5 << 1) | 1},
795 {48000, (6 << 1) | 0}
796 };
797
798 int i, n, selected = -1;
799
800 n = sizeof(speed_table) / sizeof(speed_struct);
801
802 if (arg <= 0)
803 return portc->speed;
804
805 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
806 {
807 if (arg < 4000)
808 arg = 4000;
809 if (arg > 50000)
810 arg = 50000;
811
812 portc->speed = arg;
813 portc->speed_bits = speed_table[3].bits;
814 return portc->speed;
815 }
816 if (arg < speed_table[0].speed)
817 selected = 0;
818 if (arg > speed_table[n - 1].speed)
819 selected = n - 1;
820
821 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
822 {
823 if (speed_table[i].speed == arg)
824 selected = i;
825 else if (speed_table[i].speed > arg)
826 {
827 int diff1, diff2;
828
829 diff1 = arg - speed_table[i - 1].speed;
830 diff2 = speed_table[i].speed - arg;
831
832 if (diff1 < diff2)
833 selected = i - 1;
834 else
835 selected = i;
836 }
837 }
838 if (selected == -1)
839 {
840 printk(KERN_WARNING "ad1848: Can't find speed???\n");
841 selected = 3;
842 }
843 portc->speed = speed_table[selected].speed;
844 portc->speed_bits = speed_table[selected].bits;
845 return portc->speed;
846 }
847
848 static short ad1848_set_channels(int dev, short arg)
849 {
850 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
851
852 if (arg != 1 && arg != 2)
853 return portc->channels;
854
855 portc->channels = arg;
856 return arg;
857 }
858
859 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
860 {
861 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
862 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
863
864 static struct format_tbl
865 {
866 int format;
867 unsigned char bits;
868 }
869 format2bits[] =
870 {
871 {
872 0, 0
873 }
874 ,
875 {
876 AFMT_MU_LAW, 1
877 }
878 ,
879 {
880 AFMT_A_LAW, 3
881 }
882 ,
883 {
884 AFMT_IMA_ADPCM, 5
885 }
886 ,
887 {
888 AFMT_U8, 0
889 }
890 ,
891 {
892 AFMT_S16_LE, 2
893 }
894 ,
895 {
896 AFMT_S16_BE, 6
897 }
898 ,
899 {
900 AFMT_S8, 0
901 }
902 ,
903 {
904 AFMT_U16_LE, 0
905 }
906 ,
907 {
908 AFMT_U16_BE, 0
909 }
910 };
911 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
912
913 if (arg == 0)
914 return portc->audio_format;
915
916 if (!(arg & ad_format_mask[devc->model]))
917 arg = AFMT_U8;
918
919 portc->audio_format = arg;
920
921 for (i = 0; i < n; i++)
922 if (format2bits[i].format == arg)
923 {
924 if ((portc->format_bits = format2bits[i].bits) == 0)
925 return portc->audio_format = AFMT_U8; /* Was not supported */
926
927 return arg;
928 }
929 /* Still hanging here. Something must be terribly wrong */
930 portc->format_bits = 0;
931 return portc->audio_format = AFMT_U8;
932 }
933
934 static struct audio_driver ad1848_audio_driver =
935 {
936 .owner = THIS_MODULE,
937 .open = ad1848_open,
938 .close = ad1848_close,
939 .output_block = ad1848_output_block,
940 .start_input = ad1848_start_input,
941 .prepare_for_input = ad1848_prepare_for_input,
942 .prepare_for_output = ad1848_prepare_for_output,
943 .halt_io = ad1848_halt,
944 .halt_input = ad1848_halt_input,
945 .halt_output = ad1848_halt_output,
946 .trigger = ad1848_trigger,
947 .set_speed = ad1848_set_speed,
948 .set_bits = ad1848_set_bits,
949 .set_channels = ad1848_set_channels
950 };
951
952 static struct mixer_operations ad1848_mixer_operations =
953 {
954 .owner = THIS_MODULE,
955 .id = "SOUNDPORT",
956 .name = "AD1848/CS4248/CS4231",
957 .ioctl = ad1848_mixer_ioctl
958 };
959
960 static int ad1848_open(int dev, int mode)
961 {
962 ad1848_info *devc;
963 ad1848_port_info *portc;
964 unsigned long flags;
965
966 if (dev < 0 || dev >= num_audiodevs)
967 return -ENXIO;
968
969 devc = (ad1848_info *) audio_devs[dev]->devc;
970 portc = (ad1848_port_info *) audio_devs[dev]->portc;
971
972 /* here we don't have to protect against intr */
973 spin_lock(&devc->lock);
974 if (portc->open_mode || (devc->open_mode & mode))
975 {
976 spin_unlock(&devc->lock);
977 return -EBUSY;
978 }
979 devc->dual_dma = 0;
980
981 if (audio_devs[dev]->flags & DMA_DUPLEX)
982 {
983 devc->dual_dma = 1;
984 }
985 devc->intr_active = 0;
986 devc->audio_mode = 0;
987 devc->open_mode |= mode;
988 portc->open_mode = mode;
989 spin_unlock(&devc->lock);
990 ad1848_trigger(dev, 0);
991
992 if (mode & OPEN_READ)
993 devc->record_dev = dev;
994 if (mode & OPEN_WRITE)
995 devc->playback_dev = dev;
996 /*
997 * Mute output until the playback really starts. This decreases clicking (hope so).
998 */
999 spin_lock_irqsave(&devc->lock,flags);
1000 ad_mute(devc);
1001 spin_unlock_irqrestore(&devc->lock,flags);
1002
1003 return 0;
1004 }
1005
1006 static void ad1848_close(int dev)
1007 {
1008 unsigned long flags;
1009 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1010 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1011
1012 devc->intr_active = 0;
1013 ad1848_halt(dev);
1014
1015 spin_lock_irqsave(&devc->lock,flags);
1016
1017 devc->audio_mode = 0;
1018 devc->open_mode &= ~portc->open_mode;
1019 portc->open_mode = 0;
1020
1021 ad_unmute(devc);
1022 spin_unlock_irqrestore(&devc->lock,flags);
1023 }
1024
1025 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1026 {
1027 unsigned long flags, cnt;
1028 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1029 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1030
1031 cnt = count;
1032
1033 if (portc->audio_format == AFMT_IMA_ADPCM)
1034 {
1035 cnt /= 4;
1036 }
1037 else
1038 {
1039 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1040 cnt >>= 1;
1041 }
1042 if (portc->channels > 1)
1043 cnt >>= 1;
1044 cnt--;
1045
1046 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1047 intrflag &&
1048 cnt == devc->xfer_count)
1049 {
1050 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1051 devc->intr_active = 1;
1052 return; /*
1053 * Auto DMA mode on. No need to react
1054 */
1055 }
1056 spin_lock_irqsave(&devc->lock,flags);
1057
1058 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1059 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1060
1061 devc->xfer_count = cnt;
1062 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1063 devc->intr_active = 1;
1064 spin_unlock_irqrestore(&devc->lock,flags);
1065 }
1066
1067 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1068 {
1069 unsigned long flags, cnt;
1070 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1071 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1072
1073 cnt = count;
1074 if (portc->audio_format == AFMT_IMA_ADPCM)
1075 {
1076 cnt /= 4;
1077 }
1078 else
1079 {
1080 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1081 cnt >>= 1;
1082 }
1083 if (portc->channels > 1)
1084 cnt >>= 1;
1085 cnt--;
1086
1087 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1088 intrflag &&
1089 cnt == devc->xfer_count)
1090 {
1091 devc->audio_mode |= PCM_ENABLE_INPUT;
1092 devc->intr_active = 1;
1093 return; /*
1094 * Auto DMA mode on. No need to react
1095 */
1096 }
1097 spin_lock_irqsave(&devc->lock,flags);
1098
1099 if (devc->model == MD_1848)
1100 {
1101 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1102 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1103 }
1104 else
1105 {
1106 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1107 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1108 }
1109
1110 ad_unmute(devc);
1111
1112 devc->xfer_count = cnt;
1113 devc->audio_mode |= PCM_ENABLE_INPUT;
1114 devc->intr_active = 1;
1115 spin_unlock_irqrestore(&devc->lock,flags);
1116 }
1117
1118 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1119 {
1120 int timeout;
1121 unsigned char fs, old_fs, tmp = 0;
1122 unsigned long flags;
1123 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1124 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1125
1126 ad_mute(devc);
1127
1128 spin_lock_irqsave(&devc->lock,flags);
1129 fs = portc->speed_bits | (portc->format_bits << 5);
1130
1131 if (portc->channels > 1)
1132 fs |= 0x10;
1133
1134 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1135
1136 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1137 {
1138 fs &= 0xf0; /* Mask off the rate select bits */
1139
1140 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1141 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1142 }
1143 old_fs = ad_read(devc, 8);
1144
1145 if (devc->model == MD_4232 || devc->model >= MD_4236)
1146 {
1147 tmp = ad_read(devc, 16);
1148 ad_write(devc, 16, tmp | 0x30);
1149 }
1150 if (devc->model == MD_IWAVE)
1151 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1152
1153 ad_write(devc, 8, fs);
1154
1155 /*
1156 * Write to I8 starts resynchronization. Wait until it completes.
1157 */
1158
1159 timeout = 0;
1160 while (timeout < 100 && inb(devc->base) != 0x80)
1161 timeout++;
1162 timeout = 0;
1163 while (timeout < 10000 && inb(devc->base) == 0x80)
1164 timeout++;
1165
1166 if (devc->model >= MD_4232)
1167 ad_write(devc, 16, tmp & ~0x30);
1168
1169 ad_leave_MCE(devc); /*
1170 * Starts the calibration process.
1171 */
1172 spin_unlock_irqrestore(&devc->lock,flags);
1173 devc->xfer_count = 0;
1174
1175 #ifndef EXCLUDE_TIMERS
1176 if (dev == timer_installed && devc->timer_running)
1177 if ((fs & 0x01) != (old_fs & 0x01))
1178 {
1179 ad1848_tmr_reprogram(dev);
1180 }
1181 #endif
1182 ad1848_halt_output(dev);
1183 return 0;
1184 }
1185
1186 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1187 {
1188 int timeout;
1189 unsigned char fs, old_fs, tmp = 0;
1190 unsigned long flags;
1191 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1192 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1193
1194 if (devc->audio_mode)
1195 return 0;
1196
1197 spin_lock_irqsave(&devc->lock,flags);
1198 fs = portc->speed_bits | (portc->format_bits << 5);
1199
1200 if (portc->channels > 1)
1201 fs |= 0x10;
1202
1203 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1204
1205 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1206 {
1207 fs &= 0xf0; /* Mask off the rate select bits */
1208
1209 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1210 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1211 }
1212 if (devc->model == MD_4232)
1213 {
1214 tmp = ad_read(devc, 16);
1215 ad_write(devc, 16, tmp | 0x30);
1216 }
1217 if (devc->model == MD_IWAVE)
1218 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1219
1220 /*
1221 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1222 */
1223
1224 if (devc->model != MD_1848)
1225 {
1226 old_fs = ad_read(devc, 28);
1227 ad_write(devc, 28, fs);
1228
1229 /*
1230 * Write to I28 starts resynchronization. Wait until it completes.
1231 */
1232
1233 timeout = 0;
1234 while (timeout < 100 && inb(devc->base) != 0x80)
1235 timeout++;
1236
1237 timeout = 0;
1238 while (timeout < 10000 && inb(devc->base) == 0x80)
1239 timeout++;
1240
1241 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1242 {
1243 /*
1244 * CS4231 compatible devices don't have separate sampling rate selection
1245 * register for recording an playback. The I8 register is shared so we have to
1246 * set the speed encoding bits of it too.
1247 */
1248 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1249
1250 ad_write(devc, 8, tmp);
1251 /*
1252 * Write to I8 starts resynchronization. Wait until it completes.
1253 */
1254 timeout = 0;
1255 while (timeout < 100 && inb(devc->base) != 0x80)
1256 timeout++;
1257
1258 timeout = 0;
1259 while (timeout < 10000 && inb(devc->base) == 0x80)
1260 timeout++;
1261 }
1262 }
1263 else
1264 { /* For AD1848 set I8. */
1265
1266 old_fs = ad_read(devc, 8);
1267 ad_write(devc, 8, fs);
1268 /*
1269 * Write to I8 starts resynchronization. Wait until it completes.
1270 */
1271 timeout = 0;
1272 while (timeout < 100 && inb(devc->base) != 0x80)
1273 timeout++;
1274 timeout = 0;
1275 while (timeout < 10000 && inb(devc->base) == 0x80)
1276 timeout++;
1277 }
1278
1279 if (devc->model == MD_4232)
1280 ad_write(devc, 16, tmp & ~0x30);
1281
1282 ad_leave_MCE(devc); /*
1283 * Starts the calibration process.
1284 */
1285 spin_unlock_irqrestore(&devc->lock,flags);
1286 devc->xfer_count = 0;
1287
1288 #ifndef EXCLUDE_TIMERS
1289 if (dev == timer_installed && devc->timer_running)
1290 {
1291 if ((fs & 0x01) != (old_fs & 0x01))
1292 {
1293 ad1848_tmr_reprogram(dev);
1294 }
1295 }
1296 #endif
1297 ad1848_halt_input(dev);
1298 return 0;
1299 }
1300
1301 static void ad1848_halt(int dev)
1302 {
1303 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1304 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1305
1306 unsigned char bits = ad_read(devc, 9);
1307
1308 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1309 ad1848_halt_output(dev);
1310
1311 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1312 ad1848_halt_input(dev);
1313 devc->audio_mode = 0;
1314 }
1315
1316 static void ad1848_halt_input(int dev)
1317 {
1318 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1319 unsigned long flags;
1320
1321 if (!(ad_read(devc, 9) & 0x02))
1322 return; /* Capture not enabled */
1323
1324 spin_lock_irqsave(&devc->lock,flags);
1325
1326 ad_mute(devc);
1327
1328 {
1329 int tmout;
1330
1331 if(!isa_dma_bridge_buggy)
1332 disable_dma(audio_devs[dev]->dmap_in->dma);
1333
1334 for (tmout = 0; tmout < 100000; tmout++)
1335 if (ad_read(devc, 11) & 0x10)
1336 break;
1337 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1338
1339 if(!isa_dma_bridge_buggy)
1340 enable_dma(audio_devs[dev]->dmap_in->dma);
1341 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1342 }
1343
1344 outb(0, io_Status(devc)); /* Clear interrupt status */
1345 outb(0, io_Status(devc)); /* Clear interrupt status */
1346
1347 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1348
1349 spin_unlock_irqrestore(&devc->lock,flags);
1350 }
1351
1352 static void ad1848_halt_output(int dev)
1353 {
1354 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1355 unsigned long flags;
1356
1357 if (!(ad_read(devc, 9) & 0x01))
1358 return; /* Playback not enabled */
1359
1360 spin_lock_irqsave(&devc->lock,flags);
1361
1362 ad_mute(devc);
1363 {
1364 int tmout;
1365
1366 if(!isa_dma_bridge_buggy)
1367 disable_dma(audio_devs[dev]->dmap_out->dma);
1368
1369 for (tmout = 0; tmout < 100000; tmout++)
1370 if (ad_read(devc, 11) & 0x10)
1371 break;
1372 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1373
1374 if(!isa_dma_bridge_buggy)
1375 enable_dma(audio_devs[dev]->dmap_out->dma);
1376
1377 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1378 }
1379
1380 outb((0), io_Status(devc)); /* Clear interrupt status */
1381 outb((0), io_Status(devc)); /* Clear interrupt status */
1382
1383 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1384
1385 spin_unlock_irqrestore(&devc->lock,flags);
1386 }
1387
1388 static void ad1848_trigger(int dev, int state)
1389 {
1390 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1391 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1392 unsigned long flags;
1393 unsigned char tmp, old;
1394
1395 spin_lock_irqsave(&devc->lock,flags);
1396 state &= devc->audio_mode;
1397
1398 tmp = old = ad_read(devc, 9);
1399
1400 if (portc->open_mode & OPEN_READ)
1401 {
1402 if (state & PCM_ENABLE_INPUT)
1403 tmp |= 0x02;
1404 else
1405 tmp &= ~0x02;
1406 }
1407 if (portc->open_mode & OPEN_WRITE)
1408 {
1409 if (state & PCM_ENABLE_OUTPUT)
1410 tmp |= 0x01;
1411 else
1412 tmp &= ~0x01;
1413 }
1414 /* ad_mute(devc); */
1415 if (tmp != old)
1416 {
1417 ad_write(devc, 9, tmp);
1418 ad_unmute(devc);
1419 }
1420 spin_unlock_irqrestore(&devc->lock,flags);
1421 }
1422
1423 static void ad1848_init_hw(ad1848_info * devc)
1424 {
1425 int i;
1426 int *init_values;
1427
1428 /*
1429 * Initial values for the indirect registers of CS4248/AD1848.
1430 */
1431 static int init_values_a[] =
1432 {
1433 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1434 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1435
1436 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1437 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1439 };
1440
1441 static int init_values_b[] =
1442 {
1443 /*
1444 Values for the newer chips
1445 Some of the register initialization values were changed. In
1446 order to get rid of the click that preceded PCM playback,
1447 calibration was disabled on the 10th byte. On that same byte,
1448 dual DMA was enabled; on the 11th byte, ADC dithering was
1449 enabled, since that is theoretically desirable; on the 13th
1450 byte, Mode 3 was selected, to enable access to extended
1451 registers.
1452 */
1453 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1454 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1455 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1456 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1457 };
1458
1459 /*
1460 * Select initialisation data
1461 */
1462
1463 init_values = init_values_a;
1464 if(devc->model >= MD_4236)
1465 init_values = init_values_b;
1466
1467 for (i = 0; i < 16; i++)
1468 ad_write(devc, i, init_values[i]);
1469
1470
1471 ad_mute(devc); /* Initialize some variables */
1472 ad_unmute(devc); /* Leave it unmuted now */
1473
1474 if (devc->model > MD_1848)
1475 {
1476 if (devc->model == MD_1845_SSCAPE)
1477 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1478 else
1479 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1480
1481 if (devc->model == MD_IWAVE)
1482 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1483
1484 if (devc->model != MD_1845_SSCAPE)
1485 for (i = 16; i < 32; i++)
1486 ad_write(devc, i, init_values[i]);
1487
1488 if (devc->model == MD_IWAVE)
1489 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1490 }
1491 if (devc->model > MD_1848)
1492 {
1493 if (devc->audio_flags & DMA_DUPLEX)
1494 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1495 else
1496 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1497
1498 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1499 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1500
1501 if (devc->model == MD_IWAVE)
1502 { /* Some magic Interwave specific initialization */
1503 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1504 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1505 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1506 }
1507 }
1508 else
1509 {
1510 devc->audio_flags &= ~DMA_DUPLEX;
1511 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1512 if (soundpro)
1513 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1514 }
1515
1516 outb((0), io_Status(devc)); /* Clear pending interrupts */
1517
1518 /*
1519 * Toggle the MCE bit. It completes the initialization phase.
1520 */
1521
1522 ad_enter_MCE(devc); /* In case the bit was off */
1523 ad_leave_MCE(devc);
1524
1525 ad1848_mixer_reset(devc);
1526 }
1527
1528 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1529 {
1530 unsigned char tmp;
1531 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1532 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1533 int optiC930 = 0; /* OPTi 82C930 flag */
1534 int interwave = 0;
1535 int ad1847_flag = 0;
1536 int cs4248_flag = 0;
1537 int sscape_flag = 0;
1538 int io_base = ports->start;
1539
1540 int i;
1541
1542 DDB(printk("ad1848_detect(%x)\n", io_base));
1543
1544 if (ad_flags)
1545 {
1546 if (*ad_flags == 0x12345678)
1547 {
1548 interwave = 1;
1549 *ad_flags = 0;
1550 }
1551
1552 if (*ad_flags == 0x87654321)
1553 {
1554 sscape_flag = 1;
1555 *ad_flags = 0;
1556 }
1557
1558 if (*ad_flags == 0x12345677)
1559 {
1560 cs4248_flag = 1;
1561 *ad_flags = 0;
1562 }
1563 }
1564 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1565 {
1566 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1567 return 0;
1568 }
1569 spin_lock_init(&devc->lock);
1570 devc->base = io_base;
1571 devc->irq_ok = 0;
1572 devc->timer_running = 0;
1573 devc->MCE_bit = 0x40;
1574 devc->irq = 0;
1575 devc->open_mode = 0;
1576 devc->chip_name = devc->name = "AD1848";
1577 devc->model = MD_1848; /* AD1848 or CS4248 */
1578 devc->levels = NULL;
1579 devc->debug_flag = 0;
1580
1581 /*
1582 * Check that the I/O address is in use.
1583 *
1584 * The bit 0x80 of the base I/O port is known to be 0 after the
1585 * chip has performed its power on initialization. Just assume
1586 * this has happened before the OS is starting.
1587 *
1588 * If the I/O address is unused, it typically returns 0xff.
1589 */
1590
1591 if (inb(devc->base) == 0xff)
1592 {
1593 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1594 }
1595
1596 /*
1597 * Wait for the device to stop initialization
1598 */
1599
1600 DDB(printk("ad1848_detect() - step 0\n"));
1601
1602 for (i = 0; i < 10000000; i++)
1603 {
1604 unsigned char x = inb(devc->base);
1605
1606 if (x == 0xff || !(x & 0x80))
1607 break;
1608 }
1609
1610 DDB(printk("ad1848_detect() - step A\n"));
1611
1612 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1613 ad_leave_MCE(devc);
1614
1615 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1616 {
1617 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1618 return 0;
1619 }
1620
1621 /*
1622 * Test if it's possible to change contents of the indirect registers.
1623 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1624 * so try to avoid using it.
1625 */
1626
1627 DDB(printk("ad1848_detect() - step B\n"));
1628 ad_write(devc, 0, 0xaa);
1629 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1630
1631 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1632 {
1633 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1634 ad1847_flag = 1;
1635 else
1636 {
1637 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1638 return 0;
1639 }
1640 }
1641 DDB(printk("ad1848_detect() - step C\n"));
1642 ad_write(devc, 0, 0x45);
1643 ad_write(devc, 1, 0xaa);
1644
1645 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1646 {
1647 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1648 ad1847_flag = 1;
1649 else
1650 {
1651 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1652 return 0;
1653 }
1654 }
1655
1656 /*
1657 * The indirect register I12 has some read only bits. Let's
1658 * try to change them.
1659 */
1660
1661 DDB(printk("ad1848_detect() - step D\n"));
1662 tmp = ad_read(devc, 12);
1663 ad_write(devc, 12, (~tmp) & 0x0f);
1664
1665 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1666 {
1667 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1668 return 0;
1669 }
1670
1671 /*
1672 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1673 * 0x01=RevB and 0x0A=RevC.
1674 */
1675
1676 /*
1677 * The original AD1848/CS4248 has just 15 indirect registers. This means
1678 * that I0 and I16 should return the same value (etc.).
1679 * However this doesn't work with CS4248. Actually it seems to be impossible
1680 * to detect if the chip is a CS4231 or CS4248.
1681 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1682 * with CS4231.
1683 */
1684
1685 /*
1686 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1687 * with it. Accept this situation as a possible indication of this chip.
1688 */
1689
1690 DDB(printk("ad1848_detect() - step F\n"));
1691 ad_write(devc, 12, 0); /* Mode2=disabled */
1692
1693 for (i = 0; i < 16; i++)
1694 {
1695 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1696 {
1697 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1698 if (!ad1847_flag)
1699 optiC930 = 1;
1700 break;
1701 }
1702 }
1703
1704 /*
1705 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1706 * The bit 0x80 is always 1 in CS4248 and CS4231.
1707 */
1708
1709 DDB(printk("ad1848_detect() - step G\n"));
1710
1711 if (ad_flags && *ad_flags == 400)
1712 *ad_flags = 0;
1713 else
1714 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1715
1716
1717 if (ad_flags)
1718 *ad_flags = 0;
1719
1720 tmp1 = ad_read(devc, 12);
1721 if (tmp1 & 0x80)
1722 {
1723 if (ad_flags)
1724 *ad_flags |= AD_F_CS4248;
1725
1726 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1727 }
1728 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1729 {
1730 /*
1731 * CS4231 detected - is it?
1732 *
1733 * Verify that setting I0 doesn't change I16.
1734 */
1735
1736 DDB(printk("ad1848_detect() - step H\n"));
1737 ad_write(devc, 16, 0); /* Set I16 to known value */
1738
1739 ad_write(devc, 0, 0x45);
1740 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1741 {
1742 ad_write(devc, 0, 0xaa);
1743 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1744 {
1745 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1746 return 0;
1747 }
1748
1749 /*
1750 * Verify that some bits of I25 are read only.
1751 */
1752
1753 DDB(printk("ad1848_detect() - step I\n"));
1754 tmp1 = ad_read(devc, 25); /* Original bits */
1755 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1756 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1757 {
1758 int id;
1759
1760 /*
1761 * It's at least CS4231
1762 */
1763
1764 devc->chip_name = "CS4231";
1765 devc->model = MD_4231;
1766
1767 /*
1768 * It could be an AD1845 or CS4231A as well.
1769 * CS4231 and AD1845 report the same revision info in I25
1770 * while the CS4231A reports different.
1771 */
1772
1773 id = ad_read(devc, 25);
1774 if ((id & 0xe7) == 0x80) /* Device busy??? */
1775 id = ad_read(devc, 25);
1776 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1777 id = ad_read(devc, 25);
1778 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1779
1780 if ((id & 0xe7) == 0x80) {
1781 /*
1782 * It must be a CS4231 or AD1845. The register I23 of
1783 * CS4231 is undefined and it appears to be read only.
1784 * AD1845 uses I23 for setting sample rate. Assume
1785 * the chip is AD1845 if I23 is changeable.
1786 */
1787
1788 unsigned char tmp = ad_read(devc, 23);
1789 ad_write(devc, 23, ~tmp);
1790
1791 if (interwave)
1792 {
1793 devc->model = MD_IWAVE;
1794 devc->chip_name = "IWave";
1795 }
1796 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1797 {
1798 devc->chip_name = "AD1845";
1799 devc->model = MD_1845;
1800 }
1801 else if (cs4248_flag)
1802 {
1803 if (ad_flags)
1804 *ad_flags |= AD_F_CS4248;
1805 devc->chip_name = "CS4248";
1806 devc->model = MD_1848;
1807 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1808 }
1809 ad_write(devc, 23, tmp); /* Restore */
1810 }
1811 else
1812 {
1813 switch (id & 0x1f) {
1814 case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1815 {
1816 int xid;
1817 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1818 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1819 xid = inb(io_Indexed_Data(devc));
1820 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1821 switch (xid & 0x1f)
1822 {
1823 case 0x00:
1824 devc->chip_name = "CS4237B(B)";
1825 devc->model = MD_42xB;
1826 break;
1827 case 0x08:
1828 /* Seems to be a 4238 ?? */
1829 devc->chip_name = "CS4238";
1830 devc->model = MD_42xB;
1831 break;
1832 case 0x09:
1833 devc->chip_name = "CS4238B";
1834 devc->model = MD_42xB;
1835 break;
1836 case 0x0b:
1837 devc->chip_name = "CS4236B";
1838 devc->model = MD_4236;
1839 break;
1840 case 0x10:
1841 devc->chip_name = "CS4237B";
1842 devc->model = MD_42xB;
1843 break;
1844 case 0x1d:
1845 devc->chip_name = "CS4235";
1846 devc->model = MD_4235;
1847 break;
1848 case 0x1e:
1849 devc->chip_name = "CS4239";
1850 devc->model = MD_4239;
1851 break;
1852 default:
1853 printk("Chip ident is %X.\n", xid&0x1F);
1854 devc->chip_name = "CS42xx";
1855 devc->model = MD_4232;
1856 break;
1857 }
1858 }
1859 break;
1860
1861 case 2: /* CS4232/CS4232A */
1862 devc->chip_name = "CS4232";
1863 devc->model = MD_4232;
1864 break;
1865
1866 case 0:
1867 if ((id & 0xe0) == 0xa0)
1868 {
1869 devc->chip_name = "CS4231A";
1870 devc->model = MD_4231A;
1871 }
1872 else
1873 {
1874 devc->chip_name = "CS4321";
1875 devc->model = MD_4231;
1876 }
1877 break;
1878
1879 default: /* maybe */
1880 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1881 if (optiC930)
1882 {
1883 devc->chip_name = "82C930";
1884 devc->model = MD_C930;
1885 }
1886 else
1887 {
1888 devc->chip_name = "CS4231";
1889 devc->model = MD_4231;
1890 }
1891 }
1892 }
1893 }
1894 ad_write(devc, 25, tmp1); /* Restore bits */
1895
1896 DDB(printk("ad1848_detect() - step K\n"));
1897 }
1898 } else if (tmp1 == 0x0a) {
1899 /*
1900 * Is it perhaps a SoundPro CMI8330?
1901 * If so, then we should be able to change indirect registers
1902 * greater than I15 after activating MODE2, even though reading
1903 * back I12 does not show it.
1904 */
1905
1906 /*
1907 * Let's try comparing register values
1908 */
1909 for (i = 0; i < 16; i++) {
1910 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1911 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1912 soundpro = 1;
1913 devc->chip_name = "SoundPro CMI 8330";
1914 break;
1915 }
1916 }
1917 }
1918
1919 DDB(printk("ad1848_detect() - step L\n"));
1920 if (ad_flags)
1921 {
1922 if (devc->model != MD_1848)
1923 *ad_flags |= AD_F_CS4231;
1924 }
1925 DDB(printk("ad1848_detect() - Detected OK\n"));
1926
1927 if (devc->model == MD_1848 && ad1847_flag)
1928 devc->chip_name = "AD1847";
1929
1930
1931 if (sscape_flag == 1)
1932 devc->model = MD_1845_SSCAPE;
1933
1934 return 1;
1935 }
1936
1937 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1938 int dma_capture, int share_dma, int *osp, struct module *owner)
1939 {
1940 /*
1941 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1942 * so that this driver doesn't need to allocate/deallocate it.
1943 * The actually used IRQ is ABS(irq).
1944 */
1945
1946 int my_dev;
1947 char dev_name[100];
1948 int e;
1949
1950 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1951
1952 ad1848_port_info *portc = NULL;
1953
1954 devc->irq = (irq > 0) ? irq : 0;
1955 devc->open_mode = 0;
1956 devc->timer_ticks = 0;
1957 devc->dma1 = dma_playback;
1958 devc->dma2 = dma_capture;
1959 devc->subtype = cfg.card_subtype;
1960 devc->audio_flags = DMA_AUTOMODE;
1961 devc->playback_dev = devc->record_dev = 0;
1962 if (name != NULL)
1963 devc->name = name;
1964
1965 if (name != NULL && name[0] != 0)
1966 sprintf(dev_name,
1967 "%s (%s)", name, devc->chip_name);
1968 else
1969 sprintf(dev_name,
1970 "Generic audio codec (%s)", devc->chip_name);
1971
1972 rename_region(ports, devc->name);
1973
1974 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1975
1976 if (devc->model == MD_1848 || devc->model == MD_C930)
1977 devc->audio_flags |= DMA_HARDSTOP;
1978
1979 if (devc->model > MD_1848)
1980 {
1981 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1982 devc->audio_flags &= ~DMA_DUPLEX;
1983 else
1984 devc->audio_flags |= DMA_DUPLEX;
1985 }
1986
1987 portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1988 if(portc==NULL) {
1989 release_region(devc->base, 4);
1990 return -1;
1991 }
1992
1993 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
1994 dev_name,
1995 &ad1848_audio_driver,
1996 sizeof(struct audio_driver),
1997 devc->audio_flags,
1998 ad_format_mask[devc->model],
1999 devc,
2000 dma_playback,
2001 dma_capture)) < 0)
2002 {
2003 release_region(devc->base, 4);
2004 kfree(portc);
2005 return -1;
2006 }
2007
2008 audio_devs[my_dev]->portc = portc;
2009 audio_devs[my_dev]->mixer_dev = -1;
2010 if (owner)
2011 audio_devs[my_dev]->d->owner = owner;
2012 memset((char *) portc, 0, sizeof(*portc));
2013
2014 nr_ad1848_devs++;
2015
2016 ad1848_init_hw(devc);
2017
2018 if (irq > 0)
2019 {
2020 devc->dev_no = my_dev;
2021 if (request_irq(devc->irq, adintr, 0, devc->name,
2022 (void *)(long)my_dev) < 0)
2023 {
2024 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2025 /* Don't free it either then.. */
2026 devc->irq = 0;
2027 }
2028 if (capabilities[devc->model].flags & CAP_F_TIMER)
2029 {
2030 #ifndef CONFIG_SMP
2031 int x;
2032 unsigned char tmp = ad_read(devc, 16);
2033 #endif
2034
2035 devc->timer_ticks = 0;
2036
2037 ad_write(devc, 21, 0x00); /* Timer MSB */
2038 ad_write(devc, 20, 0x10); /* Timer LSB */
2039 #ifndef CONFIG_SMP
2040 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2041 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2042 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
2043
2044 if (devc->timer_ticks == 0)
2045 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2046 else
2047 {
2048 DDB(printk("Interrupt test OK\n"));
2049 devc->irq_ok = 1;
2050 }
2051 #else
2052 devc->irq_ok = 1;
2053 #endif
2054 }
2055 else
2056 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
2057 } else if (irq < 0)
2058 devc->dev_no = my_dev;
2059
2060 #ifndef EXCLUDE_TIMERS
2061 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2062 devc->irq_ok)
2063 ad1848_tmr_install(my_dev);
2064 #endif
2065
2066 if (!share_dma)
2067 {
2068 if (sound_alloc_dma(dma_playback, devc->name))
2069 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2070
2071 if (dma_capture != dma_playback)
2072 if (sound_alloc_dma(dma_capture, devc->name))
2073 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2074 }
2075
2076 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2077 dev_name,
2078 &ad1848_mixer_operations,
2079 sizeof(struct mixer_operations),
2080 devc)) >= 0)
2081 {
2082 audio_devs[my_dev]->mixer_dev = e;
2083 if (owner)
2084 mixer_devs[e]->owner = owner;
2085 }
2086 return my_dev;
2087 }
2088
2089 int ad1848_control(int cmd, int arg)
2090 {
2091 ad1848_info *devc;
2092 unsigned long flags;
2093
2094 if (nr_ad1848_devs < 1)
2095 return -ENODEV;
2096
2097 devc = &adev_info[nr_ad1848_devs - 1];
2098
2099 switch (cmd)
2100 {
2101 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
2102 if (devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
2103 return -EINVAL;
2104 spin_lock_irqsave(&devc->lock,flags);
2105 ad_enter_MCE(devc);
2106 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2107 ad_leave_MCE(devc);
2108 spin_unlock_irqrestore(&devc->lock,flags);
2109 break;
2110
2111 case AD1848_MIXER_REROUTE:
2112 {
2113 int o = (arg >> 8) & 0xff;
2114 int n = arg & 0xff;
2115
2116 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2117 return -EINVAL;
2118
2119 if (!(devc->supported_devices & (1 << o)) &&
2120 !(devc->supported_rec_devices & (1 << o)))
2121 return -EINVAL;
2122
2123 if (n == SOUND_MIXER_NONE)
2124 { /* Just hide this control */
2125 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2126 devc->supported_devices &= ~(1 << o);
2127 devc->supported_rec_devices &= ~(1 << o);
2128 break;
2129 }
2130
2131 /* Make the mixer control identified by o to appear as n */
2132 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2133 return -EINVAL;
2134
2135 devc->mixer_reroute[n] = o; /* Rename the control */
2136 if (devc->supported_devices & (1 << o))
2137 devc->supported_devices |= (1 << n);
2138 if (devc->supported_rec_devices & (1 << o))
2139 devc->supported_rec_devices |= (1 << n);
2140
2141 devc->supported_devices &= ~(1 << o);
2142 devc->supported_rec_devices &= ~(1 << o);
2143 }
2144 break;
2145 }
2146 return 0;
2147 }
2148
2149 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2150 {
2151 int i, mixer, dev = 0;
2152 ad1848_info *devc = NULL;
2153
2154 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2155 {
2156 if (adev_info[i].base == io_base)
2157 {
2158 devc = &adev_info[i];
2159 dev = devc->dev_no;
2160 }
2161 }
2162
2163 if (devc != NULL)
2164 {
2165 kfree(audio_devs[dev]->portc);
2166 release_region(devc->base, 4);
2167
2168 if (!share_dma)
2169 {
2170 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2171 free_irq(devc->irq, (void *)(long)devc->dev_no);
2172
2173 sound_free_dma(dma_playback);
2174
2175 if (dma_playback != dma_capture)
2176 sound_free_dma(dma_capture);
2177
2178 }
2179 mixer = audio_devs[devc->dev_no]->mixer_dev;
2180 if(mixer>=0)
2181 sound_unload_mixerdev(mixer);
2182
2183 nr_ad1848_devs--;
2184 for ( ; i < nr_ad1848_devs ; i++)
2185 adev_info[i] = adev_info[i+1];
2186 }
2187 else
2188 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2189 }
2190
2191 static irqreturn_t adintr(int irq, void *dev_id)
2192 {
2193 unsigned char status;
2194 ad1848_info *devc;
2195 int dev;
2196 int alt_stat = 0xff;
2197 unsigned char c930_stat = 0;
2198 int cnt = 0;
2199
2200 dev = (long)dev_id;
2201 devc = (ad1848_info *) audio_devs[dev]->devc;
2202
2203 interrupt_again: /* Jump back here if int status doesn't reset */
2204
2205 status = inb(io_Status(devc));
2206
2207 if (status == 0x80)
2208 printk(KERN_DEBUG "adintr: Why?\n");
2209 if (devc->model == MD_1848)
2210 outb((0), io_Status(devc)); /* Clear interrupt status */
2211
2212 if (status & 0x01)
2213 {
2214 if (devc->model == MD_C930)
2215 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2216
2217 spin_lock(&devc->lock);
2218
2219 /* 0xe0e is C930 address port
2220 * 0xe0f is C930 data port
2221 */
2222 outb(11, 0xe0e);
2223 c930_stat = inb(0xe0f);
2224 outb((~c930_stat), 0xe0f);
2225
2226 spin_unlock(&devc->lock);
2227
2228 alt_stat = (c930_stat << 2) & 0x30;
2229 }
2230 else if (devc->model != MD_1848)
2231 {
2232 spin_lock(&devc->lock);
2233 alt_stat = ad_read(devc, 24);
2234 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2235 spin_unlock(&devc->lock);
2236 }
2237
2238 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2239 {
2240 DMAbuf_inputintr(devc->record_dev);
2241 }
2242 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2243 (alt_stat & 0x10))
2244 {
2245 DMAbuf_outputintr(devc->playback_dev, 1);
2246 }
2247 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2248 {
2249 devc->timer_ticks++;
2250 #ifndef EXCLUDE_TIMERS
2251 if (timer_installed == dev && devc->timer_running)
2252 sound_timer_interrupt();
2253 #endif
2254 }
2255 }
2256 /*
2257 * Sometimes playback or capture interrupts occur while a timer interrupt
2258 * is being handled. The interrupt will not be retriggered if we don't
2259 * handle it now. Check if an interrupt is still pending and restart
2260 * the handler in this case.
2261 */
2262 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2263 {
2264 goto interrupt_again;
2265 }
2266 return IRQ_HANDLED;
2267 }
2268
2269 /*
2270 * Experimental initialization sequence for the integrated sound system
2271 * of the Compaq Deskpro M.
2272 */
2273
2274 static int init_deskpro_m(struct address_info *hw_config)
2275 {
2276 unsigned char tmp;
2277
2278 if ((tmp = inb(0xc44)) == 0xff)
2279 {
2280 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2281 return 0;
2282 }
2283
2284 outb(0x10, 0xc44);
2285 outb(0x40, 0xc45);
2286 outb(0x00, 0xc46);
2287 outb(0xe8, 0xc47);
2288 outb(0x14, 0xc44);
2289 outb(0x40, 0xc45);
2290 outb(0x00, 0xc46);
2291 outb(0xe8, 0xc47);
2292 outb(0x10, 0xc44);
2293
2294 return 1;
2295 }
2296
2297 /*
2298 * Experimental initialization sequence for the integrated sound system
2299 * of Compaq Deskpro XL.
2300 */
2301
2302 static int init_deskpro(struct address_info *hw_config)
2303 {
2304 unsigned char tmp;
2305
2306 if ((tmp = inb(0xc44)) == 0xff)
2307 {
2308 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2309 return 0;
2310 }
2311 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2312 if (inb(0xc44) != 0x04)
2313 {
2314 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2315 return 0;
2316 }
2317 /*
2318 * OK. It looks like a Deskpro so let's proceed.
2319 */
2320
2321 /*
2322 * I/O port 0xc44 Audio configuration register.
2323 *
2324 * bits 0xc0: Audio revision bits
2325 * 0x00 = Compaq Business Audio
2326 * 0x40 = MS Sound System Compatible (reset default)
2327 * 0x80 = Reserved
2328 * 0xc0 = Reserved
2329 * bit 0x20: No Wait State Enable
2330 * 0x00 = Disabled (reset default, DMA mode)
2331 * 0x20 = Enabled (programmed I/O mode)
2332 * bit 0x10: MS Sound System Decode Enable
2333 * 0x00 = Decoding disabled (reset default)
2334 * 0x10 = Decoding enabled
2335 * bit 0x08: FM Synthesis Decode Enable
2336 * 0x00 = Decoding Disabled (reset default)
2337 * 0x08 = Decoding enabled
2338 * bit 0x04 Bank select
2339 * 0x00 = Bank 0
2340 * 0x04 = Bank 1
2341 * bits 0x03 MSS Base address
2342 * 0x00 = 0x530 (reset default)
2343 * 0x01 = 0x604
2344 * 0x02 = 0xf40
2345 * 0x03 = 0xe80
2346 */
2347
2348 #ifdef DEBUGXL
2349 /* Debug printing */
2350 printk("Port 0xc44 (before): ");
2351 outb((tmp & ~0x04), 0xc44);
2352 printk("%02x ", inb(0xc44));
2353 outb((tmp | 0x04), 0xc44);
2354 printk("%02x\n", inb(0xc44));
2355 #endif
2356
2357 /* Set bank 1 of the register */
2358 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2359
2360 switch (hw_config->io_base)
2361 {
2362 case 0x530:
2363 tmp |= 0x00;
2364 break;
2365 case 0x604:
2366 tmp |= 0x01;
2367 break;
2368 case 0xf40:
2369 tmp |= 0x02;
2370 break;
2371 case 0xe80:
2372 tmp |= 0x03;
2373 break;
2374 default:
2375 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2376 return 0;
2377 }
2378 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2379
2380 #ifdef DEBUGXL
2381 /* Debug printing */
2382 printk("Port 0xc44 (after): ");
2383 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2384 printk("%02x ", inb(0xc44));
2385 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2386 printk("%02x\n", inb(0xc44));
2387 #endif
2388
2389 /*
2390 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2391 *
2392 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2393 * bank=0, bit 0x01: SBIC Power Control Bit
2394 * 0x00 = Powered up
2395 * 0x01 = Powered down
2396 * bank=1, bits 0xfc: MSS ID (default=0x40)
2397 */
2398
2399 #ifdef DEBUGXL
2400 /* Debug printing */
2401 printk("Port 0xc45 (before): ");
2402 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2403 printk("%02x ", inb(0xc45));
2404 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2405 printk("%02x\n", inb(0xc45));
2406 #endif
2407
2408 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2409 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2410 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2411 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2412
2413 #ifdef DEBUGXL
2414 /* Debug printing */
2415 printk("Port 0xc45 (after): ");
2416 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2417 printk("%02x ", inb(0xc45));
2418 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2419 printk("%02x\n", inb(0xc45));
2420 #endif
2421
2422
2423 /*
2424 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2425 *
2426 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2427 * bank=1, bits 0xff: Audio addressing ASIC id
2428 */
2429
2430 #ifdef DEBUGXL
2431 /* Debug printing */
2432 printk("Port 0xc46 (before): ");
2433 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2434 printk("%02x ", inb(0xc46));
2435 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2436 printk("%02x\n", inb(0xc46));
2437 #endif
2438
2439 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2440 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2441 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2442 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2443
2444 #ifdef DEBUGXL
2445 /* Debug printing */
2446 printk("Port 0xc46 (after): ");
2447 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2448 printk("%02x ", inb(0xc46));
2449 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2450 printk("%02x\n", inb(0xc46));
2451 #endif
2452
2453 /*
2454 * I/O port 0xc47 FM Address Decode Register.
2455 *
2456 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2457 * bank=1, bits 0xff: Reserved
2458 */
2459
2460 #ifdef DEBUGXL
2461 /* Debug printing */
2462 printk("Port 0xc47 (before): ");
2463 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2464 printk("%02x ", inb(0xc47));
2465 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2466 printk("%02x\n", inb(0xc47));
2467 #endif
2468
2469 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2470 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2471 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2472 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2473
2474 #ifdef DEBUGXL
2475 /* Debug printing */
2476 printk("Port 0xc47 (after): ");
2477 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2478 printk("%02x ", inb(0xc47));
2479 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2480 printk("%02x\n", inb(0xc47));
2481 #endif
2482
2483 /*
2484 * I/O port 0xc6f = Audio Disable Function Register
2485 */
2486
2487 #ifdef DEBUGXL
2488 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2489 #endif
2490
2491 outb((0x80), 0xc6f);
2492
2493 #ifdef DEBUGXL
2494 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2495 #endif
2496
2497 return 1;
2498 }
2499
2500 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2501 {
2502 unsigned char tmp;
2503
2504 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2505
2506 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2507 {
2508 /* check_opl3(0x388, hw_config); */
2509 return ad1848_detect(ports, NULL, hw_config->osp);
2510 }
2511
2512 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2513 {
2514 if (!init_deskpro(hw_config))
2515 return 0;
2516 }
2517
2518 if (deskpro_m) /* Compaq Deskpro M */
2519 {
2520 if (!init_deskpro_m(hw_config))
2521 return 0;
2522 }
2523
2524 /*
2525 * Check if the IO port returns valid signature. The original MS Sound
2526 * system returns 0x04 while some cards (AudioTrix Pro for example)
2527 * return 0x00 or 0x0f.
2528 */
2529
2530 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2531 {
2532 int ret;
2533
2534 DDB(printk("I/O address is inactive (%x)\n", tmp));
2535 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2536 return 0;
2537 return 1;
2538 }
2539 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2540 if ((tmp & 0x3f) != 0x04 &&
2541 (tmp & 0x3f) != 0x0f &&
2542 (tmp & 0x3f) != 0x00)
2543 {
2544 int ret;
2545
2546 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2547 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2548 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2549 return 0;
2550
2551 hw_config->card_subtype = 1;
2552 return 1;
2553 }
2554 if ((hw_config->irq != 5) &&
2555 (hw_config->irq != 7) &&
2556 (hw_config->irq != 9) &&
2557 (hw_config->irq != 10) &&
2558 (hw_config->irq != 11) &&
2559 (hw_config->irq != 12))
2560 {
2561 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2562 return 0;
2563 }
2564 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2565 {
2566 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2567 return 0;
2568 }
2569 /*
2570 * Check that DMA0 is not in use with a 8 bit board.
2571 */
2572
2573 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2574 {
2575 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2576 return 0;
2577 }
2578 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2579 {
2580 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2581 return 0;
2582 }
2583 return ad1848_detect(ports, NULL, hw_config->osp);
2584 }
2585
2586 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2587 {
2588 static signed char interrupt_bits[12] =
2589 {
2590 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2591 };
2592 signed char bits;
2593 char dma2_bit = 0;
2594
2595 static char dma_bits[4] =
2596 {
2597 1, 2, 0, 3
2598 };
2599
2600 int config_port = hw_config->io_base + 0;
2601 int version_port = hw_config->io_base + 3;
2602 int dma = hw_config->dma;
2603 int dma2 = hw_config->dma2;
2604
2605 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2606 {
2607 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2608 hw_config->irq,
2609 hw_config->dma,
2610 hw_config->dma2, 0,
2611 hw_config->osp,
2612 owner);
2613 return;
2614 }
2615 /*
2616 * Set the IRQ and DMA addresses.
2617 */
2618
2619 bits = interrupt_bits[hw_config->irq];
2620 if (bits == -1)
2621 {
2622 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2623 release_region(ports->start, 4);
2624 release_region(ports->start - 4, 4);
2625 return;
2626 }
2627 outb((bits | 0x40), config_port);
2628 if ((inb(version_port) & 0x40) == 0)
2629 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2630
2631 /*
2632 * Handle the capture DMA channel
2633 */
2634
2635 if (dma2 != -1 && dma2 != dma)
2636 {
2637 if (!((dma == 0 && dma2 == 1) ||
2638 (dma == 1 && dma2 == 0) ||
2639 (dma == 3 && dma2 == 0)))
2640 { /* Unsupported combination. Try to swap channels */
2641 int tmp = dma;
2642
2643 dma = dma2;
2644 dma2 = tmp;
2645 }
2646 if ((dma == 0 && dma2 == 1) ||
2647 (dma == 1 && dma2 == 0) ||
2648 (dma == 3 && dma2 == 0))
2649 {
2650 dma2_bit = 0x04; /* Enable capture DMA */
2651 }
2652 else
2653 {
2654 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2655 dma2 = dma;
2656 }
2657 }
2658 else
2659 {
2660 dma2 = dma;
2661 }
2662
2663 hw_config->dma = dma;
2664 hw_config->dma2 = dma2;
2665
2666 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2667
2668 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2669 hw_config->irq,
2670 dma, dma2, 0,
2671 hw_config->osp,
2672 THIS_MODULE);
2673 }
2674
2675 void unload_ms_sound(struct address_info *hw_config)
2676 {
2677 ad1848_unload(hw_config->io_base + 4,
2678 hw_config->irq,
2679 hw_config->dma,
2680 hw_config->dma2, 0);
2681 sound_unload_audiodev(hw_config->slots[0]);
2682 release_region(hw_config->io_base, 4);
2683 }
2684
2685 #ifndef EXCLUDE_TIMERS
2686
2687 /*
2688 * Timer stuff (for /dev/music).
2689 */
2690
2691 static unsigned int current_interval;
2692
2693 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2694 {
2695 unsigned long flags;
2696 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2697 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2698 unsigned long divider;
2699
2700 spin_lock_irqsave(&devc->lock,flags);
2701
2702 /*
2703 * Length of the timer interval (in nanoseconds) depends on the
2704 * selected crystal oscillator. Check this from bit 0x01 of I8.
2705 *
2706 * AD1845 has just one oscillator which has cycle time of 10.050 us
2707 * (when a 24.576 MHz xtal oscillator is used).
2708 *
2709 * Convert requested interval to nanoseconds before computing
2710 * the timer divider.
2711 */
2712
2713 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2714 xtal_nsecs = 10050;
2715 else if (ad_read(devc, 8) & 0x01)
2716 xtal_nsecs = 9920;
2717 else
2718 xtal_nsecs = 9969;
2719
2720 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2721
2722 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2723 divider = 100;
2724
2725 if (divider > 65535) /* Overflow check */
2726 divider = 65535;
2727
2728 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2729 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2730 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2731 devc->timer_running = 1;
2732 spin_unlock_irqrestore(&devc->lock,flags);
2733
2734 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2735 }
2736
2737 static void ad1848_tmr_reprogram(int dev)
2738 {
2739 /*
2740 * Audio driver has changed sampling rate so that a different xtal
2741 * oscillator was selected. We have to reprogram the timer rate.
2742 */
2743
2744 ad1848_tmr_start(dev, current_interval);
2745 sound_timer_syncinterval(current_interval);
2746 }
2747
2748 static void ad1848_tmr_disable(int dev)
2749 {
2750 unsigned long flags;
2751 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2752
2753 spin_lock_irqsave(&devc->lock,flags);
2754 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2755 devc->timer_running = 0;
2756 spin_unlock_irqrestore(&devc->lock,flags);
2757 }
2758
2759 static void ad1848_tmr_restart(int dev)
2760 {
2761 unsigned long flags;
2762 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2763
2764 if (current_interval == 0)
2765 return;
2766
2767 spin_lock_irqsave(&devc->lock,flags);
2768 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2769 devc->timer_running = 1;
2770 spin_unlock_irqrestore(&devc->lock,flags);
2771 }
2772
2773 static struct sound_lowlev_timer ad1848_tmr =
2774 {
2775 0,
2776 2,
2777 ad1848_tmr_start,
2778 ad1848_tmr_disable,
2779 ad1848_tmr_restart
2780 };
2781
2782 static int ad1848_tmr_install(int dev)
2783 {
2784 if (timer_installed != -1)
2785 return 0; /* Don't install another timer */
2786
2787 timer_installed = ad1848_tmr.dev = dev;
2788 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2789
2790 return 1;
2791 }
2792 #endif /* EXCLUDE_TIMERS */
2793
2794 EXPORT_SYMBOL(ad1848_detect);
2795 EXPORT_SYMBOL(ad1848_init);
2796 EXPORT_SYMBOL(ad1848_unload);
2797 EXPORT_SYMBOL(ad1848_control);
2798 EXPORT_SYMBOL(probe_ms_sound);
2799 EXPORT_SYMBOL(attach_ms_sound);
2800 EXPORT_SYMBOL(unload_ms_sound);
2801
2802 static int __initdata io = -1;
2803 static int __initdata irq = -1;
2804 static int __initdata dma = -1;
2805 static int __initdata dma2 = -1;
2806 static int __initdata type = 0;
2807
2808 module_param_hw(io, int, ioport, 0); /* I/O for a raw AD1848 card */
2809 module_param_hw(irq, int, irq, 0); /* IRQ to use */
2810 module_param_hw(dma, int, dma, 0); /* First DMA channel */
2811 module_param_hw(dma2, int, dma, 0); /* Second DMA channel */
2812 module_param(type, int, 0); /* Card type */
2813 module_param(deskpro_xl, bool, 0); /* Special magic for Deskpro XL boxen */
2814 module_param(deskpro_m, bool, 0); /* Special magic for Deskpro M box */
2815 module_param(soundpro, bool, 0); /* More special magic for SoundPro chips */
2816
2817 #ifdef CONFIG_PNP
2818 module_param(isapnp, int, 0);
2819 module_param(isapnpjump, int, 0);
2820 module_param(reverse, bool, 0);
2821 MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
2822 MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2823 MODULE_PARM_DESC(reverse, "When set to 1, will reverse ISAPnP search order");
2824
2825 static struct pnp_dev *ad1848_dev = NULL;
2826
2827 /* Please add new entries at the end of the table */
2828 static struct {
2829 char *name;
2830 unsigned short card_vendor, card_device,
2831 vendor, function;
2832 short mss_io, irq, dma, dma2; /* index into isapnp table */
2833 int type;
2834 } ad1848_isapnp_list[] __initdata = {
2835 {"CMI 8330 SoundPRO",
2836 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2837 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2838 0, 0, 0,-1, 0},
2839 {"CS4232 based card",
2840 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2841 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2842 0, 0, 0, 1, 0},
2843 {"CS4232 based card",
2844 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2845 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2846 0, 0, 0, 1, 0},
2847 {"OPL3-SA2 WSS mode",
2848 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2849 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2850 1, 0, 0, 1, 1},
2851 {"Advanced Gravis InterWave Audio",
2852 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2853 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2854 0, 0, 0, 1, 0},
2855 {NULL}
2856 };
2857
2858 #ifdef MODULE
2859 static struct isapnp_device_id id_table[] = {
2860 { ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2861 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2862 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2863 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2864 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2865 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2866 /* The main driver for this card is opl3sa2
2867 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2868 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2869 */
2870 { ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2871 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2872 {0}
2873 };
2874
2875 MODULE_DEVICE_TABLE(isapnp, id_table);
2876 #endif
2877
2878 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2879 {
2880 int err;
2881
2882 err = pnp_device_attach(dev);
2883 if (err < 0)
2884 return(NULL);
2885
2886 if((err = pnp_activate_dev(dev)) < 0) {
2887 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2888
2889 pnp_device_detach(dev);
2890
2891 return(NULL);
2892 }
2893 audio_activated = 1;
2894 return(dev);
2895 }
2896
2897 static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
2898 struct address_info *hw_config, int slot)
2899 {
2900
2901 /* Configure Audio device */
2902 if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
2903 {
2904 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
2905 {
2906 hw_config->io_base = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
2907 hw_config->irq = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
2908 hw_config->dma = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
2909 if(ad1848_isapnp_list[slot].dma2 != -1)
2910 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
2911 else
2912 hw_config->dma2 = -1;
2913 hw_config->card_subtype = ad1848_isapnp_list[slot].type;
2914 } else
2915 return(NULL);
2916 } else
2917 return(NULL);
2918
2919 return(ad1848_dev);
2920 }
2921
2922 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
2923 {
2924 char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
2925
2926 /* Initialize this baby. */
2927
2928 if(ad1848_init_generic(bus, hw_config, slot)) {
2929 /* We got it. */
2930
2931 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
2932 busname,
2933 hw_config->io_base, hw_config->irq, hw_config->dma,
2934 hw_config->dma2);
2935 return 1;
2936 }
2937 return 0;
2938 }
2939
2940 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
2941 {
2942 static int first = 1;
2943 int i;
2944
2945 /* Count entries in sb_isapnp_list */
2946 for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
2947 i--;
2948
2949 /* Check and adjust isapnpjump */
2950 if( isapnpjump < 0 || isapnpjump > i) {
2951 isapnpjump = reverse ? i : 0;
2952 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
2953 }
2954
2955 if(!first || !reverse)
2956 i = isapnpjump;
2957 first = 0;
2958 while(ad1848_isapnp_list[i].card_vendor != 0) {
2959 static struct pnp_card *bus = NULL;
2960
2961 while ((bus = pnp_find_card(
2962 ad1848_isapnp_list[i].card_vendor,
2963 ad1848_isapnp_list[i].card_device,
2964 bus))) {
2965
2966 if(ad1848_isapnp_init(hw_config, bus, i)) {
2967 isapnpjump = i; /* start next search from here */
2968 return 0;
2969 }
2970 }
2971 i += reverse ? -1 : 1;
2972 }
2973
2974 return -ENODEV;
2975 }
2976 #endif
2977
2978
2979 static int __init init_ad1848(void)
2980 {
2981 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2982
2983 #ifdef CONFIG_PNP
2984 if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
2985 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
2986 isapnp = 0;
2987 }
2988 #endif
2989
2990 if(io != -1) {
2991 struct resource *ports;
2992 if( isapnp == 0 )
2993 {
2994 if(irq == -1 || dma == -1) {
2995 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
2996 return -EINVAL;
2997 }
2998
2999 cfg.irq = irq;
3000 cfg.io_base = io;
3001 cfg.dma = dma;
3002 cfg.dma2 = dma2;
3003 cfg.card_subtype = type;
3004 }
3005
3006 ports = request_region(io + 4, 4, "ad1848");
3007
3008 if (!ports)
3009 return -EBUSY;
3010
3011 if (!request_region(io, 4, "WSS config")) {
3012 release_region(io + 4, 4);
3013 return -EBUSY;
3014 }
3015
3016 if (!probe_ms_sound(&cfg, ports)) {
3017 release_region(io + 4, 4);
3018 release_region(io, 4);
3019 return -ENODEV;
3020 }
3021 attach_ms_sound(&cfg, ports, THIS_MODULE);
3022 loaded = 1;
3023 }
3024 return 0;
3025 }
3026
3027 static void __exit cleanup_ad1848(void)
3028 {
3029 if(loaded)
3030 unload_ms_sound(&cfg);
3031
3032 #ifdef CONFIG_PNP
3033 if(ad1848_dev){
3034 if(audio_activated)
3035 pnp_device_detach(ad1848_dev);
3036 }
3037 #endif
3038 }
3039
3040 module_init(init_ad1848);
3041 module_exit(cleanup_ad1848);
3042
3043 #ifndef MODULE
3044 static int __init setup_ad1848(char *str)
3045 {
3046 /* io, irq, dma, dma2, type */
3047 int ints[6];
3048
3049 str = get_options(str, ARRAY_SIZE(ints), ints);
3050
3051 io = ints[1];
3052 irq = ints[2];
3053 dma = ints[3];
3054 dma2 = ints[4];
3055 type = ints[5];
3056
3057 return 1;
3058 }
3059
3060 __setup("ad1848=", setup_ad1848);
3061 #endif
3062 MODULE_LICENSE("GPL");
Linux with added FPC-III support