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dmaengine: imx-sdma: Let the core do the device node validation
[linux/fpc-iii.git] / drivers / scsi / myrs.h
blobe6702ee85e9f4a47e86e61e7cbd3cd3038982009
1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
4 *
5 * This driver supports the newer, SCSI-based firmware interface only.
6 *
7 * Copyright 2018 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
8 *
9 * Based on the original DAC960 driver, which has
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
11 * Portions Copyright 2002 by Mylex (An IBM Business Unit)
12 */
13
14 #ifndef _MYRS_H
15 #define _MYRS_H
16
17 #define MYRS_MAILBOX_TIMEOUT 1000000
18
19 #define MYRS_DCMD_TAG 1
20 #define MYRS_MCMD_TAG 2
21
22 #define MYRS_LINE_BUFFER_SIZE 128
23
24 #define MYRS_PRIMARY_MONITOR_INTERVAL (10 * HZ)
25 #define MYRS_SECONDARY_MONITOR_INTERVAL (60 * HZ)
26
27 /* Maximum number of Scatter/Gather Segments supported */
28 #define MYRS_SG_LIMIT 128
29
30 /*
31 * Number of Command and Status Mailboxes used by the
32 * DAC960 V2 Firmware Memory Mailbox Interface.
33 */
34 #define MYRS_MAX_CMD_MBOX 512
35 #define MYRS_MAX_STAT_MBOX 512
36
37 #define MYRS_DCDB_SIZE 16
38 #define MYRS_SENSE_SIZE 14
39
40 /*
41 * DAC960 V2 Firmware Command Opcodes.
42 */
43 enum myrs_cmd_opcode {
44 MYRS_CMD_OP_MEMCOPY = 0x01,
45 MYRS_CMD_OP_SCSI_10_PASSTHRU = 0x02,
46 MYRS_CMD_OP_SCSI_255_PASSTHRU = 0x03,
47 MYRS_CMD_OP_SCSI_10 = 0x04,
48 MYRS_CMD_OP_SCSI_256 = 0x05,
49 MYRS_CMD_OP_IOCTL = 0x20,
50 } __packed;
51
52 /*
53 * DAC960 V2 Firmware IOCTL Opcodes.
54 */
55 enum myrs_ioctl_opcode {
56 MYRS_IOCTL_GET_CTLR_INFO = 0x01,
57 MYRS_IOCTL_GET_LDEV_INFO_VALID = 0x03,
58 MYRS_IOCTL_GET_PDEV_INFO_VALID = 0x05,
59 MYRS_IOCTL_GET_HEALTH_STATUS = 0x11,
60 MYRS_IOCTL_GET_EVENT = 0x15,
61 MYRS_IOCTL_START_DISCOVERY = 0x81,
62 MYRS_IOCTL_SET_DEVICE_STATE = 0x82,
63 MYRS_IOCTL_INIT_PDEV_START = 0x84,
64 MYRS_IOCTL_INIT_PDEV_STOP = 0x85,
65 MYRS_IOCTL_INIT_LDEV_START = 0x86,
66 MYRS_IOCTL_INIT_LDEV_STOP = 0x87,
67 MYRS_IOCTL_RBLD_DEVICE_START = 0x88,
68 MYRS_IOCTL_RBLD_DEVICE_STOP = 0x89,
69 MYRS_IOCTL_MAKE_CONSISTENT_START = 0x8A,
70 MYRS_IOCTL_MAKE_CONSISTENT_STOP = 0x8B,
71 MYRS_IOCTL_CC_START = 0x8C,
72 MYRS_IOCTL_CC_STOP = 0x8D,
73 MYRS_IOCTL_SET_MEM_MBOX = 0x8E,
74 MYRS_IOCTL_RESET_DEVICE = 0x90,
75 MYRS_IOCTL_FLUSH_DEVICE_DATA = 0x91,
76 MYRS_IOCTL_PAUSE_DEVICE = 0x92,
77 MYRS_IOCTL_UNPAUS_EDEVICE = 0x93,
78 MYRS_IOCTL_LOCATE_DEVICE = 0x94,
79 MYRS_IOCTL_CREATE_CONFIGURATION = 0xC0,
80 MYRS_IOCTL_DELETE_LDEV = 0xC1,
81 MYRS_IOCTL_REPLACE_INTERNALDEVICE = 0xC2,
82 MYRS_IOCTL_RENAME_LDEV = 0xC3,
83 MYRS_IOCTL_ADD_CONFIGURATION = 0xC4,
84 MYRS_IOCTL_XLATE_PDEV_TO_LDEV = 0xC5,
85 MYRS_IOCTL_CLEAR_CONFIGURATION = 0xCA,
86 } __packed;
87
88 /*
89 * DAC960 V2 Firmware Command Status Codes.
90 */
91 #define MYRS_STATUS_SUCCESS 0x00
92 #define MYRS_STATUS_FAILED 0x02
93 #define MYRS_STATUS_DEVICE_BUSY 0x08
94 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE 0x0E
95 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE2 0x0F
96 #define MYRS_STATUS_RESERVATION_CONFLICT 0x18
97
98 /*
99 * DAC960 V2 Firmware Memory Type structure.
100 */
101 struct myrs_mem_type {
102 enum {
103 MYRS_MEMTYPE_RESERVED = 0x00,
104 MYRS_MEMTYPE_DRAM = 0x01,
105 MYRS_MEMTYPE_EDRAM = 0x02,
106 MYRS_MEMTYPE_EDO = 0x03,
107 MYRS_MEMTYPE_SDRAM = 0x04,
108 MYRS_MEMTYPE_LAST = 0x1F,
109 } __packed mem_type:5; /* Byte 0 Bits 0-4 */
110 unsigned rsvd:1; /* Byte 0 Bit 5 */
111 unsigned mem_parity:1; /* Byte 0 Bit 6 */
112 unsigned mem_ecc:1; /* Byte 0 Bit 7 */
113 };
114
115 /*
116 * DAC960 V2 Firmware Processor Type structure.
117 */
118 enum myrs_cpu_type {
119 MYRS_CPUTYPE_i960CA = 0x01,
120 MYRS_CPUTYPE_i960RD = 0x02,
121 MYRS_CPUTYPE_i960RN = 0x03,
122 MYRS_CPUTYPE_i960RP = 0x04,
123 MYRS_CPUTYPE_NorthBay = 0x05,
124 MYRS_CPUTYPE_StrongArm = 0x06,
125 MYRS_CPUTYPE_i960RM = 0x07,
126 } __packed;
127
128 /*
129 * DAC960 V2 Firmware Get Controller Info reply structure.
130 */
131 struct myrs_ctlr_info {
132 unsigned char rsvd1; /* Byte 0 */
133 enum {
134 MYRS_SCSI_BUS = 0x00,
135 MYRS_Fibre_BUS = 0x01,
136 MYRS_PCI_BUS = 0x03
137 } __packed bus; /* Byte 1 */
138 enum {
139 MYRS_CTLR_DAC960E = 0x01,
140 MYRS_CTLR_DAC960M = 0x08,
141 MYRS_CTLR_DAC960PD = 0x10,
142 MYRS_CTLR_DAC960PL = 0x11,
143 MYRS_CTLR_DAC960PU = 0x12,
144 MYRS_CTLR_DAC960PE = 0x13,
145 MYRS_CTLR_DAC960PG = 0x14,
146 MYRS_CTLR_DAC960PJ = 0x15,
147 MYRS_CTLR_DAC960PTL0 = 0x16,
148 MYRS_CTLR_DAC960PR = 0x17,
149 MYRS_CTLR_DAC960PRL = 0x18,
150 MYRS_CTLR_DAC960PT = 0x19,
151 MYRS_CTLR_DAC1164P = 0x1A,
152 MYRS_CTLR_DAC960PTL1 = 0x1B,
153 MYRS_CTLR_EXR2000P = 0x1C,
154 MYRS_CTLR_EXR3000P = 0x1D,
155 MYRS_CTLR_ACCELERAID352 = 0x1E,
156 MYRS_CTLR_ACCELERAID170 = 0x1F,
157 MYRS_CTLR_ACCELERAID160 = 0x20,
158 MYRS_CTLR_DAC960S = 0x60,
159 MYRS_CTLR_DAC960SU = 0x61,
160 MYRS_CTLR_DAC960SX = 0x62,
161 MYRS_CTLR_DAC960SF = 0x63,
162 MYRS_CTLR_DAC960SS = 0x64,
163 MYRS_CTLR_DAC960FL = 0x65,
164 MYRS_CTLR_DAC960LL = 0x66,
165 MYRS_CTLR_DAC960FF = 0x67,
166 MYRS_CTLR_DAC960HP = 0x68,
167 MYRS_CTLR_RAIDBRICK = 0x69,
168 MYRS_CTLR_METEOR_FL = 0x6A,
169 MYRS_CTLR_METEOR_FF = 0x6B
170 } __packed ctlr_type; /* Byte 2 */
171 unsigned char rsvd2; /* Byte 3 */
172 unsigned short bus_speed_mhz; /* Bytes 4-5 */
173 unsigned char bus_width; /* Byte 6 */
174 unsigned char flash_code; /* Byte 7 */
175 unsigned char ports_present; /* Byte 8 */
176 unsigned char rsvd3[7]; /* Bytes 9-15 */
177 unsigned char bus_name[16]; /* Bytes 16-31 */
178 unsigned char ctlr_name[16]; /* Bytes 32-47 */
179 unsigned char rsvd4[16]; /* Bytes 48-63 */
180 /* Firmware Release Information */
181 unsigned char fw_major_version; /* Byte 64 */
182 unsigned char fw_minor_version; /* Byte 65 */
183 unsigned char fw_turn_number; /* Byte 66 */
184 unsigned char fw_build_number; /* Byte 67 */
185 unsigned char fw_release_day; /* Byte 68 */
186 unsigned char fw_release_month; /* Byte 69 */
187 unsigned char fw_release_year_hi; /* Byte 70 */
188 unsigned char fw_release_year_lo; /* Byte 71 */
189 /* Hardware Release Information */
190 unsigned char hw_rev; /* Byte 72 */
191 unsigned char rsvd5[3]; /* Bytes 73-75 */
192 unsigned char hw_release_day; /* Byte 76 */
193 unsigned char hw_release_month; /* Byte 77 */
194 unsigned char hw_release_year_hi; /* Byte 78 */
195 unsigned char hw_release_year_lo; /* Byte 79 */
196 /* Hardware Manufacturing Information */
197 unsigned char manuf_batch_num; /* Byte 80 */
198 unsigned char rsvd6; /* Byte 81 */
199 unsigned char manuf_plant_num; /* Byte 82 */
200 unsigned char rsvd7; /* Byte 83 */
201 unsigned char hw_manuf_day; /* Byte 84 */
202 unsigned char hw_manuf_month; /* Byte 85 */
203 unsigned char hw_manuf_year_hi; /* Byte 86 */
204 unsigned char hw_manuf_year_lo; /* Byte 87 */
205 unsigned char max_pd_per_xld; /* Byte 88 */
206 unsigned char max_ild_per_xld; /* Byte 89 */
207 unsigned short nvram_size_kb; /* Bytes 90-91 */
208 unsigned char max_xld; /* Byte 92 */
209 unsigned char rsvd8[3]; /* Bytes 93-95 */
210 /* Unique Information per Controller */
211 unsigned char serial_number[16]; /* Bytes 96-111 */
212 unsigned char rsvd9[16]; /* Bytes 112-127 */
213 /* Vendor Information */
214 unsigned char rsvd10[3]; /* Bytes 128-130 */
215 unsigned char oem_code; /* Byte 131 */
216 unsigned char vendor[16]; /* Bytes 132-147 */
217 /* Other Physical/Controller/Operation Information */
218 unsigned char bbu_present:1; /* Byte 148 Bit 0 */
219 unsigned char cluster_mode:1; /* Byte 148 Bit 1 */
220 unsigned char rsvd11:6; /* Byte 148 Bits 2-7 */
221 unsigned char rsvd12[3]; /* Bytes 149-151 */
222 /* Physical Device Scan Information */
223 unsigned char pscan_active:1; /* Byte 152 Bit 0 */
224 unsigned char rsvd13:7; /* Byte 152 Bits 1-7 */
225 unsigned char pscan_chan; /* Byte 153 */
226 unsigned char pscan_target; /* Byte 154 */
227 unsigned char pscan_lun; /* Byte 155 */
228 /* Maximum Command Data Transfer Sizes */
229 unsigned short max_transfer_size; /* Bytes 156-157 */
230 unsigned short max_sge; /* Bytes 158-159 */
231 /* Logical/Physical Device Counts */
232 unsigned short ldev_present; /* Bytes 160-161 */
233 unsigned short ldev_critical; /* Bytes 162-163 */
234 unsigned short ldev_offline; /* Bytes 164-165 */
235 unsigned short pdev_present; /* Bytes 166-167 */
236 unsigned short pdisk_present; /* Bytes 168-169 */
237 unsigned short pdisk_critical; /* Bytes 170-171 */
238 unsigned short pdisk_offline; /* Bytes 172-173 */
239 unsigned short max_tcq; /* Bytes 174-175 */
240 /* Channel and Target ID Information */
241 unsigned char physchan_present; /* Byte 176 */
242 unsigned char virtchan_present; /* Byte 177 */
243 unsigned char physchan_max; /* Byte 178 */
244 unsigned char virtchan_max; /* Byte 179 */
245 unsigned char max_targets[16]; /* Bytes 180-195 */
246 unsigned char rsvd14[12]; /* Bytes 196-207 */
247 /* Memory/Cache Information */
248 unsigned short mem_size_mb; /* Bytes 208-209 */
249 unsigned short cache_size_mb; /* Bytes 210-211 */
250 unsigned int valid_cache_bytes; /* Bytes 212-215 */
251 unsigned int dirty_cache_bytes; /* Bytes 216-219 */
252 unsigned short mem_speed_mhz; /* Bytes 220-221 */
253 unsigned char mem_data_width; /* Byte 222 */
254 struct myrs_mem_type mem_type; /* Byte 223 */
255 unsigned char cache_mem_type_name[16]; /* Bytes 224-239 */
256 /* Execution Memory Information */
257 unsigned short exec_mem_size_mb; /* Bytes 240-241 */
258 unsigned short exec_l2_cache_size_mb; /* Bytes 242-243 */
259 unsigned char rsvd15[8]; /* Bytes 244-251 */
260 unsigned short exec_mem_speed_mhz; /* Bytes 252-253 */
261 unsigned char exec_mem_data_width; /* Byte 254 */
262 struct myrs_mem_type exec_mem_type; /* Byte 255 */
263 unsigned char exec_mem_type_name[16]; /* Bytes 256-271 */
264 /* CPU Type Information */
265 struct { /* Bytes 272-335 */
266 unsigned short cpu_speed_mhz;
267 enum myrs_cpu_type cpu_type;
268 unsigned char cpu_count;
269 unsigned char rsvd16[12];
270 unsigned char cpu_name[16];
271 } __packed cpu[2];
272 /* Debugging/Profiling/Command Time Tracing Information */
273 unsigned short cur_prof_page_num; /* Bytes 336-337 */
274 unsigned short num_prof_waiters; /* Bytes 338-339 */
275 unsigned short cur_trace_page_num; /* Bytes 340-341 */
276 unsigned short num_trace_waiters; /* Bytes 342-343 */
277 unsigned char rsvd18[8]; /* Bytes 344-351 */
278 /* Error Counters on Physical Devices */
279 unsigned short pdev_bus_resets; /* Bytes 352-353 */
280 unsigned short pdev_parity_errors; /* Bytes 355-355 */
281 unsigned short pdev_soft_errors; /* Bytes 356-357 */
282 unsigned short pdev_cmds_failed; /* Bytes 358-359 */
283 unsigned short pdev_misc_errors; /* Bytes 360-361 */
284 unsigned short pdev_cmd_timeouts; /* Bytes 362-363 */
285 unsigned short pdev_sel_timeouts; /* Bytes 364-365 */
286 unsigned short pdev_retries_done; /* Bytes 366-367 */
287 unsigned short pdev_aborts_done; /* Bytes 368-369 */
288 unsigned short pdev_host_aborts_done; /* Bytes 370-371 */
289 unsigned short pdev_predicted_failures; /* Bytes 372-373 */
290 unsigned short pdev_host_cmds_failed; /* Bytes 374-375 */
291 unsigned short pdev_hard_errors; /* Bytes 376-377 */
292 unsigned char rsvd19[6]; /* Bytes 378-383 */
293 /* Error Counters on Logical Devices */
294 unsigned short ldev_soft_errors; /* Bytes 384-385 */
295 unsigned short ldev_cmds_failed; /* Bytes 386-387 */
296 unsigned short ldev_host_aborts_done; /* Bytes 388-389 */
297 unsigned char rsvd20[2]; /* Bytes 390-391 */
298 /* Error Counters on Controller */
299 unsigned short ctlr_mem_errors; /* Bytes 392-393 */
300 unsigned short ctlr_host_aborts_done; /* Bytes 394-395 */
301 unsigned char rsvd21[4]; /* Bytes 396-399 */
302 /* Long Duration Activity Information */
303 unsigned short bg_init_active; /* Bytes 400-401 */
304 unsigned short ldev_init_active; /* Bytes 402-403 */
305 unsigned short pdev_init_active; /* Bytes 404-405 */
306 unsigned short cc_active; /* Bytes 406-407 */
307 unsigned short rbld_active; /* Bytes 408-409 */
308 unsigned short exp_active; /* Bytes 410-411 */
309 unsigned short patrol_active; /* Bytes 412-413 */
310 unsigned char rsvd22[2]; /* Bytes 414-415 */
311 /* Flash ROM Information */
312 unsigned char flash_type; /* Byte 416 */
313 unsigned char rsvd23; /* Byte 417 */
314 unsigned short flash_size_MB; /* Bytes 418-419 */
315 unsigned int flash_limit; /* Bytes 420-423 */
316 unsigned int flash_count; /* Bytes 424-427 */
317 unsigned char rsvd24[4]; /* Bytes 428-431 */
318 unsigned char flash_type_name[16]; /* Bytes 432-447 */
319 /* Firmware Run Time Information */
320 unsigned char rbld_rate; /* Byte 448 */
321 unsigned char bg_init_rate; /* Byte 449 */
322 unsigned char fg_init_rate; /* Byte 450 */
323 unsigned char cc_rate; /* Byte 451 */
324 unsigned char rsvd25[4]; /* Bytes 452-455 */
325 unsigned int max_dp; /* Bytes 456-459 */
326 unsigned int free_dp; /* Bytes 460-463 */
327 unsigned int max_iop; /* Bytes 464-467 */
328 unsigned int free_iop; /* Bytes 468-471 */
329 unsigned short max_combined_len; /* Bytes 472-473 */
330 unsigned short num_cfg_groups; /* Bytes 474-475 */
331 unsigned installation_abort_status:1; /* Byte 476 Bit 0 */
332 unsigned maint_mode_status:1; /* Byte 476 Bit 1 */
333 unsigned rsvd26:6; /* Byte 476 Bits 2-7 */
334 unsigned char rsvd27[6]; /* Bytes 477-511 */
335 unsigned char rsvd28[512]; /* Bytes 512-1023 */
336 };
337
338 /*
339 * DAC960 V2 Firmware Device State type.
340 */
341 enum myrs_devstate {
342 MYRS_DEVICE_UNCONFIGURED = 0x00,
343 MYRS_DEVICE_ONLINE = 0x01,
344 MYRS_DEVICE_REBUILD = 0x03,
345 MYRS_DEVICE_MISSING = 0x04,
346 MYRS_DEVICE_SUSPECTED_CRITICAL = 0x05,
347 MYRS_DEVICE_OFFLINE = 0x08,
348 MYRS_DEVICE_CRITICAL = 0x09,
349 MYRS_DEVICE_SUSPECTED_DEAD = 0x0C,
350 MYRS_DEVICE_COMMANDED_OFFLINE = 0x10,
351 MYRS_DEVICE_STANDBY = 0x21,
352 MYRS_DEVICE_INVALID_STATE = 0xFF,
353 } __packed;
354
355 /*
356 * DAC960 V2 RAID Levels
357 */
358 enum myrs_raid_level {
359 MYRS_RAID_LEVEL0 = 0x0, /* RAID 0 */
360 MYRS_RAID_LEVEL1 = 0x1, /* RAID 1 */
361 MYRS_RAID_LEVEL3 = 0x3, /* RAID 3 right asymmetric parity */
362 MYRS_RAID_LEVEL5 = 0x5, /* RAID 5 right asymmetric parity */
363 MYRS_RAID_LEVEL6 = 0x6, /* RAID 6 (Mylex RAID 6) */
364 MYRS_RAID_JBOD = 0x7, /* RAID 7 (JBOD) */
365 MYRS_RAID_NEWSPAN = 0x8, /* New Mylex SPAN */
366 MYRS_RAID_LEVEL3F = 0x9, /* RAID 3 fixed parity */
367 MYRS_RAID_LEVEL3L = 0xb, /* RAID 3 left symmetric parity */
368 MYRS_RAID_SPAN = 0xc, /* current spanning implementation */
369 MYRS_RAID_LEVEL5L = 0xd, /* RAID 5 left symmetric parity */
370 MYRS_RAID_LEVELE = 0xe, /* RAID E (concatenation) */
371 MYRS_RAID_PHYSICAL = 0xf, /* physical device */
372 } __packed;
373
374 enum myrs_stripe_size {
375 MYRS_STRIPE_SIZE_0 = 0x0, /* no stripe (RAID 1, RAID 7, etc) */
376 MYRS_STRIPE_SIZE_512B = 0x1,
377 MYRS_STRIPE_SIZE_1K = 0x2,
378 MYRS_STRIPE_SIZE_2K = 0x3,
379 MYRS_STRIPE_SIZE_4K = 0x4,
380 MYRS_STRIPE_SIZE_8K = 0x5,
381 MYRS_STRIPE_SIZE_16K = 0x6,
382 MYRS_STRIPE_SIZE_32K = 0x7,
383 MYRS_STRIPE_SIZE_64K = 0x8,
384 MYRS_STRIPE_SIZE_128K = 0x9,
385 MYRS_STRIPE_SIZE_256K = 0xa,
386 MYRS_STRIPE_SIZE_512K = 0xb,
387 MYRS_STRIPE_SIZE_1M = 0xc,
388 } __packed;
389
390 enum myrs_cacheline_size {
391 MYRS_CACHELINE_ZERO = 0x0, /* caching cannot be enabled */
392 MYRS_CACHELINE_512B = 0x1,
393 MYRS_CACHELINE_1K = 0x2,
394 MYRS_CACHELINE_2K = 0x3,
395 MYRS_CACHELINE_4K = 0x4,
396 MYRS_CACHELINE_8K = 0x5,
397 MYRS_CACHELINE_16K = 0x6,
398 MYRS_CACHELINE_32K = 0x7,
399 MYRS_CACHELINE_64K = 0x8,
400 } __packed;
401
402 /*
403 * DAC960 V2 Firmware Get Logical Device Info reply structure.
404 */
405 struct myrs_ldev_info {
406 unsigned char ctlr; /* Byte 0 */
407 unsigned char channel; /* Byte 1 */
408 unsigned char target; /* Byte 2 */
409 unsigned char lun; /* Byte 3 */
410 enum myrs_devstate dev_state; /* Byte 4 */
411 unsigned char raid_level; /* Byte 5 */
412 enum myrs_stripe_size stripe_size; /* Byte 6 */
413 enum myrs_cacheline_size cacheline_size; /* Byte 7 */
414 struct {
415 enum {
416 MYRS_READCACHE_DISABLED = 0x0,
417 MYRS_READCACHE_ENABLED = 0x1,
418 MYRS_READAHEAD_ENABLED = 0x2,
419 MYRS_INTELLIGENT_READAHEAD_ENABLED = 0x3,
420 MYRS_READCACHE_LAST = 0x7,
421 } __packed rce:3; /* Byte 8 Bits 0-2 */
422 enum {
423 MYRS_WRITECACHE_DISABLED = 0x0,
424 MYRS_LOGICALDEVICE_RO = 0x1,
425 MYRS_WRITECACHE_ENABLED = 0x2,
426 MYRS_INTELLIGENT_WRITECACHE_ENABLED = 0x3,
427 MYRS_WRITECACHE_LAST = 0x7,
428 } __packed wce:3; /* Byte 8 Bits 3-5 */
429 unsigned rsvd1:1; /* Byte 8 Bit 6 */
430 unsigned ldev_init_done:1; /* Byte 8 Bit 7 */
431 } ldev_control; /* Byte 8 */
432 /* Logical Device Operations Status */
433 unsigned char cc_active:1; /* Byte 9 Bit 0 */
434 unsigned char rbld_active:1; /* Byte 9 Bit 1 */
435 unsigned char bg_init_active:1; /* Byte 9 Bit 2 */
436 unsigned char fg_init_active:1; /* Byte 9 Bit 3 */
437 unsigned char migration_active:1; /* Byte 9 Bit 4 */
438 unsigned char patrol_active:1; /* Byte 9 Bit 5 */
439 unsigned char rsvd2:2; /* Byte 9 Bits 6-7 */
440 unsigned char raid5_writeupdate; /* Byte 10 */
441 unsigned char raid5_algo; /* Byte 11 */
442 unsigned short ldev_num; /* Bytes 12-13 */
443 /* BIOS Info */
444 unsigned char bios_disabled:1; /* Byte 14 Bit 0 */
445 unsigned char cdrom_boot:1; /* Byte 14 Bit 1 */
446 unsigned char drv_coercion:1; /* Byte 14 Bit 2 */
447 unsigned char write_same_disabled:1; /* Byte 14 Bit 3 */
448 unsigned char hba_mode:1; /* Byte 14 Bit 4 */
449 enum {
450 MYRS_GEOMETRY_128_32 = 0x0,
451 MYRS_GEOMETRY_255_63 = 0x1,
452 MYRS_GEOMETRY_RSVD1 = 0x2,
453 MYRS_GEOMETRY_RSVD2 = 0x3
454 } __packed drv_geom:2; /* Byte 14 Bits 5-6 */
455 unsigned char super_ra_enabled:1; /* Byte 14 Bit 7 */
456 unsigned char rsvd3; /* Byte 15 */
457 /* Error Counters */
458 unsigned short soft_errs; /* Bytes 16-17 */
459 unsigned short cmds_failed; /* Bytes 18-19 */
460 unsigned short cmds_aborted; /* Bytes 20-21 */
461 unsigned short deferred_write_errs; /* Bytes 22-23 */
462 unsigned int rsvd4; /* Bytes 24-27 */
463 unsigned int rsvd5; /* Bytes 28-31 */
464 /* Device Size Information */
465 unsigned short rsvd6; /* Bytes 32-33 */
466 unsigned short devsize_bytes; /* Bytes 34-35 */
467 unsigned int orig_devsize; /* Bytes 36-39 */
468 unsigned int cfg_devsize; /* Bytes 40-43 */
469 unsigned int rsvd7; /* Bytes 44-47 */
470 unsigned char ldev_name[32]; /* Bytes 48-79 */
471 unsigned char inquiry[36]; /* Bytes 80-115 */
472 unsigned char rsvd8[12]; /* Bytes 116-127 */
473 u64 last_read_lba; /* Bytes 128-135 */
474 u64 last_write_lba; /* Bytes 136-143 */
475 u64 cc_lba; /* Bytes 144-151 */
476 u64 rbld_lba; /* Bytes 152-159 */
477 u64 bg_init_lba; /* Bytes 160-167 */
478 u64 fg_init_lba; /* Bytes 168-175 */
479 u64 migration_lba; /* Bytes 176-183 */
480 u64 patrol_lba; /* Bytes 184-191 */
481 unsigned char rsvd9[64]; /* Bytes 192-255 */
482 };
483
484 /*
485 * DAC960 V2 Firmware Get Physical Device Info reply structure.
486 */
487 struct myrs_pdev_info {
488 unsigned char rsvd1; /* Byte 0 */
489 unsigned char channel; /* Byte 1 */
490 unsigned char target; /* Byte 2 */
491 unsigned char lun; /* Byte 3 */
492 /* Configuration Status Bits */
493 unsigned char pdev_fault_tolerant:1; /* Byte 4 Bit 0 */
494 unsigned char pdev_connected:1; /* Byte 4 Bit 1 */
495 unsigned char pdev_local_to_ctlr:1; /* Byte 4 Bit 2 */
496 unsigned char rsvd2:5; /* Byte 4 Bits 3-7 */
497 /* Multiple Host/Controller Status Bits */
498 unsigned char remote_host_dead:1; /* Byte 5 Bit 0 */
499 unsigned char remove_ctlr_dead:1; /* Byte 5 Bit 1 */
500 unsigned char rsvd3:6; /* Byte 5 Bits 2-7 */
501 enum myrs_devstate dev_state; /* Byte 6 */
502 unsigned char nego_data_width; /* Byte 7 */
503 unsigned short nego_sync_rate; /* Bytes 8-9 */
504 /* Multiported Physical Device Information */
505 unsigned char num_ports; /* Byte 10 */
506 unsigned char drv_access_bitmap; /* Byte 11 */
507 unsigned int rsvd4; /* Bytes 12-15 */
508 unsigned char ip_address[16]; /* Bytes 16-31 */
509 unsigned short max_tags; /* Bytes 32-33 */
510 /* Physical Device Operations Status */
511 unsigned char cc_in_progress:1; /* Byte 34 Bit 0 */
512 unsigned char rbld_in_progress:1; /* Byte 34 Bit 1 */
513 unsigned char makecc_in_progress:1; /* Byte 34 Bit 2 */
514 unsigned char pdevinit_in_progress:1; /* Byte 34 Bit 3 */
515 unsigned char migration_in_progress:1; /* Byte 34 Bit 4 */
516 unsigned char patrol_in_progress:1; /* Byte 34 Bit 5 */
517 unsigned char rsvd5:2; /* Byte 34 Bits 6-7 */
518 unsigned char long_op_status; /* Byte 35 */
519 unsigned char parity_errs; /* Byte 36 */
520 unsigned char soft_errs; /* Byte 37 */
521 unsigned char hard_errs; /* Byte 38 */
522 unsigned char misc_errs; /* Byte 39 */
523 unsigned char cmd_timeouts; /* Byte 40 */
524 unsigned char retries; /* Byte 41 */
525 unsigned char aborts; /* Byte 42 */
526 unsigned char pred_failures; /* Byte 43 */
527 unsigned int rsvd6; /* Bytes 44-47 */
528 unsigned short rsvd7; /* Bytes 48-49 */
529 unsigned short devsize_bytes; /* Bytes 50-51 */
530 unsigned int orig_devsize; /* Bytes 52-55 */
531 unsigned int cfg_devsize; /* Bytes 56-59 */
532 unsigned int rsvd8; /* Bytes 60-63 */
533 unsigned char pdev_name[16]; /* Bytes 64-79 */
534 unsigned char rsvd9[16]; /* Bytes 80-95 */
535 unsigned char rsvd10[32]; /* Bytes 96-127 */
536 unsigned char inquiry[36]; /* Bytes 128-163 */
537 unsigned char rsvd11[20]; /* Bytes 164-183 */
538 unsigned char rsvd12[8]; /* Bytes 184-191 */
539 u64 last_read_lba; /* Bytes 192-199 */
540 u64 last_write_lba; /* Bytes 200-207 */
541 u64 cc_lba; /* Bytes 208-215 */
542 u64 rbld_lba; /* Bytes 216-223 */
543 u64 makecc_lba; /* Bytes 224-231 */
544 u64 devinit_lba; /* Bytes 232-239 */
545 u64 migration_lba; /* Bytes 240-247 */
546 u64 patrol_lba; /* Bytes 248-255 */
547 unsigned char rsvd13[256]; /* Bytes 256-511 */
548 };
549
550 /*
551 * DAC960 V2 Firmware Health Status Buffer structure.
552 */
553 struct myrs_fwstat {
554 unsigned int uptime_usecs; /* Bytes 0-3 */
555 unsigned int uptime_msecs; /* Bytes 4-7 */
556 unsigned int seconds; /* Bytes 8-11 */
557 unsigned char rsvd1[4]; /* Bytes 12-15 */
558 unsigned int epoch; /* Bytes 16-19 */
559 unsigned char rsvd2[4]; /* Bytes 20-23 */
560 unsigned int dbg_msgbuf_idx; /* Bytes 24-27 */
561 unsigned int coded_msgbuf_idx; /* Bytes 28-31 */
562 unsigned int cur_timetrace_page; /* Bytes 32-35 */
563 unsigned int cur_prof_page; /* Bytes 36-39 */
564 unsigned int next_evseq; /* Bytes 40-43 */
565 unsigned char rsvd3[4]; /* Bytes 44-47 */
566 unsigned char rsvd4[16]; /* Bytes 48-63 */
567 unsigned char rsvd5[64]; /* Bytes 64-127 */
568 };
569
570 /*
571 * DAC960 V2 Firmware Get Event reply structure.
572 */
573 struct myrs_event {
574 unsigned int ev_seq; /* Bytes 0-3 */
575 unsigned int ev_time; /* Bytes 4-7 */
576 unsigned int ev_code; /* Bytes 8-11 */
577 unsigned char rsvd1; /* Byte 12 */
578 unsigned char channel; /* Byte 13 */
579 unsigned char target; /* Byte 14 */
580 unsigned char lun; /* Byte 15 */
581 unsigned int rsvd2; /* Bytes 16-19 */
582 unsigned int ev_parm; /* Bytes 20-23 */
583 unsigned char sense_data[40]; /* Bytes 24-63 */
584 };
585
586 /*
587 * DAC960 V2 Firmware Command Control Bits structure.
588 */
589 struct myrs_cmd_ctrl {
590 unsigned char fua:1; /* Byte 0 Bit 0 */
591 unsigned char disable_pgout:1; /* Byte 0 Bit 1 */
592 unsigned char rsvd1:1; /* Byte 0 Bit 2 */
593 unsigned char add_sge_mem:1; /* Byte 0 Bit 3 */
594 unsigned char dma_ctrl_to_host:1; /* Byte 0 Bit 4 */
595 unsigned char rsvd2:1; /* Byte 0 Bit 5 */
596 unsigned char no_autosense:1; /* Byte 0 Bit 6 */
597 unsigned char disc_prohibited:1; /* Byte 0 Bit 7 */
598 };
599
600 /*
601 * DAC960 V2 Firmware Command Timeout structure.
602 */
603 struct myrs_cmd_tmo {
604 unsigned char tmo_val:6; /* Byte 0 Bits 0-5 */
605 enum {
606 MYRS_TMO_SCALE_SECONDS = 0,
607 MYRS_TMO_SCALE_MINUTES = 1,
608 MYRS_TMO_SCALE_HOURS = 2,
609 MYRS_TMO_SCALE_RESERVED = 3
610 } __packed tmo_scale:2; /* Byte 0 Bits 6-7 */
611 };
612
613 /*
614 * DAC960 V2 Firmware Physical Device structure.
615 */
616 struct myrs_pdev {
617 unsigned char lun; /* Byte 0 */
618 unsigned char target; /* Byte 1 */
619 unsigned char channel:3; /* Byte 2 Bits 0-2 */
620 unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
621 } __packed;
622
623 /*
624 * DAC960 V2 Firmware Logical Device structure.
625 */
626 struct myrs_ldev {
627 unsigned short ldev_num; /* Bytes 0-1 */
628 unsigned char rsvd:3; /* Byte 2 Bits 0-2 */
629 unsigned char ctlr:5; /* Byte 2 Bits 3-7 */
630 } __packed;
631
632 /*
633 * DAC960 V2 Firmware Operation Device type.
634 */
635 enum myrs_opdev {
636 MYRS_PHYSICAL_DEVICE = 0x00,
637 MYRS_RAID_DEVICE = 0x01,
638 MYRS_PHYSICAL_CHANNEL = 0x02,
639 MYRS_RAID_CHANNEL = 0x03,
640 MYRS_PHYSICAL_CONTROLLER = 0x04,
641 MYRS_RAID_CONTROLLER = 0x05,
642 MYRS_CONFIGURATION_GROUP = 0x10,
643 MYRS_ENCLOSURE = 0x11,
644 } __packed;
645
646 /*
647 * DAC960 V2 Firmware Translate Physical To Logical Device structure.
648 */
649 struct myrs_devmap {
650 unsigned short ldev_num; /* Bytes 0-1 */
651 unsigned short rsvd; /* Bytes 2-3 */
652 unsigned char prev_boot_ctlr; /* Byte 4 */
653 unsigned char prev_boot_channel; /* Byte 5 */
654 unsigned char prev_boot_target; /* Byte 6 */
655 unsigned char prev_boot_lun; /* Byte 7 */
656 };
657
658 /*
659 * DAC960 V2 Firmware Scatter/Gather List Entry structure.
660 */
661 struct myrs_sge {
662 u64 sge_addr; /* Bytes 0-7 */
663 u64 sge_count; /* Bytes 8-15 */
664 };
665
666 /*
667 * DAC960 V2 Firmware Data Transfer Memory Address structure.
668 */
669 union myrs_sgl {
670 struct myrs_sge sge[2]; /* Bytes 0-31 */
671 struct {
672 unsigned short sge0_len; /* Bytes 0-1 */
673 unsigned short sge1_len; /* Bytes 2-3 */
674 unsigned short sge2_len; /* Bytes 4-5 */
675 unsigned short rsvd; /* Bytes 6-7 */
676 u64 sge0_addr; /* Bytes 8-15 */
677 u64 sge1_addr; /* Bytes 16-23 */
678 u64 sge2_addr; /* Bytes 24-31 */
679 } ext;
680 };
681
682 /*
683 * 64 Byte DAC960 V2 Firmware Command Mailbox structure.
684 */
685 union myrs_cmd_mbox {
686 unsigned int words[16]; /* Words 0-15 */
687 struct {
688 unsigned short id; /* Bytes 0-1 */
689 enum myrs_cmd_opcode opcode; /* Byte 2 */
690 struct myrs_cmd_ctrl control; /* Byte 3 */
691 u32 dma_size:24; /* Bytes 4-6 */
692 unsigned char dma_num; /* Byte 7 */
693 u64 sense_addr; /* Bytes 8-15 */
694 unsigned int rsvd1:24; /* Bytes 16-18 */
695 struct myrs_cmd_tmo tmo; /* Byte 19 */
696 unsigned char sense_len; /* Byte 20 */
697 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
698 unsigned char rsvd2[10]; /* Bytes 22-31 */
699 union myrs_sgl dma_addr; /* Bytes 32-63 */
700 } common;
701 struct {
702 unsigned short id; /* Bytes 0-1 */
703 enum myrs_cmd_opcode opcode; /* Byte 2 */
704 struct myrs_cmd_ctrl control; /* Byte 3 */
705 u32 dma_size; /* Bytes 4-7 */
706 u64 sense_addr; /* Bytes 8-15 */
707 struct myrs_pdev pdev; /* Bytes 16-18 */
708 struct myrs_cmd_tmo tmo; /* Byte 19 */
709 unsigned char sense_len; /* Byte 20 */
710 unsigned char cdb_len; /* Byte 21 */
711 unsigned char cdb[10]; /* Bytes 22-31 */
712 union myrs_sgl dma_addr; /* Bytes 32-63 */
713 } SCSI_10;
714 struct {
715 unsigned short id; /* Bytes 0-1 */
716 enum myrs_cmd_opcode opcode; /* Byte 2 */
717 struct myrs_cmd_ctrl control; /* Byte 3 */
718 u32 dma_size; /* Bytes 4-7 */
719 u64 sense_addr; /* Bytes 8-15 */
720 struct myrs_pdev pdev; /* Bytes 16-18 */
721 struct myrs_cmd_tmo tmo; /* Byte 19 */
722 unsigned char sense_len; /* Byte 20 */
723 unsigned char cdb_len; /* Byte 21 */
724 unsigned short rsvd; /* Bytes 22-23 */
725 u64 cdb_addr; /* Bytes 24-31 */
726 union myrs_sgl dma_addr; /* Bytes 32-63 */
727 } SCSI_255;
728 struct {
729 unsigned short id; /* Bytes 0-1 */
730 enum myrs_cmd_opcode opcode; /* Byte 2 */
731 struct myrs_cmd_ctrl control; /* Byte 3 */
732 u32 dma_size:24; /* Bytes 4-6 */
733 unsigned char dma_num; /* Byte 7 */
734 u64 sense_addr; /* Bytes 8-15 */
735 unsigned short rsvd1; /* Bytes 16-17 */
736 unsigned char ctlr_num; /* Byte 18 */
737 struct myrs_cmd_tmo tmo; /* Byte 19 */
738 unsigned char sense_len; /* Byte 20 */
739 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
740 unsigned char rsvd2[10]; /* Bytes 22-31 */
741 union myrs_sgl dma_addr; /* Bytes 32-63 */
742 } ctlr_info;
743 struct {
744 unsigned short id; /* Bytes 0-1 */
745 enum myrs_cmd_opcode opcode; /* Byte 2 */
746 struct myrs_cmd_ctrl control; /* Byte 3 */
747 u32 dma_size:24; /* Bytes 4-6 */
748 unsigned char dma_num; /* Byte 7 */
749 u64 sense_addr; /* Bytes 8-15 */
750 struct myrs_ldev ldev; /* Bytes 16-18 */
751 struct myrs_cmd_tmo tmo; /* Byte 19 */
752 unsigned char sense_len; /* Byte 20 */
753 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
754 unsigned char rsvd[10]; /* Bytes 22-31 */
755 union myrs_sgl dma_addr; /* Bytes 32-63 */
756 } ldev_info;
757 struct {
758 unsigned short id; /* Bytes 0-1 */
759 enum myrs_cmd_opcode opcode; /* Byte 2 */
760 struct myrs_cmd_ctrl control; /* Byte 3 */
761 u32 dma_size:24; /* Bytes 4-6 */
762 unsigned char dma_num; /* Byte 7 */
763 u64 sense_addr; /* Bytes 8-15 */
764 struct myrs_pdev pdev; /* Bytes 16-18 */
765 struct myrs_cmd_tmo tmo; /* Byte 19 */
766 unsigned char sense_len; /* Byte 20 */
767 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
768 unsigned char rsvd[10]; /* Bytes 22-31 */
769 union myrs_sgl dma_addr; /* Bytes 32-63 */
770 } pdev_info;
771 struct {
772 unsigned short id; /* Bytes 0-1 */
773 enum myrs_cmd_opcode opcode; /* Byte 2 */
774 struct myrs_cmd_ctrl control; /* Byte 3 */
775 u32 dma_size:24; /* Bytes 4-6 */
776 unsigned char dma_num; /* Byte 7 */
777 u64 sense_addr; /* Bytes 8-15 */
778 unsigned short evnum_upper; /* Bytes 16-17 */
779 unsigned char ctlr_num; /* Byte 18 */
780 struct myrs_cmd_tmo tmo; /* Byte 19 */
781 unsigned char sense_len; /* Byte 20 */
782 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
783 unsigned short evnum_lower; /* Bytes 22-23 */
784 unsigned char rsvd[8]; /* Bytes 24-31 */
785 union myrs_sgl dma_addr; /* Bytes 32-63 */
786 } get_event;
787 struct {
788 unsigned short id; /* Bytes 0-1 */
789 enum myrs_cmd_opcode opcode; /* Byte 2 */
790 struct myrs_cmd_ctrl control; /* Byte 3 */
791 u32 dma_size:24; /* Bytes 4-6 */
792 unsigned char dma_num; /* Byte 7 */
793 u64 sense_addr; /* Bytes 8-15 */
794 union {
795 struct myrs_ldev ldev; /* Bytes 16-18 */
796 struct myrs_pdev pdev; /* Bytes 16-18 */
797 };
798 struct myrs_cmd_tmo tmo; /* Byte 19 */
799 unsigned char sense_len; /* Byte 20 */
800 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
801 enum myrs_devstate state; /* Byte 22 */
802 unsigned char rsvd[9]; /* Bytes 23-31 */
803 union myrs_sgl dma_addr; /* Bytes 32-63 */
804 } set_devstate;
805 struct {
806 unsigned short id; /* Bytes 0-1 */
807 enum myrs_cmd_opcode opcode; /* Byte 2 */
808 struct myrs_cmd_ctrl control; /* Byte 3 */
809 u32 dma_size:24; /* Bytes 4-6 */
810 unsigned char dma_num; /* Byte 7 */
811 u64 sense_addr; /* Bytes 8-15 */
812 struct myrs_ldev ldev; /* Bytes 16-18 */
813 struct myrs_cmd_tmo tmo; /* Byte 19 */
814 unsigned char sense_len; /* Byte 20 */
815 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
816 unsigned char restore_consistency:1; /* Byte 22 Bit 0 */
817 unsigned char initialized_area_only:1; /* Byte 22 Bit 1 */
818 unsigned char rsvd1:6; /* Byte 22 Bits 2-7 */
819 unsigned char rsvd2[9]; /* Bytes 23-31 */
820 union myrs_sgl dma_addr; /* Bytes 32-63 */
821 } cc;
822 struct {
823 unsigned short id; /* Bytes 0-1 */
824 enum myrs_cmd_opcode opcode; /* Byte 2 */
825 struct myrs_cmd_ctrl control; /* Byte 3 */
826 unsigned char first_cmd_mbox_size_kb; /* Byte 4 */
827 unsigned char first_stat_mbox_size_kb; /* Byte 5 */
828 unsigned char second_cmd_mbox_size_kb; /* Byte 6 */
829 unsigned char second_stat_mbox_size_kb; /* Byte 7 */
830 u64 sense_addr; /* Bytes 8-15 */
831 unsigned int rsvd1:24; /* Bytes 16-18 */
832 struct myrs_cmd_tmo tmo; /* Byte 19 */
833 unsigned char sense_len; /* Byte 20 */
834 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
835 unsigned char fwstat_buf_size_kb; /* Byte 22 */
836 unsigned char rsvd2; /* Byte 23 */
837 u64 fwstat_buf_addr; /* Bytes 24-31 */
838 u64 first_cmd_mbox_addr; /* Bytes 32-39 */
839 u64 first_stat_mbox_addr; /* Bytes 40-47 */
840 u64 second_cmd_mbox_addr; /* Bytes 48-55 */
841 u64 second_stat_mbox_addr; /* Bytes 56-63 */
842 } set_mbox;
843 struct {
844 unsigned short id; /* Bytes 0-1 */
845 enum myrs_cmd_opcode opcode; /* Byte 2 */
846 struct myrs_cmd_ctrl control; /* Byte 3 */
847 u32 dma_size:24; /* Bytes 4-6 */
848 unsigned char dma_num; /* Byte 7 */
849 u64 sense_addr; /* Bytes 8-15 */
850 struct myrs_pdev pdev; /* Bytes 16-18 */
851 struct myrs_cmd_tmo tmo; /* Byte 19 */
852 unsigned char sense_len; /* Byte 20 */
853 enum myrs_ioctl_opcode ioctl_opcode; /* Byte 21 */
854 enum myrs_opdev opdev; /* Byte 22 */
855 unsigned char rsvd[9]; /* Bytes 23-31 */
856 union myrs_sgl dma_addr; /* Bytes 32-63 */
857 } dev_op;
858 };
859
860 /*
861 * DAC960 V2 Firmware Controller Status Mailbox structure.
862 */
863 struct myrs_stat_mbox {
864 unsigned short id; /* Bytes 0-1 */
865 unsigned char status; /* Byte 2 */
866 unsigned char sense_len; /* Byte 3 */
867 int residual; /* Bytes 4-7 */
868 };
869
870 struct myrs_cmdblk {
871 union myrs_cmd_mbox mbox;
872 unsigned char status;
873 unsigned char sense_len;
874 int residual;
875 struct completion *complete;
876 struct myrs_sge *sgl;
877 dma_addr_t sgl_addr;
878 unsigned char *dcdb;
879 dma_addr_t dcdb_dma;
880 unsigned char *sense;
881 dma_addr_t sense_addr;
882 };
883
884 /*
885 * DAC960 Driver Controller structure.
886 */
887 struct myrs_hba {
888 void __iomem *io_base;
889 void __iomem *mmio_base;
890 phys_addr_t io_addr;
891 phys_addr_t pci_addr;
892 unsigned int irq;
893
894 unsigned char model_name[28];
895 unsigned char fw_version[12];
896
897 struct Scsi_Host *host;
898 struct pci_dev *pdev;
899
900 unsigned int epoch;
901 unsigned int next_evseq;
902 /* Monitor flags */
903 bool needs_update;
904 bool disable_enc_msg;
905
906 struct workqueue_struct *work_q;
907 char work_q_name[20];
908 struct delayed_work monitor_work;
909 unsigned long primary_monitor_time;
910 unsigned long secondary_monitor_time;
911
912 spinlock_t queue_lock;
913
914 struct dma_pool *sg_pool;
915 struct dma_pool *sense_pool;
916 struct dma_pool *dcdb_pool;
917
918 void (*write_cmd_mbox)(union myrs_cmd_mbox *next_mbox,
919 union myrs_cmd_mbox *cmd_mbox);
920 void (*get_cmd_mbox)(void __iomem *base);
921 void (*disable_intr)(void __iomem *base);
922 void (*reset)(void __iomem *base);
923
924 dma_addr_t cmd_mbox_addr;
925 size_t cmd_mbox_size;
926 union myrs_cmd_mbox *first_cmd_mbox;
927 union myrs_cmd_mbox *last_cmd_mbox;
928 union myrs_cmd_mbox *next_cmd_mbox;
929 union myrs_cmd_mbox *prev_cmd_mbox1;
930 union myrs_cmd_mbox *prev_cmd_mbox2;
931
932 dma_addr_t stat_mbox_addr;
933 size_t stat_mbox_size;
934 struct myrs_stat_mbox *first_stat_mbox;
935 struct myrs_stat_mbox *last_stat_mbox;
936 struct myrs_stat_mbox *next_stat_mbox;
937
938 struct myrs_cmdblk dcmd_blk;
939 struct myrs_cmdblk mcmd_blk;
940 struct mutex dcmd_mutex;
941
942 struct myrs_fwstat *fwstat_buf;
943 dma_addr_t fwstat_addr;
944
945 struct myrs_ctlr_info *ctlr_info;
946 struct mutex cinfo_mutex;
947
948 struct myrs_event *event_buf;
949 };
950
951 typedef unsigned char (*enable_mbox_t)(void __iomem *base, dma_addr_t addr);
952 typedef int (*myrs_hwinit_t)(struct pci_dev *pdev,
953 struct myrs_hba *c, void __iomem *base);
954
955 struct myrs_privdata {
956 myrs_hwinit_t hw_init;
957 irq_handler_t irq_handler;
958 unsigned int mmio_size;
959 };
960
961 /*
962 * DAC960 GEM Series Controller Interface Register Offsets.
963 */
964
965 #define DAC960_GEM_mmio_size 0x600
966
967 enum DAC960_GEM_reg_offset {
968 DAC960_GEM_IDB_READ_OFFSET = 0x214,
969 DAC960_GEM_IDB_CLEAR_OFFSET = 0x218,
970 DAC960_GEM_ODB_READ_OFFSET = 0x224,
971 DAC960_GEM_ODB_CLEAR_OFFSET = 0x228,
972 DAC960_GEM_IRQSTS_OFFSET = 0x208,
973 DAC960_GEM_IRQMASK_READ_OFFSET = 0x22C,
974 DAC960_GEM_IRQMASK_CLEAR_OFFSET = 0x230,
975 DAC960_GEM_CMDMBX_OFFSET = 0x510,
976 DAC960_GEM_CMDSTS_OFFSET = 0x518,
977 DAC960_GEM_ERRSTS_READ_OFFSET = 0x224,
978 DAC960_GEM_ERRSTS_CLEAR_OFFSET = 0x228,
979 };
980
981 /*
982 * DAC960 GEM Series Inbound Door Bell Register.
983 */
984 #define DAC960_GEM_IDB_HWMBOX_NEW_CMD 0x01
985 #define DAC960_GEM_IDB_HWMBOX_ACK_STS 0x02
986 #define DAC960_GEM_IDB_GEN_IRQ 0x04
987 #define DAC960_GEM_IDB_CTRL_RESET 0x08
988 #define DAC960_GEM_IDB_MMBOX_NEW_CMD 0x10
989
990 #define DAC960_GEM_IDB_HWMBOX_FULL 0x01
991 #define DAC960_GEM_IDB_INIT_IN_PROGRESS 0x02
992
993 /*
994 * DAC960 GEM Series Outbound Door Bell Register.
995 */
996 #define DAC960_GEM_ODB_HWMBOX_ACK_IRQ 0x01
997 #define DAC960_GEM_ODB_MMBOX_ACK_IRQ 0x02
998 #define DAC960_GEM_ODB_HWMBOX_STS_AVAIL 0x01
999 #define DAC960_GEM_ODB_MMBOX_STS_AVAIL 0x02
1000
1001 /*
1002 * DAC960 GEM Series Interrupt Mask Register.
1003 */
1004 #define DAC960_GEM_IRQMASK_HWMBOX_IRQ 0x01
1005 #define DAC960_GEM_IRQMASK_MMBOX_IRQ 0x02
1006
1007 /*
1008 * DAC960 GEM Series Error Status Register.
1009 */
1010 #define DAC960_GEM_ERRSTS_PENDING 0x20
1011
1012 /*
1013 * dma_addr_writeql is provided to write dma_addr_t types
1014 * to a 64-bit pci address space register. The controller
1015 * will accept having the register written as two 32-bit
1016 * values.
1017 *
1018 * In HIGHMEM kernels, dma_addr_t is a 64-bit value.
1019 * without HIGHMEM, dma_addr_t is a 32-bit value.
1020 *
1021 * The compiler should always fix up the assignment
1022 * to u.wq appropriately, depending upon the size of
1023 * dma_addr_t.
1024 */
1025 static inline
1026 void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
1027 {
1028 union {
1029 u64 wq;
1030 uint wl[2];
1031 } u;
1032
1033 u.wq = addr;
1034
1035 writel(u.wl[0], write_address);
1036 writel(u.wl[1], write_address + 4);
1037 }
1038
1039 /*
1040 * DAC960 BA Series Controller Interface Register Offsets.
1041 */
1042
1043 #define DAC960_BA_mmio_size 0x80
1044
1045 enum DAC960_BA_reg_offset {
1046 DAC960_BA_IRQSTS_OFFSET = 0x30,
1047 DAC960_BA_IRQMASK_OFFSET = 0x34,
1048 DAC960_BA_CMDMBX_OFFSET = 0x50,
1049 DAC960_BA_CMDSTS_OFFSET = 0x58,
1050 DAC960_BA_IDB_OFFSET = 0x60,
1051 DAC960_BA_ODB_OFFSET = 0x61,
1052 DAC960_BA_ERRSTS_OFFSET = 0x63,
1053 };
1054
1055 /*
1056 * DAC960 BA Series Inbound Door Bell Register.
1057 */
1058 #define DAC960_BA_IDB_HWMBOX_NEW_CMD 0x01
1059 #define DAC960_BA_IDB_HWMBOX_ACK_STS 0x02
1060 #define DAC960_BA_IDB_GEN_IRQ 0x04
1061 #define DAC960_BA_IDB_CTRL_RESET 0x08
1062 #define DAC960_BA_IDB_MMBOX_NEW_CMD 0x10
1063
1064 #define DAC960_BA_IDB_HWMBOX_EMPTY 0x01
1065 #define DAC960_BA_IDB_INIT_DONE 0x02
1066
1067 /*
1068 * DAC960 BA Series Outbound Door Bell Register.
1069 */
1070 #define DAC960_BA_ODB_HWMBOX_ACK_IRQ 0x01
1071 #define DAC960_BA_ODB_MMBOX_ACK_IRQ 0x02
1072
1073 #define DAC960_BA_ODB_HWMBOX_STS_AVAIL 0x01
1074 #define DAC960_BA_ODB_MMBOX_STS_AVAIL 0x02
1075
1076 /*
1077 * DAC960 BA Series Interrupt Mask Register.
1078 */
1079 #define DAC960_BA_IRQMASK_DISABLE_IRQ 0x04
1080 #define DAC960_BA_IRQMASK_DISABLEW_I2O 0x08
1081
1082 /*
1083 * DAC960 BA Series Error Status Register.
1084 */
1085 #define DAC960_BA_ERRSTS_PENDING 0x04
1086
1087 /*
1088 * DAC960 LP Series Controller Interface Register Offsets.
1089 */
1090
1091 #define DAC960_LP_mmio_size 0x80
1092
1093 enum DAC960_LP_reg_offset {
1094 DAC960_LP_CMDMBX_OFFSET = 0x10,
1095 DAC960_LP_CMDSTS_OFFSET = 0x18,
1096 DAC960_LP_IDB_OFFSET = 0x20,
1097 DAC960_LP_ODB_OFFSET = 0x2C,
1098 DAC960_LP_ERRSTS_OFFSET = 0x2E,
1099 DAC960_LP_IRQSTS_OFFSET = 0x30,
1100 DAC960_LP_IRQMASK_OFFSET = 0x34,
1101 };
1102
1103 /*
1104 * DAC960 LP Series Inbound Door Bell Register.
1105 */
1106 #define DAC960_LP_IDB_HWMBOX_NEW_CMD 0x01
1107 #define DAC960_LP_IDB_HWMBOX_ACK_STS 0x02
1108 #define DAC960_LP_IDB_GEN_IRQ 0x04
1109 #define DAC960_LP_IDB_CTRL_RESET 0x08
1110 #define DAC960_LP_IDB_MMBOX_NEW_CMD 0x10
1111
1112 #define DAC960_LP_IDB_HWMBOX_FULL 0x01
1113 #define DAC960_LP_IDB_INIT_IN_PROGRESS 0x02
1114
1115 /*
1116 * DAC960 LP Series Outbound Door Bell Register.
1117 */
1118 #define DAC960_LP_ODB_HWMBOX_ACK_IRQ 0x01
1119 #define DAC960_LP_ODB_MMBOX_ACK_IRQ 0x02
1120
1121 #define DAC960_LP_ODB_HWMBOX_STS_AVAIL 0x01
1122 #define DAC960_LP_ODB_MMBOX_STS_AVAIL 0x02
1123
1124 /*
1125 * DAC960 LP Series Interrupt Mask Register.
1126 */
1127 #define DAC960_LP_IRQMASK_DISABLE_IRQ 0x04
1128
1129 /*
1130 * DAC960 LP Series Error Status Register.
1131 */
1132 #define DAC960_LP_ERRSTS_PENDING 0x04
1133
1134 #endif /* _MYRS_H */
Linux with added FPC-III support