drivers/scsi/ufs/ufs-mediatek.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc.
   4  */
   5
   6 #ifndef _UFS_MEDIATEK_H
   7 #define _UFS_MEDIATEK_H
   8
   9 /*
  10  * Vendor specific pre-defined parameters
  11  */
  12 #define UFS_MTK_LIMIT_NUM_LANES_RX  1
  13 #define UFS_MTK_LIMIT_NUM_LANES_TX  1
  14 #define UFS_MTK_LIMIT_HSGEAR_RX     UFS_HS_G3
  15 #define UFS_MTK_LIMIT_HSGEAR_TX     UFS_HS_G3
  16 #define UFS_MTK_LIMIT_PWMGEAR_RX    UFS_PWM_G4
  17 #define UFS_MTK_LIMIT_PWMGEAR_TX    UFS_PWM_G4
  18 #define UFS_MTK_LIMIT_RX_PWR_PWM    SLOW_MODE
  19 #define UFS_MTK_LIMIT_TX_PWR_PWM    SLOW_MODE
  20 #define UFS_MTK_LIMIT_RX_PWR_HS     FAST_MODE
  21 #define UFS_MTK_LIMIT_TX_PWR_HS     FAST_MODE
  22 #define UFS_MTK_LIMIT_HS_RATE       PA_HS_MODE_B
  23 #define UFS_MTK_LIMIT_DESIRED_MODE  UFS_HS_MODE
  24
  25 /*
  26  * Other attributes
  27  */
  28 #define VS_DEBUGCLOCKENABLE         0xD0A1
  29 #define VS_SAVEPOWERCONTROL         0xD0A6
  30 #define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
  31
  32 /*
  33  * VS_DEBUGCLOCKENABLE
  34  */
  35 enum {
  36         TX_SYMBOL_CLK_REQ_FORCE = 5,
  37 };
  38
  39 /*
  40  * VS_SAVEPOWERCONTROL
  41  */
  42 enum {
  43         RX_SYMBOL_CLK_GATE_EN   = 0,
  44         SYS_CLK_GATE_EN         = 2,
  45         TX_CLK_GATE_EN          = 3,
  46 };
  47
  48 struct ufs_mtk_host {
  49         struct ufs_hba *hba;
  50         struct phy *mphy;
  51 };
  52
  53 #endif /* !_UFS_MEDIATEK_H */