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dmaengine: imx-sdma: Let the core do the device node validation
[linux/fpc-iii.git] / drivers / thermal / rockchip_thermal.c
blobbda1ca199abd3f9cbbe3a8195d9ae93a61036139
1 /*
2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Caesar Wang <wxt@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/thermal.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/pinctrl/consumer.h>
29
30 /**
31 * If the temperature over a period of time High,
32 * the resulting TSHUT gave CRU module,let it reset the entire chip,
33 * or via GPIO give PMIC.
34 */
35 enum tshut_mode {
36 TSHUT_MODE_CRU = 0,
37 TSHUT_MODE_GPIO,
38 };
39
40 /**
41 * The system Temperature Sensors tshut(tshut) polarity
42 * the bit 8 is tshut polarity.
43 * 0: low active, 1: high active
44 */
45 enum tshut_polarity {
46 TSHUT_LOW_ACTIVE = 0,
47 TSHUT_HIGH_ACTIVE,
48 };
49
50 /**
51 * The system has two Temperature Sensors.
52 * sensor0 is for CPU, and sensor1 is for GPU.
53 */
54 enum sensor_id {
55 SENSOR_CPU = 0,
56 SENSOR_GPU,
57 };
58
59 /**
60 * The conversion table has the adc value and temperature.
61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
63 */
64 enum adc_sort_mode {
65 ADC_DECREMENT = 0,
66 ADC_INCREMENT,
67 };
68
69 /**
70 * The max sensors is two in rockchip SoCs.
71 * Two sensors: CPU and GPU sensor.
72 */
73 #define SOC_MAX_SENSORS 2
74
75 /**
76 * struct chip_tsadc_table - hold information about chip-specific differences
77 * @id: conversion table
78 * @length: size of conversion table
79 * @data_mask: mask to apply on data inputs
80 * @mode: sort mode of this adc variant (incrementing or decrementing)
81 */
82 struct chip_tsadc_table {
83 const struct tsadc_table *id;
84 unsigned int length;
85 u32 data_mask;
86 enum adc_sort_mode mode;
87 };
88
89 /**
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @tshut_temp: the hardware-controlled shutdown temperature value
94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
96 * @initialize: SoC special initialize tsadc controller method
97 * @irq_ack: clear the interrupt
98 * @get_temp: get the temperature
99 * @set_alarm_temp: set the high temperature interrupt
100 * @set_tshut_temp: set the hardware-controlled shutdown temperature
101 * @set_tshut_mode: set the hardware-controlled shutdown mode
102 * @table: the chip-specific conversion table
103 */
104 struct rockchip_tsadc_chip {
105 /* The sensor id of chip correspond to the ADC channel */
106 int chn_id[SOC_MAX_SENSORS];
107 int chn_num;
108
109 /* The hardware-controlled tshut property */
110 int tshut_temp;
111 enum tshut_mode tshut_mode;
112 enum tshut_polarity tshut_polarity;
113
114 /* Chip-wide methods */
115 void (*initialize)(struct regmap *grf,
116 void __iomem *reg, enum tshut_polarity p);
117 void (*irq_ack)(void __iomem *reg);
118 void (*control)(void __iomem *reg, bool on);
119
120 /* Per-sensor methods */
121 int (*get_temp)(const struct chip_tsadc_table *table,
122 int chn, void __iomem *reg, int *temp);
123 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
124 int chn, void __iomem *reg, int temp);
125 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
126 int chn, void __iomem *reg, int temp);
127 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
128
129 /* Per-table methods */
130 struct chip_tsadc_table table;
131 };
132
133 /**
134 * struct rockchip_thermal_sensor - hold the information of thermal sensor
135 * @thermal: pointer to the platform/configuration data
136 * @tzd: pointer to a thermal zone
137 * @id: identifier of the thermal sensor
138 */
139 struct rockchip_thermal_sensor {
140 struct rockchip_thermal_data *thermal;
141 struct thermal_zone_device *tzd;
142 int id;
143 };
144
145 /**
146 * struct rockchip_thermal_data - hold the private data of thermal driver
147 * @chip: pointer to the platform/configuration data
148 * @pdev: platform device of thermal
149 * @reset: the reset controller of tsadc
150 * @sensors[SOC_MAX_SENSORS]: the thermal sensor
151 * @clk: the controller clock is divided by the exteral 24MHz
152 * @pclk: the advanced peripherals bus clock
153 * @grf: the general register file will be used to do static set by software
154 * @regs: the base address of tsadc controller
155 * @tshut_temp: the hardware-controlled shutdown temperature value
156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
158 */
159 struct rockchip_thermal_data {
160 const struct rockchip_tsadc_chip *chip;
161 struct platform_device *pdev;
162 struct reset_control *reset;
163
164 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
165
166 struct clk *clk;
167 struct clk *pclk;
168
169 struct regmap *grf;
170 void __iomem *regs;
171
172 int tshut_temp;
173 enum tshut_mode tshut_mode;
174 enum tshut_polarity tshut_polarity;
175 struct pinctrl *pinctrl;
176 struct pinctrl_state *gpio_state;
177 struct pinctrl_state *otp_state;
178 };
179
180 /**
181 * TSADC Sensor Register description:
182 *
183 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
184 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
185 *
186 */
187 #define TSADCV2_USER_CON 0x00
188 #define TSADCV2_AUTO_CON 0x04
189 #define TSADCV2_INT_EN 0x08
190 #define TSADCV2_INT_PD 0x0c
191 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
192 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
193 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
194 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
195 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
196 #define TSADCV2_AUTO_PERIOD 0x68
197 #define TSADCV2_AUTO_PERIOD_HT 0x6c
198
199 #define TSADCV2_AUTO_EN BIT(0)
200 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
201 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
202
203 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
204
205 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
206 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
207 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
208
209 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
210 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
211
212 #define TSADCV2_DATA_MASK 0xfff
213 #define TSADCV3_DATA_MASK 0x3ff
214
215 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
216 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
217 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
218 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
219 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
220 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
221
222 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
223
224 #define GRF_SARADC_TESTBIT 0x0e644
225 #define GRF_TSADC_TESTBIT_L 0x0e648
226 #define GRF_TSADC_TESTBIT_H 0x0e64c
227
228 #define PX30_GRF_SOC_CON2 0x0408
229
230 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
231 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
232 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
233 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
234
235 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
236
237 /**
238 * struct tsadc_table - code to temperature conversion table
239 * @code: the value of adc channel
240 * @temp: the temperature
241 * Note:
242 * code to temperature mapping of the temperature sensor is a piece wise linear
243 * curve.Any temperature, code faling between to 2 give temperatures can be
244 * linearly interpolated.
245 * Code to Temperature mapping should be updated based on manufacturer results.
246 */
247 struct tsadc_table {
248 u32 code;
249 int temp;
250 };
251
252 static const struct tsadc_table rv1108_table[] = {
253 {0, -40000},
254 {374, -40000},
255 {382, -35000},
256 {389, -30000},
257 {397, -25000},
258 {405, -20000},
259 {413, -15000},
260 {421, -10000},
261 {429, -5000},
262 {436, 0},
263 {444, 5000},
264 {452, 10000},
265 {460, 15000},
266 {468, 20000},
267 {476, 25000},
268 {483, 30000},
269 {491, 35000},
270 {499, 40000},
271 {507, 45000},
272 {515, 50000},
273 {523, 55000},
274 {531, 60000},
275 {539, 65000},
276 {547, 70000},
277 {555, 75000},
278 {562, 80000},
279 {570, 85000},
280 {578, 90000},
281 {586, 95000},
282 {594, 100000},
283 {602, 105000},
284 {610, 110000},
285 {618, 115000},
286 {626, 120000},
287 {634, 125000},
288 {TSADCV2_DATA_MASK, 125000},
289 };
290
291 static const struct tsadc_table rk3228_code_table[] = {
292 {0, -40000},
293 {588, -40000},
294 {593, -35000},
295 {598, -30000},
296 {603, -25000},
297 {608, -20000},
298 {613, -15000},
299 {618, -10000},
300 {623, -5000},
301 {629, 0},
302 {634, 5000},
303 {639, 10000},
304 {644, 15000},
305 {649, 20000},
306 {654, 25000},
307 {660, 30000},
308 {665, 35000},
309 {670, 40000},
310 {675, 45000},
311 {681, 50000},
312 {686, 55000},
313 {691, 60000},
314 {696, 65000},
315 {702, 70000},
316 {707, 75000},
317 {712, 80000},
318 {717, 85000},
319 {723, 90000},
320 {728, 95000},
321 {733, 100000},
322 {738, 105000},
323 {744, 110000},
324 {749, 115000},
325 {754, 120000},
326 {760, 125000},
327 {TSADCV2_DATA_MASK, 125000},
328 };
329
330 static const struct tsadc_table rk3288_code_table[] = {
331 {TSADCV2_DATA_MASK, -40000},
332 {3800, -40000},
333 {3792, -35000},
334 {3783, -30000},
335 {3774, -25000},
336 {3765, -20000},
337 {3756, -15000},
338 {3747, -10000},
339 {3737, -5000},
340 {3728, 0},
341 {3718, 5000},
342 {3708, 10000},
343 {3698, 15000},
344 {3688, 20000},
345 {3678, 25000},
346 {3667, 30000},
347 {3656, 35000},
348 {3645, 40000},
349 {3634, 45000},
350 {3623, 50000},
351 {3611, 55000},
352 {3600, 60000},
353 {3588, 65000},
354 {3575, 70000},
355 {3563, 75000},
356 {3550, 80000},
357 {3537, 85000},
358 {3524, 90000},
359 {3510, 95000},
360 {3496, 100000},
361 {3482, 105000},
362 {3467, 110000},
363 {3452, 115000},
364 {3437, 120000},
365 {3421, 125000},
366 {0, 125000},
367 };
368
369 static const struct tsadc_table rk3328_code_table[] = {
370 {0, -40000},
371 {296, -40000},
372 {304, -35000},
373 {313, -30000},
374 {331, -20000},
375 {340, -15000},
376 {349, -10000},
377 {359, -5000},
378 {368, 0},
379 {378, 5000},
380 {388, 10000},
381 {398, 15000},
382 {408, 20000},
383 {418, 25000},
384 {429, 30000},
385 {440, 35000},
386 {451, 40000},
387 {462, 45000},
388 {473, 50000},
389 {485, 55000},
390 {496, 60000},
391 {508, 65000},
392 {521, 70000},
393 {533, 75000},
394 {546, 80000},
395 {559, 85000},
396 {572, 90000},
397 {586, 95000},
398 {600, 100000},
399 {614, 105000},
400 {629, 110000},
401 {644, 115000},
402 {659, 120000},
403 {675, 125000},
404 {TSADCV2_DATA_MASK, 125000},
405 };
406
407 static const struct tsadc_table rk3368_code_table[] = {
408 {0, -40000},
409 {106, -40000},
410 {108, -35000},
411 {110, -30000},
412 {112, -25000},
413 {114, -20000},
414 {116, -15000},
415 {118, -10000},
416 {120, -5000},
417 {122, 0},
418 {124, 5000},
419 {126, 10000},
420 {128, 15000},
421 {130, 20000},
422 {132, 25000},
423 {134, 30000},
424 {136, 35000},
425 {138, 40000},
426 {140, 45000},
427 {142, 50000},
428 {144, 55000},
429 {146, 60000},
430 {148, 65000},
431 {150, 70000},
432 {152, 75000},
433 {154, 80000},
434 {156, 85000},
435 {158, 90000},
436 {160, 95000},
437 {162, 100000},
438 {163, 105000},
439 {165, 110000},
440 {167, 115000},
441 {169, 120000},
442 {171, 125000},
443 {TSADCV3_DATA_MASK, 125000},
444 };
445
446 static const struct tsadc_table rk3399_code_table[] = {
447 {0, -40000},
448 {402, -40000},
449 {410, -35000},
450 {419, -30000},
451 {427, -25000},
452 {436, -20000},
453 {444, -15000},
454 {453, -10000},
455 {461, -5000},
456 {470, 0},
457 {478, 5000},
458 {487, 10000},
459 {496, 15000},
460 {504, 20000},
461 {513, 25000},
462 {521, 30000},
463 {530, 35000},
464 {538, 40000},
465 {547, 45000},
466 {555, 50000},
467 {564, 55000},
468 {573, 60000},
469 {581, 65000},
470 {590, 70000},
471 {599, 75000},
472 {607, 80000},
473 {616, 85000},
474 {624, 90000},
475 {633, 95000},
476 {642, 100000},
477 {650, 105000},
478 {659, 110000},
479 {668, 115000},
480 {677, 120000},
481 {685, 125000},
482 {TSADCV3_DATA_MASK, 125000},
483 };
484
485 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
486 int temp)
487 {
488 int high, low, mid;
489 unsigned long num;
490 unsigned int denom;
491 u32 error = table->data_mask;
492
493 low = 0;
494 high = (table->length - 1) - 1; /* ignore the last check for table */
495 mid = (high + low) / 2;
496
497 /* Return mask code data when the temp is over table range */
498 if (temp < table->id[low].temp || temp > table->id[high].temp)
499 goto exit;
500
501 while (low <= high) {
502 if (temp == table->id[mid].temp)
503 return table->id[mid].code;
504 else if (temp < table->id[mid].temp)
505 high = mid - 1;
506 else
507 low = mid + 1;
508 mid = (low + high) / 2;
509 }
510
511 /*
512 * The conversion code granularity provided by the table. Let's
513 * assume that the relationship between temperature and
514 * analog value between 2 table entries is linear and interpolate
515 * to produce less granular result.
516 */
517 num = abs(table->id[mid + 1].code - table->id[mid].code);
518 num *= temp - table->id[mid].temp;
519 denom = table->id[mid + 1].temp - table->id[mid].temp;
520
521 switch (table->mode) {
522 case ADC_DECREMENT:
523 return table->id[mid].code - (num / denom);
524 case ADC_INCREMENT:
525 return table->id[mid].code + (num / denom);
526 default:
527 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
528 return error;
529 }
530
531 exit:
532 pr_err("%s: invalid temperature, temp=%d error=%d\n",
533 __func__, temp, error);
534 return error;
535 }
536
537 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
538 u32 code, int *temp)
539 {
540 unsigned int low = 1;
541 unsigned int high = table->length - 1;
542 unsigned int mid = (low + high) / 2;
543 unsigned int num;
544 unsigned long denom;
545
546 WARN_ON(table->length < 2);
547
548 switch (table->mode) {
549 case ADC_DECREMENT:
550 code &= table->data_mask;
551 if (code <= table->id[high].code)
552 return -EAGAIN; /* Incorrect reading */
553
554 while (low <= high) {
555 if (code >= table->id[mid].code &&
556 code < table->id[mid - 1].code)
557 break;
558 else if (code < table->id[mid].code)
559 low = mid + 1;
560 else
561 high = mid - 1;
562
563 mid = (low + high) / 2;
564 }
565 break;
566 case ADC_INCREMENT:
567 code &= table->data_mask;
568 if (code < table->id[low].code)
569 return -EAGAIN; /* Incorrect reading */
570
571 while (low <= high) {
572 if (code <= table->id[mid].code &&
573 code > table->id[mid - 1].code)
574 break;
575 else if (code > table->id[mid].code)
576 low = mid + 1;
577 else
578 high = mid - 1;
579
580 mid = (low + high) / 2;
581 }
582 break;
583 default:
584 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
585 return -EINVAL;
586 }
587
588 /*
589 * The 5C granularity provided by the table is too much. Let's
590 * assume that the relationship between sensor readings and
591 * temperature between 2 table entries is linear and interpolate
592 * to produce less granular result.
593 */
594 num = table->id[mid].temp - table->id[mid - 1].temp;
595 num *= abs(table->id[mid - 1].code - code);
596 denom = abs(table->id[mid - 1].code - table->id[mid].code);
597 *temp = table->id[mid - 1].temp + (num / denom);
598
599 return 0;
600 }
601
602 /**
603 * rk_tsadcv2_initialize - initialize TASDC Controller.
604 *
605 * (1) Set TSADC_V2_AUTO_PERIOD:
606 * Configure the interleave between every two accessing of
607 * TSADC in normal operation.
608 *
609 * (2) Set TSADCV2_AUTO_PERIOD_HT:
610 * Configure the interleave between every two accessing of
611 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
612 *
613 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
614 * If the temperature is higher than COMP_INT or COMP_SHUT for
615 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
616 */
617 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
618 enum tshut_polarity tshut_polarity)
619 {
620 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
621 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
622 regs + TSADCV2_AUTO_CON);
623 else
624 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
625 regs + TSADCV2_AUTO_CON);
626
627 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
628 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
629 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
630 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
631 regs + TSADCV2_AUTO_PERIOD_HT);
632 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
633 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
634 }
635
636 /**
637 * rk_tsadcv3_initialize - initialize TASDC Controller.
638 *
639 * (1) The tsadc control power sequence.
640 *
641 * (2) Set TSADC_V2_AUTO_PERIOD:
642 * Configure the interleave between every two accessing of
643 * TSADC in normal operation.
644 *
645 * (2) Set TSADCV2_AUTO_PERIOD_HT:
646 * Configure the interleave between every two accessing of
647 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
648 *
649 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
650 * If the temperature is higher than COMP_INT or COMP_SHUT for
651 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
652 */
653 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
654 enum tshut_polarity tshut_polarity)
655 {
656 /* The tsadc control power sequence */
657 if (IS_ERR(grf)) {
658 /* Set interleave value to workround ic time sync issue */
659 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
660 TSADCV2_USER_CON);
661
662 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
663 regs + TSADCV2_AUTO_PERIOD);
664 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
665 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
666 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
667 regs + TSADCV2_AUTO_PERIOD_HT);
668 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
669 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
670
671 } else {
672 /* Enable the voltage common mode feature */
673 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
674 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
675
676 usleep_range(15, 100); /* The spec note says at least 15 us */
677 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
678 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
679 usleep_range(90, 200); /* The spec note says at least 90 us */
680
681 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
682 regs + TSADCV2_AUTO_PERIOD);
683 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
684 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
685 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
686 regs + TSADCV2_AUTO_PERIOD_HT);
687 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
688 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
689 }
690
691 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
692 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
693 regs + TSADCV2_AUTO_CON);
694 else
695 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
696 regs + TSADCV2_AUTO_CON);
697 }
698
699 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
700 enum tshut_polarity tshut_polarity)
701 {
702 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
703 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
704 }
705
706 static void rk_tsadcv2_irq_ack(void __iomem *regs)
707 {
708 u32 val;
709
710 val = readl_relaxed(regs + TSADCV2_INT_PD);
711 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
712 }
713
714 static void rk_tsadcv3_irq_ack(void __iomem *regs)
715 {
716 u32 val;
717
718 val = readl_relaxed(regs + TSADCV2_INT_PD);
719 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
720 }
721
722 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
723 {
724 u32 val;
725
726 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
727 if (enable)
728 val |= TSADCV2_AUTO_EN;
729 else
730 val &= ~TSADCV2_AUTO_EN;
731
732 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
733 }
734
735 /**
736 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
737 *
738 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
739 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
740 * adc value if setting this bit to enable.
741 */
742 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
743 {
744 u32 val;
745
746 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
747 if (enable)
748 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
749 else
750 val &= ~TSADCV2_AUTO_EN;
751
752 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
753 }
754
755 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
756 int chn, void __iomem *regs, int *temp)
757 {
758 u32 val;
759
760 val = readl_relaxed(regs + TSADCV2_DATA(chn));
761
762 return rk_tsadcv2_code_to_temp(table, val, temp);
763 }
764
765 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
766 int chn, void __iomem *regs, int temp)
767 {
768 u32 alarm_value;
769 u32 int_en, int_clr;
770
771 /*
772 * In some cases, some sensors didn't need the trip points, the
773 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
774 * in the end, ignore this case and disable the high temperature
775 * interrupt.
776 */
777 if (temp == INT_MAX) {
778 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
779 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
780 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
781 return 0;
782 }
783
784 /* Make sure the value is valid */
785 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
786 if (alarm_value == table->data_mask)
787 return -ERANGE;
788
789 writel_relaxed(alarm_value & table->data_mask,
790 regs + TSADCV2_COMP_INT(chn));
791
792 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
793 int_en |= TSADCV2_INT_SRC_EN(chn);
794 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
795
796 return 0;
797 }
798
799 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
800 int chn, void __iomem *regs, int temp)
801 {
802 u32 tshut_value, val;
803
804 /* Make sure the value is valid */
805 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
806 if (tshut_value == table->data_mask)
807 return -ERANGE;
808
809 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
810
811 /* TSHUT will be valid */
812 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
813 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
814
815 return 0;
816 }
817
818 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
819 enum tshut_mode mode)
820 {
821 u32 val;
822
823 val = readl_relaxed(regs + TSADCV2_INT_EN);
824 if (mode == TSHUT_MODE_GPIO) {
825 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
826 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
827 } else {
828 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
829 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
830 }
831
832 writel_relaxed(val, regs + TSADCV2_INT_EN);
833 }
834
835 static const struct rockchip_tsadc_chip px30_tsadc_data = {
836 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
837 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
838 .chn_num = 2, /* 2 channels for tsadc */
839
840 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
841 .tshut_temp = 95000,
842
843 .initialize = rk_tsadcv4_initialize,
844 .irq_ack = rk_tsadcv3_irq_ack,
845 .control = rk_tsadcv3_control,
846 .get_temp = rk_tsadcv2_get_temp,
847 .set_alarm_temp = rk_tsadcv2_alarm_temp,
848 .set_tshut_temp = rk_tsadcv2_tshut_temp,
849 .set_tshut_mode = rk_tsadcv2_tshut_mode,
850
851 .table = {
852 .id = rk3328_code_table,
853 .length = ARRAY_SIZE(rk3328_code_table),
854 .data_mask = TSADCV2_DATA_MASK,
855 .mode = ADC_INCREMENT,
856 },
857 };
858
859 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
860 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
861 .chn_num = 1, /* one channel for tsadc */
862
863 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
864 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
865 .tshut_temp = 95000,
866
867 .initialize = rk_tsadcv2_initialize,
868 .irq_ack = rk_tsadcv3_irq_ack,
869 .control = rk_tsadcv3_control,
870 .get_temp = rk_tsadcv2_get_temp,
871 .set_alarm_temp = rk_tsadcv2_alarm_temp,
872 .set_tshut_temp = rk_tsadcv2_tshut_temp,
873 .set_tshut_mode = rk_tsadcv2_tshut_mode,
874
875 .table = {
876 .id = rv1108_table,
877 .length = ARRAY_SIZE(rv1108_table),
878 .data_mask = TSADCV2_DATA_MASK,
879 .mode = ADC_INCREMENT,
880 },
881 };
882
883 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
884 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
885 .chn_num = 1, /* one channel for tsadc */
886
887 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
888 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
889 .tshut_temp = 95000,
890
891 .initialize = rk_tsadcv2_initialize,
892 .irq_ack = rk_tsadcv3_irq_ack,
893 .control = rk_tsadcv3_control,
894 .get_temp = rk_tsadcv2_get_temp,
895 .set_alarm_temp = rk_tsadcv2_alarm_temp,
896 .set_tshut_temp = rk_tsadcv2_tshut_temp,
897 .set_tshut_mode = rk_tsadcv2_tshut_mode,
898
899 .table = {
900 .id = rk3228_code_table,
901 .length = ARRAY_SIZE(rk3228_code_table),
902 .data_mask = TSADCV3_DATA_MASK,
903 .mode = ADC_INCREMENT,
904 },
905 };
906
907 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
908 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
909 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
910 .chn_num = 2, /* two channels for tsadc */
911
912 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
913 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
914 .tshut_temp = 95000,
915
916 .initialize = rk_tsadcv2_initialize,
917 .irq_ack = rk_tsadcv2_irq_ack,
918 .control = rk_tsadcv2_control,
919 .get_temp = rk_tsadcv2_get_temp,
920 .set_alarm_temp = rk_tsadcv2_alarm_temp,
921 .set_tshut_temp = rk_tsadcv2_tshut_temp,
922 .set_tshut_mode = rk_tsadcv2_tshut_mode,
923
924 .table = {
925 .id = rk3288_code_table,
926 .length = ARRAY_SIZE(rk3288_code_table),
927 .data_mask = TSADCV2_DATA_MASK,
928 .mode = ADC_DECREMENT,
929 },
930 };
931
932 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
933 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
934 .chn_num = 1, /* one channels for tsadc */
935
936 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
937 .tshut_temp = 95000,
938
939 .initialize = rk_tsadcv2_initialize,
940 .irq_ack = rk_tsadcv3_irq_ack,
941 .control = rk_tsadcv3_control,
942 .get_temp = rk_tsadcv2_get_temp,
943 .set_alarm_temp = rk_tsadcv2_alarm_temp,
944 .set_tshut_temp = rk_tsadcv2_tshut_temp,
945 .set_tshut_mode = rk_tsadcv2_tshut_mode,
946
947 .table = {
948 .id = rk3328_code_table,
949 .length = ARRAY_SIZE(rk3328_code_table),
950 .data_mask = TSADCV2_DATA_MASK,
951 .mode = ADC_INCREMENT,
952 },
953 };
954
955 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
956 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
957 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
958 .chn_num = 2, /* two channels for tsadc */
959
960 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
961 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
962 .tshut_temp = 95000,
963
964 .initialize = rk_tsadcv3_initialize,
965 .irq_ack = rk_tsadcv3_irq_ack,
966 .control = rk_tsadcv3_control,
967 .get_temp = rk_tsadcv2_get_temp,
968 .set_alarm_temp = rk_tsadcv2_alarm_temp,
969 .set_tshut_temp = rk_tsadcv2_tshut_temp,
970 .set_tshut_mode = rk_tsadcv2_tshut_mode,
971
972 .table = {
973 .id = rk3228_code_table,
974 .length = ARRAY_SIZE(rk3228_code_table),
975 .data_mask = TSADCV3_DATA_MASK,
976 .mode = ADC_INCREMENT,
977 },
978 };
979
980 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
981 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
982 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
983 .chn_num = 2, /* two channels for tsadc */
984
985 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
986 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
987 .tshut_temp = 95000,
988
989 .initialize = rk_tsadcv2_initialize,
990 .irq_ack = rk_tsadcv2_irq_ack,
991 .control = rk_tsadcv2_control,
992 .get_temp = rk_tsadcv2_get_temp,
993 .set_alarm_temp = rk_tsadcv2_alarm_temp,
994 .set_tshut_temp = rk_tsadcv2_tshut_temp,
995 .set_tshut_mode = rk_tsadcv2_tshut_mode,
996
997 .table = {
998 .id = rk3368_code_table,
999 .length = ARRAY_SIZE(rk3368_code_table),
1000 .data_mask = TSADCV3_DATA_MASK,
1001 .mode = ADC_INCREMENT,
1002 },
1003 };
1004
1005 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1006 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1007 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1008 .chn_num = 2, /* two channels for tsadc */
1009
1010 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1011 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1012 .tshut_temp = 95000,
1013
1014 .initialize = rk_tsadcv3_initialize,
1015 .irq_ack = rk_tsadcv3_irq_ack,
1016 .control = rk_tsadcv3_control,
1017 .get_temp = rk_tsadcv2_get_temp,
1018 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1019 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1020 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1021
1022 .table = {
1023 .id = rk3399_code_table,
1024 .length = ARRAY_SIZE(rk3399_code_table),
1025 .data_mask = TSADCV3_DATA_MASK,
1026 .mode = ADC_INCREMENT,
1027 },
1028 };
1029
1030 static const struct of_device_id of_rockchip_thermal_match[] = {
1031 { .compatible = "rockchip,px30-tsadc",
1032 .data = (void *)&px30_tsadc_data,
1033 },
1034 {
1035 .compatible = "rockchip,rv1108-tsadc",
1036 .data = (void *)&rv1108_tsadc_data,
1037 },
1038 {
1039 .compatible = "rockchip,rk3228-tsadc",
1040 .data = (void *)&rk3228_tsadc_data,
1041 },
1042 {
1043 .compatible = "rockchip,rk3288-tsadc",
1044 .data = (void *)&rk3288_tsadc_data,
1045 },
1046 {
1047 .compatible = "rockchip,rk3328-tsadc",
1048 .data = (void *)&rk3328_tsadc_data,
1049 },
1050 {
1051 .compatible = "rockchip,rk3366-tsadc",
1052 .data = (void *)&rk3366_tsadc_data,
1053 },
1054 {
1055 .compatible = "rockchip,rk3368-tsadc",
1056 .data = (void *)&rk3368_tsadc_data,
1057 },
1058 {
1059 .compatible = "rockchip,rk3399-tsadc",
1060 .data = (void *)&rk3399_tsadc_data,
1061 },
1062 { /* end */ },
1063 };
1064 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1065
1066 static void
1067 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1068 {
1069 struct thermal_zone_device *tzd = sensor->tzd;
1070
1071 tzd->ops->set_mode(tzd,
1072 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
1073 }
1074
1075 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1076 {
1077 struct rockchip_thermal_data *thermal = dev;
1078 int i;
1079
1080 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1081
1082 thermal->chip->irq_ack(thermal->regs);
1083
1084 for (i = 0; i < thermal->chip->chn_num; i++)
1085 thermal_zone_device_update(thermal->sensors[i].tzd,
1086 THERMAL_EVENT_UNSPECIFIED);
1087
1088 return IRQ_HANDLED;
1089 }
1090
1091 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1092 {
1093 struct rockchip_thermal_sensor *sensor = _sensor;
1094 struct rockchip_thermal_data *thermal = sensor->thermal;
1095 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1096
1097 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1098 __func__, sensor->id, low, high);
1099
1100 return tsadc->set_alarm_temp(&tsadc->table,
1101 sensor->id, thermal->regs, high);
1102 }
1103
1104 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1105 {
1106 struct rockchip_thermal_sensor *sensor = _sensor;
1107 struct rockchip_thermal_data *thermal = sensor->thermal;
1108 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1109 int retval;
1110
1111 retval = tsadc->get_temp(&tsadc->table,
1112 sensor->id, thermal->regs, out_temp);
1113 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1114 sensor->id, *out_temp, retval);
1115
1116 return retval;
1117 }
1118
1119 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1120 .get_temp = rockchip_thermal_get_temp,
1121 .set_trips = rockchip_thermal_set_trips,
1122 };
1123
1124 static int rockchip_configure_from_dt(struct device *dev,
1125 struct device_node *np,
1126 struct rockchip_thermal_data *thermal)
1127 {
1128 u32 shut_temp, tshut_mode, tshut_polarity;
1129
1130 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1131 dev_warn(dev,
1132 "Missing tshut temp property, using default %d\n",
1133 thermal->chip->tshut_temp);
1134 thermal->tshut_temp = thermal->chip->tshut_temp;
1135 } else {
1136 if (shut_temp > INT_MAX) {
1137 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1138 shut_temp);
1139 return -ERANGE;
1140 }
1141 thermal->tshut_temp = shut_temp;
1142 }
1143
1144 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1145 dev_warn(dev,
1146 "Missing tshut mode property, using default (%s)\n",
1147 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1148 "gpio" : "cru");
1149 thermal->tshut_mode = thermal->chip->tshut_mode;
1150 } else {
1151 thermal->tshut_mode = tshut_mode;
1152 }
1153
1154 if (thermal->tshut_mode > 1) {
1155 dev_err(dev, "Invalid tshut mode specified: %d\n",
1156 thermal->tshut_mode);
1157 return -EINVAL;
1158 }
1159
1160 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1161 &tshut_polarity)) {
1162 dev_warn(dev,
1163 "Missing tshut-polarity property, using default (%s)\n",
1164 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1165 "low" : "high");
1166 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1167 } else {
1168 thermal->tshut_polarity = tshut_polarity;
1169 }
1170
1171 if (thermal->tshut_polarity > 1) {
1172 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1173 thermal->tshut_polarity);
1174 return -EINVAL;
1175 }
1176
1177 /* The tsadc wont to handle the error in here since some SoCs didn't
1178 * need this property.
1179 */
1180 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1181 if (IS_ERR(thermal->grf))
1182 dev_warn(dev, "Missing rockchip,grf property\n");
1183
1184 return 0;
1185 }
1186
1187 static int
1188 rockchip_thermal_register_sensor(struct platform_device *pdev,
1189 struct rockchip_thermal_data *thermal,
1190 struct rockchip_thermal_sensor *sensor,
1191 int id)
1192 {
1193 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1194 int error;
1195
1196 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1197
1198 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1199 thermal->tshut_temp);
1200 if (error)
1201 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1202 __func__, thermal->tshut_temp, error);
1203
1204 sensor->thermal = thermal;
1205 sensor->id = id;
1206 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1207 sensor, &rockchip_of_thermal_ops);
1208 if (IS_ERR(sensor->tzd)) {
1209 error = PTR_ERR(sensor->tzd);
1210 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1211 id, error);
1212 return error;
1213 }
1214
1215 return 0;
1216 }
1217
1218 /**
1219 * Reset TSADC Controller, reset all tsadc registers.
1220 */
1221 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1222 {
1223 reset_control_assert(reset);
1224 usleep_range(10, 20);
1225 reset_control_deassert(reset);
1226 }
1227
1228 static int rockchip_thermal_probe(struct platform_device *pdev)
1229 {
1230 struct device_node *np = pdev->dev.of_node;
1231 struct rockchip_thermal_data *thermal;
1232 const struct of_device_id *match;
1233 struct resource *res;
1234 int irq;
1235 int i;
1236 int error;
1237
1238 match = of_match_node(of_rockchip_thermal_match, np);
1239 if (!match)
1240 return -ENXIO;
1241
1242 irq = platform_get_irq(pdev, 0);
1243 if (irq < 0) {
1244 dev_err(&pdev->dev, "no irq resource?\n");
1245 return -EINVAL;
1246 }
1247
1248 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1249 GFP_KERNEL);
1250 if (!thermal)
1251 return -ENOMEM;
1252
1253 thermal->pdev = pdev;
1254
1255 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1256 if (!thermal->chip)
1257 return -EINVAL;
1258
1259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1261 if (IS_ERR(thermal->regs))
1262 return PTR_ERR(thermal->regs);
1263
1264 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1265 if (IS_ERR(thermal->reset)) {
1266 error = PTR_ERR(thermal->reset);
1267 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1268 return error;
1269 }
1270
1271 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1272 if (IS_ERR(thermal->clk)) {
1273 error = PTR_ERR(thermal->clk);
1274 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1275 return error;
1276 }
1277
1278 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1279 if (IS_ERR(thermal->pclk)) {
1280 error = PTR_ERR(thermal->pclk);
1281 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1282 error);
1283 return error;
1284 }
1285
1286 thermal->chip->control(thermal->regs, false);
1287
1288 error = clk_prepare_enable(thermal->clk);
1289 if (error) {
1290 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1291 error);
1292 return error;
1293 }
1294
1295 error = clk_prepare_enable(thermal->pclk);
1296 if (error) {
1297 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1298 goto err_disable_clk;
1299 }
1300
1301 rockchip_thermal_reset_controller(thermal->reset);
1302
1303 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1304 if (error) {
1305 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1306 error);
1307 goto err_disable_pclk;
1308 }
1309
1310 thermal->chip->initialize(thermal->grf, thermal->regs,
1311 thermal->tshut_polarity);
1312
1313 if (thermal->tshut_mode == TSHUT_MODE_GPIO) {
1314 thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
1315 if (IS_ERR(thermal->pinctrl)) {
1316 dev_err(&pdev->dev, "failed to find thermal pinctrl\n");
1317 return PTR_ERR(thermal->pinctrl);
1318 }
1319
1320 thermal->gpio_state = pinctrl_lookup_state(thermal->pinctrl,
1321 "gpio");
1322 if (IS_ERR_OR_NULL(thermal->gpio_state)) {
1323 dev_err(&pdev->dev, "failed to find thermal gpio state\n");
1324 return -EINVAL;
1325 }
1326
1327 thermal->otp_state = pinctrl_lookup_state(thermal->pinctrl,
1328 "otpout");
1329 if (IS_ERR_OR_NULL(thermal->otp_state)) {
1330 dev_err(&pdev->dev, "failed to find thermal otpout state\n");
1331 return -EINVAL;
1332 }
1333
1334 pinctrl_select_state(thermal->pinctrl, thermal->otp_state);
1335 }
1336
1337 for (i = 0; i < thermal->chip->chn_num; i++) {
1338 error = rockchip_thermal_register_sensor(pdev, thermal,
1339 &thermal->sensors[i],
1340 thermal->chip->chn_id[i]);
1341 if (error) {
1342 dev_err(&pdev->dev,
1343 "failed to register sensor[%d] : error = %d\n",
1344 i, error);
1345 goto err_disable_pclk;
1346 }
1347 }
1348
1349 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1350 &rockchip_thermal_alarm_irq_thread,
1351 IRQF_ONESHOT,
1352 "rockchip_thermal", thermal);
1353 if (error) {
1354 dev_err(&pdev->dev,
1355 "failed to request tsadc irq: %d\n", error);
1356 goto err_disable_pclk;
1357 }
1358
1359 thermal->chip->control(thermal->regs, true);
1360
1361 for (i = 0; i < thermal->chip->chn_num; i++)
1362 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1363
1364 platform_set_drvdata(pdev, thermal);
1365
1366 return 0;
1367
1368 err_disable_pclk:
1369 clk_disable_unprepare(thermal->pclk);
1370 err_disable_clk:
1371 clk_disable_unprepare(thermal->clk);
1372
1373 return error;
1374 }
1375
1376 static int rockchip_thermal_remove(struct platform_device *pdev)
1377 {
1378 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1379 int i;
1380
1381 for (i = 0; i < thermal->chip->chn_num; i++) {
1382 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1383
1384 rockchip_thermal_toggle_sensor(sensor, false);
1385 }
1386
1387 thermal->chip->control(thermal->regs, false);
1388
1389 clk_disable_unprepare(thermal->pclk);
1390 clk_disable_unprepare(thermal->clk);
1391
1392 return 0;
1393 }
1394
1395 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1396 {
1397 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1398 int i;
1399
1400 for (i = 0; i < thermal->chip->chn_num; i++)
1401 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1402
1403 thermal->chip->control(thermal->regs, false);
1404
1405 clk_disable(thermal->pclk);
1406 clk_disable(thermal->clk);
1407 if (thermal->tshut_mode == TSHUT_MODE_GPIO)
1408 pinctrl_select_state(thermal->pinctrl, thermal->gpio_state);
1409
1410 return 0;
1411 }
1412
1413 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1414 {
1415 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1416 int i;
1417 int error;
1418
1419 error = clk_enable(thermal->clk);
1420 if (error)
1421 return error;
1422
1423 error = clk_enable(thermal->pclk);
1424 if (error) {
1425 clk_disable(thermal->clk);
1426 return error;
1427 }
1428
1429 rockchip_thermal_reset_controller(thermal->reset);
1430
1431 thermal->chip->initialize(thermal->grf, thermal->regs,
1432 thermal->tshut_polarity);
1433
1434 for (i = 0; i < thermal->chip->chn_num; i++) {
1435 int id = thermal->sensors[i].id;
1436
1437 thermal->chip->set_tshut_mode(id, thermal->regs,
1438 thermal->tshut_mode);
1439
1440 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1441 id, thermal->regs,
1442 thermal->tshut_temp);
1443 if (error)
1444 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1445 __func__, thermal->tshut_temp, error);
1446 }
1447
1448 thermal->chip->control(thermal->regs, true);
1449
1450 for (i = 0; i < thermal->chip->chn_num; i++)
1451 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1452
1453 if (thermal->tshut_mode == TSHUT_MODE_GPIO)
1454 pinctrl_select_state(thermal->pinctrl, thermal->otp_state);
1455
1456 return 0;
1457 }
1458
1459 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1460 rockchip_thermal_suspend, rockchip_thermal_resume);
1461
1462 static struct platform_driver rockchip_thermal_driver = {
1463 .driver = {
1464 .name = "rockchip-thermal",
1465 .pm = &rockchip_thermal_pm_ops,
1466 .of_match_table = of_rockchip_thermal_match,
1467 },
1468 .probe = rockchip_thermal_probe,
1469 .remove = rockchip_thermal_remove,
1470 };
1471
1472 module_platform_driver(rockchip_thermal_driver);
1473
1474 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1475 MODULE_AUTHOR("Rockchip, Inc.");
1476 MODULE_LICENSE("GPL v2");
1477 MODULE_ALIAS("platform:rockchip-thermal");
Linux with added FPC-III support