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niu: panic on reset
[linux/fpc-iii.git] / drivers / net / cassini.c
blob83768df27806be9394fb087acac83ee6f87f08a0
1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
2 *
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
19 * 02111-1307, USA.
20 *
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
23 *
24 * The cassini chip has a number of features that distinguish it from
25 * the gem chip:
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
33 *
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
37 * on them.
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
40 * to make them happy.
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
46 * the page.
47 *
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
50 *
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl.
57 *
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
64 * instead.
65 *
66 * by default, the selective clear mask is set up to process rx packets.
67 */
68
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/types.h>
73 #include <linux/compiler.h>
74 #include <linux/slab.h>
75 #include <linux/delay.h>
76 #include <linux/init.h>
77 #include <linux/ioport.h>
78 #include <linux/pci.h>
79 #include <linux/mm.h>
80 #include <linux/highmem.h>
81 #include <linux/list.h>
82 #include <linux/dma-mapping.h>
83
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/crc32.h>
89 #include <linux/random.h>
90 #include <linux/mii.h>
91 #include <linux/ip.h>
92 #include <linux/tcp.h>
93 #include <linux/mutex.h>
94
95 #include <net/checksum.h>
96
97 #include <asm/atomic.h>
98 #include <asm/system.h>
99 #include <asm/io.h>
100 #include <asm/byteorder.h>
101 #include <asm/uaccess.h>
102
103 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
104 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define CAS_NCPUS num_online_cpus()
106
107 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
108 #define USE_NAPI
109 #define cas_skb_release(x) netif_receive_skb(x)
110 #else
111 #define cas_skb_release(x) netif_rx(x)
112 #endif
113
114 /* select which firmware to use */
115 #define USE_HP_WORKAROUND
116 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
117 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
118
119 #include "cassini.h"
120
121 #define USE_TX_COMPWB /* use completion writeback registers */
122 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
123 #define USE_RX_BLANK /* hw interrupt mitigation */
124 #undef USE_ENTROPY_DEV /* don't test for entropy device */
125
126 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
127 * also, we need to make cp->lock finer-grained.
128 */
129 #undef USE_PCI_INTB
130 #undef USE_PCI_INTC
131 #undef USE_PCI_INTD
132 #undef USE_QOS
133
134 #undef USE_VPD_DEBUG /* debug vpd information if defined */
135
136 /* rx processing options */
137 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
138 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
139 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
140 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
141 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
142
143 #define DRV_MODULE_NAME "cassini"
144 #define PFX DRV_MODULE_NAME ": "
145 #define DRV_MODULE_VERSION "1.6"
146 #define DRV_MODULE_RELDATE "21 May 2008"
147
148 #define CAS_DEF_MSG_ENABLE \
149 (NETIF_MSG_DRV | \
150 NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK | \
152 NETIF_MSG_TIMER | \
153 NETIF_MSG_IFDOWN | \
154 NETIF_MSG_IFUP | \
155 NETIF_MSG_RX_ERR | \
156 NETIF_MSG_TX_ERR)
157
158 /* length of time before we decide the hardware is borked,
159 * and dev->tx_timeout() should be called to fix the problem
160 */
161 #define CAS_TX_TIMEOUT (HZ)
162 #define CAS_LINK_TIMEOUT (22*HZ/10)
163 #define CAS_LINK_FAST_TIMEOUT (1)
164
165 /* timeout values for state changing. these specify the number
166 * of 10us delays to be used before giving up.
167 */
168 #define STOP_TRIES_PHY 1000
169 #define STOP_TRIES 5000
170
171 /* specify a minimum frame size to deal with some fifo issues
172 * max mtu == 2 * page size - ethernet header - 64 - swivel =
173 * 2 * page_size - 0x50
174 */
175 #define CAS_MIN_FRAME 97
176 #define CAS_1000MB_MIN_FRAME 255
177 #define CAS_MIN_MTU 60
178 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
179
180 #if 1
181 /*
182 * Eliminate these and use separate atomic counters for each, to
183 * avoid a race condition.
184 */
185 #else
186 #define CAS_RESET_MTU 1
187 #define CAS_RESET_ALL 2
188 #define CAS_RESET_SPARE 3
189 #endif
190
191 static char version[] __devinitdata =
192 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
193
194 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
195 static int link_mode;
196
197 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
198 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
199 MODULE_LICENSE("GPL");
200 module_param(cassini_debug, int, 0);
201 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
202 module_param(link_mode, int, 0);
203 MODULE_PARM_DESC(link_mode, "default link mode");
204
205 /*
206 * Work around for a PCS bug in which the link goes down due to the chip
207 * being confused and never showing a link status of "up."
208 */
209 #define DEFAULT_LINKDOWN_TIMEOUT 5
210 /*
211 * Value in seconds, for user input.
212 */
213 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
214 module_param(linkdown_timeout, int, 0);
215 MODULE_PARM_DESC(linkdown_timeout,
216 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
217
218 /*
219 * value in 'ticks' (units used by jiffies). Set when we init the
220 * module because 'HZ' in actually a function call on some flavors of
221 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
222 */
223 static int link_transition_timeout;
224
225
226
227 static u16 link_modes[] __devinitdata = {
228 BMCR_ANENABLE, /* 0 : autoneg */
229 0, /* 1 : 10bt half duplex */
230 BMCR_SPEED100, /* 2 : 100bt half duplex */
231 BMCR_FULLDPLX, /* 3 : 10bt full duplex */
232 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
233 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
234 };
235
236 static struct pci_device_id cas_pci_tbl[] __devinitdata = {
237 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
239 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
241 { 0, }
242 };
243
244 MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
245
246 static void cas_set_link_modes(struct cas *cp);
247
248 static inline void cas_lock_tx(struct cas *cp)
249 {
250 int i;
251
252 for (i = 0; i < N_TX_RINGS; i++)
253 spin_lock(&cp->tx_lock[i]);
254 }
255
256 static inline void cas_lock_all(struct cas *cp)
257 {
258 spin_lock_irq(&cp->lock);
259 cas_lock_tx(cp);
260 }
261
262 /* WTZ: QA was finding deadlock problems with the previous
263 * versions after long test runs with multiple cards per machine.
264 * See if replacing cas_lock_all with safer versions helps. The
265 * symptoms QA is reporting match those we'd expect if interrupts
266 * aren't being properly restored, and we fixed a previous deadlock
267 * with similar symptoms by using save/restore versions in other
268 * places.
269 */
270 #define cas_lock_all_save(cp, flags) \
271 do { \
272 struct cas *xxxcp = (cp); \
273 spin_lock_irqsave(&xxxcp->lock, flags); \
274 cas_lock_tx(xxxcp); \
275 } while (0)
276
277 static inline void cas_unlock_tx(struct cas *cp)
278 {
279 int i;
280
281 for (i = N_TX_RINGS; i > 0; i--)
282 spin_unlock(&cp->tx_lock[i - 1]);
283 }
284
285 static inline void cas_unlock_all(struct cas *cp)
286 {
287 cas_unlock_tx(cp);
288 spin_unlock_irq(&cp->lock);
289 }
290
291 #define cas_unlock_all_restore(cp, flags) \
292 do { \
293 struct cas *xxxcp = (cp); \
294 cas_unlock_tx(xxxcp); \
295 spin_unlock_irqrestore(&xxxcp->lock, flags); \
296 } while (0)
297
298 static void cas_disable_irq(struct cas *cp, const int ring)
299 {
300 /* Make sure we won't get any more interrupts */
301 if (ring == 0) {
302 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
303 return;
304 }
305
306 /* disable completion interrupts and selectively mask */
307 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
308 switch (ring) {
309 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
310 #ifdef USE_PCI_INTB
311 case 1:
312 #endif
313 #ifdef USE_PCI_INTC
314 case 2:
315 #endif
316 #ifdef USE_PCI_INTD
317 case 3:
318 #endif
319 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
320 cp->regs + REG_PLUS_INTRN_MASK(ring));
321 break;
322 #endif
323 default:
324 writel(INTRN_MASK_CLEAR_ALL, cp->regs +
325 REG_PLUS_INTRN_MASK(ring));
326 break;
327 }
328 }
329 }
330
331 static inline void cas_mask_intr(struct cas *cp)
332 {
333 int i;
334
335 for (i = 0; i < N_RX_COMP_RINGS; i++)
336 cas_disable_irq(cp, i);
337 }
338
339 static void cas_enable_irq(struct cas *cp, const int ring)
340 {
341 if (ring == 0) { /* all but TX_DONE */
342 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
343 return;
344 }
345
346 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
347 switch (ring) {
348 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
349 #ifdef USE_PCI_INTB
350 case 1:
351 #endif
352 #ifdef USE_PCI_INTC
353 case 2:
354 #endif
355 #ifdef USE_PCI_INTD
356 case 3:
357 #endif
358 writel(INTRN_MASK_RX_EN, cp->regs +
359 REG_PLUS_INTRN_MASK(ring));
360 break;
361 #endif
362 default:
363 break;
364 }
365 }
366 }
367
368 static inline void cas_unmask_intr(struct cas *cp)
369 {
370 int i;
371
372 for (i = 0; i < N_RX_COMP_RINGS; i++)
373 cas_enable_irq(cp, i);
374 }
375
376 static inline void cas_entropy_gather(struct cas *cp)
377 {
378 #ifdef USE_ENTROPY_DEV
379 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
380 return;
381
382 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
383 readl(cp->regs + REG_ENTROPY_IV),
384 sizeof(uint64_t)*8);
385 #endif
386 }
387
388 static inline void cas_entropy_reset(struct cas *cp)
389 {
390 #ifdef USE_ENTROPY_DEV
391 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
392 return;
393
394 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
395 cp->regs + REG_BIM_LOCAL_DEV_EN);
396 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
397 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
398
399 /* if we read back 0x0, we don't have an entropy device */
400 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
401 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
402 #endif
403 }
404
405 /* access to the phy. the following assumes that we've initialized the MIF to
406 * be in frame rather than bit-bang mode
407 */
408 static u16 cas_phy_read(struct cas *cp, int reg)
409 {
410 u32 cmd;
411 int limit = STOP_TRIES_PHY;
412
413 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
414 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
415 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
416 cmd |= MIF_FRAME_TURN_AROUND_MSB;
417 writel(cmd, cp->regs + REG_MIF_FRAME);
418
419 /* poll for completion */
420 while (limit-- > 0) {
421 udelay(10);
422 cmd = readl(cp->regs + REG_MIF_FRAME);
423 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
424 return (cmd & MIF_FRAME_DATA_MASK);
425 }
426 return 0xFFFF; /* -1 */
427 }
428
429 static int cas_phy_write(struct cas *cp, int reg, u16 val)
430 {
431 int limit = STOP_TRIES_PHY;
432 u32 cmd;
433
434 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
435 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
436 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
437 cmd |= MIF_FRAME_TURN_AROUND_MSB;
438 cmd |= val & MIF_FRAME_DATA_MASK;
439 writel(cmd, cp->regs + REG_MIF_FRAME);
440
441 /* poll for completion */
442 while (limit-- > 0) {
443 udelay(10);
444 cmd = readl(cp->regs + REG_MIF_FRAME);
445 if (cmd & MIF_FRAME_TURN_AROUND_LSB)
446 return 0;
447 }
448 return -1;
449 }
450
451 static void cas_phy_powerup(struct cas *cp)
452 {
453 u16 ctl = cas_phy_read(cp, MII_BMCR);
454
455 if ((ctl & BMCR_PDOWN) == 0)
456 return;
457 ctl &= ~BMCR_PDOWN;
458 cas_phy_write(cp, MII_BMCR, ctl);
459 }
460
461 static void cas_phy_powerdown(struct cas *cp)
462 {
463 u16 ctl = cas_phy_read(cp, MII_BMCR);
464
465 if (ctl & BMCR_PDOWN)
466 return;
467 ctl |= BMCR_PDOWN;
468 cas_phy_write(cp, MII_BMCR, ctl);
469 }
470
471 /* cp->lock held. note: the last put_page will free the buffer */
472 static int cas_page_free(struct cas *cp, cas_page_t *page)
473 {
474 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
475 PCI_DMA_FROMDEVICE);
476 __free_pages(page->buffer, cp->page_order);
477 kfree(page);
478 return 0;
479 }
480
481 #ifdef RX_COUNT_BUFFERS
482 #define RX_USED_ADD(x, y) ((x)->used += (y))
483 #define RX_USED_SET(x, y) ((x)->used = (y))
484 #else
485 #define RX_USED_ADD(x, y)
486 #define RX_USED_SET(x, y)
487 #endif
488
489 /* local page allocation routines for the receive buffers. jumbo pages
490 * require at least 8K contiguous and 8K aligned buffers.
491 */
492 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
493 {
494 cas_page_t *page;
495
496 page = kmalloc(sizeof(cas_page_t), flags);
497 if (!page)
498 return NULL;
499
500 INIT_LIST_HEAD(&page->list);
501 RX_USED_SET(page, 0);
502 page->buffer = alloc_pages(flags, cp->page_order);
503 if (!page->buffer)
504 goto page_err;
505 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
506 cp->page_size, PCI_DMA_FROMDEVICE);
507 return page;
508
509 page_err:
510 kfree(page);
511 return NULL;
512 }
513
514 /* initialize spare pool of rx buffers, but allocate during the open */
515 static void cas_spare_init(struct cas *cp)
516 {
517 spin_lock(&cp->rx_inuse_lock);
518 INIT_LIST_HEAD(&cp->rx_inuse_list);
519 spin_unlock(&cp->rx_inuse_lock);
520
521 spin_lock(&cp->rx_spare_lock);
522 INIT_LIST_HEAD(&cp->rx_spare_list);
523 cp->rx_spares_needed = RX_SPARE_COUNT;
524 spin_unlock(&cp->rx_spare_lock);
525 }
526
527 /* used on close. free all the spare buffers. */
528 static void cas_spare_free(struct cas *cp)
529 {
530 struct list_head list, *elem, *tmp;
531
532 /* free spare buffers */
533 INIT_LIST_HEAD(&list);
534 spin_lock(&cp->rx_spare_lock);
535 list_splice_init(&cp->rx_spare_list, &list);
536 spin_unlock(&cp->rx_spare_lock);
537 list_for_each_safe(elem, tmp, &list) {
538 cas_page_free(cp, list_entry(elem, cas_page_t, list));
539 }
540
541 INIT_LIST_HEAD(&list);
542 #if 1
543 /*
544 * Looks like Adrian had protected this with a different
545 * lock than used everywhere else to manipulate this list.
546 */
547 spin_lock(&cp->rx_inuse_lock);
548 list_splice_init(&cp->rx_inuse_list, &list);
549 spin_unlock(&cp->rx_inuse_lock);
550 #else
551 spin_lock(&cp->rx_spare_lock);
552 list_splice_init(&cp->rx_inuse_list, &list);
553 spin_unlock(&cp->rx_spare_lock);
554 #endif
555 list_for_each_safe(elem, tmp, &list) {
556 cas_page_free(cp, list_entry(elem, cas_page_t, list));
557 }
558 }
559
560 /* replenish spares if needed */
561 static void cas_spare_recover(struct cas *cp, const gfp_t flags)
562 {
563 struct list_head list, *elem, *tmp;
564 int needed, i;
565
566 /* check inuse list. if we don't need any more free buffers,
567 * just free it
568 */
569
570 /* make a local copy of the list */
571 INIT_LIST_HEAD(&list);
572 spin_lock(&cp->rx_inuse_lock);
573 list_splice_init(&cp->rx_inuse_list, &list);
574 spin_unlock(&cp->rx_inuse_lock);
575
576 list_for_each_safe(elem, tmp, &list) {
577 cas_page_t *page = list_entry(elem, cas_page_t, list);
578
579 if (page_count(page->buffer) > 1)
580 continue;
581
582 list_del(elem);
583 spin_lock(&cp->rx_spare_lock);
584 if (cp->rx_spares_needed > 0) {
585 list_add(elem, &cp->rx_spare_list);
586 cp->rx_spares_needed--;
587 spin_unlock(&cp->rx_spare_lock);
588 } else {
589 spin_unlock(&cp->rx_spare_lock);
590 cas_page_free(cp, page);
591 }
592 }
593
594 /* put any inuse buffers back on the list */
595 if (!list_empty(&list)) {
596 spin_lock(&cp->rx_inuse_lock);
597 list_splice(&list, &cp->rx_inuse_list);
598 spin_unlock(&cp->rx_inuse_lock);
599 }
600
601 spin_lock(&cp->rx_spare_lock);
602 needed = cp->rx_spares_needed;
603 spin_unlock(&cp->rx_spare_lock);
604 if (!needed)
605 return;
606
607 /* we still need spares, so try to allocate some */
608 INIT_LIST_HEAD(&list);
609 i = 0;
610 while (i < needed) {
611 cas_page_t *spare = cas_page_alloc(cp, flags);
612 if (!spare)
613 break;
614 list_add(&spare->list, &list);
615 i++;
616 }
617
618 spin_lock(&cp->rx_spare_lock);
619 list_splice(&list, &cp->rx_spare_list);
620 cp->rx_spares_needed -= i;
621 spin_unlock(&cp->rx_spare_lock);
622 }
623
624 /* pull a page from the list. */
625 static cas_page_t *cas_page_dequeue(struct cas *cp)
626 {
627 struct list_head *entry;
628 int recover;
629
630 spin_lock(&cp->rx_spare_lock);
631 if (list_empty(&cp->rx_spare_list)) {
632 /* try to do a quick recovery */
633 spin_unlock(&cp->rx_spare_lock);
634 cas_spare_recover(cp, GFP_ATOMIC);
635 spin_lock(&cp->rx_spare_lock);
636 if (list_empty(&cp->rx_spare_list)) {
637 if (netif_msg_rx_err(cp))
638 printk(KERN_ERR "%s: no spare buffers "
639 "available.\n", cp->dev->name);
640 spin_unlock(&cp->rx_spare_lock);
641 return NULL;
642 }
643 }
644
645 entry = cp->rx_spare_list.next;
646 list_del(entry);
647 recover = ++cp->rx_spares_needed;
648 spin_unlock(&cp->rx_spare_lock);
649
650 /* trigger the timer to do the recovery */
651 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
652 #if 1
653 atomic_inc(&cp->reset_task_pending);
654 atomic_inc(&cp->reset_task_pending_spare);
655 schedule_work(&cp->reset_task);
656 #else
657 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
658 schedule_work(&cp->reset_task);
659 #endif
660 }
661 return list_entry(entry, cas_page_t, list);
662 }
663
664
665 static void cas_mif_poll(struct cas *cp, const int enable)
666 {
667 u32 cfg;
668
669 cfg = readl(cp->regs + REG_MIF_CFG);
670 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
671
672 if (cp->phy_type & CAS_PHY_MII_MDIO1)
673 cfg |= MIF_CFG_PHY_SELECT;
674
675 /* poll and interrupt on link status change. */
676 if (enable) {
677 cfg |= MIF_CFG_POLL_EN;
678 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
679 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
680 }
681 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
682 cp->regs + REG_MIF_MASK);
683 writel(cfg, cp->regs + REG_MIF_CFG);
684 }
685
686 /* Must be invoked under cp->lock */
687 static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
688 {
689 u16 ctl;
690 #if 1
691 int lcntl;
692 int changed = 0;
693 int oldstate = cp->lstate;
694 int link_was_not_down = !(oldstate == link_down);
695 #endif
696 /* Setup link parameters */
697 if (!ep)
698 goto start_aneg;
699 lcntl = cp->link_cntl;
700 if (ep->autoneg == AUTONEG_ENABLE)
701 cp->link_cntl = BMCR_ANENABLE;
702 else {
703 cp->link_cntl = 0;
704 if (ep->speed == SPEED_100)
705 cp->link_cntl |= BMCR_SPEED100;
706 else if (ep->speed == SPEED_1000)
707 cp->link_cntl |= CAS_BMCR_SPEED1000;
708 if (ep->duplex == DUPLEX_FULL)
709 cp->link_cntl |= BMCR_FULLDPLX;
710 }
711 #if 1
712 changed = (lcntl != cp->link_cntl);
713 #endif
714 start_aneg:
715 if (cp->lstate == link_up) {
716 printk(KERN_INFO "%s: PCS link down.\n",
717 cp->dev->name);
718 } else {
719 if (changed) {
720 printk(KERN_INFO "%s: link configuration changed\n",
721 cp->dev->name);
722 }
723 }
724 cp->lstate = link_down;
725 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
726 if (!cp->hw_running)
727 return;
728 #if 1
729 /*
730 * WTZ: If the old state was link_up, we turn off the carrier
731 * to replicate everything we do elsewhere on a link-down
732 * event when we were already in a link-up state..
733 */
734 if (oldstate == link_up)
735 netif_carrier_off(cp->dev);
736 if (changed && link_was_not_down) {
737 /*
738 * WTZ: This branch will simply schedule a full reset after
739 * we explicitly changed link modes in an ioctl. See if this
740 * fixes the link-problems we were having for forced mode.
741 */
742 atomic_inc(&cp->reset_task_pending);
743 atomic_inc(&cp->reset_task_pending_all);
744 schedule_work(&cp->reset_task);
745 cp->timer_ticks = 0;
746 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
747 return;
748 }
749 #endif
750 if (cp->phy_type & CAS_PHY_SERDES) {
751 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
752
753 if (cp->link_cntl & BMCR_ANENABLE) {
754 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
755 cp->lstate = link_aneg;
756 } else {
757 if (cp->link_cntl & BMCR_FULLDPLX)
758 val |= PCS_MII_CTRL_DUPLEX;
759 val &= ~PCS_MII_AUTONEG_EN;
760 cp->lstate = link_force_ok;
761 }
762 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
763 writel(val, cp->regs + REG_PCS_MII_CTRL);
764
765 } else {
766 cas_mif_poll(cp, 0);
767 ctl = cas_phy_read(cp, MII_BMCR);
768 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
769 CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
770 ctl |= cp->link_cntl;
771 if (ctl & BMCR_ANENABLE) {
772 ctl |= BMCR_ANRESTART;
773 cp->lstate = link_aneg;
774 } else {
775 cp->lstate = link_force_ok;
776 }
777 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
778 cas_phy_write(cp, MII_BMCR, ctl);
779 cas_mif_poll(cp, 1);
780 }
781
782 cp->timer_ticks = 0;
783 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
784 }
785
786 /* Must be invoked under cp->lock. */
787 static int cas_reset_mii_phy(struct cas *cp)
788 {
789 int limit = STOP_TRIES_PHY;
790 u16 val;
791
792 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
793 udelay(100);
794 while (limit--) {
795 val = cas_phy_read(cp, MII_BMCR);
796 if ((val & BMCR_RESET) == 0)
797 break;
798 udelay(10);
799 }
800 return (limit <= 0);
801 }
802
803 static void cas_saturn_firmware_load(struct cas *cp)
804 {
805 cas_saturn_patch_t *patch = cas_saturn_patch;
806
807 cas_phy_powerdown(cp);
808
809 /* expanded memory access mode */
810 cas_phy_write(cp, DP83065_MII_MEM, 0x0);
811
812 /* pointer configuration for new firmware */
813 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
814 cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
815 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
816 cas_phy_write(cp, DP83065_MII_REGD, 0x82);
817 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
818 cas_phy_write(cp, DP83065_MII_REGD, 0x0);
819 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
820 cas_phy_write(cp, DP83065_MII_REGD, 0x39);
821
822 /* download new firmware */
823 cas_phy_write(cp, DP83065_MII_MEM, 0x1);
824 cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
825 while (patch->addr) {
826 cas_phy_write(cp, DP83065_MII_REGD, patch->val);
827 patch++;
828 }
829
830 /* enable firmware */
831 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
832 cas_phy_write(cp, DP83065_MII_REGD, 0x1);
833 }
834
835
836 /* phy initialization */
837 static void cas_phy_init(struct cas *cp)
838 {
839 u16 val;
840
841 /* if we're in MII/GMII mode, set up phy */
842 if (CAS_PHY_MII(cp->phy_type)) {
843 writel(PCS_DATAPATH_MODE_MII,
844 cp->regs + REG_PCS_DATAPATH_MODE);
845
846 cas_mif_poll(cp, 0);
847 cas_reset_mii_phy(cp); /* take out of isolate mode */
848
849 if (PHY_LUCENT_B0 == cp->phy_id) {
850 /* workaround link up/down issue with lucent */
851 cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
852 cas_phy_write(cp, MII_BMCR, 0x00f1);
853 cas_phy_write(cp, LUCENT_MII_REG, 0x0);
854
855 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
856 /* workarounds for broadcom phy */
857 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
858 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
859 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
860 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
861 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
862 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
863 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
864 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
865 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
866 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
867 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
868
869 } else if (PHY_BROADCOM_5411 == cp->phy_id) {
870 val = cas_phy_read(cp, BROADCOM_MII_REG4);
871 val = cas_phy_read(cp, BROADCOM_MII_REG4);
872 if (val & 0x0080) {
873 /* link workaround */
874 cas_phy_write(cp, BROADCOM_MII_REG4,
875 val & ~0x0080);
876 }
877
878 } else if (cp->cas_flags & CAS_FLAG_SATURN) {
879 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
880 SATURN_PCFG_FSI : 0x0,
881 cp->regs + REG_SATURN_PCFG);
882
883 /* load firmware to address 10Mbps auto-negotiation
884 * issue. NOTE: this will need to be changed if the
885 * default firmware gets fixed.
886 */
887 if (PHY_NS_DP83065 == cp->phy_id) {
888 cas_saturn_firmware_load(cp);
889 }
890 cas_phy_powerup(cp);
891 }
892
893 /* advertise capabilities */
894 val = cas_phy_read(cp, MII_BMCR);
895 val &= ~BMCR_ANENABLE;
896 cas_phy_write(cp, MII_BMCR, val);
897 udelay(10);
898
899 cas_phy_write(cp, MII_ADVERTISE,
900 cas_phy_read(cp, MII_ADVERTISE) |
901 (ADVERTISE_10HALF | ADVERTISE_10FULL |
902 ADVERTISE_100HALF | ADVERTISE_100FULL |
903 CAS_ADVERTISE_PAUSE |
904 CAS_ADVERTISE_ASYM_PAUSE));
905
906 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
907 /* make sure that we don't advertise half
908 * duplex to avoid a chip issue
909 */
910 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
911 val &= ~CAS_ADVERTISE_1000HALF;
912 val |= CAS_ADVERTISE_1000FULL;
913 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
914 }
915
916 } else {
917 /* reset pcs for serdes */
918 u32 val;
919 int limit;
920
921 writel(PCS_DATAPATH_MODE_SERDES,
922 cp->regs + REG_PCS_DATAPATH_MODE);
923
924 /* enable serdes pins on saturn */
925 if (cp->cas_flags & CAS_FLAG_SATURN)
926 writel(0, cp->regs + REG_SATURN_PCFG);
927
928 /* Reset PCS unit. */
929 val = readl(cp->regs + REG_PCS_MII_CTRL);
930 val |= PCS_MII_RESET;
931 writel(val, cp->regs + REG_PCS_MII_CTRL);
932
933 limit = STOP_TRIES;
934 while (limit-- > 0) {
935 udelay(10);
936 if ((readl(cp->regs + REG_PCS_MII_CTRL) &
937 PCS_MII_RESET) == 0)
938 break;
939 }
940 if (limit <= 0)
941 printk(KERN_WARNING "%s: PCS reset bit would not "
942 "clear [%08x].\n", cp->dev->name,
943 readl(cp->regs + REG_PCS_STATE_MACHINE));
944
945 /* Make sure PCS is disabled while changing advertisement
946 * configuration.
947 */
948 writel(0x0, cp->regs + REG_PCS_CFG);
949
950 /* Advertise all capabilities except half-duplex. */
951 val = readl(cp->regs + REG_PCS_MII_ADVERT);
952 val &= ~PCS_MII_ADVERT_HD;
953 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
954 PCS_MII_ADVERT_ASYM_PAUSE);
955 writel(val, cp->regs + REG_PCS_MII_ADVERT);
956
957 /* enable PCS */
958 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
959
960 /* pcs workaround: enable sync detect */
961 writel(PCS_SERDES_CTRL_SYNCD_EN,
962 cp->regs + REG_PCS_SERDES_CTRL);
963 }
964 }
965
966
967 static int cas_pcs_link_check(struct cas *cp)
968 {
969 u32 stat, state_machine;
970 int retval = 0;
971
972 /* The link status bit latches on zero, so you must
973 * read it twice in such a case to see a transition
974 * to the link being up.
975 */
976 stat = readl(cp->regs + REG_PCS_MII_STATUS);
977 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
978 stat = readl(cp->regs + REG_PCS_MII_STATUS);
979
980 /* The remote-fault indication is only valid
981 * when autoneg has completed.
982 */
983 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
984 PCS_MII_STATUS_REMOTE_FAULT)) ==
985 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
986 if (netif_msg_link(cp))
987 printk(KERN_INFO "%s: PCS RemoteFault\n",
988 cp->dev->name);
989 }
990
991 /* work around link detection issue by querying the PCS state
992 * machine directly.
993 */
994 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
995 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
996 stat &= ~PCS_MII_STATUS_LINK_STATUS;
997 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
998 stat |= PCS_MII_STATUS_LINK_STATUS;
999 }
1000
1001 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1002 if (cp->lstate != link_up) {
1003 if (cp->opened) {
1004 cp->lstate = link_up;
1005 cp->link_transition = LINK_TRANSITION_LINK_UP;
1006
1007 cas_set_link_modes(cp);
1008 netif_carrier_on(cp->dev);
1009 }
1010 }
1011 } else if (cp->lstate == link_up) {
1012 cp->lstate = link_down;
1013 if (link_transition_timeout != 0 &&
1014 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1015 !cp->link_transition_jiffies_valid) {
1016 /*
1017 * force a reset, as a workaround for the
1018 * link-failure problem. May want to move this to a
1019 * point a bit earlier in the sequence. If we had
1020 * generated a reset a short time ago, we'll wait for
1021 * the link timer to check the status until a
1022 * timer expires (link_transistion_jiffies_valid is
1023 * true when the timer is running.) Instead of using
1024 * a system timer, we just do a check whenever the
1025 * link timer is running - this clears the flag after
1026 * a suitable delay.
1027 */
1028 retval = 1;
1029 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1030 cp->link_transition_jiffies = jiffies;
1031 cp->link_transition_jiffies_valid = 1;
1032 } else {
1033 cp->link_transition = LINK_TRANSITION_ON_FAILURE;
1034 }
1035 netif_carrier_off(cp->dev);
1036 if (cp->opened && netif_msg_link(cp)) {
1037 printk(KERN_INFO "%s: PCS link down.\n",
1038 cp->dev->name);
1039 }
1040
1041 /* Cassini only: if you force a mode, there can be
1042 * sync problems on link down. to fix that, the following
1043 * things need to be checked:
1044 * 1) read serialink state register
1045 * 2) read pcs status register to verify link down.
1046 * 3) if link down and serial link == 0x03, then you need
1047 * to global reset the chip.
1048 */
1049 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
1050 /* should check to see if we're in a forced mode */
1051 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1052 if (stat == 0x03)
1053 return 1;
1054 }
1055 } else if (cp->lstate == link_down) {
1056 if (link_transition_timeout != 0 &&
1057 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
1058 !cp->link_transition_jiffies_valid) {
1059 /* force a reset, as a workaround for the
1060 * link-failure problem. May want to move
1061 * this to a point a bit earlier in the
1062 * sequence.
1063 */
1064 retval = 1;
1065 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
1066 cp->link_transition_jiffies = jiffies;
1067 cp->link_transition_jiffies_valid = 1;
1068 } else {
1069 cp->link_transition = LINK_TRANSITION_STILL_FAILED;
1070 }
1071 }
1072
1073 return retval;
1074 }
1075
1076 static int cas_pcs_interrupt(struct net_device *dev,
1077 struct cas *cp, u32 status)
1078 {
1079 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1080
1081 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1082 return 0;
1083 return cas_pcs_link_check(cp);
1084 }
1085
1086 static int cas_txmac_interrupt(struct net_device *dev,
1087 struct cas *cp, u32 status)
1088 {
1089 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
1090
1091 if (!txmac_stat)
1092 return 0;
1093
1094 if (netif_msg_intr(cp))
1095 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
1096 cp->dev->name, txmac_stat);
1097
1098 /* Defer timer expiration is quite normal,
1099 * don't even log the event.
1100 */
1101 if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
1102 !(txmac_stat & ~MAC_TX_DEFER_TIMER))
1103 return 0;
1104
1105 spin_lock(&cp->stat_lock[0]);
1106 if (txmac_stat & MAC_TX_UNDERRUN) {
1107 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
1108 dev->name);
1109 cp->net_stats[0].tx_fifo_errors++;
1110 }
1111
1112 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
1113 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
1114 dev->name);
1115 cp->net_stats[0].tx_errors++;
1116 }
1117
1118 /* The rest are all cases of one of the 16-bit TX
1119 * counters expiring.
1120 */
1121 if (txmac_stat & MAC_TX_COLL_NORMAL)
1122 cp->net_stats[0].collisions += 0x10000;
1123
1124 if (txmac_stat & MAC_TX_COLL_EXCESS) {
1125 cp->net_stats[0].tx_aborted_errors += 0x10000;
1126 cp->net_stats[0].collisions += 0x10000;
1127 }
1128
1129 if (txmac_stat & MAC_TX_COLL_LATE) {
1130 cp->net_stats[0].tx_aborted_errors += 0x10000;
1131 cp->net_stats[0].collisions += 0x10000;
1132 }
1133 spin_unlock(&cp->stat_lock[0]);
1134
1135 /* We do not keep track of MAC_TX_COLL_FIRST and
1136 * MAC_TX_PEAK_ATTEMPTS events.
1137 */
1138 return 0;
1139 }
1140
1141 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
1142 {
1143 cas_hp_inst_t *inst;
1144 u32 val;
1145 int i;
1146
1147 i = 0;
1148 while ((inst = firmware) && inst->note) {
1149 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
1150
1151 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1152 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1153 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1154
1155 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1156 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1157 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1158 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1159 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1160 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1162 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1163
1164 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1165 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1166 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1167 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1168 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1169 ++firmware;
1170 ++i;
1171 }
1172 }
1173
1174 static void cas_init_rx_dma(struct cas *cp)
1175 {
1176 u64 desc_dma = cp->block_dvma;
1177 u32 val;
1178 int i, size;
1179
1180 /* rx free descriptors */
1181 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1182 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1183 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1184 if ((N_RX_DESC_RINGS > 1) &&
1185 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
1186 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1187 writel(val, cp->regs + REG_RX_CFG);
1188
1189 val = (unsigned long) cp->init_rxds[0] -
1190 (unsigned long) cp->init_block;
1191 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1192 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1193 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
1194
1195 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1196 /* rx desc 2 is for IPSEC packets. however,
1197 * we don't it that for that purpose.
1198 */
1199 val = (unsigned long) cp->init_rxds[1] -
1200 (unsigned long) cp->init_block;
1201 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1202 writel((desc_dma + val) & 0xffffffff, cp->regs +
1203 REG_PLUS_RX_DB1_LOW);
1204 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
1205 REG_PLUS_RX_KICK1);
1206 }
1207
1208 /* rx completion registers */
1209 val = (unsigned long) cp->init_rxcs[0] -
1210 (unsigned long) cp->init_block;
1211 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1212 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1213
1214 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1215 /* rx comp 2-4 */
1216 for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
1217 val = (unsigned long) cp->init_rxcs[i] -
1218 (unsigned long) cp->init_block;
1219 writel((desc_dma + val) >> 32, cp->regs +
1220 REG_PLUS_RX_CBN_HI(i));
1221 writel((desc_dma + val) & 0xffffffff, cp->regs +
1222 REG_PLUS_RX_CBN_LOW(i));
1223 }
1224 }
1225
1226 /* read selective clear regs to prevent spurious interrupts
1227 * on reset because complete == kick.
1228 * selective clear set up to prevent interrupts on resets
1229 */
1230 readl(cp->regs + REG_INTR_STATUS_ALIAS);
1231 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
1232 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1233 for (i = 1; i < N_RX_COMP_RINGS; i++)
1234 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
1235
1236 /* 2 is different from 3 and 4 */
1237 if (N_RX_COMP_RINGS > 1)
1238 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
1239 cp->regs + REG_PLUS_ALIASN_CLEAR(1));
1240
1241 for (i = 2; i < N_RX_COMP_RINGS; i++)
1242 writel(INTR_RX_DONE_ALT,
1243 cp->regs + REG_PLUS_ALIASN_CLEAR(i));
1244 }
1245
1246 /* set up pause thresholds */
1247 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1248 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
1249 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1250 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
1251 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1252
1253 /* zero out dma reassembly buffers */
1254 for (i = 0; i < 64; i++) {
1255 writel(i, cp->regs + REG_RX_TABLE_ADDR);
1256 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
1257 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
1258 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
1259 }
1260
1261 /* make sure address register is 0 for normal operation */
1262 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
1263 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
1264
1265 /* interrupt mitigation */
1266 #ifdef USE_RX_BLANK
1267 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1268 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1269 writel(val, cp->regs + REG_RX_BLANK);
1270 #else
1271 writel(0x0, cp->regs + REG_RX_BLANK);
1272 #endif
1273
1274 /* interrupt generation as a function of low water marks for
1275 * free desc and completion entries. these are used to trigger
1276 * housekeeping for rx descs. we don't use the free interrupt
1277 * as it's not very useful
1278 */
1279 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1280 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1281 writel(val, cp->regs + REG_RX_AE_THRESH);
1282 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
1283 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1284 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1285 }
1286
1287 /* Random early detect registers. useful for congestion avoidance.
1288 * this should be tunable.
1289 */
1290 writel(0x0, cp->regs + REG_RX_RED);
1291
1292 /* receive page sizes. default == 2K (0x800) */
1293 val = 0;
1294 if (cp->page_size == 0x1000)
1295 val = 0x1;
1296 else if (cp->page_size == 0x2000)
1297 val = 0x2;
1298 else if (cp->page_size == 0x4000)
1299 val = 0x3;
1300
1301 /* round mtu + offset. constrain to page size. */
1302 size = cp->dev->mtu + 64;
1303 if (size > cp->page_size)
1304 size = cp->page_size;
1305
1306 if (size <= 0x400)
1307 i = 0x0;
1308 else if (size <= 0x800)
1309 i = 0x1;
1310 else if (size <= 0x1000)
1311 i = 0x2;
1312 else
1313 i = 0x3;
1314
1315 cp->mtu_stride = 1 << (i + 10);
1316 val = CAS_BASE(RX_PAGE_SIZE, val);
1317 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1318 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1319 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1320 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1321
1322 /* enable the header parser if desired */
1323 if (CAS_HP_FIRMWARE == cas_prog_null)
1324 return;
1325
1326 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1327 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1328 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1329 writel(val, cp->regs + REG_HP_CFG);
1330 }
1331
1332 static inline void cas_rxc_init(struct cas_rx_comp *rxc)
1333 {
1334 memset(rxc, 0, sizeof(*rxc));
1335 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
1336 }
1337
1338 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1339 * flipping is protected by the fact that the chip will not
1340 * hand back the same page index while it's being processed.
1341 */
1342 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
1343 {
1344 cas_page_t *page = cp->rx_pages[1][index];
1345 cas_page_t *new;
1346
1347 if (page_count(page->buffer) == 1)
1348 return page;
1349
1350 new = cas_page_dequeue(cp);
1351 if (new) {
1352 spin_lock(&cp->rx_inuse_lock);
1353 list_add(&page->list, &cp->rx_inuse_list);
1354 spin_unlock(&cp->rx_inuse_lock);
1355 }
1356 return new;
1357 }
1358
1359 /* this needs to be changed if we actually use the ENC RX DESC ring */
1360 static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
1361 const int index)
1362 {
1363 cas_page_t **page0 = cp->rx_pages[0];
1364 cas_page_t **page1 = cp->rx_pages[1];
1365
1366 /* swap if buffer is in use */
1367 if (page_count(page0[index]->buffer) > 1) {
1368 cas_page_t *new = cas_page_spare(cp, index);
1369 if (new) {
1370 page1[index] = page0[index];
1371 page0[index] = new;
1372 }
1373 }
1374 RX_USED_SET(page0[index], 0);
1375 return page0[index];
1376 }
1377
1378 static void cas_clean_rxds(struct cas *cp)
1379 {
1380 /* only clean ring 0 as ring 1 is used for spare buffers */
1381 struct cas_rx_desc *rxd = cp->init_rxds[0];
1382 int i, size;
1383
1384 /* release all rx flows */
1385 for (i = 0; i < N_RX_FLOWS; i++) {
1386 struct sk_buff *skb;
1387 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
1388 cas_skb_release(skb);
1389 }
1390 }
1391
1392 /* initialize descriptors */
1393 size = RX_DESC_RINGN_SIZE(0);
1394 for (i = 0; i < size; i++) {
1395 cas_page_t *page = cas_page_swap(cp, 0, i);
1396 rxd[i].buffer = cpu_to_le64(page->dma_addr);
1397 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
1398 CAS_BASE(RX_INDEX_RING, 0));
1399 }
1400
1401 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
1402 cp->rx_last[0] = 0;
1403 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
1404 }
1405
1406 static void cas_clean_rxcs(struct cas *cp)
1407 {
1408 int i, j;
1409
1410 /* take ownership of rx comp descriptors */
1411 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
1412 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
1413 for (i = 0; i < N_RX_COMP_RINGS; i++) {
1414 struct cas_rx_comp *rxc = cp->init_rxcs[i];
1415 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
1416 cas_rxc_init(rxc + j);
1417 }
1418 }
1419 }
1420
1421 #if 0
1422 /* When we get a RX fifo overflow, the RX unit is probably hung
1423 * so we do the following.
1424 *
1425 * If any part of the reset goes wrong, we return 1 and that causes the
1426 * whole chip to be reset.
1427 */
1428 static int cas_rxmac_reset(struct cas *cp)
1429 {
1430 struct net_device *dev = cp->dev;
1431 int limit;
1432 u32 val;
1433
1434 /* First, reset MAC RX. */
1435 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1436 for (limit = 0; limit < STOP_TRIES; limit++) {
1437 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
1438 break;
1439 udelay(10);
1440 }
1441 if (limit == STOP_TRIES) {
1442 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
1443 "chip.\n", dev->name);
1444 return 1;
1445 }
1446
1447 /* Second, disable RX DMA. */
1448 writel(0, cp->regs + REG_RX_CFG);
1449 for (limit = 0; limit < STOP_TRIES; limit++) {
1450 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
1451 break;
1452 udelay(10);
1453 }
1454 if (limit == STOP_TRIES) {
1455 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
1456 "chip.\n", dev->name);
1457 return 1;
1458 }
1459
1460 mdelay(5);
1461
1462 /* Execute RX reset command. */
1463 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1464 for (limit = 0; limit < STOP_TRIES; limit++) {
1465 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
1466 break;
1467 udelay(10);
1468 }
1469 if (limit == STOP_TRIES) {
1470 printk(KERN_ERR "%s: RX reset command will not execute, "
1471 "resetting whole chip.\n", dev->name);
1472 return 1;
1473 }
1474
1475 /* reset driver rx state */
1476 cas_clean_rxds(cp);
1477 cas_clean_rxcs(cp);
1478
1479 /* Now, reprogram the rest of RX unit. */
1480 cas_init_rx_dma(cp);
1481
1482 /* re-enable */
1483 val = readl(cp->regs + REG_RX_CFG);
1484 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1485 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1486 val = readl(cp->regs + REG_MAC_RX_CFG);
1487 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1488 return 0;
1489 }
1490 #endif
1491
1492 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
1493 u32 status)
1494 {
1495 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1496
1497 if (!stat)
1498 return 0;
1499
1500 if (netif_msg_intr(cp))
1501 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
1502 cp->dev->name, stat);
1503
1504 /* these are all rollovers */
1505 spin_lock(&cp->stat_lock[0]);
1506 if (stat & MAC_RX_ALIGN_ERR)
1507 cp->net_stats[0].rx_frame_errors += 0x10000;
1508
1509 if (stat & MAC_RX_CRC_ERR)
1510 cp->net_stats[0].rx_crc_errors += 0x10000;
1511
1512 if (stat & MAC_RX_LEN_ERR)
1513 cp->net_stats[0].rx_length_errors += 0x10000;
1514
1515 if (stat & MAC_RX_OVERFLOW) {
1516 cp->net_stats[0].rx_over_errors++;
1517 cp->net_stats[0].rx_fifo_errors++;
1518 }
1519
1520 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1521 * events.
1522 */
1523 spin_unlock(&cp->stat_lock[0]);
1524 return 0;
1525 }
1526
1527 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
1528 u32 status)
1529 {
1530 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1531
1532 if (!stat)
1533 return 0;
1534
1535 if (netif_msg_intr(cp))
1536 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
1537 cp->dev->name, stat);
1538
1539 /* This interrupt is just for pause frame and pause
1540 * tracking. It is useful for diagnostics and debug
1541 * but probably by default we will mask these events.
1542 */
1543 if (stat & MAC_CTRL_PAUSE_STATE)
1544 cp->pause_entered++;
1545
1546 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1547 cp->pause_last_time_recvd = (stat >> 16);
1548
1549 return 0;
1550 }
1551
1552
1553 /* Must be invoked under cp->lock. */
1554 static inline int cas_mdio_link_not_up(struct cas *cp)
1555 {
1556 u16 val;
1557
1558 switch (cp->lstate) {
1559 case link_force_ret:
1560 if (netif_msg_link(cp))
1561 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1562 " forced mode\n", cp->dev->name);
1563 cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
1564 cp->timer_ticks = 5;
1565 cp->lstate = link_force_ok;
1566 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1567 break;
1568
1569 case link_aneg:
1570 val = cas_phy_read(cp, MII_BMCR);
1571
1572 /* Try forced modes. we try things in the following order:
1573 * 1000 full -> 100 full/half -> 10 half
1574 */
1575 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1576 val |= BMCR_FULLDPLX;
1577 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1578 CAS_BMCR_SPEED1000 : BMCR_SPEED100;
1579 cas_phy_write(cp, MII_BMCR, val);
1580 cp->timer_ticks = 5;
1581 cp->lstate = link_force_try;
1582 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1583 break;
1584
1585 case link_force_try:
1586 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1587 val = cas_phy_read(cp, MII_BMCR);
1588 cp->timer_ticks = 5;
1589 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1590 val &= ~CAS_BMCR_SPEED1000;
1591 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1592 cas_phy_write(cp, MII_BMCR, val);
1593 break;
1594 }
1595
1596 if (val & BMCR_SPEED100) {
1597 if (val & BMCR_FULLDPLX) /* fd failed */
1598 val &= ~BMCR_FULLDPLX;
1599 else { /* 100Mbps failed */
1600 val &= ~BMCR_SPEED100;
1601 }
1602 cas_phy_write(cp, MII_BMCR, val);
1603 break;
1604 }
1605 default:
1606 break;
1607 }
1608 return 0;
1609 }
1610
1611
1612 /* must be invoked with cp->lock held */
1613 static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
1614 {
1615 int restart;
1616
1617 if (bmsr & BMSR_LSTATUS) {
1618 /* Ok, here we got a link. If we had it due to a forced
1619 * fallback, and we were configured for autoneg, we
1620 * retry a short autoneg pass. If you know your hub is
1621 * broken, use ethtool ;)
1622 */
1623 if ((cp->lstate == link_force_try) &&
1624 (cp->link_cntl & BMCR_ANENABLE)) {
1625 cp->lstate = link_force_ret;
1626 cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
1627 cas_mif_poll(cp, 0);
1628 cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
1629 cp->timer_ticks = 5;
1630 if (cp->opened && netif_msg_link(cp))
1631 printk(KERN_INFO "%s: Got link after fallback, retrying"
1632 " autoneg once...\n", cp->dev->name);
1633 cas_phy_write(cp, MII_BMCR,
1634 cp->link_fcntl | BMCR_ANENABLE |
1635 BMCR_ANRESTART);
1636 cas_mif_poll(cp, 1);
1637
1638 } else if (cp->lstate != link_up) {
1639 cp->lstate = link_up;
1640 cp->link_transition = LINK_TRANSITION_LINK_UP;
1641
1642 if (cp->opened) {
1643 cas_set_link_modes(cp);
1644 netif_carrier_on(cp->dev);
1645 }
1646 }
1647 return 0;
1648 }
1649
1650 /* link not up. if the link was previously up, we restart the
1651 * whole process
1652 */
1653 restart = 0;
1654 if (cp->lstate == link_up) {
1655 cp->lstate = link_down;
1656 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
1657
1658 netif_carrier_off(cp->dev);
1659 if (cp->opened && netif_msg_link(cp))
1660 printk(KERN_INFO "%s: Link down\n",
1661 cp->dev->name);
1662 restart = 1;
1663
1664 } else if (++cp->timer_ticks > 10)
1665 cas_mdio_link_not_up(cp);
1666
1667 return restart;
1668 }
1669
1670 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
1671 u32 status)
1672 {
1673 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1674 u16 bmsr;
1675
1676 /* check for a link change */
1677 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1678 return 0;
1679
1680 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1681 return cas_mii_link_check(cp, bmsr);
1682 }
1683
1684 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
1685 u32 status)
1686 {
1687 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1688
1689 if (!stat)
1690 return 0;
1691
1692 printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
1693 readl(cp->regs + REG_BIM_DIAG));
1694
1695 /* cassini+ has this reserved */
1696 if ((stat & PCI_ERR_BADACK) &&
1697 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
1698 printk("<No ACK64# during ABS64 cycle> ");
1699
1700 if (stat & PCI_ERR_DTRTO)
1701 printk("<Delayed transaction timeout> ");
1702 if (stat & PCI_ERR_OTHER)
1703 printk("<other> ");
1704 if (stat & PCI_ERR_BIM_DMA_WRITE)
1705 printk("<BIM DMA 0 write req> ");
1706 if (stat & PCI_ERR_BIM_DMA_READ)
1707 printk("<BIM DMA 0 read req> ");
1708 printk("\n");
1709
1710 if (stat & PCI_ERR_OTHER) {
1711 u16 cfg;
1712
1713 /* Interrogate PCI config space for the
1714 * true cause.
1715 */
1716 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
1717 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
1718 dev->name, cfg);
1719 if (cfg & PCI_STATUS_PARITY)
1720 printk(KERN_ERR "%s: PCI parity error detected.\n",
1721 dev->name);
1722 if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
1723 printk(KERN_ERR "%s: PCI target abort.\n",
1724 dev->name);
1725 if (cfg & PCI_STATUS_REC_TARGET_ABORT)
1726 printk(KERN_ERR "%s: PCI master acks target abort.\n",
1727 dev->name);
1728 if (cfg & PCI_STATUS_REC_MASTER_ABORT)
1729 printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
1730 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
1731 printk(KERN_ERR "%s: PCI system error SERR#.\n",
1732 dev->name);
1733 if (cfg & PCI_STATUS_DETECTED_PARITY)
1734 printk(KERN_ERR "%s: PCI parity error.\n",
1735 dev->name);
1736
1737 /* Write the error bits back to clear them. */
1738 cfg &= (PCI_STATUS_PARITY |
1739 PCI_STATUS_SIG_TARGET_ABORT |
1740 PCI_STATUS_REC_TARGET_ABORT |
1741 PCI_STATUS_REC_MASTER_ABORT |
1742 PCI_STATUS_SIG_SYSTEM_ERROR |
1743 PCI_STATUS_DETECTED_PARITY);
1744 pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
1745 }
1746
1747 /* For all PCI errors, we should reset the chip. */
1748 return 1;
1749 }
1750
1751 /* All non-normal interrupt conditions get serviced here.
1752 * Returns non-zero if we should just exit the interrupt
1753 * handler right now (ie. if we reset the card which invalidates
1754 * all of the other original irq status bits).
1755 */
1756 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
1757 u32 status)
1758 {
1759 if (status & INTR_RX_TAG_ERROR) {
1760 /* corrupt RX tag framing */
1761 if (netif_msg_rx_err(cp))
1762 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
1763 cp->dev->name);
1764 spin_lock(&cp->stat_lock[0]);
1765 cp->net_stats[0].rx_errors++;
1766 spin_unlock(&cp->stat_lock[0]);
1767 goto do_reset;
1768 }
1769
1770 if (status & INTR_RX_LEN_MISMATCH) {
1771 /* length mismatch. */
1772 if (netif_msg_rx_err(cp))
1773 printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
1774 cp->dev->name);
1775 spin_lock(&cp->stat_lock[0]);
1776 cp->net_stats[0].rx_errors++;
1777 spin_unlock(&cp->stat_lock[0]);
1778 goto do_reset;
1779 }
1780
1781 if (status & INTR_PCS_STATUS) {
1782 if (cas_pcs_interrupt(dev, cp, status))
1783 goto do_reset;
1784 }
1785
1786 if (status & INTR_TX_MAC_STATUS) {
1787 if (cas_txmac_interrupt(dev, cp, status))
1788 goto do_reset;
1789 }
1790
1791 if (status & INTR_RX_MAC_STATUS) {
1792 if (cas_rxmac_interrupt(dev, cp, status))
1793 goto do_reset;
1794 }
1795
1796 if (status & INTR_MAC_CTRL_STATUS) {
1797 if (cas_mac_interrupt(dev, cp, status))
1798 goto do_reset;
1799 }
1800
1801 if (status & INTR_MIF_STATUS) {
1802 if (cas_mif_interrupt(dev, cp, status))
1803 goto do_reset;
1804 }
1805
1806 if (status & INTR_PCI_ERROR_STATUS) {
1807 if (cas_pci_interrupt(dev, cp, status))
1808 goto do_reset;
1809 }
1810 return 0;
1811
1812 do_reset:
1813 #if 1
1814 atomic_inc(&cp->reset_task_pending);
1815 atomic_inc(&cp->reset_task_pending_all);
1816 printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
1817 dev->name, status);
1818 schedule_work(&cp->reset_task);
1819 #else
1820 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
1821 printk(KERN_ERR "reset called in cas_abnormal_irq\n");
1822 schedule_work(&cp->reset_task);
1823 #endif
1824 return 1;
1825 }
1826
1827 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1828 * determining whether to do a netif_stop/wakeup
1829 */
1830 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1831 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1832 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
1833 const int len)
1834 {
1835 unsigned long off = addr + len;
1836
1837 if (CAS_TABORT(cp) == 1)
1838 return 0;
1839 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
1840 return 0;
1841 return TX_TARGET_ABORT_LEN;
1842 }
1843
1844 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
1845 {
1846 struct cas_tx_desc *txds;
1847 struct sk_buff **skbs;
1848 struct net_device *dev = cp->dev;
1849 int entry, count;
1850
1851 spin_lock(&cp->tx_lock[ring]);
1852 txds = cp->init_txds[ring];
1853 skbs = cp->tx_skbs[ring];
1854 entry = cp->tx_old[ring];
1855
1856 count = TX_BUFF_COUNT(ring, entry, limit);
1857 while (entry != limit) {
1858 struct sk_buff *skb = skbs[entry];
1859 dma_addr_t daddr;
1860 u32 dlen;
1861 int frag;
1862
1863 if (!skb) {
1864 /* this should never occur */
1865 entry = TX_DESC_NEXT(ring, entry);
1866 continue;
1867 }
1868
1869 /* however, we might get only a partial skb release. */
1870 count -= skb_shinfo(skb)->nr_frags +
1871 + cp->tx_tiny_use[ring][entry].nbufs + 1;
1872 if (count < 0)
1873 break;
1874
1875 if (netif_msg_tx_done(cp))
1876 printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
1877 cp->dev->name, ring, entry);
1878
1879 skbs[entry] = NULL;
1880 cp->tx_tiny_use[ring][entry].nbufs = 0;
1881
1882 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1883 struct cas_tx_desc *txd = txds + entry;
1884
1885 daddr = le64_to_cpu(txd->buffer);
1886 dlen = CAS_VAL(TX_DESC_BUFLEN,
1887 le64_to_cpu(txd->control));
1888 pci_unmap_page(cp->pdev, daddr, dlen,
1889 PCI_DMA_TODEVICE);
1890 entry = TX_DESC_NEXT(ring, entry);
1891
1892 /* tiny buffer may follow */
1893 if (cp->tx_tiny_use[ring][entry].used) {
1894 cp->tx_tiny_use[ring][entry].used = 0;
1895 entry = TX_DESC_NEXT(ring, entry);
1896 }
1897 }
1898
1899 spin_lock(&cp->stat_lock[ring]);
1900 cp->net_stats[ring].tx_packets++;
1901 cp->net_stats[ring].tx_bytes += skb->len;
1902 spin_unlock(&cp->stat_lock[ring]);
1903 dev_kfree_skb_irq(skb);
1904 }
1905 cp->tx_old[ring] = entry;
1906
1907 /* this is wrong for multiple tx rings. the net device needs
1908 * multiple queues for this to do the right thing. we wait
1909 * for 2*packets to be available when using tiny buffers
1910 */
1911 if (netif_queue_stopped(dev) &&
1912 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
1913 netif_wake_queue(dev);
1914 spin_unlock(&cp->tx_lock[ring]);
1915 }
1916
1917 static void cas_tx(struct net_device *dev, struct cas *cp,
1918 u32 status)
1919 {
1920 int limit, ring;
1921 #ifdef USE_TX_COMPWB
1922 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
1923 #endif
1924 if (netif_msg_intr(cp))
1925 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
1926 cp->dev->name, status, (unsigned long long)compwb);
1927 /* process all the rings */
1928 for (ring = 0; ring < N_TX_RINGS; ring++) {
1929 #ifdef USE_TX_COMPWB
1930 /* use the completion writeback registers */
1931 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
1932 CAS_VAL(TX_COMPWB_LSB, compwb);
1933 compwb = TX_COMPWB_NEXT(compwb);
1934 #else
1935 limit = readl(cp->regs + REG_TX_COMPN(ring));
1936 #endif
1937 if (cp->tx_old[ring] != limit)
1938 cas_tx_ringN(cp, ring, limit);
1939 }
1940 }
1941
1942
1943 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
1944 int entry, const u64 *words,
1945 struct sk_buff **skbref)
1946 {
1947 int dlen, hlen, len, i, alloclen;
1948 int off, swivel = RX_SWIVEL_OFF_VAL;
1949 struct cas_page *page;
1950 struct sk_buff *skb;
1951 void *addr, *crcaddr;
1952 __sum16 csum;
1953 char *p;
1954
1955 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
1956 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
1957 len = hlen + dlen;
1958
1959 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
1960 alloclen = len;
1961 else
1962 alloclen = max(hlen, RX_COPY_MIN);
1963
1964 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
1965 if (skb == NULL)
1966 return -1;
1967
1968 *skbref = skb;
1969 skb_reserve(skb, swivel);
1970
1971 p = skb->data;
1972 addr = crcaddr = NULL;
1973 if (hlen) { /* always copy header pages */
1974 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
1975 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
1976 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
1977 swivel;
1978
1979 i = hlen;
1980 if (!dlen) /* attach FCS */
1981 i += cp->crc_size;
1982 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
1983 PCI_DMA_FROMDEVICE);
1984 addr = cas_page_map(page->buffer);
1985 memcpy(p, addr + off, i);
1986 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
1987 PCI_DMA_FROMDEVICE);
1988 cas_page_unmap(addr);
1989 RX_USED_ADD(page, 0x100);
1990 p += hlen;
1991 swivel = 0;
1992 }
1993
1994
1995 if (alloclen < (hlen + dlen)) {
1996 skb_frag_t *frag = skb_shinfo(skb)->frags;
1997
1998 /* normal or jumbo packets. we use frags */
1999 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2000 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2001 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2002
2003 hlen = min(cp->page_size - off, dlen);
2004 if (hlen < 0) {
2005 if (netif_msg_rx_err(cp)) {
2006 printk(KERN_DEBUG "%s: rx page overflow: "
2007 "%d\n", cp->dev->name, hlen);
2008 }
2009 dev_kfree_skb_irq(skb);
2010 return -1;
2011 }
2012 i = hlen;
2013 if (i == dlen) /* attach FCS */
2014 i += cp->crc_size;
2015 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2016 PCI_DMA_FROMDEVICE);
2017
2018 /* make sure we always copy a header */
2019 swivel = 0;
2020 if (p == (char *) skb->data) { /* not split */
2021 addr = cas_page_map(page->buffer);
2022 memcpy(p, addr + off, RX_COPY_MIN);
2023 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2024 PCI_DMA_FROMDEVICE);
2025 cas_page_unmap(addr);
2026 off += RX_COPY_MIN;
2027 swivel = RX_COPY_MIN;
2028 RX_USED_ADD(page, cp->mtu_stride);
2029 } else {
2030 RX_USED_ADD(page, hlen);
2031 }
2032 skb_put(skb, alloclen);
2033
2034 skb_shinfo(skb)->nr_frags++;
2035 skb->data_len += hlen - swivel;
2036 skb->truesize += hlen - swivel;
2037 skb->len += hlen - swivel;
2038
2039 get_page(page->buffer);
2040 frag->page = page->buffer;
2041 frag->page_offset = off;
2042 frag->size = hlen - swivel;
2043
2044 /* any more data? */
2045 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2046 hlen = dlen;
2047 off = 0;
2048
2049 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2050 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2051 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2052 hlen + cp->crc_size,
2053 PCI_DMA_FROMDEVICE);
2054 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2055 hlen + cp->crc_size,
2056 PCI_DMA_FROMDEVICE);
2057
2058 skb_shinfo(skb)->nr_frags++;
2059 skb->data_len += hlen;
2060 skb->len += hlen;
2061 frag++;
2062
2063 get_page(page->buffer);
2064 frag->page = page->buffer;
2065 frag->page_offset = 0;
2066 frag->size = hlen;
2067 RX_USED_ADD(page, hlen + cp->crc_size);
2068 }
2069
2070 if (cp->crc_size) {
2071 addr = cas_page_map(page->buffer);
2072 crcaddr = addr + off + hlen;
2073 }
2074
2075 } else {
2076 /* copying packet */
2077 if (!dlen)
2078 goto end_copy_pkt;
2079
2080 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2081 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2082 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
2083 hlen = min(cp->page_size - off, dlen);
2084 if (hlen < 0) {
2085 if (netif_msg_rx_err(cp)) {
2086 printk(KERN_DEBUG "%s: rx page overflow: "
2087 "%d\n", cp->dev->name, hlen);
2088 }
2089 dev_kfree_skb_irq(skb);
2090 return -1;
2091 }
2092 i = hlen;
2093 if (i == dlen) /* attach FCS */
2094 i += cp->crc_size;
2095 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
2096 PCI_DMA_FROMDEVICE);
2097 addr = cas_page_map(page->buffer);
2098 memcpy(p, addr + off, i);
2099 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
2100 PCI_DMA_FROMDEVICE);
2101 cas_page_unmap(addr);
2102 if (p == (char *) skb->data) /* not split */
2103 RX_USED_ADD(page, cp->mtu_stride);
2104 else
2105 RX_USED_ADD(page, i);
2106
2107 /* any more data? */
2108 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
2109 p += hlen;
2110 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2111 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
2112 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
2113 dlen + cp->crc_size,
2114 PCI_DMA_FROMDEVICE);
2115 addr = cas_page_map(page->buffer);
2116 memcpy(p, addr, dlen + cp->crc_size);
2117 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
2118 dlen + cp->crc_size,
2119 PCI_DMA_FROMDEVICE);
2120 cas_page_unmap(addr);
2121 RX_USED_ADD(page, dlen + cp->crc_size);
2122 }
2123 end_copy_pkt:
2124 if (cp->crc_size) {
2125 addr = NULL;
2126 crcaddr = skb->data + alloclen;
2127 }
2128 skb_put(skb, alloclen);
2129 }
2130
2131 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
2132 if (cp->crc_size) {
2133 /* checksum includes FCS. strip it out. */
2134 csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
2135 csum_unfold(csum)));
2136 if (addr)
2137 cas_page_unmap(addr);
2138 }
2139 skb->protocol = eth_type_trans(skb, cp->dev);
2140 if (skb->protocol == htons(ETH_P_IP)) {
2141 skb->csum = csum_unfold(~csum);
2142 skb->ip_summed = CHECKSUM_COMPLETE;
2143 } else
2144 skb->ip_summed = CHECKSUM_NONE;
2145 return len;
2146 }
2147
2148
2149 /* we can handle up to 64 rx flows at a time. we do the same thing
2150 * as nonreassm except that we batch up the buffers.
2151 * NOTE: we currently just treat each flow as a bunch of packets that
2152 * we pass up. a better way would be to coalesce the packets
2153 * into a jumbo packet. to do that, we need to do the following:
2154 * 1) the first packet will have a clean split between header and
2155 * data. save both.
2156 * 2) each time the next flow packet comes in, extend the
2157 * data length and merge the checksums.
2158 * 3) on flow release, fix up the header.
2159 * 4) make sure the higher layer doesn't care.
2160 * because packets get coalesced, we shouldn't run into fragment count
2161 * issues.
2162 */
2163 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
2164 struct sk_buff *skb)
2165 {
2166 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
2167 struct sk_buff_head *flow = &cp->rx_flows[flowid];
2168
2169 /* this is protected at a higher layer, so no need to
2170 * do any additional locking here. stick the buffer
2171 * at the end.
2172 */
2173 __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
2174 if (words[0] & RX_COMP1_RELEASE_FLOW) {
2175 while ((skb = __skb_dequeue(flow))) {
2176 cas_skb_release(skb);
2177 }
2178 }
2179 }
2180
2181 /* put rx descriptor back on ring. if a buffer is in use by a higher
2182 * layer, this will need to put in a replacement.
2183 */
2184 static void cas_post_page(struct cas *cp, const int ring, const int index)
2185 {
2186 cas_page_t *new;
2187 int entry;
2188
2189 entry = cp->rx_old[ring];
2190
2191 new = cas_page_swap(cp, ring, index);
2192 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
2193 cp->init_rxds[ring][entry].index =
2194 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
2195 CAS_BASE(RX_INDEX_RING, ring));
2196
2197 entry = RX_DESC_ENTRY(ring, entry + 1);
2198 cp->rx_old[ring] = entry;
2199
2200 if (entry % 4)
2201 return;
2202
2203 if (ring == 0)
2204 writel(entry, cp->regs + REG_RX_KICK);
2205 else if ((N_RX_DESC_RINGS > 1) &&
2206 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2207 writel(entry, cp->regs + REG_PLUS_RX_KICK1);
2208 }
2209
2210
2211 /* only when things are bad */
2212 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
2213 {
2214 unsigned int entry, last, count, released;
2215 int cluster;
2216 cas_page_t **page = cp->rx_pages[ring];
2217
2218 entry = cp->rx_old[ring];
2219
2220 if (netif_msg_intr(cp))
2221 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
2222 cp->dev->name, ring, entry);
2223
2224 cluster = -1;
2225 count = entry & 0x3;
2226 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
2227 released = 0;
2228 while (entry != last) {
2229 /* make a new buffer if it's still in use */
2230 if (page_count(page[entry]->buffer) > 1) {
2231 cas_page_t *new = cas_page_dequeue(cp);
2232 if (!new) {
2233 /* let the timer know that we need to
2234 * do this again
2235 */
2236 cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
2237 if (!timer_pending(&cp->link_timer))
2238 mod_timer(&cp->link_timer, jiffies +
2239 CAS_LINK_FAST_TIMEOUT);
2240 cp->rx_old[ring] = entry;
2241 cp->rx_last[ring] = num ? num - released : 0;
2242 return -ENOMEM;
2243 }
2244 spin_lock(&cp->rx_inuse_lock);
2245 list_add(&page[entry]->list, &cp->rx_inuse_list);
2246 spin_unlock(&cp->rx_inuse_lock);
2247 cp->init_rxds[ring][entry].buffer =
2248 cpu_to_le64(new->dma_addr);
2249 page[entry] = new;
2250
2251 }
2252
2253 if (++count == 4) {
2254 cluster = entry;
2255 count = 0;
2256 }
2257 released++;
2258 entry = RX_DESC_ENTRY(ring, entry + 1);
2259 }
2260 cp->rx_old[ring] = entry;
2261
2262 if (cluster < 0)
2263 return 0;
2264
2265 if (ring == 0)
2266 writel(cluster, cp->regs + REG_RX_KICK);
2267 else if ((N_RX_DESC_RINGS > 1) &&
2268 (cp->cas_flags & CAS_FLAG_REG_PLUS))
2269 writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
2270 return 0;
2271 }
2272
2273
2274 /* process a completion ring. packets are set up in three basic ways:
2275 * small packets: should be copied header + data in single buffer.
2276 * large packets: header and data in a single buffer.
2277 * split packets: header in a separate buffer from data.
2278 * data may be in multiple pages. data may be > 256
2279 * bytes but in a single page.
2280 *
2281 * NOTE: RX page posting is done in this routine as well. while there's
2282 * the capability of using multiple RX completion rings, it isn't
2283 * really worthwhile due to the fact that the page posting will
2284 * force serialization on the single descriptor ring.
2285 */
2286 static int cas_rx_ringN(struct cas *cp, int ring, int budget)
2287 {
2288 struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
2289 int entry, drops;
2290 int npackets = 0;
2291
2292 if (netif_msg_intr(cp))
2293 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
2294 cp->dev->name, ring,
2295 readl(cp->regs + REG_RX_COMP_HEAD),
2296 cp->rx_new[ring]);
2297
2298 entry = cp->rx_new[ring];
2299 drops = 0;
2300 while (1) {
2301 struct cas_rx_comp *rxc = rxcs + entry;
2302 struct sk_buff *skb;
2303 int type, len;
2304 u64 words[4];
2305 int i, dring;
2306
2307 words[0] = le64_to_cpu(rxc->word1);
2308 words[1] = le64_to_cpu(rxc->word2);
2309 words[2] = le64_to_cpu(rxc->word3);
2310 words[3] = le64_to_cpu(rxc->word4);
2311
2312 /* don't touch if still owned by hw */
2313 type = CAS_VAL(RX_COMP1_TYPE, words[0]);
2314 if (type == 0)
2315 break;
2316
2317 /* hw hasn't cleared the zero bit yet */
2318 if (words[3] & RX_COMP4_ZERO) {
2319 break;
2320 }
2321
2322 /* get info on the packet */
2323 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
2324 spin_lock(&cp->stat_lock[ring]);
2325 cp->net_stats[ring].rx_errors++;
2326 if (words[3] & RX_COMP4_LEN_MISMATCH)
2327 cp->net_stats[ring].rx_length_errors++;
2328 if (words[3] & RX_COMP4_BAD)
2329 cp->net_stats[ring].rx_crc_errors++;
2330 spin_unlock(&cp->stat_lock[ring]);
2331
2332 /* We'll just return it to Cassini. */
2333 drop_it:
2334 spin_lock(&cp->stat_lock[ring]);
2335 ++cp->net_stats[ring].rx_dropped;
2336 spin_unlock(&cp->stat_lock[ring]);
2337 goto next;
2338 }
2339
2340 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
2341 if (len < 0) {
2342 ++drops;
2343 goto drop_it;
2344 }
2345
2346 /* see if it's a flow re-assembly or not. the driver
2347 * itself handles release back up.
2348 */
2349 if (RX_DONT_BATCH || (type == 0x2)) {
2350 /* non-reassm: these always get released */
2351 cas_skb_release(skb);
2352 } else {
2353 cas_rx_flow_pkt(cp, words, skb);
2354 }
2355
2356 spin_lock(&cp->stat_lock[ring]);
2357 cp->net_stats[ring].rx_packets++;
2358 cp->net_stats[ring].rx_bytes += len;
2359 spin_unlock(&cp->stat_lock[ring]);
2360 cp->dev->last_rx = jiffies;
2361
2362 next:
2363 npackets++;
2364
2365 /* should it be released? */
2366 if (words[0] & RX_COMP1_RELEASE_HDR) {
2367 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
2368 dring = CAS_VAL(RX_INDEX_RING, i);
2369 i = CAS_VAL(RX_INDEX_NUM, i);
2370 cas_post_page(cp, dring, i);
2371 }
2372
2373 if (words[0] & RX_COMP1_RELEASE_DATA) {
2374 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
2375 dring = CAS_VAL(RX_INDEX_RING, i);
2376 i = CAS_VAL(RX_INDEX_NUM, i);
2377 cas_post_page(cp, dring, i);
2378 }
2379
2380 if (words[0] & RX_COMP1_RELEASE_NEXT) {
2381 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
2382 dring = CAS_VAL(RX_INDEX_RING, i);
2383 i = CAS_VAL(RX_INDEX_NUM, i);
2384 cas_post_page(cp, dring, i);
2385 }
2386
2387 /* skip to the next entry */
2388 entry = RX_COMP_ENTRY(ring, entry + 1 +
2389 CAS_VAL(RX_COMP1_SKIP, words[0]));
2390 #ifdef USE_NAPI
2391 if (budget && (npackets >= budget))
2392 break;
2393 #endif
2394 }
2395 cp->rx_new[ring] = entry;
2396
2397 if (drops)
2398 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
2399 cp->dev->name);
2400 return npackets;
2401 }
2402
2403
2404 /* put completion entries back on the ring */
2405 static void cas_post_rxcs_ringN(struct net_device *dev,
2406 struct cas *cp, int ring)
2407 {
2408 struct cas_rx_comp *rxc = cp->init_rxcs[ring];
2409 int last, entry;
2410
2411 last = cp->rx_cur[ring];
2412 entry = cp->rx_new[ring];
2413 if (netif_msg_intr(cp))
2414 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
2415 dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
2416 entry);
2417
2418 /* zero and re-mark descriptors */
2419 while (last != entry) {
2420 cas_rxc_init(rxc + last);
2421 last = RX_COMP_ENTRY(ring, last + 1);
2422 }
2423 cp->rx_cur[ring] = last;
2424
2425 if (ring == 0)
2426 writel(last, cp->regs + REG_RX_COMP_TAIL);
2427 else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
2428 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
2429 }
2430
2431
2432
2433 /* cassini can use all four PCI interrupts for the completion ring.
2434 * rings 3 and 4 are identical
2435 */
2436 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2437 static inline void cas_handle_irqN(struct net_device *dev,
2438 struct cas *cp, const u32 status,
2439 const int ring)
2440 {
2441 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
2442 cas_post_rxcs_ringN(dev, cp, ring);
2443 }
2444
2445 static irqreturn_t cas_interruptN(int irq, void *dev_id)
2446 {
2447 struct net_device *dev = dev_id;
2448 struct cas *cp = netdev_priv(dev);
2449 unsigned long flags;
2450 int ring;
2451 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
2452
2453 /* check for shared irq */
2454 if (status == 0)
2455 return IRQ_NONE;
2456
2457 ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
2458 spin_lock_irqsave(&cp->lock, flags);
2459 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2460 #ifdef USE_NAPI
2461 cas_mask_intr(cp);
2462 netif_rx_schedule(dev, &cp->napi);
2463 #else
2464 cas_rx_ringN(cp, ring, 0);
2465 #endif
2466 status &= ~INTR_RX_DONE_ALT;
2467 }
2468
2469 if (status)
2470 cas_handle_irqN(dev, cp, status, ring);
2471 spin_unlock_irqrestore(&cp->lock, flags);
2472 return IRQ_HANDLED;
2473 }
2474 #endif
2475
2476 #ifdef USE_PCI_INTB
2477 /* everything but rx packets */
2478 static inline void cas_handle_irq1(struct cas *cp, const u32 status)
2479 {
2480 if (status & INTR_RX_BUF_UNAVAIL_1) {
2481 /* Frame arrived, no free RX buffers available.
2482 * NOTE: we can get this on a link transition. */
2483 cas_post_rxds_ringN(cp, 1, 0);
2484 spin_lock(&cp->stat_lock[1]);
2485 cp->net_stats[1].rx_dropped++;
2486 spin_unlock(&cp->stat_lock[1]);
2487 }
2488
2489 if (status & INTR_RX_BUF_AE_1)
2490 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
2491 RX_AE_FREEN_VAL(1));
2492
2493 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2494 cas_post_rxcs_ringN(cp, 1);
2495 }
2496
2497 /* ring 2 handles a few more events than 3 and 4 */
2498 static irqreturn_t cas_interrupt1(int irq, void *dev_id)
2499 {
2500 struct net_device *dev = dev_id;
2501 struct cas *cp = netdev_priv(dev);
2502 unsigned long flags;
2503 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2504
2505 /* check for shared interrupt */
2506 if (status == 0)
2507 return IRQ_NONE;
2508
2509 spin_lock_irqsave(&cp->lock, flags);
2510 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
2511 #ifdef USE_NAPI
2512 cas_mask_intr(cp);
2513 netif_rx_schedule(dev, &cp->napi);
2514 #else
2515 cas_rx_ringN(cp, 1, 0);
2516 #endif
2517 status &= ~INTR_RX_DONE_ALT;
2518 }
2519 if (status)
2520 cas_handle_irq1(cp, status);
2521 spin_unlock_irqrestore(&cp->lock, flags);
2522 return IRQ_HANDLED;
2523 }
2524 #endif
2525
2526 static inline void cas_handle_irq(struct net_device *dev,
2527 struct cas *cp, const u32 status)
2528 {
2529 /* housekeeping interrupts */
2530 if (status & INTR_ERROR_MASK)
2531 cas_abnormal_irq(dev, cp, status);
2532
2533 if (status & INTR_RX_BUF_UNAVAIL) {
2534 /* Frame arrived, no free RX buffers available.
2535 * NOTE: we can get this on a link transition.
2536 */
2537 cas_post_rxds_ringN(cp, 0, 0);
2538 spin_lock(&cp->stat_lock[0]);
2539 cp->net_stats[0].rx_dropped++;
2540 spin_unlock(&cp->stat_lock[0]);
2541 } else if (status & INTR_RX_BUF_AE) {
2542 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
2543 RX_AE_FREEN_VAL(0));
2544 }
2545
2546 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
2547 cas_post_rxcs_ringN(dev, cp, 0);
2548 }
2549
2550 static irqreturn_t cas_interrupt(int irq, void *dev_id)
2551 {
2552 struct net_device *dev = dev_id;
2553 struct cas *cp = netdev_priv(dev);
2554 unsigned long flags;
2555 u32 status = readl(cp->regs + REG_INTR_STATUS);
2556
2557 if (status == 0)
2558 return IRQ_NONE;
2559
2560 spin_lock_irqsave(&cp->lock, flags);
2561 if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
2562 cas_tx(dev, cp, status);
2563 status &= ~(INTR_TX_ALL | INTR_TX_INTME);
2564 }
2565
2566 if (status & INTR_RX_DONE) {
2567 #ifdef USE_NAPI
2568 cas_mask_intr(cp);
2569 netif_rx_schedule(dev, &cp->napi);
2570 #else
2571 cas_rx_ringN(cp, 0, 0);
2572 #endif
2573 status &= ~INTR_RX_DONE;
2574 }
2575
2576 if (status)
2577 cas_handle_irq(dev, cp, status);
2578 spin_unlock_irqrestore(&cp->lock, flags);
2579 return IRQ_HANDLED;
2580 }
2581
2582
2583 #ifdef USE_NAPI
2584 static int cas_poll(struct napi_struct *napi, int budget)
2585 {
2586 struct cas *cp = container_of(napi, struct cas, napi);
2587 struct net_device *dev = cp->dev;
2588 int i, enable_intr, credits;
2589 u32 status = readl(cp->regs + REG_INTR_STATUS);
2590 unsigned long flags;
2591
2592 spin_lock_irqsave(&cp->lock, flags);
2593 cas_tx(dev, cp, status);
2594 spin_unlock_irqrestore(&cp->lock, flags);
2595
2596 /* NAPI rx packets. we spread the credits across all of the
2597 * rxc rings
2598 *
2599 * to make sure we're fair with the work we loop through each
2600 * ring N_RX_COMP_RING times with a request of
2601 * budget / N_RX_COMP_RINGS
2602 */
2603 enable_intr = 1;
2604 credits = 0;
2605 for (i = 0; i < N_RX_COMP_RINGS; i++) {
2606 int j;
2607 for (j = 0; j < N_RX_COMP_RINGS; j++) {
2608 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS);
2609 if (credits >= budget) {
2610 enable_intr = 0;
2611 goto rx_comp;
2612 }
2613 }
2614 }
2615
2616 rx_comp:
2617 /* final rx completion */
2618 spin_lock_irqsave(&cp->lock, flags);
2619 if (status)
2620 cas_handle_irq(dev, cp, status);
2621
2622 #ifdef USE_PCI_INTB
2623 if (N_RX_COMP_RINGS > 1) {
2624 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
2625 if (status)
2626 cas_handle_irq1(dev, cp, status);
2627 }
2628 #endif
2629
2630 #ifdef USE_PCI_INTC
2631 if (N_RX_COMP_RINGS > 2) {
2632 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
2633 if (status)
2634 cas_handle_irqN(dev, cp, status, 2);
2635 }
2636 #endif
2637
2638 #ifdef USE_PCI_INTD
2639 if (N_RX_COMP_RINGS > 3) {
2640 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
2641 if (status)
2642 cas_handle_irqN(dev, cp, status, 3);
2643 }
2644 #endif
2645 spin_unlock_irqrestore(&cp->lock, flags);
2646 if (enable_intr) {
2647 netif_rx_complete(dev, napi);
2648 cas_unmask_intr(cp);
2649 }
2650 return credits;
2651 }
2652 #endif
2653
2654 #ifdef CONFIG_NET_POLL_CONTROLLER
2655 static void cas_netpoll(struct net_device *dev)
2656 {
2657 struct cas *cp = netdev_priv(dev);
2658
2659 cas_disable_irq(cp, 0);
2660 cas_interrupt(cp->pdev->irq, dev);
2661 cas_enable_irq(cp, 0);
2662
2663 #ifdef USE_PCI_INTB
2664 if (N_RX_COMP_RINGS > 1) {
2665 /* cas_interrupt1(); */
2666 }
2667 #endif
2668 #ifdef USE_PCI_INTC
2669 if (N_RX_COMP_RINGS > 2) {
2670 /* cas_interruptN(); */
2671 }
2672 #endif
2673 #ifdef USE_PCI_INTD
2674 if (N_RX_COMP_RINGS > 3) {
2675 /* cas_interruptN(); */
2676 }
2677 #endif
2678 }
2679 #endif
2680
2681 static void cas_tx_timeout(struct net_device *dev)
2682 {
2683 struct cas *cp = netdev_priv(dev);
2684
2685 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2686 if (!cp->hw_running) {
2687 printk("%s: hrm.. hw not running!\n", dev->name);
2688 return;
2689 }
2690
2691 printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
2692 dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
2693
2694 printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
2695 dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
2696
2697 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
2698 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2699 dev->name,
2700 readl(cp->regs + REG_TX_CFG),
2701 readl(cp->regs + REG_MAC_TX_STATUS),
2702 readl(cp->regs + REG_MAC_TX_CFG),
2703 readl(cp->regs + REG_TX_FIFO_PKT_CNT),
2704 readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
2705 readl(cp->regs + REG_TX_FIFO_READ_PTR),
2706 readl(cp->regs + REG_TX_SM_1),
2707 readl(cp->regs + REG_TX_SM_2));
2708
2709 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
2710 dev->name,
2711 readl(cp->regs + REG_RX_CFG),
2712 readl(cp->regs + REG_MAC_RX_STATUS),
2713 readl(cp->regs + REG_MAC_RX_CFG));
2714
2715 printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2716 dev->name,
2717 readl(cp->regs + REG_HP_STATE_MACHINE),
2718 readl(cp->regs + REG_HP_STATUS0),
2719 readl(cp->regs + REG_HP_STATUS1),
2720 readl(cp->regs + REG_HP_STATUS2));
2721
2722 #if 1
2723 atomic_inc(&cp->reset_task_pending);
2724 atomic_inc(&cp->reset_task_pending_all);
2725 schedule_work(&cp->reset_task);
2726 #else
2727 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
2728 schedule_work(&cp->reset_task);
2729 #endif
2730 }
2731
2732 static inline int cas_intme(int ring, int entry)
2733 {
2734 /* Algorithm: IRQ every 1/2 of descriptors. */
2735 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
2736 return 1;
2737 return 0;
2738 }
2739
2740
2741 static void cas_write_txd(struct cas *cp, int ring, int entry,
2742 dma_addr_t mapping, int len, u64 ctrl, int last)
2743 {
2744 struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
2745
2746 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
2747 if (cas_intme(ring, entry))
2748 ctrl |= TX_DESC_INTME;
2749 if (last)
2750 ctrl |= TX_DESC_EOF;
2751 txd->control = cpu_to_le64(ctrl);
2752 txd->buffer = cpu_to_le64(mapping);
2753 }
2754
2755 static inline void *tx_tiny_buf(struct cas *cp, const int ring,
2756 const int entry)
2757 {
2758 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
2759 }
2760
2761 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
2762 const int entry, const int tentry)
2763 {
2764 cp->tx_tiny_use[ring][tentry].nbufs++;
2765 cp->tx_tiny_use[ring][entry].used = 1;
2766 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
2767 }
2768
2769 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
2770 struct sk_buff *skb)
2771 {
2772 struct net_device *dev = cp->dev;
2773 int entry, nr_frags, frag, tabort, tentry;
2774 dma_addr_t mapping;
2775 unsigned long flags;
2776 u64 ctrl;
2777 u32 len;
2778
2779 spin_lock_irqsave(&cp->tx_lock[ring], flags);
2780
2781 /* This is a hard error, log it. */
2782 if (TX_BUFFS_AVAIL(cp, ring) <=
2783 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
2784 netif_stop_queue(dev);
2785 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2786 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
2787 "queue awake!\n", dev->name);
2788 return 1;
2789 }
2790
2791 ctrl = 0;
2792 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2793 const u64 csum_start_off = skb_transport_offset(skb);
2794 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
2795
2796 ctrl = TX_DESC_CSUM_EN |
2797 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
2798 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
2799 }
2800
2801 entry = cp->tx_new[ring];
2802 cp->tx_skbs[ring][entry] = skb;
2803
2804 nr_frags = skb_shinfo(skb)->nr_frags;
2805 len = skb_headlen(skb);
2806 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
2807 offset_in_page(skb->data), len,
2808 PCI_DMA_TODEVICE);
2809
2810 tentry = entry;
2811 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
2812 if (unlikely(tabort)) {
2813 /* NOTE: len is always > tabort */
2814 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2815 ctrl | TX_DESC_SOF, 0);
2816 entry = TX_DESC_NEXT(ring, entry);
2817
2818 skb_copy_from_linear_data_offset(skb, len - tabort,
2819 tx_tiny_buf(cp, ring, entry), tabort);
2820 mapping = tx_tiny_map(cp, ring, entry, tentry);
2821 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
2822 (nr_frags == 0));
2823 } else {
2824 cas_write_txd(cp, ring, entry, mapping, len, ctrl |
2825 TX_DESC_SOF, (nr_frags == 0));
2826 }
2827 entry = TX_DESC_NEXT(ring, entry);
2828
2829 for (frag = 0; frag < nr_frags; frag++) {
2830 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
2831
2832 len = fragp->size;
2833 mapping = pci_map_page(cp->pdev, fragp->page,
2834 fragp->page_offset, len,
2835 PCI_DMA_TODEVICE);
2836
2837 tabort = cas_calc_tabort(cp, fragp->page_offset, len);
2838 if (unlikely(tabort)) {
2839 void *addr;
2840
2841 /* NOTE: len is always > tabort */
2842 cas_write_txd(cp, ring, entry, mapping, len - tabort,
2843 ctrl, 0);
2844 entry = TX_DESC_NEXT(ring, entry);
2845
2846 addr = cas_page_map(fragp->page);
2847 memcpy(tx_tiny_buf(cp, ring, entry),
2848 addr + fragp->page_offset + len - tabort,
2849 tabort);
2850 cas_page_unmap(addr);
2851 mapping = tx_tiny_map(cp, ring, entry, tentry);
2852 len = tabort;
2853 }
2854
2855 cas_write_txd(cp, ring, entry, mapping, len, ctrl,
2856 (frag + 1 == nr_frags));
2857 entry = TX_DESC_NEXT(ring, entry);
2858 }
2859
2860 cp->tx_new[ring] = entry;
2861 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
2862 netif_stop_queue(dev);
2863
2864 if (netif_msg_tx_queued(cp))
2865 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
2866 "avail %d\n",
2867 dev->name, ring, entry, skb->len,
2868 TX_BUFFS_AVAIL(cp, ring));
2869 writel(entry, cp->regs + REG_TX_KICKN(ring));
2870 spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
2871 return 0;
2872 }
2873
2874 static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
2875 {
2876 struct cas *cp = netdev_priv(dev);
2877
2878 /* this is only used as a load-balancing hint, so it doesn't
2879 * need to be SMP safe
2880 */
2881 static int ring;
2882
2883 if (skb_padto(skb, cp->min_frame_size))
2884 return 0;
2885
2886 /* XXX: we need some higher-level QoS hooks to steer packets to
2887 * individual queues.
2888 */
2889 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
2890 return 1;
2891 dev->trans_start = jiffies;
2892 return 0;
2893 }
2894
2895 static void cas_init_tx_dma(struct cas *cp)
2896 {
2897 u64 desc_dma = cp->block_dvma;
2898 unsigned long off;
2899 u32 val;
2900 int i;
2901
2902 /* set up tx completion writeback registers. must be 8-byte aligned */
2903 #ifdef USE_TX_COMPWB
2904 off = offsetof(struct cas_init_block, tx_compwb);
2905 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
2906 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
2907 #endif
2908
2909 /* enable completion writebacks, enable paced mode,
2910 * disable read pipe, and disable pre-interrupt compwbs
2911 */
2912 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2913 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
2914 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
2915 TX_CFG_INTR_COMPWB_DIS;
2916
2917 /* write out tx ring info and tx desc bases */
2918 for (i = 0; i < MAX_TX_RINGS; i++) {
2919 off = (unsigned long) cp->init_txds[i] -
2920 (unsigned long) cp->init_block;
2921
2922 val |= CAS_TX_RINGN_BASE(i);
2923 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
2924 writel((desc_dma + off) & 0xffffffff, cp->regs +
2925 REG_TX_DBN_LOW(i));
2926 /* don't zero out the kick register here as the system
2927 * will wedge
2928 */
2929 }
2930 writel(val, cp->regs + REG_TX_CFG);
2931
2932 /* program max burst sizes. these numbers should be different
2933 * if doing QoS.
2934 */
2935 #ifdef USE_QOS
2936 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2937 writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
2938 writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
2939 writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
2940 #else
2941 writel(0x800, cp->regs + REG_TX_MAXBURST_0);
2942 writel(0x800, cp->regs + REG_TX_MAXBURST_1);
2943 writel(0x800, cp->regs + REG_TX_MAXBURST_2);
2944 writel(0x800, cp->regs + REG_TX_MAXBURST_3);
2945 #endif
2946 }
2947
2948 /* Must be invoked under cp->lock. */
2949 static inline void cas_init_dma(struct cas *cp)
2950 {
2951 cas_init_tx_dma(cp);
2952 cas_init_rx_dma(cp);
2953 }
2954
2955 /* Must be invoked under cp->lock. */
2956 static u32 cas_setup_multicast(struct cas *cp)
2957 {
2958 u32 rxcfg = 0;
2959 int i;
2960
2961 if (cp->dev->flags & IFF_PROMISC) {
2962 rxcfg |= MAC_RX_CFG_PROMISC_EN;
2963
2964 } else if (cp->dev->flags & IFF_ALLMULTI) {
2965 for (i=0; i < 16; i++)
2966 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
2967 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
2968
2969 } else {
2970 u16 hash_table[16];
2971 u32 crc;
2972 struct dev_mc_list *dmi = cp->dev->mc_list;
2973 int i;
2974
2975 /* use the alternate mac address registers for the
2976 * first 15 multicast addresses
2977 */
2978 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
2979 if (!dmi) {
2980 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
2981 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
2982 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
2983 continue;
2984 }
2985 writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
2986 cp->regs + REG_MAC_ADDRN(i*3 + 0));
2987 writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
2988 cp->regs + REG_MAC_ADDRN(i*3 + 1));
2989 writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
2990 cp->regs + REG_MAC_ADDRN(i*3 + 2));
2991 dmi = dmi->next;
2992 }
2993
2994 /* use hw hash table for the next series of
2995 * multicast addresses
2996 */
2997 memset(hash_table, 0, sizeof(hash_table));
2998 while (dmi) {
2999 crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
3000 crc >>= 24;
3001 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
3002 dmi = dmi->next;
3003 }
3004 for (i=0; i < 16; i++)
3005 writel(hash_table[i], cp->regs +
3006 REG_MAC_HASH_TABLEN(i));
3007 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
3008 }
3009
3010 return rxcfg;
3011 }
3012
3013 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3014 static void cas_clear_mac_err(struct cas *cp)
3015 {
3016 writel(0, cp->regs + REG_MAC_COLL_NORMAL);
3017 writel(0, cp->regs + REG_MAC_COLL_FIRST);
3018 writel(0, cp->regs + REG_MAC_COLL_EXCESS);
3019 writel(0, cp->regs + REG_MAC_COLL_LATE);
3020 writel(0, cp->regs + REG_MAC_TIMER_DEFER);
3021 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
3022 writel(0, cp->regs + REG_MAC_RECV_FRAME);
3023 writel(0, cp->regs + REG_MAC_LEN_ERR);
3024 writel(0, cp->regs + REG_MAC_ALIGN_ERR);
3025 writel(0, cp->regs + REG_MAC_FCS_ERR);
3026 writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
3027 }
3028
3029
3030 static void cas_mac_reset(struct cas *cp)
3031 {
3032 int i;
3033
3034 /* do both TX and RX reset */
3035 writel(0x1, cp->regs + REG_MAC_TX_RESET);
3036 writel(0x1, cp->regs + REG_MAC_RX_RESET);
3037
3038 /* wait for TX */
3039 i = STOP_TRIES;
3040 while (i-- > 0) {
3041 if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
3042 break;
3043 udelay(10);
3044 }
3045
3046 /* wait for RX */
3047 i = STOP_TRIES;
3048 while (i-- > 0) {
3049 if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
3050 break;
3051 udelay(10);
3052 }
3053
3054 if (readl(cp->regs + REG_MAC_TX_RESET) |
3055 readl(cp->regs + REG_MAC_RX_RESET))
3056 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3057 cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
3058 readl(cp->regs + REG_MAC_RX_RESET),
3059 readl(cp->regs + REG_MAC_STATE_MACHINE));
3060 }
3061
3062
3063 /* Must be invoked under cp->lock. */
3064 static void cas_init_mac(struct cas *cp)
3065 {
3066 unsigned char *e = &cp->dev->dev_addr[0];
3067 int i;
3068 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3069 u32 rxcfg;
3070 #endif
3071 cas_mac_reset(cp);
3072
3073 /* setup core arbitration weight register */
3074 writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
3075
3076 /* XXX Use pci_dma_burst_advice() */
3077 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3078 /* set the infinite burst register for chips that don't have
3079 * pci issues.
3080 */
3081 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
3082 writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
3083 #endif
3084
3085 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
3086
3087 writel(0x00, cp->regs + REG_MAC_IPG0);
3088 writel(0x08, cp->regs + REG_MAC_IPG1);
3089 writel(0x04, cp->regs + REG_MAC_IPG2);
3090
3091 /* change later for 802.3z */
3092 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3093
3094 /* min frame + FCS */
3095 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
3096
3097 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3098 * specify the maximum frame size to prevent RX tag errors on
3099 * oversized frames.
3100 */
3101 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
3102 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
3103 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
3104 cp->regs + REG_MAC_FRAMESIZE_MAX);
3105
3106 /* NOTE: crc_size is used as a surrogate for half-duplex.
3107 * workaround saturn half-duplex issue by increasing preamble
3108 * size to 65 bytes.
3109 */
3110 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
3111 writel(0x41, cp->regs + REG_MAC_PA_SIZE);
3112 else
3113 writel(0x07, cp->regs + REG_MAC_PA_SIZE);
3114 writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
3115 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
3116 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
3117
3118 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
3119
3120 writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
3121 writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
3122 writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
3123 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
3124 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
3125
3126 /* setup mac address in perfect filter array */
3127 for (i = 0; i < 45; i++)
3128 writel(0x0, cp->regs + REG_MAC_ADDRN(i));
3129
3130 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
3131 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
3132 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
3133
3134 writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
3135 writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
3136 writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
3137
3138 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3139 cp->mac_rx_cfg = cas_setup_multicast(cp);
3140 #else
3141 /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3142 * a writel does not seem to be necessary because Cassini
3143 * seems to preserve the configuration when we do the reset.
3144 * If the chip is in trouble, though, it is not clear if we
3145 * can really count on this behavior. cas_set_multicast uses
3146 * spin_lock_irqsave, but we are called only in cas_init_hw and
3147 * cas_init_hw is protected by cas_lock_all, which calls
3148 * spin_lock_irq (so it doesn't need to save the flags, and
3149 * we should be OK for the writel, as that is the only
3150 * difference).
3151 */
3152 cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
3153 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
3154 #endif
3155 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3156 cas_clear_mac_err(cp);
3157 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3158
3159 /* Setup MAC interrupts. We want to get all of the interesting
3160 * counter expiration events, but we do not want to hear about
3161 * normal rx/tx as the DMA engine tells us that.
3162 */
3163 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
3164 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
3165
3166 /* Don't enable even the PAUSE interrupts for now, we
3167 * make no use of those events other than to record them.
3168 */
3169 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
3170 }
3171
3172 /* Must be invoked under cp->lock. */
3173 static void cas_init_pause_thresholds(struct cas *cp)
3174 {
3175 /* Calculate pause thresholds. Setting the OFF threshold to the
3176 * full RX fifo size effectively disables PAUSE generation
3177 */
3178 if (cp->rx_fifo_size <= (2 * 1024)) {
3179 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
3180 } else {
3181 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
3182 if (max_frame * 3 > cp->rx_fifo_size) {
3183 cp->rx_pause_off = 7104;
3184 cp->rx_pause_on = 960;
3185 } else {
3186 int off = (cp->rx_fifo_size - (max_frame * 2));
3187 int on = off - max_frame;
3188 cp->rx_pause_off = off;
3189 cp->rx_pause_on = on;
3190 }
3191 }
3192 }
3193
3194 static int cas_vpd_match(const void __iomem *p, const char *str)
3195 {
3196 int len = strlen(str) + 1;
3197 int i;
3198
3199 for (i = 0; i < len; i++) {
3200 if (readb(p + i) != str[i])
3201 return 0;
3202 }
3203 return 1;
3204 }
3205
3206
3207 /* get the mac address by reading the vpd information in the rom.
3208 * also get the phy type and determine if there's an entropy generator.
3209 * NOTE: this is a bit convoluted for the following reasons:
3210 * 1) vpd info has order-dependent mac addresses for multinic cards
3211 * 2) the only way to determine the nic order is to use the slot
3212 * number.
3213 * 3) fiber cards don't have bridges, so their slot numbers don't
3214 * mean anything.
3215 * 4) we don't actually know we have a fiber card until after
3216 * the mac addresses are parsed.
3217 */
3218 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
3219 const int offset)
3220 {
3221 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
3222 void __iomem *base, *kstart;
3223 int i, len;
3224 int found = 0;
3225 #define VPD_FOUND_MAC 0x01
3226 #define VPD_FOUND_PHY 0x02
3227
3228 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
3229 int mac_off = 0;
3230
3231 /* give us access to the PROM */
3232 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
3233 cp->regs + REG_BIM_LOCAL_DEV_EN);
3234
3235 /* check for an expansion rom */
3236 if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
3237 goto use_random_mac_addr;
3238
3239 /* search for beginning of vpd */
3240 base = NULL;
3241 for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
3242 /* check for PCIR */
3243 if ((readb(p + i + 0) == 0x50) &&
3244 (readb(p + i + 1) == 0x43) &&
3245 (readb(p + i + 2) == 0x49) &&
3246 (readb(p + i + 3) == 0x52)) {
3247 base = p + (readb(p + i + 8) |
3248 (readb(p + i + 9) << 8));
3249 break;
3250 }
3251 }
3252
3253 if (!base || (readb(base) != 0x82))
3254 goto use_random_mac_addr;
3255
3256 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
3257 while (i < EXPANSION_ROM_SIZE) {
3258 if (readb(base + i) != 0x90) /* no vpd found */
3259 goto use_random_mac_addr;
3260
3261 /* found a vpd field */
3262 len = readb(base + i + 1) | (readb(base + i + 2) << 8);
3263
3264 /* extract keywords */
3265 kstart = base + i + 3;
3266 p = kstart;
3267 while ((p - kstart) < len) {
3268 int klen = readb(p + 2);
3269 int j;
3270 char type;
3271
3272 p += 3;
3273
3274 /* look for the following things:
3275 * -- correct length == 29
3276 * 3 (type) + 2 (size) +
3277 * 18 (strlen("local-mac-address") + 1) +
3278 * 6 (mac addr)
3279 * -- VPD Instance 'I'
3280 * -- VPD Type Bytes 'B'
3281 * -- VPD data length == 6
3282 * -- property string == local-mac-address
3283 *
3284 * -- correct length == 24
3285 * 3 (type) + 2 (size) +
3286 * 12 (strlen("entropy-dev") + 1) +
3287 * 7 (strlen("vms110") + 1)
3288 * -- VPD Instance 'I'
3289 * -- VPD Type String 'B'
3290 * -- VPD data length == 7
3291 * -- property string == entropy-dev
3292 *
3293 * -- correct length == 18
3294 * 3 (type) + 2 (size) +
3295 * 9 (strlen("phy-type") + 1) +
3296 * 4 (strlen("pcs") + 1)
3297 * -- VPD Instance 'I'
3298 * -- VPD Type String 'S'
3299 * -- VPD data length == 4
3300 * -- property string == phy-type
3301 *
3302 * -- correct length == 23
3303 * 3 (type) + 2 (size) +
3304 * 14 (strlen("phy-interface") + 1) +
3305 * 4 (strlen("pcs") + 1)
3306 * -- VPD Instance 'I'
3307 * -- VPD Type String 'S'
3308 * -- VPD data length == 4
3309 * -- property string == phy-interface
3310 */
3311 if (readb(p) != 'I')
3312 goto next;
3313
3314 /* finally, check string and length */
3315 type = readb(p + 3);
3316 if (type == 'B') {
3317 if ((klen == 29) && readb(p + 4) == 6 &&
3318 cas_vpd_match(p + 5,
3319 "local-mac-address")) {
3320 if (mac_off++ > offset)
3321 goto next;
3322
3323 /* set mac address */
3324 for (j = 0; j < 6; j++)
3325 dev_addr[j] =
3326 readb(p + 23 + j);
3327 goto found_mac;
3328 }
3329 }
3330
3331 if (type != 'S')
3332 goto next;
3333
3334 #ifdef USE_ENTROPY_DEV
3335 if ((klen == 24) &&
3336 cas_vpd_match(p + 5, "entropy-dev") &&
3337 cas_vpd_match(p + 17, "vms110")) {
3338 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
3339 goto next;
3340 }
3341 #endif
3342
3343 if (found & VPD_FOUND_PHY)
3344 goto next;
3345
3346 if ((klen == 18) && readb(p + 4) == 4 &&
3347 cas_vpd_match(p + 5, "phy-type")) {
3348 if (cas_vpd_match(p + 14, "pcs")) {
3349 phy_type = CAS_PHY_SERDES;
3350 goto found_phy;
3351 }
3352 }
3353
3354 if ((klen == 23) && readb(p + 4) == 4 &&
3355 cas_vpd_match(p + 5, "phy-interface")) {
3356 if (cas_vpd_match(p + 19, "pcs")) {
3357 phy_type = CAS_PHY_SERDES;
3358 goto found_phy;
3359 }
3360 }
3361 found_mac:
3362 found |= VPD_FOUND_MAC;
3363 goto next;
3364
3365 found_phy:
3366 found |= VPD_FOUND_PHY;
3367
3368 next:
3369 p += klen;
3370 }
3371 i += len + 3;
3372 }
3373
3374 use_random_mac_addr:
3375 if (found & VPD_FOUND_MAC)
3376 goto done;
3377
3378 /* Sun MAC prefix then 3 random bytes. */
3379 printk(PFX "MAC address not found in ROM VPD\n");
3380 dev_addr[0] = 0x08;
3381 dev_addr[1] = 0x00;
3382 dev_addr[2] = 0x20;
3383 get_random_bytes(dev_addr + 3, 3);
3384
3385 done:
3386 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3387 return phy_type;
3388 }
3389
3390 /* check pci invariants */
3391 static void cas_check_pci_invariants(struct cas *cp)
3392 {
3393 struct pci_dev *pdev = cp->pdev;
3394
3395 cp->cas_flags = 0;
3396 if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
3397 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
3398 if (pdev->revision >= CAS_ID_REVPLUS)
3399 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3400 if (pdev->revision < CAS_ID_REVPLUS02u)
3401 cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
3402
3403 /* Original Cassini supports HW CSUM, but it's not
3404 * enabled by default as it can trigger TX hangs.
3405 */
3406 if (pdev->revision < CAS_ID_REV2)
3407 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
3408 } else {
3409 /* Only sun has original cassini chips. */
3410 cp->cas_flags |= CAS_FLAG_REG_PLUS;
3411
3412 /* We use a flag because the same phy might be externally
3413 * connected.
3414 */
3415 if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
3416 (pdev->device == PCI_DEVICE_ID_NS_SATURN))
3417 cp->cas_flags |= CAS_FLAG_SATURN;
3418 }
3419 }
3420
3421
3422 static int cas_check_invariants(struct cas *cp)
3423 {
3424 struct pci_dev *pdev = cp->pdev;
3425 u32 cfg;
3426 int i;
3427
3428 /* get page size for rx buffers. */
3429 cp->page_order = 0;
3430 #ifdef USE_PAGE_ORDER
3431 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
3432 /* see if we can allocate larger pages */
3433 struct page *page = alloc_pages(GFP_ATOMIC,
3434 CAS_JUMBO_PAGE_SHIFT -
3435 PAGE_SHIFT);
3436 if (page) {
3437 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
3438 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
3439 } else {
3440 printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
3441 }
3442 }
3443 #endif
3444 cp->page_size = (PAGE_SIZE << cp->page_order);
3445
3446 /* Fetch the FIFO configurations. */
3447 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
3448 cp->rx_fifo_size = RX_FIFO_SIZE;
3449
3450 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3451 * they're both connected.
3452 */
3453 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
3454 PCI_SLOT(pdev->devfn));
3455 if (cp->phy_type & CAS_PHY_SERDES) {
3456 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3457 return 0; /* no more checking needed */
3458 }
3459
3460 /* MII */
3461 cfg = readl(cp->regs + REG_MIF_CFG);
3462 if (cfg & MIF_CFG_MDIO_1) {
3463 cp->phy_type = CAS_PHY_MII_MDIO1;
3464 } else if (cfg & MIF_CFG_MDIO_0) {
3465 cp->phy_type = CAS_PHY_MII_MDIO0;
3466 }
3467
3468 cas_mif_poll(cp, 0);
3469 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3470
3471 for (i = 0; i < 32; i++) {
3472 u32 phy_id;
3473 int j;
3474
3475 for (j = 0; j < 3; j++) {
3476 cp->phy_addr = i;
3477 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
3478 phy_id |= cas_phy_read(cp, MII_PHYSID2);
3479 if (phy_id && (phy_id != 0xFFFFFFFF)) {
3480 cp->phy_id = phy_id;
3481 goto done;
3482 }
3483 }
3484 }
3485 printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
3486 readl(cp->regs + REG_MIF_STATE_MACHINE));
3487 return -1;
3488
3489 done:
3490 /* see if we can do gigabit */
3491 cfg = cas_phy_read(cp, MII_BMSR);
3492 if ((cfg & CAS_BMSR_1000_EXTEND) &&
3493 cas_phy_read(cp, CAS_MII_1000_EXTEND))
3494 cp->cas_flags |= CAS_FLAG_1000MB_CAP;
3495 return 0;
3496 }
3497
3498 /* Must be invoked under cp->lock. */
3499 static inline void cas_start_dma(struct cas *cp)
3500 {
3501 int i;
3502 u32 val;
3503 int txfailed = 0;
3504
3505 /* enable dma */
3506 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3507 writel(val, cp->regs + REG_TX_CFG);
3508 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3509 writel(val, cp->regs + REG_RX_CFG);
3510
3511 /* enable the mac */
3512 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3513 writel(val, cp->regs + REG_MAC_TX_CFG);
3514 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3515 writel(val, cp->regs + REG_MAC_RX_CFG);
3516
3517 i = STOP_TRIES;
3518 while (i-- > 0) {
3519 val = readl(cp->regs + REG_MAC_TX_CFG);
3520 if ((val & MAC_TX_CFG_EN))
3521 break;
3522 udelay(10);
3523 }
3524 if (i < 0) txfailed = 1;
3525 i = STOP_TRIES;
3526 while (i-- > 0) {
3527 val = readl(cp->regs + REG_MAC_RX_CFG);
3528 if ((val & MAC_RX_CFG_EN)) {
3529 if (txfailed) {
3530 printk(KERN_ERR
3531 "%s: enabling mac failed [tx:%08x:%08x].\n",
3532 cp->dev->name,
3533 readl(cp->regs + REG_MIF_STATE_MACHINE),
3534 readl(cp->regs + REG_MAC_STATE_MACHINE));
3535 }
3536 goto enable_rx_done;
3537 }
3538 udelay(10);
3539 }
3540 printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
3541 cp->dev->name,
3542 (txfailed? "tx,rx":"rx"),
3543 readl(cp->regs + REG_MIF_STATE_MACHINE),
3544 readl(cp->regs + REG_MAC_STATE_MACHINE));
3545
3546 enable_rx_done:
3547 cas_unmask_intr(cp); /* enable interrupts */
3548 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
3549 writel(0, cp->regs + REG_RX_COMP_TAIL);
3550
3551 if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
3552 if (N_RX_DESC_RINGS > 1)
3553 writel(RX_DESC_RINGN_SIZE(1) - 4,
3554 cp->regs + REG_PLUS_RX_KICK1);
3555
3556 for (i = 1; i < N_RX_COMP_RINGS; i++)
3557 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
3558 }
3559 }
3560
3561 /* Must be invoked under cp->lock. */
3562 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
3563 int *pause)
3564 {
3565 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3566 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3567 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3568 if (val & PCS_MII_LPA_ASYM_PAUSE)
3569 *pause |= 0x10;
3570 *spd = 1000;
3571 }
3572
3573 /* Must be invoked under cp->lock. */
3574 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
3575 int *pause)
3576 {
3577 u32 val;
3578
3579 *fd = 0;
3580 *spd = 10;
3581 *pause = 0;
3582
3583 /* use GMII registers */
3584 val = cas_phy_read(cp, MII_LPA);
3585 if (val & CAS_LPA_PAUSE)
3586 *pause = 0x01;
3587
3588 if (val & CAS_LPA_ASYM_PAUSE)
3589 *pause |= 0x10;
3590
3591 if (val & LPA_DUPLEX)
3592 *fd = 1;
3593 if (val & LPA_100)
3594 *spd = 100;
3595
3596 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
3597 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3598 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3599 *spd = 1000;
3600 if (val & CAS_LPA_1000FULL)
3601 *fd = 1;
3602 }
3603 }
3604
3605 /* A link-up condition has occurred, initialize and enable the
3606 * rest of the chip.
3607 *
3608 * Must be invoked under cp->lock.
3609 */
3610 static void cas_set_link_modes(struct cas *cp)
3611 {
3612 u32 val;
3613 int full_duplex, speed, pause;
3614
3615 full_duplex = 0;
3616 speed = 10;
3617 pause = 0;
3618
3619 if (CAS_PHY_MII(cp->phy_type)) {
3620 cas_mif_poll(cp, 0);
3621 val = cas_phy_read(cp, MII_BMCR);
3622 if (val & BMCR_ANENABLE) {
3623 cas_read_mii_link_mode(cp, &full_duplex, &speed,
3624 &pause);
3625 } else {
3626 if (val & BMCR_FULLDPLX)
3627 full_duplex = 1;
3628
3629 if (val & BMCR_SPEED100)
3630 speed = 100;
3631 else if (val & CAS_BMCR_SPEED1000)
3632 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
3633 1000 : 100;
3634 }
3635 cas_mif_poll(cp, 1);
3636
3637 } else {
3638 val = readl(cp->regs + REG_PCS_MII_CTRL);
3639 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
3640 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3641 if (val & PCS_MII_CTRL_DUPLEX)
3642 full_duplex = 1;
3643 }
3644 }
3645
3646 if (netif_msg_link(cp))
3647 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
3648 cp->dev->name, speed, (full_duplex ? "full" : "half"));
3649
3650 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3651 if (CAS_PHY_MII(cp->phy_type)) {
3652 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3653 if (!full_duplex)
3654 val |= MAC_XIF_DISABLE_ECHO;
3655 }
3656 if (full_duplex)
3657 val |= MAC_XIF_FDPLX_LED;
3658 if (speed == 1000)
3659 val |= MAC_XIF_GMII_MODE;
3660 writel(val, cp->regs + REG_MAC_XIF_CFG);
3661
3662 /* deal with carrier and collision detect. */
3663 val = MAC_TX_CFG_IPG_EN;
3664 if (full_duplex) {
3665 val |= MAC_TX_CFG_IGNORE_CARRIER;
3666 val |= MAC_TX_CFG_IGNORE_COLL;
3667 } else {
3668 #ifndef USE_CSMA_CD_PROTO
3669 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3670 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3671 #endif
3672 }
3673 /* val now set up for REG_MAC_TX_CFG */
3674
3675 /* If gigabit and half-duplex, enable carrier extension
3676 * mode. increase slot time to 512 bytes as well.
3677 * else, disable it and make sure slot time is 64 bytes.
3678 * also activate checksum bug workaround
3679 */
3680 if ((speed == 1000) && !full_duplex) {
3681 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3682 cp->regs + REG_MAC_TX_CFG);
3683
3684 val = readl(cp->regs + REG_MAC_RX_CFG);
3685 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3686 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3687 cp->regs + REG_MAC_RX_CFG);
3688
3689 writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
3690
3691 cp->crc_size = 4;
3692 /* minimum size gigabit frame at half duplex */
3693 cp->min_frame_size = CAS_1000MB_MIN_FRAME;
3694
3695 } else {
3696 writel(val, cp->regs + REG_MAC_TX_CFG);
3697
3698 /* checksum bug workaround. don't strip FCS when in
3699 * half-duplex mode
3700 */
3701 val = readl(cp->regs + REG_MAC_RX_CFG);
3702 if (full_duplex) {
3703 val |= MAC_RX_CFG_STRIP_FCS;
3704 cp->crc_size = 0;
3705 cp->min_frame_size = CAS_MIN_MTU;
3706 } else {
3707 val &= ~MAC_RX_CFG_STRIP_FCS;
3708 cp->crc_size = 4;
3709 cp->min_frame_size = CAS_MIN_FRAME;
3710 }
3711 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3712 cp->regs + REG_MAC_RX_CFG);
3713 writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
3714 }
3715
3716 if (netif_msg_link(cp)) {
3717 if (pause & 0x01) {
3718 printk(KERN_INFO "%s: Pause is enabled "
3719 "(rxfifo: %d off: %d on: %d)\n",
3720 cp->dev->name,
3721 cp->rx_fifo_size,
3722 cp->rx_pause_off,
3723 cp->rx_pause_on);
3724 } else if (pause & 0x10) {
3725 printk(KERN_INFO "%s: TX pause enabled\n",
3726 cp->dev->name);
3727 } else {
3728 printk(KERN_INFO "%s: Pause is disabled\n",
3729 cp->dev->name);
3730 }
3731 }
3732
3733 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3734 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3735 if (pause) { /* symmetric or asymmetric pause */
3736 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3737 if (pause & 0x01) { /* symmetric pause */
3738 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3739 }
3740 }
3741 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3742 cas_start_dma(cp);
3743 }
3744
3745 /* Must be invoked under cp->lock. */
3746 static void cas_init_hw(struct cas *cp, int restart_link)
3747 {
3748 if (restart_link)
3749 cas_phy_init(cp);
3750
3751 cas_init_pause_thresholds(cp);
3752 cas_init_mac(cp);
3753 cas_init_dma(cp);
3754
3755 if (restart_link) {
3756 /* Default aneg parameters */
3757 cp->timer_ticks = 0;
3758 cas_begin_auto_negotiation(cp, NULL);
3759 } else if (cp->lstate == link_up) {
3760 cas_set_link_modes(cp);
3761 netif_carrier_on(cp->dev);
3762 }
3763 }
3764
3765 /* Must be invoked under cp->lock. on earlier cassini boards,
3766 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3767 * let it settle out, and then restore pci state.
3768 */
3769 static void cas_hard_reset(struct cas *cp)
3770 {
3771 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
3772 udelay(20);
3773 pci_restore_state(cp->pdev);
3774 }
3775
3776
3777 static void cas_global_reset(struct cas *cp, int blkflag)
3778 {
3779 int limit;
3780
3781 /* issue a global reset. don't use RSTOUT. */
3782 if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
3783 /* For PCS, when the blkflag is set, we should set the
3784 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3785 * the last autonegotiation from being cleared. We'll
3786 * need some special handling if the chip is set into a
3787 * loopback mode.
3788 */
3789 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
3790 cp->regs + REG_SW_RESET);
3791 } else {
3792 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
3793 }
3794
3795 /* need to wait at least 3ms before polling register */
3796 mdelay(3);
3797
3798 limit = STOP_TRIES;
3799 while (limit-- > 0) {
3800 u32 val = readl(cp->regs + REG_SW_RESET);
3801 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3802 goto done;
3803 udelay(10);
3804 }
3805 printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
3806
3807 done:
3808 /* enable various BIM interrupts */
3809 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
3810 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
3811
3812 /* clear out pci error status mask for handled errors.
3813 * we don't deal with DMA counter overflows as they happen
3814 * all the time.
3815 */
3816 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
3817 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
3818 PCI_ERR_BIM_DMA_READ), cp->regs +
3819 REG_PCI_ERR_STATUS_MASK);
3820
3821 /* set up for MII by default to address mac rx reset timeout
3822 * issue
3823 */
3824 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
3825 }
3826
3827 static void cas_reset(struct cas *cp, int blkflag)
3828 {
3829 u32 val;
3830
3831 cas_mask_intr(cp);
3832 cas_global_reset(cp, blkflag);
3833 cas_mac_reset(cp);
3834 cas_entropy_reset(cp);
3835
3836 /* disable dma engines. */
3837 val = readl(cp->regs + REG_TX_CFG);
3838 val &= ~TX_CFG_DMA_EN;
3839 writel(val, cp->regs + REG_TX_CFG);
3840
3841 val = readl(cp->regs + REG_RX_CFG);
3842 val &= ~RX_CFG_DMA_EN;
3843 writel(val, cp->regs + REG_RX_CFG);
3844
3845 /* program header parser */
3846 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
3847 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
3848 cas_load_firmware(cp, CAS_HP_FIRMWARE);
3849 } else {
3850 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
3851 }
3852
3853 /* clear out error registers */
3854 spin_lock(&cp->stat_lock[N_TX_RINGS]);
3855 cas_clear_mac_err(cp);
3856 spin_unlock(&cp->stat_lock[N_TX_RINGS]);
3857 }
3858
3859 /* Shut down the chip, must be called with pm_mutex held. */
3860 static void cas_shutdown(struct cas *cp)
3861 {
3862 unsigned long flags;
3863
3864 /* Make us not-running to avoid timers respawning */
3865 cp->hw_running = 0;
3866
3867 del_timer_sync(&cp->link_timer);
3868
3869 /* Stop the reset task */
3870 #if 0
3871 while (atomic_read(&cp->reset_task_pending_mtu) ||
3872 atomic_read(&cp->reset_task_pending_spare) ||
3873 atomic_read(&cp->reset_task_pending_all))
3874 schedule();
3875
3876 #else
3877 while (atomic_read(&cp->reset_task_pending))
3878 schedule();
3879 #endif
3880 /* Actually stop the chip */
3881 cas_lock_all_save(cp, flags);
3882 cas_reset(cp, 0);
3883 if (cp->cas_flags & CAS_FLAG_SATURN)
3884 cas_phy_powerdown(cp);
3885 cas_unlock_all_restore(cp, flags);
3886 }
3887
3888 static int cas_change_mtu(struct net_device *dev, int new_mtu)
3889 {
3890 struct cas *cp = netdev_priv(dev);
3891
3892 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
3893 return -EINVAL;
3894
3895 dev->mtu = new_mtu;
3896 if (!netif_running(dev) || !netif_device_present(dev))
3897 return 0;
3898
3899 /* let the reset task handle it */
3900 #if 1
3901 atomic_inc(&cp->reset_task_pending);
3902 if ((cp->phy_type & CAS_PHY_SERDES)) {
3903 atomic_inc(&cp->reset_task_pending_all);
3904 } else {
3905 atomic_inc(&cp->reset_task_pending_mtu);
3906 }
3907 schedule_work(&cp->reset_task);
3908 #else
3909 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
3910 CAS_RESET_ALL : CAS_RESET_MTU);
3911 printk(KERN_ERR "reset called in cas_change_mtu\n");
3912 schedule_work(&cp->reset_task);
3913 #endif
3914
3915 flush_scheduled_work();
3916 return 0;
3917 }
3918
3919 static void cas_clean_txd(struct cas *cp, int ring)
3920 {
3921 struct cas_tx_desc *txd = cp->init_txds[ring];
3922 struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
3923 u64 daddr, dlen;
3924 int i, size;
3925
3926 size = TX_DESC_RINGN_SIZE(ring);
3927 for (i = 0; i < size; i++) {
3928 int frag;
3929
3930 if (skbs[i] == NULL)
3931 continue;
3932
3933 skb = skbs[i];
3934 skbs[i] = NULL;
3935
3936 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
3937 int ent = i & (size - 1);
3938
3939 /* first buffer is never a tiny buffer and so
3940 * needs to be unmapped.
3941 */
3942 daddr = le64_to_cpu(txd[ent].buffer);
3943 dlen = CAS_VAL(TX_DESC_BUFLEN,
3944 le64_to_cpu(txd[ent].control));
3945 pci_unmap_page(cp->pdev, daddr, dlen,
3946 PCI_DMA_TODEVICE);
3947
3948 if (frag != skb_shinfo(skb)->nr_frags) {
3949 i++;
3950
3951 /* next buffer might by a tiny buffer.
3952 * skip past it.
3953 */
3954 ent = i & (size - 1);
3955 if (cp->tx_tiny_use[ring][ent].used)
3956 i++;
3957 }
3958 }
3959 dev_kfree_skb_any(skb);
3960 }
3961
3962 /* zero out tiny buf usage */
3963 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
3964 }
3965
3966 /* freed on close */
3967 static inline void cas_free_rx_desc(struct cas *cp, int ring)
3968 {
3969 cas_page_t **page = cp->rx_pages[ring];
3970 int i, size;
3971
3972 size = RX_DESC_RINGN_SIZE(ring);
3973 for (i = 0; i < size; i++) {
3974 if (page[i]) {
3975 cas_page_free(cp, page[i]);
3976 page[i] = NULL;
3977 }
3978 }
3979 }
3980
3981 static void cas_free_rxds(struct cas *cp)
3982 {
3983 int i;
3984
3985 for (i = 0; i < N_RX_DESC_RINGS; i++)
3986 cas_free_rx_desc(cp, i);
3987 }
3988
3989 /* Must be invoked under cp->lock. */
3990 static void cas_clean_rings(struct cas *cp)
3991 {
3992 int i;
3993
3994 /* need to clean all tx rings */
3995 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
3996 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
3997 for (i = 0; i < N_TX_RINGS; i++)
3998 cas_clean_txd(cp, i);
3999
4000 /* zero out init block */
4001 memset(cp->init_block, 0, sizeof(struct cas_init_block));
4002 cas_clean_rxds(cp);
4003 cas_clean_rxcs(cp);
4004 }
4005
4006 /* allocated on open */
4007 static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
4008 {
4009 cas_page_t **page = cp->rx_pages[ring];
4010 int size, i = 0;
4011
4012 size = RX_DESC_RINGN_SIZE(ring);
4013 for (i = 0; i < size; i++) {
4014 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
4015 return -1;
4016 }
4017 return 0;
4018 }
4019
4020 static int cas_alloc_rxds(struct cas *cp)
4021 {
4022 int i;
4023
4024 for (i = 0; i < N_RX_DESC_RINGS; i++) {
4025 if (cas_alloc_rx_desc(cp, i) < 0) {
4026 cas_free_rxds(cp);
4027 return -1;
4028 }
4029 }
4030 return 0;
4031 }
4032
4033 static void cas_reset_task(struct work_struct *work)
4034 {
4035 struct cas *cp = container_of(work, struct cas, reset_task);
4036 #if 0
4037 int pending = atomic_read(&cp->reset_task_pending);
4038 #else
4039 int pending_all = atomic_read(&cp->reset_task_pending_all);
4040 int pending_spare = atomic_read(&cp->reset_task_pending_spare);
4041 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
4042
4043 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
4044 /* We can have more tasks scheduled than actually
4045 * needed.
4046 */
4047 atomic_dec(&cp->reset_task_pending);
4048 return;
4049 }
4050 #endif
4051 /* The link went down, we reset the ring, but keep
4052 * DMA stopped. Use this function for reset
4053 * on error as well.
4054 */
4055 if (cp->hw_running) {
4056 unsigned long flags;
4057
4058 /* Make sure we don't get interrupts or tx packets */
4059 netif_device_detach(cp->dev);
4060 cas_lock_all_save(cp, flags);
4061
4062 if (cp->opened) {
4063 /* We call cas_spare_recover when we call cas_open.
4064 * but we do not initialize the lists cas_spare_recover
4065 * uses until cas_open is called.
4066 */
4067 cas_spare_recover(cp, GFP_ATOMIC);
4068 }
4069 #if 1
4070 /* test => only pending_spare set */
4071 if (!pending_all && !pending_mtu)
4072 goto done;
4073 #else
4074 if (pending == CAS_RESET_SPARE)
4075 goto done;
4076 #endif
4077 /* when pending == CAS_RESET_ALL, the following
4078 * call to cas_init_hw will restart auto negotiation.
4079 * Setting the second argument of cas_reset to
4080 * !(pending == CAS_RESET_ALL) will set this argument
4081 * to 1 (avoiding reinitializing the PHY for the normal
4082 * PCS case) when auto negotiation is not restarted.
4083 */
4084 #if 1
4085 cas_reset(cp, !(pending_all > 0));
4086 if (cp->opened)
4087 cas_clean_rings(cp);
4088 cas_init_hw(cp, (pending_all > 0));
4089 #else
4090 cas_reset(cp, !(pending == CAS_RESET_ALL));
4091 if (cp->opened)
4092 cas_clean_rings(cp);
4093 cas_init_hw(cp, pending == CAS_RESET_ALL);
4094 #endif
4095
4096 done:
4097 cas_unlock_all_restore(cp, flags);
4098 netif_device_attach(cp->dev);
4099 }
4100 #if 1
4101 atomic_sub(pending_all, &cp->reset_task_pending_all);
4102 atomic_sub(pending_spare, &cp->reset_task_pending_spare);
4103 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
4104 atomic_dec(&cp->reset_task_pending);
4105 #else
4106 atomic_set(&cp->reset_task_pending, 0);
4107 #endif
4108 }
4109
4110 static void cas_link_timer(unsigned long data)
4111 {
4112 struct cas *cp = (struct cas *) data;
4113 int mask, pending = 0, reset = 0;
4114 unsigned long flags;
4115
4116 if (link_transition_timeout != 0 &&
4117 cp->link_transition_jiffies_valid &&
4118 ((jiffies - cp->link_transition_jiffies) >
4119 (link_transition_timeout))) {
4120 /* One-second counter so link-down workaround doesn't
4121 * cause resets to occur so fast as to fool the switch
4122 * into thinking the link is down.
4123 */
4124 cp->link_transition_jiffies_valid = 0;
4125 }
4126
4127 if (!cp->hw_running)
4128 return;
4129
4130 spin_lock_irqsave(&cp->lock, flags);
4131 cas_lock_tx(cp);
4132 cas_entropy_gather(cp);
4133
4134 /* If the link task is still pending, we just
4135 * reschedule the link timer
4136 */
4137 #if 1
4138 if (atomic_read(&cp->reset_task_pending_all) ||
4139 atomic_read(&cp->reset_task_pending_spare) ||
4140 atomic_read(&cp->reset_task_pending_mtu))
4141 goto done;
4142 #else
4143 if (atomic_read(&cp->reset_task_pending))
4144 goto done;
4145 #endif
4146
4147 /* check for rx cleaning */
4148 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
4149 int i, rmask;
4150
4151 for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
4152 rmask = CAS_FLAG_RXD_POST(i);
4153 if ((mask & rmask) == 0)
4154 continue;
4155
4156 /* post_rxds will do a mod_timer */
4157 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
4158 pending = 1;
4159 continue;
4160 }
4161 cp->cas_flags &= ~rmask;
4162 }
4163 }
4164
4165 if (CAS_PHY_MII(cp->phy_type)) {
4166 u16 bmsr;
4167 cas_mif_poll(cp, 0);
4168 bmsr = cas_phy_read(cp, MII_BMSR);
4169 /* WTZ: Solaris driver reads this twice, but that
4170 * may be due to the PCS case and the use of a
4171 * common implementation. Read it twice here to be
4172 * safe.
4173 */
4174 bmsr = cas_phy_read(cp, MII_BMSR);
4175 cas_mif_poll(cp, 1);
4176 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
4177 reset = cas_mii_link_check(cp, bmsr);
4178 } else {
4179 reset = cas_pcs_link_check(cp);
4180 }
4181
4182 if (reset)
4183 goto done;
4184
4185 /* check for tx state machine confusion */
4186 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
4187 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4188 u32 wptr, rptr;
4189 int tlm = CAS_VAL(MAC_SM_TLM, val);
4190
4191 if (((tlm == 0x5) || (tlm == 0x3)) &&
4192 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4193 if (netif_msg_tx_err(cp))
4194 printk(KERN_DEBUG "%s: tx err: "
4195 "MAC_STATE[%08x]\n",
4196 cp->dev->name, val);
4197 reset = 1;
4198 goto done;
4199 }
4200
4201 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4202 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4203 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
4204 if ((val == 0) && (wptr != rptr)) {
4205 if (netif_msg_tx_err(cp))
4206 printk(KERN_DEBUG "%s: tx err: "
4207 "TX_FIFO[%08x:%08x:%08x]\n",
4208 cp->dev->name, val, wptr, rptr);
4209 reset = 1;
4210 }
4211
4212 if (reset)
4213 cas_hard_reset(cp);
4214 }
4215
4216 done:
4217 if (reset) {
4218 #if 1
4219 atomic_inc(&cp->reset_task_pending);
4220 atomic_inc(&cp->reset_task_pending_all);
4221 schedule_work(&cp->reset_task);
4222 #else
4223 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
4224 printk(KERN_ERR "reset called in cas_link_timer\n");
4225 schedule_work(&cp->reset_task);
4226 #endif
4227 }
4228
4229 if (!pending)
4230 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
4231 cas_unlock_tx(cp);
4232 spin_unlock_irqrestore(&cp->lock, flags);
4233 }
4234
4235 /* tiny buffers are used to avoid target abort issues with
4236 * older cassini's
4237 */
4238 static void cas_tx_tiny_free(struct cas *cp)
4239 {
4240 struct pci_dev *pdev = cp->pdev;
4241 int i;
4242
4243 for (i = 0; i < N_TX_RINGS; i++) {
4244 if (!cp->tx_tiny_bufs[i])
4245 continue;
4246
4247 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
4248 cp->tx_tiny_bufs[i],
4249 cp->tx_tiny_dvma[i]);
4250 cp->tx_tiny_bufs[i] = NULL;
4251 }
4252 }
4253
4254 static int cas_tx_tiny_alloc(struct cas *cp)
4255 {
4256 struct pci_dev *pdev = cp->pdev;
4257 int i;
4258
4259 for (i = 0; i < N_TX_RINGS; i++) {
4260 cp->tx_tiny_bufs[i] =
4261 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
4262 &cp->tx_tiny_dvma[i]);
4263 if (!cp->tx_tiny_bufs[i]) {
4264 cas_tx_tiny_free(cp);
4265 return -1;
4266 }
4267 }
4268 return 0;
4269 }
4270
4271
4272 static int cas_open(struct net_device *dev)
4273 {
4274 struct cas *cp = netdev_priv(dev);
4275 int hw_was_up, err;
4276 unsigned long flags;
4277
4278 mutex_lock(&cp->pm_mutex);
4279
4280 hw_was_up = cp->hw_running;
4281
4282 /* The power-management mutex protects the hw_running
4283 * etc. state so it is safe to do this bit without cp->lock
4284 */
4285 if (!cp->hw_running) {
4286 /* Reset the chip */
4287 cas_lock_all_save(cp, flags);
4288 /* We set the second arg to cas_reset to zero
4289 * because cas_init_hw below will have its second
4290 * argument set to non-zero, which will force
4291 * autonegotiation to start.
4292 */
4293 cas_reset(cp, 0);
4294 cp->hw_running = 1;
4295 cas_unlock_all_restore(cp, flags);
4296 }
4297
4298 if (cas_tx_tiny_alloc(cp) < 0)
4299 return -ENOMEM;
4300
4301 /* alloc rx descriptors */
4302 err = -ENOMEM;
4303 if (cas_alloc_rxds(cp) < 0)
4304 goto err_tx_tiny;
4305
4306 /* allocate spares */
4307 cas_spare_init(cp);
4308 cas_spare_recover(cp, GFP_KERNEL);
4309
4310 /* We can now request the interrupt as we know it's masked
4311 * on the controller. cassini+ has up to 4 interrupts
4312 * that can be used, but you need to do explicit pci interrupt
4313 * mapping to expose them
4314 */
4315 if (request_irq(cp->pdev->irq, cas_interrupt,
4316 IRQF_SHARED, dev->name, (void *) dev)) {
4317 printk(KERN_ERR "%s: failed to request irq !\n",
4318 cp->dev->name);
4319 err = -EAGAIN;
4320 goto err_spare;
4321 }
4322
4323 #ifdef USE_NAPI
4324 napi_enable(&cp->napi);
4325 #endif
4326 /* init hw */
4327 cas_lock_all_save(cp, flags);
4328 cas_clean_rings(cp);
4329 cas_init_hw(cp, !hw_was_up);
4330 cp->opened = 1;
4331 cas_unlock_all_restore(cp, flags);
4332
4333 netif_start_queue(dev);
4334 mutex_unlock(&cp->pm_mutex);
4335 return 0;
4336
4337 err_spare:
4338 cas_spare_free(cp);
4339 cas_free_rxds(cp);
4340 err_tx_tiny:
4341 cas_tx_tiny_free(cp);
4342 mutex_unlock(&cp->pm_mutex);
4343 return err;
4344 }
4345
4346 static int cas_close(struct net_device *dev)
4347 {
4348 unsigned long flags;
4349 struct cas *cp = netdev_priv(dev);
4350
4351 #ifdef USE_NAPI
4352 napi_disable(&cp->napi);
4353 #endif
4354 /* Make sure we don't get distracted by suspend/resume */
4355 mutex_lock(&cp->pm_mutex);
4356
4357 netif_stop_queue(dev);
4358
4359 /* Stop traffic, mark us closed */
4360 cas_lock_all_save(cp, flags);
4361 cp->opened = 0;
4362 cas_reset(cp, 0);
4363 cas_phy_init(cp);
4364 cas_begin_auto_negotiation(cp, NULL);
4365 cas_clean_rings(cp);
4366 cas_unlock_all_restore(cp, flags);
4367
4368 free_irq(cp->pdev->irq, (void *) dev);
4369 cas_spare_free(cp);
4370 cas_free_rxds(cp);
4371 cas_tx_tiny_free(cp);
4372 mutex_unlock(&cp->pm_mutex);
4373 return 0;
4374 }
4375
4376 static struct {
4377 const char name[ETH_GSTRING_LEN];
4378 } ethtool_cassini_statnames[] = {
4379 {"collisions"},
4380 {"rx_bytes"},
4381 {"rx_crc_errors"},
4382 {"rx_dropped"},
4383 {"rx_errors"},
4384 {"rx_fifo_errors"},
4385 {"rx_frame_errors"},
4386 {"rx_length_errors"},
4387 {"rx_over_errors"},
4388 {"rx_packets"},
4389 {"tx_aborted_errors"},
4390 {"tx_bytes"},
4391 {"tx_dropped"},
4392 {"tx_errors"},
4393 {"tx_fifo_errors"},
4394 {"tx_packets"}
4395 };
4396 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames)
4397
4398 static struct {
4399 const int offsets; /* neg. values for 2nd arg to cas_read_phy */
4400 } ethtool_register_table[] = {
4401 {-MII_BMSR},
4402 {-MII_BMCR},
4403 {REG_CAWR},
4404 {REG_INF_BURST},
4405 {REG_BIM_CFG},
4406 {REG_RX_CFG},
4407 {REG_HP_CFG},
4408 {REG_MAC_TX_CFG},
4409 {REG_MAC_RX_CFG},
4410 {REG_MAC_CTRL_CFG},
4411 {REG_MAC_XIF_CFG},
4412 {REG_MIF_CFG},
4413 {REG_PCS_CFG},
4414 {REG_SATURN_PCFG},
4415 {REG_PCS_MII_STATUS},
4416 {REG_PCS_STATE_MACHINE},
4417 {REG_MAC_COLL_EXCESS},
4418 {REG_MAC_COLL_LATE}
4419 };
4420 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table)
4421 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4422
4423 static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
4424 {
4425 u8 *p;
4426 int i;
4427 unsigned long flags;
4428
4429 spin_lock_irqsave(&cp->lock, flags);
4430 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
4431 u16 hval;
4432 u32 val;
4433 if (ethtool_register_table[i].offsets < 0) {
4434 hval = cas_phy_read(cp,
4435 -ethtool_register_table[i].offsets);
4436 val = hval;
4437 } else {
4438 val= readl(cp->regs+ethtool_register_table[i].offsets);
4439 }
4440 memcpy(p, (u8 *)&val, sizeof(u32));
4441 }
4442 spin_unlock_irqrestore(&cp->lock, flags);
4443 }
4444
4445 static struct net_device_stats *cas_get_stats(struct net_device *dev)
4446 {
4447 struct cas *cp = netdev_priv(dev);
4448 struct net_device_stats *stats = cp->net_stats;
4449 unsigned long flags;
4450 int i;
4451 unsigned long tmp;
4452
4453 /* we collate all of the stats into net_stats[N_TX_RING] */
4454 if (!cp->hw_running)
4455 return stats + N_TX_RINGS;
4456
4457 /* collect outstanding stats */
4458 /* WTZ: the Cassini spec gives these as 16 bit counters but
4459 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4460 * in case the chip somehow puts any garbage in the other bits.
4461 * Also, counter usage didn't seem to mach what Adrian did
4462 * in the parts of the code that set these quantities. Made
4463 * that consistent.
4464 */
4465 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
4466 stats[N_TX_RINGS].rx_crc_errors +=
4467 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
4468 stats[N_TX_RINGS].rx_frame_errors +=
4469 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
4470 stats[N_TX_RINGS].rx_length_errors +=
4471 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
4472 #if 1
4473 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
4474 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
4475 stats[N_TX_RINGS].tx_aborted_errors += tmp;
4476 stats[N_TX_RINGS].collisions +=
4477 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
4478 #else
4479 stats[N_TX_RINGS].tx_aborted_errors +=
4480 readl(cp->regs + REG_MAC_COLL_EXCESS);
4481 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
4482 readl(cp->regs + REG_MAC_COLL_LATE);
4483 #endif
4484 cas_clear_mac_err(cp);
4485
4486 /* saved bits that are unique to ring 0 */
4487 spin_lock(&cp->stat_lock[0]);
4488 stats[N_TX_RINGS].collisions += stats[0].collisions;
4489 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
4490 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
4491 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
4492 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
4493 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
4494 spin_unlock(&cp->stat_lock[0]);
4495
4496 for (i = 0; i < N_TX_RINGS; i++) {
4497 spin_lock(&cp->stat_lock[i]);
4498 stats[N_TX_RINGS].rx_length_errors +=
4499 stats[i].rx_length_errors;
4500 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
4501 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
4502 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
4503 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
4504 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
4505 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
4506 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
4507 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
4508 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
4509 memset(stats + i, 0, sizeof(struct net_device_stats));
4510 spin_unlock(&cp->stat_lock[i]);
4511 }
4512 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
4513 return stats + N_TX_RINGS;
4514 }
4515
4516
4517 static void cas_set_multicast(struct net_device *dev)
4518 {
4519 struct cas *cp = netdev_priv(dev);
4520 u32 rxcfg, rxcfg_new;
4521 unsigned long flags;
4522 int limit = STOP_TRIES;
4523
4524 if (!cp->hw_running)
4525 return;
4526
4527 spin_lock_irqsave(&cp->lock, flags);
4528 rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
4529
4530 /* disable RX MAC and wait for completion */
4531 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4532 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
4533 if (!limit--)
4534 break;
4535 udelay(10);
4536 }
4537
4538 /* disable hash filter and wait for completion */
4539 limit = STOP_TRIES;
4540 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
4541 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
4542 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
4543 if (!limit--)
4544 break;
4545 udelay(10);
4546 }
4547
4548 /* program hash filters */
4549 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
4550 rxcfg |= rxcfg_new;
4551 writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
4552 spin_unlock_irqrestore(&cp->lock, flags);
4553 }
4554
4555 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4556 {
4557 struct cas *cp = netdev_priv(dev);
4558 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
4559 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
4560 info->fw_version[0] = '\0';
4561 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
4562 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
4563 cp->casreg_len : CAS_MAX_REGS;
4564 info->n_stats = CAS_NUM_STAT_KEYS;
4565 }
4566
4567 static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4568 {
4569 struct cas *cp = netdev_priv(dev);
4570 u16 bmcr;
4571 int full_duplex, speed, pause;
4572 unsigned long flags;
4573 enum link_state linkstate = link_up;
4574
4575 cmd->advertising = 0;
4576 cmd->supported = SUPPORTED_Autoneg;
4577 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
4578 cmd->supported |= SUPPORTED_1000baseT_Full;
4579 cmd->advertising |= ADVERTISED_1000baseT_Full;
4580 }
4581
4582 /* Record PHY settings if HW is on. */
4583 spin_lock_irqsave(&cp->lock, flags);
4584 bmcr = 0;
4585 linkstate = cp->lstate;
4586 if (CAS_PHY_MII(cp->phy_type)) {
4587 cmd->port = PORT_MII;
4588 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
4589 XCVR_INTERNAL : XCVR_EXTERNAL;
4590 cmd->phy_address = cp->phy_addr;
4591 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
4592 ADVERTISED_10baseT_Half |
4593 ADVERTISED_10baseT_Full |
4594 ADVERTISED_100baseT_Half |
4595 ADVERTISED_100baseT_Full;
4596
4597 cmd->supported |=
4598 (SUPPORTED_10baseT_Half |
4599 SUPPORTED_10baseT_Full |
4600 SUPPORTED_100baseT_Half |
4601 SUPPORTED_100baseT_Full |
4602 SUPPORTED_TP | SUPPORTED_MII);
4603
4604 if (cp->hw_running) {
4605 cas_mif_poll(cp, 0);
4606 bmcr = cas_phy_read(cp, MII_BMCR);
4607 cas_read_mii_link_mode(cp, &full_duplex,
4608 &speed, &pause);
4609 cas_mif_poll(cp, 1);
4610 }
4611
4612 } else {
4613 cmd->port = PORT_FIBRE;
4614 cmd->transceiver = XCVR_INTERNAL;
4615 cmd->phy_address = 0;
4616 cmd->supported |= SUPPORTED_FIBRE;
4617 cmd->advertising |= ADVERTISED_FIBRE;
4618
4619 if (cp->hw_running) {
4620 /* pcs uses the same bits as mii */
4621 bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
4622 cas_read_pcs_link_mode(cp, &full_duplex,
4623 &speed, &pause);
4624 }
4625 }
4626 spin_unlock_irqrestore(&cp->lock, flags);
4627
4628 if (bmcr & BMCR_ANENABLE) {
4629 cmd->advertising |= ADVERTISED_Autoneg;
4630 cmd->autoneg = AUTONEG_ENABLE;
4631 cmd->speed = ((speed == 10) ?
4632 SPEED_10 :
4633 ((speed == 1000) ?
4634 SPEED_1000 : SPEED_100));
4635 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
4636 } else {
4637 cmd->autoneg = AUTONEG_DISABLE;
4638 cmd->speed =
4639 (bmcr & CAS_BMCR_SPEED1000) ?
4640 SPEED_1000 :
4641 ((bmcr & BMCR_SPEED100) ? SPEED_100:
4642 SPEED_10);
4643 cmd->duplex =
4644 (bmcr & BMCR_FULLDPLX) ?
4645 DUPLEX_FULL : DUPLEX_HALF;
4646 }
4647 if (linkstate != link_up) {
4648 /* Force these to "unknown" if the link is not up and
4649 * autonogotiation in enabled. We can set the link
4650 * speed to 0, but not cmd->duplex,
4651 * because its legal values are 0 and 1. Ethtool will
4652 * print the value reported in parentheses after the
4653 * word "Unknown" for unrecognized values.
4654 *
4655 * If in forced mode, we report the speed and duplex
4656 * settings that we configured.
4657 */
4658 if (cp->link_cntl & BMCR_ANENABLE) {
4659 cmd->speed = 0;
4660 cmd->duplex = 0xff;
4661 } else {
4662 cmd->speed = SPEED_10;
4663 if (cp->link_cntl & BMCR_SPEED100) {
4664 cmd->speed = SPEED_100;
4665 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
4666 cmd->speed = SPEED_1000;
4667 }
4668 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
4669 DUPLEX_FULL : DUPLEX_HALF;
4670 }
4671 }
4672 return 0;
4673 }
4674
4675 static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4676 {
4677 struct cas *cp = netdev_priv(dev);
4678 unsigned long flags;
4679
4680 /* Verify the settings we care about. */
4681 if (cmd->autoneg != AUTONEG_ENABLE &&
4682 cmd->autoneg != AUTONEG_DISABLE)
4683 return -EINVAL;
4684
4685 if (cmd->autoneg == AUTONEG_DISABLE &&
4686 ((cmd->speed != SPEED_1000 &&
4687 cmd->speed != SPEED_100 &&
4688 cmd->speed != SPEED_10) ||
4689 (cmd->duplex != DUPLEX_HALF &&
4690 cmd->duplex != DUPLEX_FULL)))
4691 return -EINVAL;
4692
4693 /* Apply settings and restart link process. */
4694 spin_lock_irqsave(&cp->lock, flags);
4695 cas_begin_auto_negotiation(cp, cmd);
4696 spin_unlock_irqrestore(&cp->lock, flags);
4697 return 0;
4698 }
4699
4700 static int cas_nway_reset(struct net_device *dev)
4701 {
4702 struct cas *cp = netdev_priv(dev);
4703 unsigned long flags;
4704
4705 if ((cp->link_cntl & BMCR_ANENABLE) == 0)
4706 return -EINVAL;
4707
4708 /* Restart link process. */
4709 spin_lock_irqsave(&cp->lock, flags);
4710 cas_begin_auto_negotiation(cp, NULL);
4711 spin_unlock_irqrestore(&cp->lock, flags);
4712
4713 return 0;
4714 }
4715
4716 static u32 cas_get_link(struct net_device *dev)
4717 {
4718 struct cas *cp = netdev_priv(dev);
4719 return cp->lstate == link_up;
4720 }
4721
4722 static u32 cas_get_msglevel(struct net_device *dev)
4723 {
4724 struct cas *cp = netdev_priv(dev);
4725 return cp->msg_enable;
4726 }
4727
4728 static void cas_set_msglevel(struct net_device *dev, u32 value)
4729 {
4730 struct cas *cp = netdev_priv(dev);
4731 cp->msg_enable = value;
4732 }
4733
4734 static int cas_get_regs_len(struct net_device *dev)
4735 {
4736 struct cas *cp = netdev_priv(dev);
4737 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
4738 }
4739
4740 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4741 void *p)
4742 {
4743 struct cas *cp = netdev_priv(dev);
4744 regs->version = 0;
4745 /* cas_read_regs handles locks (cp->lock). */
4746 cas_read_regs(cp, p, regs->len / sizeof(u32));
4747 }
4748
4749 static int cas_get_sset_count(struct net_device *dev, int sset)
4750 {
4751 switch (sset) {
4752 case ETH_SS_STATS:
4753 return CAS_NUM_STAT_KEYS;
4754 default:
4755 return -EOPNOTSUPP;
4756 }
4757 }
4758
4759 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4760 {
4761 memcpy(data, &ethtool_cassini_statnames,
4762 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
4763 }
4764
4765 static void cas_get_ethtool_stats(struct net_device *dev,
4766 struct ethtool_stats *estats, u64 *data)
4767 {
4768 struct cas *cp = netdev_priv(dev);
4769 struct net_device_stats *stats = cas_get_stats(cp->dev);
4770 int i = 0;
4771 data[i++] = stats->collisions;
4772 data[i++] = stats->rx_bytes;
4773 data[i++] = stats->rx_crc_errors;
4774 data[i++] = stats->rx_dropped;
4775 data[i++] = stats->rx_errors;
4776 data[i++] = stats->rx_fifo_errors;
4777 data[i++] = stats->rx_frame_errors;
4778 data[i++] = stats->rx_length_errors;
4779 data[i++] = stats->rx_over_errors;
4780 data[i++] = stats->rx_packets;
4781 data[i++] = stats->tx_aborted_errors;
4782 data[i++] = stats->tx_bytes;
4783 data[i++] = stats->tx_dropped;
4784 data[i++] = stats->tx_errors;
4785 data[i++] = stats->tx_fifo_errors;
4786 data[i++] = stats->tx_packets;
4787 BUG_ON(i != CAS_NUM_STAT_KEYS);
4788 }
4789
4790 static const struct ethtool_ops cas_ethtool_ops = {
4791 .get_drvinfo = cas_get_drvinfo,
4792 .get_settings = cas_get_settings,
4793 .set_settings = cas_set_settings,
4794 .nway_reset = cas_nway_reset,
4795 .get_link = cas_get_link,
4796 .get_msglevel = cas_get_msglevel,
4797 .set_msglevel = cas_set_msglevel,
4798 .get_regs_len = cas_get_regs_len,
4799 .get_regs = cas_get_regs,
4800 .get_sset_count = cas_get_sset_count,
4801 .get_strings = cas_get_strings,
4802 .get_ethtool_stats = cas_get_ethtool_stats,
4803 };
4804
4805 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4806 {
4807 struct cas *cp = netdev_priv(dev);
4808 struct mii_ioctl_data *data = if_mii(ifr);
4809 unsigned long flags;
4810 int rc = -EOPNOTSUPP;
4811
4812 /* Hold the PM mutex while doing ioctl's or we may collide
4813 * with open/close and power management and oops.
4814 */
4815 mutex_lock(&cp->pm_mutex);
4816 switch (cmd) {
4817 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
4818 data->phy_id = cp->phy_addr;
4819 /* Fallthrough... */
4820
4821 case SIOCGMIIREG: /* Read MII PHY register. */
4822 spin_lock_irqsave(&cp->lock, flags);
4823 cas_mif_poll(cp, 0);
4824 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
4825 cas_mif_poll(cp, 1);
4826 spin_unlock_irqrestore(&cp->lock, flags);
4827 rc = 0;
4828 break;
4829
4830 case SIOCSMIIREG: /* Write MII PHY register. */
4831 if (!capable(CAP_NET_ADMIN)) {
4832 rc = -EPERM;
4833 break;
4834 }
4835 spin_lock_irqsave(&cp->lock, flags);
4836 cas_mif_poll(cp, 0);
4837 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
4838 cas_mif_poll(cp, 1);
4839 spin_unlock_irqrestore(&cp->lock, flags);
4840 break;
4841 default:
4842 break;
4843 };
4844
4845 mutex_unlock(&cp->pm_mutex);
4846 return rc;
4847 }
4848
4849 /* When this chip sits underneath an Intel 31154 bridge, it is the
4850 * only subordinate device and we can tweak the bridge settings to
4851 * reflect that fact.
4852 */
4853 static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
4854 {
4855 struct pci_dev *pdev = cas_pdev->bus->self;
4856 u32 val;
4857
4858 if (!pdev)
4859 return;
4860
4861 if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
4862 return;
4863
4864 /* Clear bit 10 (Bus Parking Control) in the Secondary
4865 * Arbiter Control/Status Register which lives at offset
4866 * 0x41. Using a 32-bit word read/modify/write at 0x40
4867 * is much simpler so that's how we do this.
4868 */
4869 pci_read_config_dword(pdev, 0x40, &val);
4870 val &= ~0x00040000;
4871 pci_write_config_dword(pdev, 0x40, val);
4872
4873 /* Max out the Multi-Transaction Timer settings since
4874 * Cassini is the only device present.
4875 *
4876 * The register is 16-bit and lives at 0x50. When the
4877 * settings are enabled, it extends the GRANT# signal
4878 * for a requestor after a transaction is complete. This
4879 * allows the next request to run without first needing
4880 * to negotiate the GRANT# signal back.
4881 *
4882 * Bits 12:10 define the grant duration:
4883 *
4884 * 1 -- 16 clocks
4885 * 2 -- 32 clocks
4886 * 3 -- 64 clocks
4887 * 4 -- 128 clocks
4888 * 5 -- 256 clocks
4889 *
4890 * All other values are illegal.
4891 *
4892 * Bits 09:00 define which REQ/GNT signal pairs get the
4893 * GRANT# signal treatment. We set them all.
4894 */
4895 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
4896
4897 /* The Read Prefecth Policy register is 16-bit and sits at
4898 * offset 0x52. It enables a "smart" pre-fetch policy. We
4899 * enable it and max out all of the settings since only one
4900 * device is sitting underneath and thus bandwidth sharing is
4901 * not an issue.
4902 *
4903 * The register has several 3 bit fields, which indicates a
4904 * multiplier applied to the base amount of prefetching the
4905 * chip would do. These fields are at:
4906 *
4907 * 15:13 --- ReRead Primary Bus
4908 * 12:10 --- FirstRead Primary Bus
4909 * 09:07 --- ReRead Secondary Bus
4910 * 06:04 --- FirstRead Secondary Bus
4911 *
4912 * Bits 03:00 control which REQ/GNT pairs the prefetch settings
4913 * get enabled on. Bit 3 is a grouped enabler which controls
4914 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
4915 * the individual REQ/GNT pairs [2:0].
4916 */
4917 pci_write_config_word(pdev, 0x52,
4918 (0x7 << 13) |
4919 (0x7 << 10) |
4920 (0x7 << 7) |
4921 (0x7 << 4) |
4922 (0xf << 0));
4923
4924 /* Force cacheline size to 0x8 */
4925 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4926
4927 /* Force latency timer to maximum setting so Cassini can
4928 * sit on the bus as long as it likes.
4929 */
4930 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
4931 }
4932
4933 static int __devinit cas_init_one(struct pci_dev *pdev,
4934 const struct pci_device_id *ent)
4935 {
4936 static int cas_version_printed = 0;
4937 unsigned long casreg_len;
4938 struct net_device *dev;
4939 struct cas *cp;
4940 int i, err, pci_using_dac;
4941 u16 pci_cmd;
4942 u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
4943 DECLARE_MAC_BUF(mac);
4944
4945 if (cas_version_printed++ == 0)
4946 printk(KERN_INFO "%s", version);
4947
4948 err = pci_enable_device(pdev);
4949 if (err) {
4950 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
4951 return err;
4952 }
4953
4954 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4955 dev_err(&pdev->dev, "Cannot find proper PCI device "
4956 "base address, aborting.\n");
4957 err = -ENODEV;
4958 goto err_out_disable_pdev;
4959 }
4960
4961 dev = alloc_etherdev(sizeof(*cp));
4962 if (!dev) {
4963 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
4964 err = -ENOMEM;
4965 goto err_out_disable_pdev;
4966 }
4967 SET_NETDEV_DEV(dev, &pdev->dev);
4968
4969 err = pci_request_regions(pdev, dev->name);
4970 if (err) {
4971 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
4972 goto err_out_free_netdev;
4973 }
4974 pci_set_master(pdev);
4975
4976 /* we must always turn on parity response or else parity
4977 * doesn't get generated properly. disable SERR/PERR as well.
4978 * in addition, we want to turn MWI on.
4979 */
4980 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4981 pci_cmd &= ~PCI_COMMAND_SERR;
4982 pci_cmd |= PCI_COMMAND_PARITY;
4983 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4984 if (pci_try_set_mwi(pdev))
4985 printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
4986 pci_name(pdev));
4987
4988 cas_program_bridge(pdev);
4989
4990 /*
4991 * On some architectures, the default cache line size set
4992 * by pci_try_set_mwi reduces perforamnce. We have to increase
4993 * it for this case. To start, we'll print some configuration
4994 * data.
4995 */
4996 #if 1
4997 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
4998 &orig_cacheline_size);
4999 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
5000 cas_cacheline_size =
5001 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
5002 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
5003 if (pci_write_config_byte(pdev,
5004 PCI_CACHE_LINE_SIZE,
5005 cas_cacheline_size)) {
5006 dev_err(&pdev->dev, "Could not set PCI cache "
5007 "line size\n");
5008 goto err_write_cacheline;
5009 }
5010 }
5011 #endif
5012
5013
5014 /* Configure DMA attributes. */
5015 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5016 pci_using_dac = 1;
5017 err = pci_set_consistent_dma_mask(pdev,
5018 DMA_64BIT_MASK);
5019 if (err < 0) {
5020 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
5021 "for consistent allocations\n");
5022 goto err_out_free_res;
5023 }
5024
5025 } else {
5026 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
5027 if (err) {
5028 dev_err(&pdev->dev, "No usable DMA configuration, "
5029 "aborting.\n");
5030 goto err_out_free_res;
5031 }
5032 pci_using_dac = 0;
5033 }
5034
5035 casreg_len = pci_resource_len(pdev, 0);
5036
5037 cp = netdev_priv(dev);
5038 cp->pdev = pdev;
5039 #if 1
5040 /* A value of 0 indicates we never explicitly set it */
5041 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
5042 #endif
5043 cp->dev = dev;
5044 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
5045 cassini_debug;
5046
5047 cp->link_transition = LINK_TRANSITION_UNKNOWN;
5048 cp->link_transition_jiffies_valid = 0;
5049
5050 spin_lock_init(&cp->lock);
5051 spin_lock_init(&cp->rx_inuse_lock);
5052 spin_lock_init(&cp->rx_spare_lock);
5053 for (i = 0; i < N_TX_RINGS; i++) {
5054 spin_lock_init(&cp->stat_lock[i]);
5055 spin_lock_init(&cp->tx_lock[i]);
5056 }
5057 spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
5058 mutex_init(&cp->pm_mutex);
5059
5060 init_timer(&cp->link_timer);
5061 cp->link_timer.function = cas_link_timer;
5062 cp->link_timer.data = (unsigned long) cp;
5063
5064 #if 1
5065 /* Just in case the implementation of atomic operations
5066 * change so that an explicit initialization is necessary.
5067 */
5068 atomic_set(&cp->reset_task_pending, 0);
5069 atomic_set(&cp->reset_task_pending_all, 0);
5070 atomic_set(&cp->reset_task_pending_spare, 0);
5071 atomic_set(&cp->reset_task_pending_mtu, 0);
5072 #endif
5073 INIT_WORK(&cp->reset_task, cas_reset_task);
5074
5075 /* Default link parameters */
5076 if (link_mode >= 0 && link_mode <= 6)
5077 cp->link_cntl = link_modes[link_mode];
5078 else
5079 cp->link_cntl = BMCR_ANENABLE;
5080 cp->lstate = link_down;
5081 cp->link_transition = LINK_TRANSITION_LINK_DOWN;
5082 netif_carrier_off(cp->dev);
5083 cp->timer_ticks = 0;
5084
5085 /* give us access to cassini registers */
5086 cp->regs = pci_iomap(pdev, 0, casreg_len);
5087 if (!cp->regs) {
5088 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
5089 goto err_out_free_res;
5090 }
5091 cp->casreg_len = casreg_len;
5092
5093 pci_save_state(pdev);
5094 cas_check_pci_invariants(cp);
5095 cas_hard_reset(cp);
5096 cas_reset(cp, 0);
5097 if (cas_check_invariants(cp))
5098 goto err_out_iounmap;
5099
5100 cp->init_block = (struct cas_init_block *)
5101 pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
5102 &cp->block_dvma);
5103 if (!cp->init_block) {
5104 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
5105 goto err_out_iounmap;
5106 }
5107
5108 for (i = 0; i < N_TX_RINGS; i++)
5109 cp->init_txds[i] = cp->init_block->txds[i];
5110
5111 for (i = 0; i < N_RX_DESC_RINGS; i++)
5112 cp->init_rxds[i] = cp->init_block->rxds[i];
5113
5114 for (i = 0; i < N_RX_COMP_RINGS; i++)
5115 cp->init_rxcs[i] = cp->init_block->rxcs[i];
5116
5117 for (i = 0; i < N_RX_FLOWS; i++)
5118 skb_queue_head_init(&cp->rx_flows[i]);
5119
5120 dev->open = cas_open;
5121 dev->stop = cas_close;
5122 dev->hard_start_xmit = cas_start_xmit;
5123 dev->get_stats = cas_get_stats;
5124 dev->set_multicast_list = cas_set_multicast;
5125 dev->do_ioctl = cas_ioctl;
5126 dev->ethtool_ops = &cas_ethtool_ops;
5127 dev->tx_timeout = cas_tx_timeout;
5128 dev->watchdog_timeo = CAS_TX_TIMEOUT;
5129 dev->change_mtu = cas_change_mtu;
5130 #ifdef USE_NAPI
5131 netif_napi_add(dev, &cp->napi, cas_poll, 64);
5132 #endif
5133 #ifdef CONFIG_NET_POLL_CONTROLLER
5134 dev->poll_controller = cas_netpoll;
5135 #endif
5136 dev->irq = pdev->irq;
5137 dev->dma = 0;
5138
5139 /* Cassini features. */
5140 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
5141 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5142
5143 if (pci_using_dac)
5144 dev->features |= NETIF_F_HIGHDMA;
5145
5146 if (register_netdev(dev)) {
5147 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5148 goto err_out_free_consistent;
5149 }
5150
5151 i = readl(cp->regs + REG_BIM_CFG);
5152 printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5153 "Ethernet[%d] %s\n", dev->name,
5154 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
5155 (i & BIM_CFG_32BIT) ? "32" : "64",
5156 (i & BIM_CFG_66MHZ) ? "66" : "33",
5157 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq,
5158 print_mac(mac, dev->dev_addr));
5159
5160 pci_set_drvdata(pdev, dev);
5161 cp->hw_running = 1;
5162 cas_entropy_reset(cp);
5163 cas_phy_init(cp);
5164 cas_begin_auto_negotiation(cp, NULL);
5165 return 0;
5166
5167 err_out_free_consistent:
5168 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5169 cp->init_block, cp->block_dvma);
5170
5171 err_out_iounmap:
5172 mutex_lock(&cp->pm_mutex);
5173 if (cp->hw_running)
5174 cas_shutdown(cp);
5175 mutex_unlock(&cp->pm_mutex);
5176
5177 pci_iounmap(pdev, cp->regs);
5178
5179
5180 err_out_free_res:
5181 pci_release_regions(pdev);
5182
5183 err_write_cacheline:
5184 /* Try to restore it in case the error occured after we
5185 * set it.
5186 */
5187 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
5188
5189 err_out_free_netdev:
5190 free_netdev(dev);
5191
5192 err_out_disable_pdev:
5193 pci_disable_device(pdev);
5194 pci_set_drvdata(pdev, NULL);
5195 return -ENODEV;
5196 }
5197
5198 static void __devexit cas_remove_one(struct pci_dev *pdev)
5199 {
5200 struct net_device *dev = pci_get_drvdata(pdev);
5201 struct cas *cp;
5202 if (!dev)
5203 return;
5204
5205 cp = netdev_priv(dev);
5206 unregister_netdev(dev);
5207
5208 mutex_lock(&cp->pm_mutex);
5209 flush_scheduled_work();
5210 if (cp->hw_running)
5211 cas_shutdown(cp);
5212 mutex_unlock(&cp->pm_mutex);
5213
5214 #if 1
5215 if (cp->orig_cacheline_size) {
5216 /* Restore the cache line size if we had modified
5217 * it.
5218 */
5219 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
5220 cp->orig_cacheline_size);
5221 }
5222 #endif
5223 pci_free_consistent(pdev, sizeof(struct cas_init_block),
5224 cp->init_block, cp->block_dvma);
5225 pci_iounmap(pdev, cp->regs);
5226 free_netdev(dev);
5227 pci_release_regions(pdev);
5228 pci_disable_device(pdev);
5229 pci_set_drvdata(pdev, NULL);
5230 }
5231
5232 #ifdef CONFIG_PM
5233 static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
5234 {
5235 struct net_device *dev = pci_get_drvdata(pdev);
5236 struct cas *cp = netdev_priv(dev);
5237 unsigned long flags;
5238
5239 mutex_lock(&cp->pm_mutex);
5240
5241 /* If the driver is opened, we stop the DMA */
5242 if (cp->opened) {
5243 netif_device_detach(dev);
5244
5245 cas_lock_all_save(cp, flags);
5246
5247 /* We can set the second arg of cas_reset to 0
5248 * because on resume, we'll call cas_init_hw with
5249 * its second arg set so that autonegotiation is
5250 * restarted.
5251 */
5252 cas_reset(cp, 0);
5253 cas_clean_rings(cp);
5254 cas_unlock_all_restore(cp, flags);
5255 }
5256
5257 if (cp->hw_running)
5258 cas_shutdown(cp);
5259 mutex_unlock(&cp->pm_mutex);
5260
5261 return 0;
5262 }
5263
5264 static int cas_resume(struct pci_dev *pdev)
5265 {
5266 struct net_device *dev = pci_get_drvdata(pdev);
5267 struct cas *cp = netdev_priv(dev);
5268
5269 printk(KERN_INFO "%s: resuming\n", dev->name);
5270
5271 mutex_lock(&cp->pm_mutex);
5272 cas_hard_reset(cp);
5273 if (cp->opened) {
5274 unsigned long flags;
5275 cas_lock_all_save(cp, flags);
5276 cas_reset(cp, 0);
5277 cp->hw_running = 1;
5278 cas_clean_rings(cp);
5279 cas_init_hw(cp, 1);
5280 cas_unlock_all_restore(cp, flags);
5281
5282 netif_device_attach(dev);
5283 }
5284 mutex_unlock(&cp->pm_mutex);
5285 return 0;
5286 }
5287 #endif /* CONFIG_PM */
5288
5289 static struct pci_driver cas_driver = {
5290 .name = DRV_MODULE_NAME,
5291 .id_table = cas_pci_tbl,
5292 .probe = cas_init_one,
5293 .remove = __devexit_p(cas_remove_one),
5294 #ifdef CONFIG_PM
5295 .suspend = cas_suspend,
5296 .resume = cas_resume
5297 #endif
5298 };
5299
5300 static int __init cas_init(void)
5301 {
5302 if (linkdown_timeout > 0)
5303 link_transition_timeout = linkdown_timeout * HZ;
5304 else
5305 link_transition_timeout = 0;
5306
5307 return pci_register_driver(&cas_driver);
5308 }
5309
5310 static void __exit cas_cleanup(void)
5311 {
5312 pci_unregister_driver(&cas_driver);
5313 }
5314
5315 module_init(cas_init);
5316 module_exit(cas_cleanup);
Linux with added FPC-III support