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niu: panic on reset
[linux/fpc-iii.git] / drivers / net / tulip / uli526x.c
blobe9e628621639b6d5d8ceaf850086bf8da9587ab1
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
18
19 #include <linux/module.h>
20
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/bitops.h>
38
39 #include <asm/processor.h>
40 #include <asm/io.h>
41 #include <asm/dma.h>
42 #include <asm/uaccess.h>
43
44
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
58 #define CR0_DEFAULT 0
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
67
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
73
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
92 #define CR9_SRCS 0x1
93 #define CR9_SRCLK 0x2
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
100
101 #define PHY_POWER_DOWN 0x800
102
103 #define SROM_V41_CODE 0x14
104
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
112
113 /* Structure/enum declaration ------------------------------- */
114 struct tx_desc {
115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
119
120 struct rx_desc {
121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
125
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
188 u8 init;
189 };
190
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196 };
197
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202 };
203
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
213
214 /* For module input parameter */
215 static int debug;
216 static u32 cr6set;
217 static int mode = 8;
218
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 #ifdef CONFIG_NET_POLL_CONTROLLER
229 static void uli526x_poll(struct net_device *dev);
230 #endif
231 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
232 static void allocate_rx_buffer(struct uli526x_board_info *);
233 static void update_cr6(u32, unsigned long);
234 static void send_filter_frame(struct net_device *, int);
235 static u16 phy_read(unsigned long, u8, u8, u32);
236 static u16 phy_readby_cr10(unsigned long, u8, u8);
237 static void phy_write(unsigned long, u8, u8, u16, u32);
238 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
239 static void phy_write_1bit(unsigned long, u32, u32);
240 static u16 phy_read_1bit(unsigned long, u32);
241 static u8 uli526x_sense_speed(struct uli526x_board_info *);
242 static void uli526x_process_mode(struct uli526x_board_info *);
243 static void uli526x_timer(unsigned long);
244 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
245 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
246 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
247 static void uli526x_dynamic_reset(struct net_device *);
248 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
249 static void uli526x_init(struct net_device *);
250 static void uli526x_set_phyxcer(struct uli526x_board_info *);
251
252 /* ULI526X network board routine ---------------------------- */
253
254 /*
255 * Search ULI526X board, allocate space and register it
256 */
257
258 static int __devinit uli526x_init_one (struct pci_dev *pdev,
259 const struct pci_device_id *ent)
260 {
261 struct uli526x_board_info *db; /* board information structure */
262 struct net_device *dev;
263 int i, err;
264 DECLARE_MAC_BUF(mac);
265
266 ULI526X_DBUG(0, "uli526x_init_one()", 0);
267
268 if (!printed_version++)
269 printk(version);
270
271 /* Init network device */
272 dev = alloc_etherdev(sizeof(*db));
273 if (dev == NULL)
274 return -ENOMEM;
275 SET_NETDEV_DEV(dev, &pdev->dev);
276
277 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
278 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
279 err = -ENODEV;
280 goto err_out_free;
281 }
282
283 /* Enable Master/IO access, Disable memory access */
284 err = pci_enable_device(pdev);
285 if (err)
286 goto err_out_free;
287
288 if (!pci_resource_start(pdev, 0)) {
289 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
290 err = -ENODEV;
291 goto err_out_disable;
292 }
293
294 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
295 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
296 err = -ENODEV;
297 goto err_out_disable;
298 }
299
300 if (pci_request_regions(pdev, DRV_NAME)) {
301 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
302 err = -ENODEV;
303 goto err_out_disable;
304 }
305
306 /* Init system & device */
307 db = netdev_priv(dev);
308
309 /* Allocate Tx/Rx descriptor memory */
310 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
311 if(db->desc_pool_ptr == NULL)
312 {
313 err = -ENOMEM;
314 goto err_out_nomem;
315 }
316 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
317 if(db->buf_pool_ptr == NULL)
318 {
319 err = -ENOMEM;
320 goto err_out_nomem;
321 }
322
323 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
324 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
325 db->buf_pool_start = db->buf_pool_ptr;
326 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
327
328 db->chip_id = ent->driver_data;
329 db->ioaddr = pci_resource_start(pdev, 0);
330
331 db->pdev = pdev;
332 db->init = 1;
333
334 dev->base_addr = db->ioaddr;
335 dev->irq = pdev->irq;
336 pci_set_drvdata(pdev, dev);
337
338 /* Register some necessary functions */
339 dev->open = &uli526x_open;
340 dev->hard_start_xmit = &uli526x_start_xmit;
341 dev->stop = &uli526x_stop;
342 dev->get_stats = &uli526x_get_stats;
343 dev->set_multicast_list = &uli526x_set_filter_mode;
344 dev->ethtool_ops = &netdev_ethtool_ops;
345 #ifdef CONFIG_NET_POLL_CONTROLLER
346 dev->poll_controller = &uli526x_poll;
347 #endif
348 spin_lock_init(&db->lock);
349
350
351 /* read 64 word srom data */
352 for (i = 0; i < 64; i++)
353 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
354
355 /* Set Node address */
356 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
357 {
358 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
359 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
360 outl(0, db->ioaddr + DCR14); //Clear reset port
361 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
362 outl(0, db->ioaddr + DCR14); //Clear reset port
363 outl(0, db->ioaddr + DCR13); //Clear CR13
364 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
365 //Read MAC address from CR14
366 for (i = 0; i < 6; i++)
367 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
368 //Read end
369 outl(0, db->ioaddr + DCR13); //Clear CR13
370 outl(0, db->ioaddr + DCR0); //Clear CR0
371 udelay(10);
372 }
373 else /*Exist SROM*/
374 {
375 for (i = 0; i < 6; i++)
376 dev->dev_addr[i] = db->srom[20 + i];
377 }
378 err = register_netdev (dev);
379 if (err)
380 goto err_out_res;
381
382 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %s, irq %d.\n",
383 dev->name,ent->driver_data >> 16,pci_name(pdev),
384 print_mac(mac, dev->dev_addr), dev->irq);
385
386 pci_set_master(pdev);
387
388 return 0;
389
390 err_out_res:
391 pci_release_regions(pdev);
392 err_out_nomem:
393 if(db->desc_pool_ptr)
394 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
395 db->desc_pool_ptr, db->desc_pool_dma_ptr);
396
397 if(db->buf_pool_ptr != NULL)
398 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
399 db->buf_pool_ptr, db->buf_pool_dma_ptr);
400 err_out_disable:
401 pci_disable_device(pdev);
402 err_out_free:
403 pci_set_drvdata(pdev, NULL);
404 free_netdev(dev);
405
406 return err;
407 }
408
409
410 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
411 {
412 struct net_device *dev = pci_get_drvdata(pdev);
413 struct uli526x_board_info *db = netdev_priv(dev);
414
415 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
416
417 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
418 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
419 db->desc_pool_dma_ptr);
420 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
421 db->buf_pool_ptr, db->buf_pool_dma_ptr);
422 unregister_netdev(dev);
423 pci_release_regions(pdev);
424 free_netdev(dev); /* free board information */
425 pci_set_drvdata(pdev, NULL);
426 pci_disable_device(pdev);
427 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
428 }
429
430
431 /*
432 * Open the interface.
433 * The interface is opened whenever "ifconfig" activates it.
434 */
435
436 static int uli526x_open(struct net_device *dev)
437 {
438 int ret;
439 struct uli526x_board_info *db = netdev_priv(dev);
440
441 ULI526X_DBUG(0, "uli526x_open", 0);
442
443 /* system variable init */
444 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
445 db->tx_packet_cnt = 0;
446 db->rx_avail_cnt = 0;
447 db->link_failed = 1;
448 netif_carrier_off(dev);
449 db->wait_reset = 0;
450
451 db->NIC_capability = 0xf; /* All capability*/
452 db->PHY_reg4 = 0x1e0;
453
454 /* CR6 operation mode decision */
455 db->cr6_data |= ULI526X_TXTH_256;
456 db->cr0_data = CR0_DEFAULT;
457
458 /* Initialize ULI526X board */
459 uli526x_init(dev);
460
461 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
462 if (ret)
463 return ret;
464
465 /* Active System Interface */
466 netif_wake_queue(dev);
467
468 /* set and active a timer process */
469 init_timer(&db->timer);
470 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
471 db->timer.data = (unsigned long)dev;
472 db->timer.function = &uli526x_timer;
473 add_timer(&db->timer);
474
475 return 0;
476 }
477
478
479 /* Initialize ULI526X board
480 * Reset ULI526X board
481 * Initialize TX/Rx descriptor chain structure
482 * Send the set-up frame
483 * Enable Tx/Rx machine
484 */
485
486 static void uli526x_init(struct net_device *dev)
487 {
488 struct uli526x_board_info *db = netdev_priv(dev);
489 unsigned long ioaddr = db->ioaddr;
490 u8 phy_tmp;
491 u8 timeout;
492 u16 phy_value;
493 u16 phy_reg_reset;
494
495
496 ULI526X_DBUG(0, "uli526x_init()", 0);
497
498 /* Reset M526x MAC controller */
499 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
500 udelay(100);
501 outl(db->cr0_data, ioaddr + DCR0);
502 udelay(5);
503
504 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
505 db->phy_addr = 1;
506 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
507 {
508 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
509 if(phy_value != 0xffff&&phy_value!=0)
510 {
511 db->phy_addr = phy_tmp;
512 break;
513 }
514 }
515 if(phy_tmp == 32)
516 printk(KERN_WARNING "Can not find the phy address!!!");
517 /* Parser SROM and media mode */
518 db->media_mode = uli526x_media_mode;
519
520 /* phyxcer capability setting */
521 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
522 phy_reg_reset = (phy_reg_reset | 0x8000);
523 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
524
525 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
526 * functions") or phy data sheet for details on phy reset
527 */
528 udelay(500);
529 timeout = 10;
530 while (timeout-- &&
531 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
532 udelay(100);
533
534 /* Process Phyxcer Media Mode */
535 uli526x_set_phyxcer(db);
536
537 /* Media Mode Process */
538 if ( !(db->media_mode & ULI526X_AUTO) )
539 db->op_mode = db->media_mode; /* Force Mode */
540
541 /* Initialize Transmit/Receive decriptor and CR3/4 */
542 uli526x_descriptor_init(db, ioaddr);
543
544 /* Init CR6 to program M526X operation */
545 update_cr6(db->cr6_data, ioaddr);
546
547 /* Send setup frame */
548 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
549
550 /* Init CR7, interrupt active bit */
551 db->cr7_data = CR7_DEFAULT;
552 outl(db->cr7_data, ioaddr + DCR7);
553
554 /* Init CR15, Tx jabber and Rx watchdog timer */
555 outl(db->cr15_data, ioaddr + DCR15);
556
557 /* Enable ULI526X Tx/Rx function */
558 db->cr6_data |= CR6_RXSC | CR6_TXSC;
559 update_cr6(db->cr6_data, ioaddr);
560 }
561
562
563 /*
564 * Hardware start transmission.
565 * Send a packet to media from the upper layer.
566 */
567
568 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
569 {
570 struct uli526x_board_info *db = netdev_priv(dev);
571 struct tx_desc *txptr;
572 unsigned long flags;
573
574 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
575
576 /* Resource flag check */
577 netif_stop_queue(dev);
578
579 /* Too large packet check */
580 if (skb->len > MAX_PACKET_SIZE) {
581 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
582 dev_kfree_skb(skb);
583 return 0;
584 }
585
586 spin_lock_irqsave(&db->lock, flags);
587
588 /* No Tx resource check, it never happen nromally */
589 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
590 spin_unlock_irqrestore(&db->lock, flags);
591 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
592 return 1;
593 }
594
595 /* Disable NIC interrupt */
596 outl(0, dev->base_addr + DCR7);
597
598 /* transmit this packet */
599 txptr = db->tx_insert_ptr;
600 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
601 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
602
603 /* Point to next transmit free descriptor */
604 db->tx_insert_ptr = txptr->next_tx_desc;
605
606 /* Transmit Packet Process */
607 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
608 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
609 db->tx_packet_cnt++; /* Ready to send */
610 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
611 dev->trans_start = jiffies; /* saved time stamp */
612 }
613
614 /* Tx resource check */
615 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
616 netif_wake_queue(dev);
617
618 /* Restore CR7 to enable interrupt */
619 spin_unlock_irqrestore(&db->lock, flags);
620 outl(db->cr7_data, dev->base_addr + DCR7);
621
622 /* free this SKB */
623 dev_kfree_skb(skb);
624
625 return 0;
626 }
627
628
629 /*
630 * Stop the interface.
631 * The interface is stopped when it is brought.
632 */
633
634 static int uli526x_stop(struct net_device *dev)
635 {
636 struct uli526x_board_info *db = netdev_priv(dev);
637 unsigned long ioaddr = dev->base_addr;
638
639 ULI526X_DBUG(0, "uli526x_stop", 0);
640
641 /* disable system */
642 netif_stop_queue(dev);
643
644 /* deleted timer */
645 del_timer_sync(&db->timer);
646
647 /* Reset & stop ULI526X board */
648 outl(ULI526X_RESET, ioaddr + DCR0);
649 udelay(5);
650 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
651
652 /* free interrupt */
653 free_irq(dev->irq, dev);
654
655 /* free allocated rx buffer */
656 uli526x_free_rxbuffer(db);
657
658 #if 0
659 /* show statistic counter */
660 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
661 db->tx_fifo_underrun, db->tx_excessive_collision,
662 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
663 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
664 db->reset_fatal, db->reset_TXtimeout);
665 #endif
666
667 return 0;
668 }
669
670
671 /*
672 * M5261/M5263 insterrupt handler
673 * receive the packet to upper layer, free the transmitted packet
674 */
675
676 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
677 {
678 struct net_device *dev = dev_id;
679 struct uli526x_board_info *db = netdev_priv(dev);
680 unsigned long ioaddr = dev->base_addr;
681 unsigned long flags;
682
683 spin_lock_irqsave(&db->lock, flags);
684 outl(0, ioaddr + DCR7);
685
686 /* Got ULI526X status */
687 db->cr5_data = inl(ioaddr + DCR5);
688 outl(db->cr5_data, ioaddr + DCR5);
689 if ( !(db->cr5_data & 0x180c1) ) {
690 /* Restore CR7 to enable interrupt mask */
691 outl(db->cr7_data, ioaddr + DCR7);
692 spin_unlock_irqrestore(&db->lock, flags);
693 return IRQ_HANDLED;
694 }
695
696 /* Check system status */
697 if (db->cr5_data & 0x2000) {
698 /* system bus error happen */
699 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
700 db->reset_fatal++;
701 db->wait_reset = 1; /* Need to RESET */
702 spin_unlock_irqrestore(&db->lock, flags);
703 return IRQ_HANDLED;
704 }
705
706 /* Received the coming packet */
707 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
708 uli526x_rx_packet(dev, db);
709
710 /* reallocate rx descriptor buffer */
711 if (db->rx_avail_cnt<RX_DESC_CNT)
712 allocate_rx_buffer(db);
713
714 /* Free the transmitted descriptor */
715 if ( db->cr5_data & 0x01)
716 uli526x_free_tx_pkt(dev, db);
717
718 /* Restore CR7 to enable interrupt mask */
719 outl(db->cr7_data, ioaddr + DCR7);
720
721 spin_unlock_irqrestore(&db->lock, flags);
722 return IRQ_HANDLED;
723 }
724
725 #ifdef CONFIG_NET_POLL_CONTROLLER
726 static void uli526x_poll(struct net_device *dev)
727 {
728 /* ISR grabs the irqsave lock, so this should be safe */
729 uli526x_interrupt(dev->irq, dev);
730 }
731 #endif
732
733 /*
734 * Free TX resource after TX complete
735 */
736
737 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
738 {
739 struct tx_desc *txptr;
740 u32 tdes0;
741
742 txptr = db->tx_remove_ptr;
743 while(db->tx_packet_cnt) {
744 tdes0 = le32_to_cpu(txptr->tdes0);
745 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
746 if (tdes0 & 0x80000000)
747 break;
748
749 /* A packet sent completed */
750 db->tx_packet_cnt--;
751 db->stats.tx_packets++;
752
753 /* Transmit statistic counter */
754 if ( tdes0 != 0x7fffffff ) {
755 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
756 db->stats.collisions += (tdes0 >> 3) & 0xf;
757 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
758 if (tdes0 & TDES0_ERR_MASK) {
759 db->stats.tx_errors++;
760 if (tdes0 & 0x0002) { /* UnderRun */
761 db->tx_fifo_underrun++;
762 if ( !(db->cr6_data & CR6_SFT) ) {
763 db->cr6_data = db->cr6_data | CR6_SFT;
764 update_cr6(db->cr6_data, db->ioaddr);
765 }
766 }
767 if (tdes0 & 0x0100)
768 db->tx_excessive_collision++;
769 if (tdes0 & 0x0200)
770 db->tx_late_collision++;
771 if (tdes0 & 0x0400)
772 db->tx_no_carrier++;
773 if (tdes0 & 0x0800)
774 db->tx_loss_carrier++;
775 if (tdes0 & 0x4000)
776 db->tx_jabber_timeout++;
777 }
778 }
779
780 txptr = txptr->next_tx_desc;
781 }/* End of while */
782
783 /* Update TX remove pointer to next */
784 db->tx_remove_ptr = txptr;
785
786 /* Resource available check */
787 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
788 netif_wake_queue(dev); /* Active upper layer, send again */
789 }
790
791
792 /*
793 * Receive the come packet and pass to upper layer
794 */
795
796 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
797 {
798 struct rx_desc *rxptr;
799 struct sk_buff *skb;
800 int rxlen;
801 u32 rdes0;
802
803 rxptr = db->rx_ready_ptr;
804
805 while(db->rx_avail_cnt) {
806 rdes0 = le32_to_cpu(rxptr->rdes0);
807 if (rdes0 & 0x80000000) /* packet owner check */
808 {
809 break;
810 }
811
812 db->rx_avail_cnt--;
813 db->interval_rx_cnt++;
814
815 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
816 if ( (rdes0 & 0x300) != 0x300) {
817 /* A packet without First/Last flag */
818 /* reuse this SKB */
819 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
820 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
821 } else {
822 /* A packet with First/Last flag */
823 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
824
825 /* error summary bit check */
826 if (rdes0 & 0x8000) {
827 /* This is a error packet */
828 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
829 db->stats.rx_errors++;
830 if (rdes0 & 1)
831 db->stats.rx_fifo_errors++;
832 if (rdes0 & 2)
833 db->stats.rx_crc_errors++;
834 if (rdes0 & 0x80)
835 db->stats.rx_length_errors++;
836 }
837
838 if ( !(rdes0 & 0x8000) ||
839 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
840 skb = rxptr->rx_skb_ptr;
841
842 /* Good packet, send to upper layer */
843 /* Shorst packet used new SKB */
844 if ( (rxlen < RX_COPY_SIZE) &&
845 ( (skb = dev_alloc_skb(rxlen + 2) )
846 != NULL) ) {
847 /* size less than COPY_SIZE, allocate a rxlen SKB */
848 skb_reserve(skb, 2); /* 16byte align */
849 memcpy(skb_put(skb, rxlen),
850 skb_tail_pointer(rxptr->rx_skb_ptr),
851 rxlen);
852 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
853 } else
854 skb_put(skb, rxlen);
855
856 skb->protocol = eth_type_trans(skb, dev);
857 netif_rx(skb);
858 dev->last_rx = jiffies;
859 db->stats.rx_packets++;
860 db->stats.rx_bytes += rxlen;
861
862 } else {
863 /* Reuse SKB buffer when the packet is error */
864 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
865 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
866 }
867 }
868
869 rxptr = rxptr->next_rx_desc;
870 }
871
872 db->rx_ready_ptr = rxptr;
873 }
874
875
876 /*
877 * Get statistics from driver.
878 */
879
880 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
881 {
882 struct uli526x_board_info *db = netdev_priv(dev);
883
884 ULI526X_DBUG(0, "uli526x_get_stats", 0);
885 return &db->stats;
886 }
887
888
889 /*
890 * Set ULI526X multicast address
891 */
892
893 static void uli526x_set_filter_mode(struct net_device * dev)
894 {
895 struct uli526x_board_info *db = dev->priv;
896 unsigned long flags;
897
898 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
899 spin_lock_irqsave(&db->lock, flags);
900
901 if (dev->flags & IFF_PROMISC) {
902 ULI526X_DBUG(0, "Enable PROM Mode", 0);
903 db->cr6_data |= CR6_PM | CR6_PBF;
904 update_cr6(db->cr6_data, db->ioaddr);
905 spin_unlock_irqrestore(&db->lock, flags);
906 return;
907 }
908
909 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
910 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
911 db->cr6_data &= ~(CR6_PM | CR6_PBF);
912 db->cr6_data |= CR6_PAM;
913 spin_unlock_irqrestore(&db->lock, flags);
914 return;
915 }
916
917 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
918 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
919 spin_unlock_irqrestore(&db->lock, flags);
920 }
921
922 static void
923 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
924 {
925 ecmd->supported = (SUPPORTED_10baseT_Half |
926 SUPPORTED_10baseT_Full |
927 SUPPORTED_100baseT_Half |
928 SUPPORTED_100baseT_Full |
929 SUPPORTED_Autoneg |
930 SUPPORTED_MII);
931
932 ecmd->advertising = (ADVERTISED_10baseT_Half |
933 ADVERTISED_10baseT_Full |
934 ADVERTISED_100baseT_Half |
935 ADVERTISED_100baseT_Full |
936 ADVERTISED_Autoneg |
937 ADVERTISED_MII);
938
939
940 ecmd->port = PORT_MII;
941 ecmd->phy_address = db->phy_addr;
942
943 ecmd->transceiver = XCVR_EXTERNAL;
944
945 ecmd->speed = 10;
946 ecmd->duplex = DUPLEX_HALF;
947
948 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
949 {
950 ecmd->speed = 100;
951 }
952 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
953 {
954 ecmd->duplex = DUPLEX_FULL;
955 }
956 if(db->link_failed)
957 {
958 ecmd->speed = -1;
959 ecmd->duplex = -1;
960 }
961
962 if (db->media_mode & ULI526X_AUTO)
963 {
964 ecmd->autoneg = AUTONEG_ENABLE;
965 }
966 }
967
968 static void netdev_get_drvinfo(struct net_device *dev,
969 struct ethtool_drvinfo *info)
970 {
971 struct uli526x_board_info *np = netdev_priv(dev);
972
973 strcpy(info->driver, DRV_NAME);
974 strcpy(info->version, DRV_VERSION);
975 if (np->pdev)
976 strcpy(info->bus_info, pci_name(np->pdev));
977 else
978 sprintf(info->bus_info, "EISA 0x%lx %d",
979 dev->base_addr, dev->irq);
980 }
981
982 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
983 struct uli526x_board_info *np = netdev_priv(dev);
984
985 ULi_ethtool_gset(np, cmd);
986
987 return 0;
988 }
989
990 static u32 netdev_get_link(struct net_device *dev) {
991 struct uli526x_board_info *np = netdev_priv(dev);
992
993 if(np->link_failed)
994 return 0;
995 else
996 return 1;
997 }
998
999 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1000 {
1001 wol->supported = WAKE_PHY | WAKE_MAGIC;
1002 wol->wolopts = 0;
1003 }
1004
1005 static const struct ethtool_ops netdev_ethtool_ops = {
1006 .get_drvinfo = netdev_get_drvinfo,
1007 .get_settings = netdev_get_settings,
1008 .get_link = netdev_get_link,
1009 .get_wol = uli526x_get_wol,
1010 };
1011
1012 /*
1013 * A periodic timer routine
1014 * Dynamic media sense, allocate Rx buffer...
1015 */
1016
1017 static void uli526x_timer(unsigned long data)
1018 {
1019 u32 tmp_cr8;
1020 unsigned char tmp_cr12=0;
1021 struct net_device *dev = (struct net_device *) data;
1022 struct uli526x_board_info *db = netdev_priv(dev);
1023 unsigned long flags;
1024 u8 TmpSpeed=10;
1025
1026 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1027 spin_lock_irqsave(&db->lock, flags);
1028
1029
1030 /* Dynamic reset ULI526X : system error or transmit time-out */
1031 tmp_cr8 = inl(db->ioaddr + DCR8);
1032 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1033 db->reset_cr8++;
1034 db->wait_reset = 1;
1035 }
1036 db->interval_rx_cnt = 0;
1037
1038 /* TX polling kick monitor */
1039 if ( db->tx_packet_cnt &&
1040 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1041 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1042
1043 // TX Timeout
1044 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1045 db->reset_TXtimeout++;
1046 db->wait_reset = 1;
1047 printk( "%s: Tx timeout - resetting\n",
1048 dev->name);
1049 }
1050 }
1051
1052 if (db->wait_reset) {
1053 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1054 db->reset_count++;
1055 uli526x_dynamic_reset(dev);
1056 db->timer.expires = ULI526X_TIMER_WUT;
1057 add_timer(&db->timer);
1058 spin_unlock_irqrestore(&db->lock, flags);
1059 return;
1060 }
1061
1062 /* Link status check, Dynamic media type change */
1063 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1064 tmp_cr12 = 3;
1065
1066 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1067 /* Link Failed */
1068 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1069 netif_carrier_off(dev);
1070 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1071 db->link_failed = 1;
1072
1073 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1074 /* AUTO don't need */
1075 if ( !(db->media_mode & 0x8) )
1076 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1077
1078 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1079 if (db->media_mode & ULI526X_AUTO) {
1080 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1081 update_cr6(db->cr6_data, db->ioaddr);
1082 }
1083 } else
1084 if ((tmp_cr12 & 0x3) && db->link_failed) {
1085 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1086 db->link_failed = 0;
1087
1088 /* Auto Sense Speed */
1089 if ( (db->media_mode & ULI526X_AUTO) &&
1090 uli526x_sense_speed(db) )
1091 db->link_failed = 1;
1092 uli526x_process_mode(db);
1093
1094 if(db->link_failed==0)
1095 {
1096 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1097 {
1098 TmpSpeed = 100;
1099 }
1100 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1101 {
1102 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1103 }
1104 else
1105 {
1106 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1107 }
1108 netif_carrier_on(dev);
1109 }
1110 /* SHOW_MEDIA_TYPE(db->op_mode); */
1111 }
1112 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1113 {
1114 if(db->init==1)
1115 {
1116 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1117 netif_carrier_off(dev);
1118 }
1119 }
1120 db->init=0;
1121
1122 /* Timer active again */
1123 db->timer.expires = ULI526X_TIMER_WUT;
1124 add_timer(&db->timer);
1125 spin_unlock_irqrestore(&db->lock, flags);
1126 }
1127
1128
1129 /*
1130 * Stop ULI526X board
1131 * Free Tx/Rx allocated memory
1132 * Init system variable
1133 */
1134
1135 static void uli526x_reset_prepare(struct net_device *dev)
1136 {
1137 struct uli526x_board_info *db = netdev_priv(dev);
1138
1139 /* Sopt MAC controller */
1140 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1141 update_cr6(db->cr6_data, dev->base_addr);
1142 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1143 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1144
1145 /* Disable upper layer interface */
1146 netif_stop_queue(dev);
1147
1148 /* Free Rx Allocate buffer */
1149 uli526x_free_rxbuffer(db);
1150
1151 /* system variable init */
1152 db->tx_packet_cnt = 0;
1153 db->rx_avail_cnt = 0;
1154 db->link_failed = 1;
1155 db->init=1;
1156 db->wait_reset = 0;
1157 }
1158
1159
1160 /*
1161 * Dynamic reset the ULI526X board
1162 * Stop ULI526X board
1163 * Free Tx/Rx allocated memory
1164 * Reset ULI526X board
1165 * Re-initialize ULI526X board
1166 */
1167
1168 static void uli526x_dynamic_reset(struct net_device *dev)
1169 {
1170 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1171
1172 uli526x_reset_prepare(dev);
1173
1174 /* Re-initialize ULI526X board */
1175 uli526x_init(dev);
1176
1177 /* Restart upper layer interface */
1178 netif_wake_queue(dev);
1179 }
1180
1181
1182 #ifdef CONFIG_PM
1183
1184 /*
1185 * Suspend the interface.
1186 */
1187
1188 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1189 {
1190 struct net_device *dev = pci_get_drvdata(pdev);
1191 pci_power_t power_state;
1192 int err;
1193
1194 ULI526X_DBUG(0, "uli526x_suspend", 0);
1195
1196 if (!netdev_priv(dev))
1197 return 0;
1198
1199 pci_save_state(pdev);
1200
1201 if (!netif_running(dev))
1202 return 0;
1203
1204 netif_device_detach(dev);
1205 uli526x_reset_prepare(dev);
1206
1207 power_state = pci_choose_state(pdev, state);
1208 pci_enable_wake(pdev, power_state, 0);
1209 err = pci_set_power_state(pdev, power_state);
1210 if (err) {
1211 netif_device_attach(dev);
1212 /* Re-initialize ULI526X board */
1213 uli526x_init(dev);
1214 /* Restart upper layer interface */
1215 netif_wake_queue(dev);
1216 }
1217
1218 return err;
1219 }
1220
1221 /*
1222 * Resume the interface.
1223 */
1224
1225 static int uli526x_resume(struct pci_dev *pdev)
1226 {
1227 struct net_device *dev = pci_get_drvdata(pdev);
1228 int err;
1229
1230 ULI526X_DBUG(0, "uli526x_resume", 0);
1231
1232 if (!netdev_priv(dev))
1233 return 0;
1234
1235 pci_restore_state(pdev);
1236
1237 if (!netif_running(dev))
1238 return 0;
1239
1240 err = pci_set_power_state(pdev, PCI_D0);
1241 if (err) {
1242 printk(KERN_WARNING "%s: Could not put device into D0\n",
1243 dev->name);
1244 return err;
1245 }
1246
1247 netif_device_attach(dev);
1248 /* Re-initialize ULI526X board */
1249 uli526x_init(dev);
1250 /* Restart upper layer interface */
1251 netif_wake_queue(dev);
1252
1253 return 0;
1254 }
1255
1256 #else /* !CONFIG_PM */
1257
1258 #define uli526x_suspend NULL
1259 #define uli526x_resume NULL
1260
1261 #endif /* !CONFIG_PM */
1262
1263
1264 /*
1265 * free all allocated rx buffer
1266 */
1267
1268 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1269 {
1270 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1271
1272 /* free allocated rx buffer */
1273 while (db->rx_avail_cnt) {
1274 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1275 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1276 db->rx_avail_cnt--;
1277 }
1278 }
1279
1280
1281 /*
1282 * Reuse the SK buffer
1283 */
1284
1285 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1286 {
1287 struct rx_desc *rxptr = db->rx_insert_ptr;
1288
1289 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1290 rxptr->rx_skb_ptr = skb;
1291 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1292 skb_tail_pointer(skb),
1293 RX_ALLOC_SIZE,
1294 PCI_DMA_FROMDEVICE));
1295 wmb();
1296 rxptr->rdes0 = cpu_to_le32(0x80000000);
1297 db->rx_avail_cnt++;
1298 db->rx_insert_ptr = rxptr->next_rx_desc;
1299 } else
1300 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1301 }
1302
1303
1304 /*
1305 * Initialize transmit/Receive descriptor
1306 * Using Chain structure, and allocate Tx/Rx buffer
1307 */
1308
1309 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1310 {
1311 struct tx_desc *tmp_tx;
1312 struct rx_desc *tmp_rx;
1313 unsigned char *tmp_buf;
1314 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1315 dma_addr_t tmp_buf_dma;
1316 int i;
1317
1318 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1319
1320 /* tx descriptor start pointer */
1321 db->tx_insert_ptr = db->first_tx_desc;
1322 db->tx_remove_ptr = db->first_tx_desc;
1323 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1324
1325 /* rx descriptor start pointer */
1326 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1327 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1328 db->rx_insert_ptr = db->first_rx_desc;
1329 db->rx_ready_ptr = db->first_rx_desc;
1330 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1331
1332 /* Init Transmit chain */
1333 tmp_buf = db->buf_pool_start;
1334 tmp_buf_dma = db->buf_pool_dma_start;
1335 tmp_tx_dma = db->first_tx_desc_dma;
1336 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1337 tmp_tx->tx_buf_ptr = tmp_buf;
1338 tmp_tx->tdes0 = cpu_to_le32(0);
1339 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1340 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1341 tmp_tx_dma += sizeof(struct tx_desc);
1342 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1343 tmp_tx->next_tx_desc = tmp_tx + 1;
1344 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1345 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1346 }
1347 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1348 tmp_tx->next_tx_desc = db->first_tx_desc;
1349
1350 /* Init Receive descriptor chain */
1351 tmp_rx_dma=db->first_rx_desc_dma;
1352 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1353 tmp_rx->rdes0 = cpu_to_le32(0);
1354 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1355 tmp_rx_dma += sizeof(struct rx_desc);
1356 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1357 tmp_rx->next_rx_desc = tmp_rx + 1;
1358 }
1359 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1360 tmp_rx->next_rx_desc = db->first_rx_desc;
1361
1362 /* pre-allocate Rx buffer */
1363 allocate_rx_buffer(db);
1364 }
1365
1366
1367 /*
1368 * Update CR6 value
1369 * Firstly stop ULI526X, then written value and start
1370 */
1371
1372 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1373 {
1374
1375 outl(cr6_data, ioaddr + DCR6);
1376 udelay(5);
1377 }
1378
1379
1380 /*
1381 * Send a setup frame for M5261/M5263
1382 * This setup frame initialize ULI526X address filter mode
1383 */
1384
1385 #ifdef __BIG_ENDIAN
1386 #define FLT_SHIFT 16
1387 #else
1388 #define FLT_SHIFT 0
1389 #endif
1390
1391 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1392 {
1393 struct uli526x_board_info *db = netdev_priv(dev);
1394 struct dev_mc_list *mcptr;
1395 struct tx_desc *txptr;
1396 u16 * addrptr;
1397 u32 * suptr;
1398 int i;
1399
1400 ULI526X_DBUG(0, "send_filter_frame()", 0);
1401
1402 txptr = db->tx_insert_ptr;
1403 suptr = (u32 *) txptr->tx_buf_ptr;
1404
1405 /* Node address */
1406 addrptr = (u16 *) dev->dev_addr;
1407 *suptr++ = addrptr[0] << FLT_SHIFT;
1408 *suptr++ = addrptr[1] << FLT_SHIFT;
1409 *suptr++ = addrptr[2] << FLT_SHIFT;
1410
1411 /* broadcast address */
1412 *suptr++ = 0xffff << FLT_SHIFT;
1413 *suptr++ = 0xffff << FLT_SHIFT;
1414 *suptr++ = 0xffff << FLT_SHIFT;
1415
1416 /* fit the multicast address */
1417 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1418 addrptr = (u16 *) mcptr->dmi_addr;
1419 *suptr++ = addrptr[0] << FLT_SHIFT;
1420 *suptr++ = addrptr[1] << FLT_SHIFT;
1421 *suptr++ = addrptr[2] << FLT_SHIFT;
1422 }
1423
1424 for (; i<14; i++) {
1425 *suptr++ = 0xffff << FLT_SHIFT;
1426 *suptr++ = 0xffff << FLT_SHIFT;
1427 *suptr++ = 0xffff << FLT_SHIFT;
1428 }
1429
1430 /* prepare the setup frame */
1431 db->tx_insert_ptr = txptr->next_tx_desc;
1432 txptr->tdes1 = cpu_to_le32(0x890000c0);
1433
1434 /* Resource Check and Send the setup packet */
1435 if (db->tx_packet_cnt < TX_DESC_CNT) {
1436 /* Resource Empty */
1437 db->tx_packet_cnt++;
1438 txptr->tdes0 = cpu_to_le32(0x80000000);
1439 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1440 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1441 update_cr6(db->cr6_data, dev->base_addr);
1442 dev->trans_start = jiffies;
1443 } else
1444 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1445 }
1446
1447
1448 /*
1449 * Allocate rx buffer,
1450 * As possible as allocate maxiumn Rx buffer
1451 */
1452
1453 static void allocate_rx_buffer(struct uli526x_board_info *db)
1454 {
1455 struct rx_desc *rxptr;
1456 struct sk_buff *skb;
1457
1458 rxptr = db->rx_insert_ptr;
1459
1460 while(db->rx_avail_cnt < RX_DESC_CNT) {
1461 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1462 break;
1463 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1464 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1465 skb_tail_pointer(skb),
1466 RX_ALLOC_SIZE,
1467 PCI_DMA_FROMDEVICE));
1468 wmb();
1469 rxptr->rdes0 = cpu_to_le32(0x80000000);
1470 rxptr = rxptr->next_rx_desc;
1471 db->rx_avail_cnt++;
1472 }
1473
1474 db->rx_insert_ptr = rxptr;
1475 }
1476
1477
1478 /*
1479 * Read one word data from the serial ROM
1480 */
1481
1482 static u16 read_srom_word(long ioaddr, int offset)
1483 {
1484 int i;
1485 u16 srom_data = 0;
1486 long cr9_ioaddr = ioaddr + DCR9;
1487
1488 outl(CR9_SROM_READ, cr9_ioaddr);
1489 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1490
1491 /* Send the Read Command 110b */
1492 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1493 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1494 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1495
1496 /* Send the offset */
1497 for (i = 5; i >= 0; i--) {
1498 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1499 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1500 }
1501
1502 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1503
1504 for (i = 16; i > 0; i--) {
1505 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1506 udelay(5);
1507 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1508 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1509 udelay(5);
1510 }
1511
1512 outl(CR9_SROM_READ, cr9_ioaddr);
1513 return srom_data;
1514 }
1515
1516
1517 /*
1518 * Auto sense the media mode
1519 */
1520
1521 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1522 {
1523 u8 ErrFlag = 0;
1524 u16 phy_mode;
1525
1526 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1527 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1528
1529 if ( (phy_mode & 0x24) == 0x24 ) {
1530
1531 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1532 if(phy_mode&0x8000)
1533 phy_mode = 0x8000;
1534 else if(phy_mode&0x4000)
1535 phy_mode = 0x4000;
1536 else if(phy_mode&0x2000)
1537 phy_mode = 0x2000;
1538 else
1539 phy_mode = 0x1000;
1540
1541 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1542 switch (phy_mode) {
1543 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1544 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1545 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1546 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1547 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1548 }
1549 } else {
1550 db->op_mode = ULI526X_10MHF;
1551 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1552 ErrFlag = 1;
1553 }
1554
1555 return ErrFlag;
1556 }
1557
1558
1559 /*
1560 * Set 10/100 phyxcer capability
1561 * AUTO mode : phyxcer register4 is NIC capability
1562 * Force mode: phyxcer register4 is the force media
1563 */
1564
1565 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1566 {
1567 u16 phy_reg;
1568
1569 /* Phyxcer capability setting */
1570 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1571
1572 if (db->media_mode & ULI526X_AUTO) {
1573 /* AUTO Mode */
1574 phy_reg |= db->PHY_reg4;
1575 } else {
1576 /* Force Mode */
1577 switch(db->media_mode) {
1578 case ULI526X_10MHF: phy_reg |= 0x20; break;
1579 case ULI526X_10MFD: phy_reg |= 0x40; break;
1580 case ULI526X_100MHF: phy_reg |= 0x80; break;
1581 case ULI526X_100MFD: phy_reg |= 0x100; break;
1582 }
1583
1584 }
1585
1586 /* Write new capability to Phyxcer Reg4 */
1587 if ( !(phy_reg & 0x01e0)) {
1588 phy_reg|=db->PHY_reg4;
1589 db->media_mode|=ULI526X_AUTO;
1590 }
1591 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1592
1593 /* Restart Auto-Negotiation */
1594 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1595 udelay(50);
1596 }
1597
1598
1599 /*
1600 * Process op-mode
1601 AUTO mode : PHY controller in Auto-negotiation Mode
1602 * Force mode: PHY controller in force mode with HUB
1603 * N-way force capability with SWITCH
1604 */
1605
1606 static void uli526x_process_mode(struct uli526x_board_info *db)
1607 {
1608 u16 phy_reg;
1609
1610 /* Full Duplex Mode Check */
1611 if (db->op_mode & 0x4)
1612 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1613 else
1614 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1615
1616 update_cr6(db->cr6_data, db->ioaddr);
1617
1618 /* 10/100M phyxcer force mode need */
1619 if ( !(db->media_mode & 0x8)) {
1620 /* Forece Mode */
1621 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1622 if ( !(phy_reg & 0x1) ) {
1623 /* parter without N-Way capability */
1624 phy_reg = 0x0;
1625 switch(db->op_mode) {
1626 case ULI526X_10MHF: phy_reg = 0x0; break;
1627 case ULI526X_10MFD: phy_reg = 0x100; break;
1628 case ULI526X_100MHF: phy_reg = 0x2000; break;
1629 case ULI526X_100MFD: phy_reg = 0x2100; break;
1630 }
1631 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1632 }
1633 }
1634 }
1635
1636
1637 /*
1638 * Write a word to Phy register
1639 */
1640
1641 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1642 {
1643 u16 i;
1644 unsigned long ioaddr;
1645
1646 if(chip_id == PCI_ULI5263_ID)
1647 {
1648 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1649 return;
1650 }
1651 /* M5261/M5263 Chip */
1652 ioaddr = iobase + DCR9;
1653
1654 /* Send 33 synchronization clock to Phy controller */
1655 for (i = 0; i < 35; i++)
1656 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1657
1658 /* Send start command(01) to Phy */
1659 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1660 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1661
1662 /* Send write command(01) to Phy */
1663 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1664 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1665
1666 /* Send Phy address */
1667 for (i = 0x10; i > 0; i = i >> 1)
1668 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1669
1670 /* Send register address */
1671 for (i = 0x10; i > 0; i = i >> 1)
1672 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1673
1674 /* written trasnition */
1675 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1676 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1677
1678 /* Write a word data to PHY controller */
1679 for ( i = 0x8000; i > 0; i >>= 1)
1680 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1681
1682 }
1683
1684
1685 /*
1686 * Read a word data from phy register
1687 */
1688
1689 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1690 {
1691 int i;
1692 u16 phy_data;
1693 unsigned long ioaddr;
1694
1695 if(chip_id == PCI_ULI5263_ID)
1696 return phy_readby_cr10(iobase, phy_addr, offset);
1697 /* M5261/M5263 Chip */
1698 ioaddr = iobase + DCR9;
1699
1700 /* Send 33 synchronization clock to Phy controller */
1701 for (i = 0; i < 35; i++)
1702 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1703
1704 /* Send start command(01) to Phy */
1705 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1706 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1707
1708 /* Send read command(10) to Phy */
1709 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1710 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1711
1712 /* Send Phy address */
1713 for (i = 0x10; i > 0; i = i >> 1)
1714 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1715
1716 /* Send register address */
1717 for (i = 0x10; i > 0; i = i >> 1)
1718 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1719
1720 /* Skip transition state */
1721 phy_read_1bit(ioaddr, chip_id);
1722
1723 /* read 16bit data */
1724 for (phy_data = 0, i = 0; i < 16; i++) {
1725 phy_data <<= 1;
1726 phy_data |= phy_read_1bit(ioaddr, chip_id);
1727 }
1728
1729 return phy_data;
1730 }
1731
1732 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1733 {
1734 unsigned long ioaddr,cr10_value;
1735
1736 ioaddr = iobase + DCR10;
1737 cr10_value = phy_addr;
1738 cr10_value = (cr10_value<<5) + offset;
1739 cr10_value = (cr10_value<<16) + 0x08000000;
1740 outl(cr10_value,ioaddr);
1741 udelay(1);
1742 while(1)
1743 {
1744 cr10_value = inl(ioaddr);
1745 if(cr10_value&0x10000000)
1746 break;
1747 }
1748 return (cr10_value&0x0ffff);
1749 }
1750
1751 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1752 {
1753 unsigned long ioaddr,cr10_value;
1754
1755 ioaddr = iobase + DCR10;
1756 cr10_value = phy_addr;
1757 cr10_value = (cr10_value<<5) + offset;
1758 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1759 outl(cr10_value,ioaddr);
1760 udelay(1);
1761 }
1762 /*
1763 * Write one bit data to Phy Controller
1764 */
1765
1766 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1767 {
1768 outl(phy_data , ioaddr); /* MII Clock Low */
1769 udelay(1);
1770 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1771 udelay(1);
1772 outl(phy_data , ioaddr); /* MII Clock Low */
1773 udelay(1);
1774 }
1775
1776
1777 /*
1778 * Read one bit phy data from PHY controller
1779 */
1780
1781 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1782 {
1783 u16 phy_data;
1784
1785 outl(0x50000 , ioaddr);
1786 udelay(1);
1787 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1788 outl(0x40000 , ioaddr);
1789 udelay(1);
1790
1791 return phy_data;
1792 }
1793
1794
1795 static struct pci_device_id uli526x_pci_tbl[] = {
1796 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1797 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1798 { 0, }
1799 };
1800 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1801
1802
1803 static struct pci_driver uli526x_driver = {
1804 .name = "uli526x",
1805 .id_table = uli526x_pci_tbl,
1806 .probe = uli526x_init_one,
1807 .remove = __devexit_p(uli526x_remove_one),
1808 .suspend = uli526x_suspend,
1809 .resume = uli526x_resume,
1810 };
1811
1812 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1813 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1814 MODULE_LICENSE("GPL");
1815
1816 module_param(debug, int, 0644);
1817 module_param(mode, int, 0);
1818 module_param(cr6set, int, 0);
1819 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1820 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1821
1822 /* Description:
1823 * when user used insmod to add module, system invoked init_module()
1824 * to register the services.
1825 */
1826
1827 static int __init uli526x_init_module(void)
1828 {
1829
1830 printk(version);
1831 printed_version = 1;
1832
1833 ULI526X_DBUG(0, "init_module() ", debug);
1834
1835 if (debug)
1836 uli526x_debug = debug; /* set debug flag */
1837 if (cr6set)
1838 uli526x_cr6_user_set = cr6set;
1839
1840 switch (mode) {
1841 case ULI526X_10MHF:
1842 case ULI526X_100MHF:
1843 case ULI526X_10MFD:
1844 case ULI526X_100MFD:
1845 uli526x_media_mode = mode;
1846 break;
1847 default:
1848 uli526x_media_mode = ULI526X_AUTO;
1849 break;
1850 }
1851
1852 return pci_register_driver(&uli526x_driver);
1853 }
1854
1855
1856 /*
1857 * Description:
1858 * when user used rmmod to delete module, system invoked clean_module()
1859 * to un-register all registered services.
1860 */
1861
1862 static void __exit uli526x_cleanup_module(void)
1863 {
1864 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1865 pci_unregister_driver(&uli526x_driver);
1866 }
1867
1868 module_init(uli526x_init_module);
1869 module_exit(uli526x_cleanup_module);
Linux with added FPC-III support