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Linux 4.1.16
[linux/fpc-iii.git] / drivers / ata / ahci.c
blobe6ea912aee31ab6490bc77bd233d8e90ec7857bc
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include "ahci.h"
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
52
53 enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nomsi,
64 board_ahci_noncq,
65 board_ahci_nosntf,
66 board_ahci_yes_fbs,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_avn,
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83 };
84
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91 static bool is_mcp89_apple(struct pci_dev *pdev);
92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 #ifdef CONFIG_PM
95 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
96 static int ahci_pci_device_resume(struct pci_dev *pdev);
97 #endif
98
99 static struct scsi_host_template ahci_sht = {
100 AHCI_SHT("ahci"),
101 };
102
103 static struct ata_port_operations ahci_vt8251_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_vt8251_hardreset,
106 };
107
108 static struct ata_port_operations ahci_p5wdh_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_p5wdh_hardreset,
111 };
112
113 static struct ata_port_operations ahci_avn_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_avn_hardreset,
116 };
117
118 static const struct ata_port_info ahci_port_info[] = {
119 /* by features */
120 [board_ahci] = {
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
125 },
126 [board_ahci_ign_iferr] = {
127 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
132 },
133 [board_ahci_nomsi] = {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_noncq] = {
141 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
147 [board_ahci_nosntf] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_yes_fbs] = {
155 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 /* by chipsets */
162 [board_ahci_avn] = {
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_avn_ops,
167 },
168 [board_ahci_mcp65] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
170 AHCI_HFLAG_YES_NCQ),
171 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_mcp77] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_mcp89] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
189 },
190 [board_ahci_mv] = {
191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
192 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
193 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
197 },
198 [board_ahci_sb600] = {
199 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
200 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
201 AHCI_HFLAG_32BIT_ONLY),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_pmp_retry_srst_ops,
206 },
207 [board_ahci_sb700] = { /* for SB700 and SB800 */
208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
209 .flags = AHCI_FLAG_COMMON,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &ahci_pmp_retry_srst_ops,
213 },
214 [board_ahci_vt8251] = {
215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
216 .flags = AHCI_FLAG_COMMON,
217 .pio_mask = ATA_PIO4,
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &ahci_vt8251_ops,
220 },
221 };
222
223 static const struct pci_device_id ahci_pci_tbl[] = {
224 /* Intel */
225 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
226 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
227 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
228 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
229 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
230 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
231 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
232 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
233 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
235 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
236 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
237 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
239 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
240 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
242 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
246 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
247 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
253 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
254 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
255 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
256 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
258 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
259 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
260 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
261 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
262 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
264 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
265 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
266 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
267 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
268 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
269 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
270 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
271 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
272 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
273 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
274 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
275 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
276 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
277 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
278 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
279 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
280 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
281 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
282 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
283 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
284 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
285 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
286 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
287 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
289 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
290 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
291 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
292 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
293 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
294 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
295 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
296 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
300 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
301 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
303 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
306 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
307 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
308 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
309 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
310 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
311 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
313 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
316 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
317 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
318 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
319 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
320 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
322 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
323 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
324 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
325 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
326 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
327 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
331 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
332 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
333 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
334 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
335 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
336 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
337 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
338 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
341 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
342 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
343 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
344 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
345
346 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
347 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
348 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
349 /* JMicron 362B and 362C have an AHCI function with IDE class code */
350 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
351 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
352 /* May need to update quirk_jmicron_async_suspend() for additions */
353
354 /* ATI */
355 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
356 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
357 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
358 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
359 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
360 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
361 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
362
363 /* AMD */
364 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
365 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
366 /* AMD is using RAID class only for ahci controllers */
367 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
368 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
369
370 /* VIA */
371 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
372 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
373
374 /* NVIDIA */
375 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
376 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
377 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
378 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
379 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
380 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
381 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
382 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
383 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
384 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
385 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
386 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
387 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
388 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
389 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
390 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
391 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
392 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
397 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
398 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
399 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
400 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
401 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
402 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
403 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
404 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
405 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
406 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
411 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
412 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
413 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
414 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
415 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
416 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
417 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
418 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
419 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
420 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
421 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
422 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
423 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
424 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
425 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
426 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
427 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
428 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
429 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
430 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
431 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
432 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
433 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
434 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
435 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
436 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
437 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
438 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
439 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
440 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
441 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
442 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
443 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
444 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
445 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
446 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
447 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
448 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
449 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
450 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
451 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
452 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
453 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
454 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
455 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
456 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
457 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
458 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
459
460 /* SiS */
461 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
462 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
463 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
464
465 /* ST Microelectronics */
466 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
467
468 /* Marvell */
469 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
470 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
472 .class = PCI_CLASS_STORAGE_SATA_AHCI,
473 .class_mask = 0xffffff,
474 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
476 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
477 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
478 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
479 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
480 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
481 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
482 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
483 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
484 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
485 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
486 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
487 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
488 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
489 .driver_data = board_ahci_yes_fbs },
490 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
491 .driver_data = board_ahci_yes_fbs },
492 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
493 .driver_data = board_ahci_yes_fbs },
494 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
495 .driver_data = board_ahci_yes_fbs },
496
497 /* Promise */
498 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
499 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
500
501 /* Asmedia */
502 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
503 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
504 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
505 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
506
507 /*
508 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
509 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
510 */
511 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
512 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
513
514 /* Enmotus */
515 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
516
517 /* Generic, PCI class code for AHCI */
518 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
519 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
520
521 { } /* terminate list */
522 };
523
524
525 static struct pci_driver ahci_pci_driver = {
526 .name = DRV_NAME,
527 .id_table = ahci_pci_tbl,
528 .probe = ahci_init_one,
529 .remove = ata_pci_remove_one,
530 #ifdef CONFIG_PM
531 .suspend = ahci_pci_device_suspend,
532 .resume = ahci_pci_device_resume,
533 #endif
534 };
535
536 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
537 static int marvell_enable;
538 #else
539 static int marvell_enable = 1;
540 #endif
541 module_param(marvell_enable, int, 0644);
542 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
543
544
545 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
546 struct ahci_host_priv *hpriv)
547 {
548 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
549 dev_info(&pdev->dev, "JMB361 has only one port\n");
550 hpriv->force_port_map = 1;
551 }
552
553 /*
554 * Temporary Marvell 6145 hack: PATA port presence
555 * is asserted through the standard AHCI port
556 * presence register, as bit 4 (counting from 0)
557 */
558 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
559 if (pdev->device == 0x6121)
560 hpriv->mask_port_map = 0x3;
561 else
562 hpriv->mask_port_map = 0xf;
563 dev_info(&pdev->dev,
564 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
565 }
566
567 ahci_save_initial_config(&pdev->dev, hpriv);
568 }
569
570 static int ahci_pci_reset_controller(struct ata_host *host)
571 {
572 struct pci_dev *pdev = to_pci_dev(host->dev);
573
574 ahci_reset_controller(host);
575
576 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
577 struct ahci_host_priv *hpriv = host->private_data;
578 u16 tmp16;
579
580 /* configure PCS */
581 pci_read_config_word(pdev, 0x92, &tmp16);
582 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
583 tmp16 |= hpriv->port_map;
584 pci_write_config_word(pdev, 0x92, tmp16);
585 }
586 }
587
588 return 0;
589 }
590
591 static void ahci_pci_init_controller(struct ata_host *host)
592 {
593 struct ahci_host_priv *hpriv = host->private_data;
594 struct pci_dev *pdev = to_pci_dev(host->dev);
595 void __iomem *port_mmio;
596 u32 tmp;
597 int mv;
598
599 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
600 if (pdev->device == 0x6121)
601 mv = 2;
602 else
603 mv = 4;
604 port_mmio = __ahci_port_base(host, mv);
605
606 writel(0, port_mmio + PORT_IRQ_MASK);
607
608 /* clear port IRQ */
609 tmp = readl(port_mmio + PORT_IRQ_STAT);
610 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
611 if (tmp)
612 writel(tmp, port_mmio + PORT_IRQ_STAT);
613 }
614
615 ahci_init_controller(host);
616 }
617
618 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
619 unsigned long deadline)
620 {
621 struct ata_port *ap = link->ap;
622 struct ahci_host_priv *hpriv = ap->host->private_data;
623 bool online;
624 int rc;
625
626 DPRINTK("ENTER\n");
627
628 ahci_stop_engine(ap);
629
630 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
631 deadline, &online, NULL);
632
633 hpriv->start_engine(ap);
634
635 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
636
637 /* vt8251 doesn't clear BSY on signature FIS reception,
638 * request follow-up softreset.
639 */
640 return online ? -EAGAIN : rc;
641 }
642
643 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
644 unsigned long deadline)
645 {
646 struct ata_port *ap = link->ap;
647 struct ahci_port_priv *pp = ap->private_data;
648 struct ahci_host_priv *hpriv = ap->host->private_data;
649 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
650 struct ata_taskfile tf;
651 bool online;
652 int rc;
653
654 ahci_stop_engine(ap);
655
656 /* clear D2H reception area to properly wait for D2H FIS */
657 ata_tf_init(link->device, &tf);
658 tf.command = ATA_BUSY;
659 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
660
661 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
662 deadline, &online, NULL);
663
664 hpriv->start_engine(ap);
665
666 /* The pseudo configuration device on SIMG4726 attached to
667 * ASUS P5W-DH Deluxe doesn't send signature FIS after
668 * hardreset if no device is attached to the first downstream
669 * port && the pseudo device locks up on SRST w/ PMP==0. To
670 * work around this, wait for !BSY only briefly. If BSY isn't
671 * cleared, perform CLO and proceed to IDENTIFY (achieved by
672 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
673 *
674 * Wait for two seconds. Devices attached to downstream port
675 * which can't process the following IDENTIFY after this will
676 * have to be reset again. For most cases, this should
677 * suffice while making probing snappish enough.
678 */
679 if (online) {
680 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
681 ahci_check_ready);
682 if (rc)
683 ahci_kick_engine(ap);
684 }
685 return rc;
686 }
687
688 /*
689 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
690 *
691 * It has been observed with some SSDs that the timing of events in the
692 * link synchronization phase can leave the port in a state that can not
693 * be recovered by a SATA-hard-reset alone. The failing signature is
694 * SStatus.DET stuck at 1 ("Device presence detected but Phy
695 * communication not established"). It was found that unloading and
696 * reloading the driver when this problem occurs allows the drive
697 * connection to be recovered (DET advanced to 0x3). The critical
698 * component of reloading the driver is that the port state machines are
699 * reset by bouncing "port enable" in the AHCI PCS configuration
700 * register. So, reproduce that effect by bouncing a port whenever we
701 * see DET==1 after a reset.
702 */
703 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
704 unsigned long deadline)
705 {
706 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
707 struct ata_port *ap = link->ap;
708 struct ahci_port_priv *pp = ap->private_data;
709 struct ahci_host_priv *hpriv = ap->host->private_data;
710 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
711 unsigned long tmo = deadline - jiffies;
712 struct ata_taskfile tf;
713 bool online;
714 int rc, i;
715
716 DPRINTK("ENTER\n");
717
718 ahci_stop_engine(ap);
719
720 for (i = 0; i < 2; i++) {
721 u16 val;
722 u32 sstatus;
723 int port = ap->port_no;
724 struct ata_host *host = ap->host;
725 struct pci_dev *pdev = to_pci_dev(host->dev);
726
727 /* clear D2H reception area to properly wait for D2H FIS */
728 ata_tf_init(link->device, &tf);
729 tf.command = ATA_BUSY;
730 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
731
732 rc = sata_link_hardreset(link, timing, deadline, &online,
733 ahci_check_ready);
734
735 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
736 (sstatus & 0xf) != 1)
737 break;
738
739 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
740 port);
741
742 pci_read_config_word(pdev, 0x92, &val);
743 val &= ~(1 << port);
744 pci_write_config_word(pdev, 0x92, val);
745 ata_msleep(ap, 1000);
746 val |= 1 << port;
747 pci_write_config_word(pdev, 0x92, val);
748 deadline += tmo;
749 }
750
751 hpriv->start_engine(ap);
752
753 if (online)
754 *class = ahci_dev_classify(ap);
755
756 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
757 return rc;
758 }
759
760
761 #ifdef CONFIG_PM
762 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
763 {
764 struct ata_host *host = pci_get_drvdata(pdev);
765 struct ahci_host_priv *hpriv = host->private_data;
766 void __iomem *mmio = hpriv->mmio;
767 u32 ctl;
768
769 if (mesg.event & PM_EVENT_SUSPEND &&
770 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
771 dev_err(&pdev->dev,
772 "BIOS update required for suspend/resume\n");
773 return -EIO;
774 }
775
776 if (mesg.event & PM_EVENT_SLEEP) {
777 /* AHCI spec rev1.1 section 8.3.3:
778 * Software must disable interrupts prior to requesting a
779 * transition of the HBA to D3 state.
780 */
781 ctl = readl(mmio + HOST_CTL);
782 ctl &= ~HOST_IRQ_EN;
783 writel(ctl, mmio + HOST_CTL);
784 readl(mmio + HOST_CTL); /* flush */
785 }
786
787 return ata_pci_device_suspend(pdev, mesg);
788 }
789
790 static int ahci_pci_device_resume(struct pci_dev *pdev)
791 {
792 struct ata_host *host = pci_get_drvdata(pdev);
793 int rc;
794
795 rc = ata_pci_device_do_resume(pdev);
796 if (rc)
797 return rc;
798
799 /* Apple BIOS helpfully mangles the registers on resume */
800 if (is_mcp89_apple(pdev))
801 ahci_mcp89_apple_enable(pdev);
802
803 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
804 rc = ahci_pci_reset_controller(host);
805 if (rc)
806 return rc;
807
808 ahci_pci_init_controller(host);
809 }
810
811 ata_host_resume(host);
812
813 return 0;
814 }
815 #endif
816
817 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
818 {
819 int rc;
820
821 /*
822 * If the device fixup already set the dma_mask to some non-standard
823 * value, don't extend it here. This happens on STA2X11, for example.
824 */
825 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
826 return 0;
827
828 if (using_dac &&
829 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
830 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
831 if (rc) {
832 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
833 if (rc) {
834 dev_err(&pdev->dev,
835 "64-bit DMA enable failed\n");
836 return rc;
837 }
838 }
839 } else {
840 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
841 if (rc) {
842 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
843 return rc;
844 }
845 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
846 if (rc) {
847 dev_err(&pdev->dev,
848 "32-bit consistent DMA enable failed\n");
849 return rc;
850 }
851 }
852 return 0;
853 }
854
855 static void ahci_pci_print_info(struct ata_host *host)
856 {
857 struct pci_dev *pdev = to_pci_dev(host->dev);
858 u16 cc;
859 const char *scc_s;
860
861 pci_read_config_word(pdev, 0x0a, &cc);
862 if (cc == PCI_CLASS_STORAGE_IDE)
863 scc_s = "IDE";
864 else if (cc == PCI_CLASS_STORAGE_SATA)
865 scc_s = "SATA";
866 else if (cc == PCI_CLASS_STORAGE_RAID)
867 scc_s = "RAID";
868 else
869 scc_s = "unknown";
870
871 ahci_print_info(host, scc_s);
872 }
873
874 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
875 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
876 * support PMP and the 4726 either directly exports the device
877 * attached to the first downstream port or acts as a hardware storage
878 * controller and emulate a single ATA device (can be RAID 0/1 or some
879 * other configuration).
880 *
881 * When there's no device attached to the first downstream port of the
882 * 4726, "Config Disk" appears, which is a pseudo ATA device to
883 * configure the 4726. However, ATA emulation of the device is very
884 * lame. It doesn't send signature D2H Reg FIS after the initial
885 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
886 *
887 * The following function works around the problem by always using
888 * hardreset on the port and not depending on receiving signature FIS
889 * afterward. If signature FIS isn't received soon, ATA class is
890 * assumed without follow-up softreset.
891 */
892 static void ahci_p5wdh_workaround(struct ata_host *host)
893 {
894 static const struct dmi_system_id sysids[] = {
895 {
896 .ident = "P5W DH Deluxe",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR,
899 "ASUSTEK COMPUTER INC"),
900 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
901 },
902 },
903 { }
904 };
905 struct pci_dev *pdev = to_pci_dev(host->dev);
906
907 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
908 dmi_check_system(sysids)) {
909 struct ata_port *ap = host->ports[1];
910
911 dev_info(&pdev->dev,
912 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
913
914 ap->ops = &ahci_p5wdh_ops;
915 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
916 }
917 }
918
919 /*
920 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
921 * booting in BIOS compatibility mode. We restore the registers but not ID.
922 */
923 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
924 {
925 u32 val;
926
927 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
928
929 pci_read_config_dword(pdev, 0xf8, &val);
930 val |= 1 << 0x1b;
931 /* the following changes the device ID, but appears not to affect function */
932 /* val = (val & ~0xf0000000) | 0x80000000; */
933 pci_write_config_dword(pdev, 0xf8, val);
934
935 pci_read_config_dword(pdev, 0x54c, &val);
936 val |= 1 << 0xc;
937 pci_write_config_dword(pdev, 0x54c, val);
938
939 pci_read_config_dword(pdev, 0x4a4, &val);
940 val &= 0xff;
941 val |= 0x01060100;
942 pci_write_config_dword(pdev, 0x4a4, val);
943
944 pci_read_config_dword(pdev, 0x54c, &val);
945 val &= ~(1 << 0xc);
946 pci_write_config_dword(pdev, 0x54c, val);
947
948 pci_read_config_dword(pdev, 0xf8, &val);
949 val &= ~(1 << 0x1b);
950 pci_write_config_dword(pdev, 0xf8, val);
951 }
952
953 static bool is_mcp89_apple(struct pci_dev *pdev)
954 {
955 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
956 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
957 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
958 pdev->subsystem_device == 0xcb89;
959 }
960
961 /* only some SB600 ahci controllers can do 64bit DMA */
962 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
963 {
964 static const struct dmi_system_id sysids[] = {
965 /*
966 * The oldest version known to be broken is 0901 and
967 * working is 1501 which was released on 2007-10-26.
968 * Enable 64bit DMA on 1501 and anything newer.
969 *
970 * Please read bko#9412 for more info.
971 */
972 {
973 .ident = "ASUS M2A-VM",
974 .matches = {
975 DMI_MATCH(DMI_BOARD_VENDOR,
976 "ASUSTeK Computer INC."),
977 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
978 },
979 .driver_data = "20071026", /* yyyymmdd */
980 },
981 /*
982 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
983 * support 64bit DMA.
984 *
985 * BIOS versions earlier than 1.5 had the Manufacturer DMI
986 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
987 * This spelling mistake was fixed in BIOS version 1.5, so
988 * 1.5 and later have the Manufacturer as
989 * "MICRO-STAR INTERNATIONAL CO.,LTD".
990 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
991 *
992 * BIOS versions earlier than 1.9 had a Board Product Name
993 * DMI field of "MS-7376". This was changed to be
994 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
995 * match on DMI_BOARD_NAME of "MS-7376".
996 */
997 {
998 .ident = "MSI K9A2 Platinum",
999 .matches = {
1000 DMI_MATCH(DMI_BOARD_VENDOR,
1001 "MICRO-STAR INTER"),
1002 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1003 },
1004 },
1005 /*
1006 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1007 * 64bit DMA.
1008 *
1009 * This board also had the typo mentioned above in the
1010 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1011 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1012 */
1013 {
1014 .ident = "MSI K9AGM2",
1015 .matches = {
1016 DMI_MATCH(DMI_BOARD_VENDOR,
1017 "MICRO-STAR INTER"),
1018 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1019 },
1020 },
1021 /*
1022 * All BIOS versions for the Asus M3A support 64bit DMA.
1023 * (all release versions from 0301 to 1206 were tested)
1024 */
1025 {
1026 .ident = "ASUS M3A",
1027 .matches = {
1028 DMI_MATCH(DMI_BOARD_VENDOR,
1029 "ASUSTeK Computer INC."),
1030 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1031 },
1032 },
1033 { }
1034 };
1035 const struct dmi_system_id *match;
1036 int year, month, date;
1037 char buf[9];
1038
1039 match = dmi_first_match(sysids);
1040 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1041 !match)
1042 return false;
1043
1044 if (!match->driver_data)
1045 goto enable_64bit;
1046
1047 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1048 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1049
1050 if (strcmp(buf, match->driver_data) >= 0)
1051 goto enable_64bit;
1052 else {
1053 dev_warn(&pdev->dev,
1054 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1055 match->ident);
1056 return false;
1057 }
1058
1059 enable_64bit:
1060 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1061 return true;
1062 }
1063
1064 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1065 {
1066 static const struct dmi_system_id broken_systems[] = {
1067 {
1068 .ident = "HP Compaq nx6310",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1072 },
1073 /* PCI slot number of the controller */
1074 .driver_data = (void *)0x1FUL,
1075 },
1076 {
1077 .ident = "HP Compaq 6720s",
1078 .matches = {
1079 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1080 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1081 },
1082 /* PCI slot number of the controller */
1083 .driver_data = (void *)0x1FUL,
1084 },
1085
1086 { } /* terminate list */
1087 };
1088 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1089
1090 if (dmi) {
1091 unsigned long slot = (unsigned long)dmi->driver_data;
1092 /* apply the quirk only to on-board controllers */
1093 return slot == PCI_SLOT(pdev->devfn);
1094 }
1095
1096 return false;
1097 }
1098
1099 static bool ahci_broken_suspend(struct pci_dev *pdev)
1100 {
1101 static const struct dmi_system_id sysids[] = {
1102 /*
1103 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1104 * to the harddisk doesn't become online after
1105 * resuming from STR. Warn and fail suspend.
1106 *
1107 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1108 *
1109 * Use dates instead of versions to match as HP is
1110 * apparently recycling both product and version
1111 * strings.
1112 *
1113 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1114 */
1115 {
1116 .ident = "dv4",
1117 .matches = {
1118 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1119 DMI_MATCH(DMI_PRODUCT_NAME,
1120 "HP Pavilion dv4 Notebook PC"),
1121 },
1122 .driver_data = "20090105", /* F.30 */
1123 },
1124 {
1125 .ident = "dv5",
1126 .matches = {
1127 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1128 DMI_MATCH(DMI_PRODUCT_NAME,
1129 "HP Pavilion dv5 Notebook PC"),
1130 },
1131 .driver_data = "20090506", /* F.16 */
1132 },
1133 {
1134 .ident = "dv6",
1135 .matches = {
1136 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1137 DMI_MATCH(DMI_PRODUCT_NAME,
1138 "HP Pavilion dv6 Notebook PC"),
1139 },
1140 .driver_data = "20090423", /* F.21 */
1141 },
1142 {
1143 .ident = "HDX18",
1144 .matches = {
1145 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1146 DMI_MATCH(DMI_PRODUCT_NAME,
1147 "HP HDX18 Notebook PC"),
1148 },
1149 .driver_data = "20090430", /* F.23 */
1150 },
1151 /*
1152 * Acer eMachines G725 has the same problem. BIOS
1153 * V1.03 is known to be broken. V3.04 is known to
1154 * work. Between, there are V1.06, V2.06 and V3.03
1155 * that we don't have much idea about. For now,
1156 * blacklist anything older than V3.04.
1157 *
1158 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1159 */
1160 {
1161 .ident = "G725",
1162 .matches = {
1163 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1164 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1165 },
1166 .driver_data = "20091216", /* V3.04 */
1167 },
1168 { } /* terminate list */
1169 };
1170 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1171 int year, month, date;
1172 char buf[9];
1173
1174 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1175 return false;
1176
1177 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1178 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1179
1180 return strcmp(buf, dmi->driver_data) < 0;
1181 }
1182
1183 static bool ahci_broken_online(struct pci_dev *pdev)
1184 {
1185 #define ENCODE_BUSDEVFN(bus, slot, func) \
1186 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1187 static const struct dmi_system_id sysids[] = {
1188 /*
1189 * There are several gigabyte boards which use
1190 * SIMG5723s configured as hardware RAID. Certain
1191 * 5723 firmware revisions shipped there keep the link
1192 * online but fail to answer properly to SRST or
1193 * IDENTIFY when no device is attached downstream
1194 * causing libata to retry quite a few times leading
1195 * to excessive detection delay.
1196 *
1197 * As these firmwares respond to the second reset try
1198 * with invalid device signature, considering unknown
1199 * sig as offline works around the problem acceptably.
1200 */
1201 {
1202 .ident = "EP45-DQ6",
1203 .matches = {
1204 DMI_MATCH(DMI_BOARD_VENDOR,
1205 "Gigabyte Technology Co., Ltd."),
1206 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1207 },
1208 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1209 },
1210 {
1211 .ident = "EP45-DS5",
1212 .matches = {
1213 DMI_MATCH(DMI_BOARD_VENDOR,
1214 "Gigabyte Technology Co., Ltd."),
1215 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1216 },
1217 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1218 },
1219 { } /* terminate list */
1220 };
1221 #undef ENCODE_BUSDEVFN
1222 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1223 unsigned int val;
1224
1225 if (!dmi)
1226 return false;
1227
1228 val = (unsigned long)dmi->driver_data;
1229
1230 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1231 }
1232
1233 static bool ahci_broken_devslp(struct pci_dev *pdev)
1234 {
1235 /* device with broken DEVSLP but still showing SDS capability */
1236 static const struct pci_device_id ids[] = {
1237 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1238 {}
1239 };
1240
1241 return pci_match_id(ids, pdev);
1242 }
1243
1244 #ifdef CONFIG_ATA_ACPI
1245 static void ahci_gtf_filter_workaround(struct ata_host *host)
1246 {
1247 static const struct dmi_system_id sysids[] = {
1248 /*
1249 * Aspire 3810T issues a bunch of SATA enable commands
1250 * via _GTF including an invalid one and one which is
1251 * rejected by the device. Among the successful ones
1252 * is FPDMA non-zero offset enable which when enabled
1253 * only on the drive side leads to NCQ command
1254 * failures. Filter it out.
1255 */
1256 {
1257 .ident = "Aspire 3810T",
1258 .matches = {
1259 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1260 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1261 },
1262 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1263 },
1264 { }
1265 };
1266 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1267 unsigned int filter;
1268 int i;
1269
1270 if (!dmi)
1271 return;
1272
1273 filter = (unsigned long)dmi->driver_data;
1274 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1275 filter, dmi->ident);
1276
1277 for (i = 0; i < host->n_ports; i++) {
1278 struct ata_port *ap = host->ports[i];
1279 struct ata_link *link;
1280 struct ata_device *dev;
1281
1282 ata_for_each_link(link, ap, EDGE)
1283 ata_for_each_dev(dev, link, ALL)
1284 dev->gtf_filter |= filter;
1285 }
1286 }
1287 #else
1288 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1289 {}
1290 #endif
1291
1292 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1293 struct ahci_host_priv *hpriv)
1294 {
1295 int rc, nvec;
1296
1297 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1298 goto intx;
1299
1300 nvec = pci_msi_vec_count(pdev);
1301 if (nvec < 0)
1302 goto intx;
1303
1304 /*
1305 * If number of MSIs is less than number of ports then Sharing Last
1306 * Message mode could be enforced. In this case assume that advantage
1307 * of multipe MSIs is negated and use single MSI mode instead.
1308 */
1309 if (nvec < n_ports)
1310 goto single_msi;
1311
1312 rc = pci_enable_msi_exact(pdev, nvec);
1313 if (rc == -ENOSPC)
1314 goto single_msi;
1315 else if (rc < 0)
1316 goto intx;
1317
1318 /* fallback to single MSI mode if the controller enforced MRSM mode */
1319 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1320 pci_disable_msi(pdev);
1321 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1322 goto single_msi;
1323 }
1324
1325 if (nvec > 1)
1326 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1327
1328 return nvec;
1329
1330 single_msi:
1331 if (pci_enable_msi(pdev))
1332 goto intx;
1333 return 1;
1334
1335 intx:
1336 pci_intx(pdev, 1);
1337 return 0;
1338 }
1339
1340 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1341 {
1342 unsigned int board_id = ent->driver_data;
1343 struct ata_port_info pi = ahci_port_info[board_id];
1344 const struct ata_port_info *ppi[] = { &pi, NULL };
1345 struct device *dev = &pdev->dev;
1346 struct ahci_host_priv *hpriv;
1347 struct ata_host *host;
1348 int n_ports, i, rc;
1349 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1350
1351 VPRINTK("ENTER\n");
1352
1353 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1354
1355 ata_print_version_once(&pdev->dev, DRV_VERSION);
1356
1357 /* The AHCI driver can only drive the SATA ports, the PATA driver
1358 can drive them all so if both drivers are selected make sure
1359 AHCI stays out of the way */
1360 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1361 return -ENODEV;
1362
1363 /* Apple BIOS on MCP89 prevents us using AHCI */
1364 if (is_mcp89_apple(pdev))
1365 ahci_mcp89_apple_enable(pdev);
1366
1367 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1368 * At the moment, we can only use the AHCI mode. Let the users know
1369 * that for SAS drives they're out of luck.
1370 */
1371 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1372 dev_info(&pdev->dev,
1373 "PDC42819 can only drive SATA devices with this driver\n");
1374
1375 /* Both Connext and Enmotus devices use non-standard BARs */
1376 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1377 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1378 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1379 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1380
1381 /* acquire resources */
1382 rc = pcim_enable_device(pdev);
1383 if (rc)
1384 return rc;
1385
1386 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1387 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1388 u8 map;
1389
1390 /* ICH6s share the same PCI ID for both piix and ahci
1391 * modes. Enabling ahci mode while MAP indicates
1392 * combined mode is a bad idea. Yield to ata_piix.
1393 */
1394 pci_read_config_byte(pdev, ICH_MAP, &map);
1395 if (map & 0x3) {
1396 dev_info(&pdev->dev,
1397 "controller is in combined mode, can't enable AHCI mode\n");
1398 return -ENODEV;
1399 }
1400 }
1401
1402 /* AHCI controllers often implement SFF compatible interface.
1403 * Grab all PCI BARs just in case.
1404 */
1405 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1406 if (rc == -EBUSY)
1407 pcim_pin_device(pdev);
1408 if (rc)
1409 return rc;
1410
1411 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1412 if (!hpriv)
1413 return -ENOMEM;
1414 hpriv->flags |= (unsigned long)pi.private_data;
1415
1416 /* MCP65 revision A1 and A2 can't do MSI */
1417 if (board_id == board_ahci_mcp65 &&
1418 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1419 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1420
1421 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1422 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1423 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1424
1425 /* only some SB600s can do 64bit DMA */
1426 if (ahci_sb600_enable_64bit(pdev))
1427 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1428
1429 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1430
1431 /* must set flag prior to save config in order to take effect */
1432 if (ahci_broken_devslp(pdev))
1433 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1434
1435 /* save initial config */
1436 ahci_pci_save_initial_config(pdev, hpriv);
1437
1438 /* prepare host */
1439 if (hpriv->cap & HOST_CAP_NCQ) {
1440 pi.flags |= ATA_FLAG_NCQ;
1441 /*
1442 * Auto-activate optimization is supposed to be
1443 * supported on all AHCI controllers indicating NCQ
1444 * capability, but it seems to be broken on some
1445 * chipsets including NVIDIAs.
1446 */
1447 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1448 pi.flags |= ATA_FLAG_FPDMA_AA;
1449
1450 /*
1451 * All AHCI controllers should be forward-compatible
1452 * with the new auxiliary field. This code should be
1453 * conditionalized if any buggy AHCI controllers are
1454 * encountered.
1455 */
1456 pi.flags |= ATA_FLAG_FPDMA_AUX;
1457 }
1458
1459 if (hpriv->cap & HOST_CAP_PMP)
1460 pi.flags |= ATA_FLAG_PMP;
1461
1462 ahci_set_em_messages(hpriv, &pi);
1463
1464 if (ahci_broken_system_poweroff(pdev)) {
1465 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1466 dev_info(&pdev->dev,
1467 "quirky BIOS, skipping spindown on poweroff\n");
1468 }
1469
1470 if (ahci_broken_suspend(pdev)) {
1471 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1472 dev_warn(&pdev->dev,
1473 "BIOS update required for suspend/resume\n");
1474 }
1475
1476 if (ahci_broken_online(pdev)) {
1477 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1478 dev_info(&pdev->dev,
1479 "online status unreliable, applying workaround\n");
1480 }
1481
1482 /* CAP.NP sometimes indicate the index of the last enabled
1483 * port, at other times, that of the last possible port, so
1484 * determining the maximum port number requires looking at
1485 * both CAP.NP and port_map.
1486 */
1487 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1488
1489 ahci_init_interrupts(pdev, n_ports, hpriv);
1490
1491 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1492 if (!host)
1493 return -ENOMEM;
1494 host->private_data = hpriv;
1495
1496 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1497 host->flags |= ATA_HOST_PARALLEL_SCAN;
1498 else
1499 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1500
1501 if (pi.flags & ATA_FLAG_EM)
1502 ahci_reset_em(host);
1503
1504 for (i = 0; i < host->n_ports; i++) {
1505 struct ata_port *ap = host->ports[i];
1506
1507 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1508 ata_port_pbar_desc(ap, ahci_pci_bar,
1509 0x100 + ap->port_no * 0x80, "port");
1510
1511 /* set enclosure management message type */
1512 if (ap->flags & ATA_FLAG_EM)
1513 ap->em_message_type = hpriv->em_msg_type;
1514
1515
1516 /* disabled/not-implemented port */
1517 if (!(hpriv->port_map & (1 << i)))
1518 ap->ops = &ata_dummy_port_ops;
1519 }
1520
1521 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1522 ahci_p5wdh_workaround(host);
1523
1524 /* apply gtf filter quirk */
1525 ahci_gtf_filter_workaround(host);
1526
1527 /* initialize adapter */
1528 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1529 if (rc)
1530 return rc;
1531
1532 rc = ahci_pci_reset_controller(host);
1533 if (rc)
1534 return rc;
1535
1536 ahci_pci_init_controller(host);
1537 ahci_pci_print_info(host);
1538
1539 pci_set_master(pdev);
1540
1541 return ahci_host_activate(host, pdev->irq, &ahci_sht);
1542 }
1543
1544 module_pci_driver(ahci_pci_driver);
1545
1546 MODULE_AUTHOR("Jeff Garzik");
1547 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1548 MODULE_LICENSE("GPL");
1549 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1550 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support