drivers/crypto/caam/regs.h

   1 /*
   2  * CAAM hardware register-level view
   3  *
   4  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   5  */
   6
   7 #ifndef REGS_H
   8 #define REGS_H
   9
  10 #include <linux/types.h>
  11 #include <linux/io.h>
  12
  13 /*
  14  * Architecture-specific register access methods
  15  *
  16  * CAAM's bus-addressable registers are 64 bits internally.
  17  * They have been wired to be safely accessible on 32-bit
  18  * architectures, however. Registers were organized such
  19  * that (a) they can be contained in 32 bits, (b) if not, then they
  20  * can be treated as two 32-bit entities, or finally (c) if they
  21  * must be treated as a single 64-bit value, then this can safely
  22  * be done with two 32-bit cycles.
  23  *
  24  * For 32-bit operations on 64-bit values, CAAM follows the same
  25  * 64-bit register access conventions as it's predecessors, in that
  26  * writes are "triggered" by a write to the register at the numerically
  27  * higher address, thus, a full 64-bit write cycle requires a write
  28  * to the lower address, followed by a write to the higher address,
  29  * which will latch/execute the write cycle.
  30  *
  31  * For example, let's assume a SW reset of CAAM through the master
  32  * configuration register.
  33  * - SWRST is in bit 31 of MCFG.
  34  * - MCFG begins at base+0x0000.
  35  * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
  36  * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
  37  *
  38  * (and on Power, the convention is 0-31, 32-63, I know...)
  39  *
  40  * Assuming a 64-bit write to this MCFG to perform a software reset
  41  * would then require a write of 0 to base+0x0000, followed by a
  42  * write of 0x80000000 to base+0x0004, which would "execute" the
  43  * reset.
  44  *
  45  * Of course, since MCFG 63-32 is all zero, we could cheat and simply
  46  * write 0x8000000 to base+0x0004, and the reset would work fine.
  47  * However, since CAAM does contain some write-and-read-intended
  48  * 64-bit registers, this code defines 64-bit access methods for
  49  * the sake of internal consistency and simplicity, and so that a
  50  * clean transition to 64-bit is possible when it becomes necessary.
  51  *
  52  * There are limitations to this that the developer must recognize.
  53  * 32-bit architectures cannot enforce an atomic-64 operation,
  54  * Therefore:
  55  *
  56  * - On writes, since the HW is assumed to latch the cycle on the
  57  *   write of the higher-numeric-address word, then ordered
  58  *   writes work OK.
  59  *
  60  * - For reads, where a register contains a relevant value of more
  61  *   that 32 bits, the hardware employs logic to latch the other
  62  *   "half" of the data until read, ensuring an accurate value.
  63  *   This is of particular relevance when dealing with CAAM's
  64  *   performance counters.
  65  *
  66  */
  67
  68 #ifdef __BIG_ENDIAN
  69 #define wr_reg32(reg, data) out_be32(reg, data)
  70 #define rd_reg32(reg) in_be32(reg)
  71 #ifdef CONFIG_64BIT
  72 #define wr_reg64(reg, data) out_be64(reg, data)
  73 #define rd_reg64(reg) in_be64(reg)
  74 #endif
  75 #else
  76 #ifdef __LITTLE_ENDIAN
  77 #define wr_reg32(reg, data) __raw_writel(data, reg)
  78 #define rd_reg32(reg) __raw_readl(reg)
  79 #ifdef CONFIG_64BIT
  80 #define wr_reg64(reg, data) __raw_writeq(data, reg)
  81 #define rd_reg64(reg) __raw_readq(reg)
  82 #endif
  83 #endif
  84 #endif
  85
  86 #ifndef CONFIG_64BIT
  87 #ifdef __BIG_ENDIAN
  88 static inline void wr_reg64(u64 __iomem *reg, u64 data)
  89 {
  90         wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
  91         wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
  92 }
  93
  94 static inline u64 rd_reg64(u64 __iomem *reg)
  95 {
  96         return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
  97                 ((u64)rd_reg32((u32 __iomem *)reg + 1));
  98 }
  99 #else
 100 #ifdef __LITTLE_ENDIAN
 101 static inline void wr_reg64(u64 __iomem *reg, u64 data)
 102 {
 103         wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
 104         wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
 105 }
 106
 107 static inline u64 rd_reg64(u64 __iomem *reg)
 108 {
 109         return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
 110                 ((u64)rd_reg32((u32 __iomem *)reg));
 111 }
 112 #endif
 113 #endif
 114 #endif
 115
 116 /*
 117  * jr_outentry
 118  * Represents each entry in a JobR output ring
 119  */
 120 struct jr_outentry {
 121         dma_addr_t desc;/* Pointer to completed descriptor */
 122         u32 jrstatus;   /* Status for completed descriptor */
 123 } __packed;
 124
 125 /*
 126  * caam_perfmon - Performance Monitor/Secure Memory Status/
 127  *                CAAM Global Status/Component Version IDs
 128  *
 129  * Spans f00-fff wherever instantiated
 130  */
 131
 132 /* Number of DECOs */
 133 #define CHA_NUM_MS_DECONUM_SHIFT        24
 134 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
 135
 136 /* CHA Version IDs */
 137 #define CHA_ID_LS_AES_SHIFT     0
 138 #define CHA_ID_LS_AES_MASK              (0xfull << CHA_ID_LS_AES_SHIFT)
 139
 140 #define CHA_ID_LS_DES_SHIFT     4
 141 #define CHA_ID_LS_DES_MASK              (0xfull << CHA_ID_LS_DES_SHIFT)
 142
 143 #define CHA_ID_LS_ARC4_SHIFT    8
 144 #define CHA_ID_LS_ARC4_MASK     (0xfull << CHA_ID_LS_ARC4_SHIFT)
 145
 146 #define CHA_ID_LS_MD_SHIFT      12
 147 #define CHA_ID_LS_MD_MASK       (0xfull << CHA_ID_LS_MD_SHIFT)
 148
 149 #define CHA_ID_LS_RNG_SHIFT     16
 150 #define CHA_ID_LS_RNG_MASK      (0xfull << CHA_ID_LS_RNG_SHIFT)
 151
 152 #define CHA_ID_LS_SNW8_SHIFT    20
 153 #define CHA_ID_LS_SNW8_MASK     (0xfull << CHA_ID_LS_SNW8_SHIFT)
 154
 155 #define CHA_ID_LS_KAS_SHIFT     24
 156 #define CHA_ID_LS_KAS_MASK      (0xfull << CHA_ID_LS_KAS_SHIFT)
 157
 158 #define CHA_ID_LS_PK_SHIFT      28
 159 #define CHA_ID_LS_PK_MASK       (0xfull << CHA_ID_LS_PK_SHIFT)
 160
 161 #define CHA_ID_MS_CRC_SHIFT     0
 162 #define CHA_ID_MS_CRC_MASK      (0xfull << CHA_ID_MS_CRC_SHIFT)
 163
 164 #define CHA_ID_MS_SNW9_SHIFT    4
 165 #define CHA_ID_MS_SNW9_MASK     (0xfull << CHA_ID_MS_SNW9_SHIFT)
 166
 167 #define CHA_ID_MS_DECO_SHIFT    24
 168 #define CHA_ID_MS_DECO_MASK     (0xfull << CHA_ID_MS_DECO_SHIFT)
 169
 170 #define CHA_ID_MS_JR_SHIFT      28
 171 #define CHA_ID_MS_JR_MASK       (0xfull << CHA_ID_MS_JR_SHIFT)
 172
 173 struct sec_vid {
 174         u16 ip_id;
 175         u8 maj_rev;
 176         u8 min_rev;
 177 };
 178
 179 struct caam_perfmon {
 180         /* Performance Monitor Registers                        f00-f9f */
 181         u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
 182         u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
 183         u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
 184         u64 ob_enc_bytes;       /* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
 185         u64 ob_prot_bytes;      /* PC_OB_PROTECT - Outbound Bytes Protected  */
 186         u64 ib_dec_bytes;       /* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
 187         u64 ib_valid_bytes;     /* PC_IB_VALIDATED Inbound Bytes Validated   */
 188         u64 rsvd[13];
 189
 190         /* CAAM Hardware Instantiation Parameters               fa0-fbf */
 191         u32 cha_rev_ms;         /* CRNR - CHA Rev No. Most significant half*/
 192         u32 cha_rev_ls;         /* CRNR - CHA Rev No. Least significant half*/
 193 #define CTPR_MS_QI_SHIFT        25
 194 #define CTPR_MS_QI_MASK         (0x1ull << CTPR_MS_QI_SHIFT)
 195 #define CTPR_MS_VIRT_EN_INCL    0x00000001
 196 #define CTPR_MS_VIRT_EN_POR     0x00000002
 197 #define CTPR_MS_PG_SZ_MASK      0x10
 198 #define CTPR_MS_PG_SZ_SHIFT     4
 199         u32 comp_parms_ms;      /* CTPR - Compile Parameters Register   */
 200         u32 comp_parms_ls;      /* CTPR - Compile Parameters Register   */
 201         u64 rsvd1[2];
 202
 203         /* CAAM Global Status                                   fc0-fdf */
 204         u64 faultaddr;  /* FAR  - Fault Address         */
 205         u32 faultliodn; /* FALR - Fault Address LIODN   */
 206         u32 faultdetail;        /* FADR - Fault Addr Detail     */
 207         u32 rsvd2;
 208         u32 status;             /* CSTA - CAAM Status */
 209         u64 rsvd3;
 210
 211         /* Component Instantiation Parameters                   fe0-fff */
 212         u32 rtic_id;            /* RVID - RTIC Version ID       */
 213         u32 ccb_id;             /* CCBVID - CCB Version ID      */
 214         u32 cha_id_ms;          /* CHAVID - CHA Version ID Most Significant*/
 215         u32 cha_id_ls;          /* CHAVID - CHA Version ID Least Significant*/
 216         u32 cha_num_ms;         /* CHANUM - CHA Number Most Significant */
 217         u32 cha_num_ls;         /* CHANUM - CHA Number Least Significant*/
 218         u32 caam_id_ms;         /* CAAMVID - CAAM Version ID MS */
 219         u32 caam_id_ls;         /* CAAMVID - CAAM Version ID LS */
 220 };
 221
 222 /* LIODN programming for DMA configuration */
 223 #define MSTRID_LOCK_LIODN       0x80000000
 224 #define MSTRID_LOCK_MAKETRUSTED 0x00010000      /* only for JR masterid */
 225
 226 #define MSTRID_LIODN_MASK       0x0fff
 227 struct masterid {
 228         u32 liodn_ms;   /* lock and make-trusted control bits */
 229         u32 liodn_ls;   /* LIODN for non-sequence and seq access */
 230 };
 231
 232 /* Partition ID for DMA configuration */
 233 struct partid {
 234         u32 rsvd1;
 235         u32 pidr;       /* partition ID, DECO */
 236 };
 237
 238 /* RNGB test mode (replicated twice in some configurations) */
 239 /* Padded out to 0x100 */
 240 struct rngtst {
 241         u32 mode;               /* RTSTMODEx - Test mode */
 242         u32 rsvd1[3];
 243         u32 reset;              /* RTSTRESETx - Test reset control */
 244         u32 rsvd2[3];
 245         u32 status;             /* RTSTSSTATUSx - Test status */
 246         u32 rsvd3;
 247         u32 errstat;            /* RTSTERRSTATx - Test error status */
 248         u32 rsvd4;
 249         u32 errctl;             /* RTSTERRCTLx - Test error control */
 250         u32 rsvd5;
 251         u32 entropy;            /* RTSTENTROPYx - Test entropy */
 252         u32 rsvd6[15];
 253         u32 verifctl;   /* RTSTVERIFCTLx - Test verification control */
 254         u32 rsvd7;
 255         u32 verifstat;  /* RTSTVERIFSTATx - Test verification status */
 256         u32 rsvd8;
 257         u32 verifdata;  /* RTSTVERIFDx - Test verification data */
 258         u32 rsvd9;
 259         u32 xkey;               /* RTSTXKEYx - Test XKEY */
 260         u32 rsvd10;
 261         u32 oscctctl;   /* RTSTOSCCTCTLx - Test osc. counter control */
 262         u32 rsvd11;
 263         u32 oscct;              /* RTSTOSCCTx - Test oscillator counter */
 264         u32 rsvd12;
 265         u32 oscctstat;  /* RTSTODCCTSTATx - Test osc counter status */
 266         u32 rsvd13[2];
 267         u32 ofifo[4];   /* RTSTOFIFOx - Test output FIFO */
 268         u32 rsvd14[15];
 269 };
 270
 271 /* RNG4 TRNG test registers */
 272 struct rng4tst {
 273 #define RTMCTL_PRGM     0x00010000      /* 1 -> program mode, 0 -> run mode */
 274 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC      0 /* use von Neumann data in
 275                                                      both entropy shifter and
 276                                                      statistical checker */
 277 #define RTMCTL_SAMP_MODE_RAW_ES_SC              1 /* use raw data in both
 278                                                      entropy shifter and
 279                                                      statistical checker */
 280 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC  2 /* use von Neumann data in
 281                                                      entropy shifter, raw data
 282                                                      in statistical checker */
 283 #define RTMCTL_SAMP_MODE_INVALID                3 /* invalid combination */
 284         u32 rtmctl;             /* misc. control register */
 285         u32 rtscmisc;           /* statistical check misc. register */
 286         u32 rtpkrrng;           /* poker range register */
 287         union {
 288                 u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
 289                 u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
 290         };
 291 #define RTSDCTL_ENT_DLY_SHIFT 16
 292 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
 293 #define RTSDCTL_ENT_DLY_MIN 3200
 294 #define RTSDCTL_ENT_DLY_MAX 12800
 295         u32 rtsdctl;            /* seed control register */
 296         union {
 297                 u32 rtsblim;    /* PRGM=1: sparse bit limit register */
 298                 u32 rttotsam;   /* PRGM=0: total samples register */
 299         };
 300         u32 rtfrqmin;           /* frequency count min. limit register */
 301 #define RTFRQMAX_DISABLE        (1 << 20)
 302         union {
 303                 u32 rtfrqmax;   /* PRGM=1: freq. count max. limit register */
 304                 u32 rtfrqcnt;   /* PRGM=0: freq. count register */
 305         };
 306         u32 rsvd1[40];
 307 #define RDSTA_SKVT 0x80000000
 308 #define RDSTA_SKVN 0x40000000
 309 #define RDSTA_IF0 0x00000001
 310 #define RDSTA_IF1 0x00000002
 311 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
 312         u32 rdsta;
 313         u32 rsvd2[15];
 314 };
 315
 316 /*
 317  * caam_ctrl - basic core configuration
 318  * starts base + 0x0000 padded out to 0x1000
 319  */
 320
 321 #define KEK_KEY_SIZE            8
 322 #define TKEK_KEY_SIZE           8
 323 #define TDSK_KEY_SIZE           8
 324
 325 #define DECO_RESET      1       /* Use with DECO reset/availability regs */
 326 #define DECO_RESET_0    (DECO_RESET << 0)
 327 #define DECO_RESET_1    (DECO_RESET << 1)
 328 #define DECO_RESET_2    (DECO_RESET << 2)
 329 #define DECO_RESET_3    (DECO_RESET << 3)
 330 #define DECO_RESET_4    (DECO_RESET << 4)
 331
 332 struct caam_ctrl {
 333         /* Basic Configuration Section                          000-01f */
 334         /* Read/Writable                                                */
 335         u32 rsvd1;
 336         u32 mcr;                /* MCFG      Master Config Register  */
 337         u32 rsvd2;
 338         u32 scfgr;              /* SCFGR, Security Config Register */
 339
 340         /* Bus Access Configuration Section                     010-11f */
 341         /* Read/Writable                                                */
 342         struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
 343         u32 rsvd3[11];
 344         u32 jrstart;                    /* JRSTART - Job Ring Start Register */
 345         struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
 346         u32 rsvd4[5];
 347         u32 deco_rsr;                   /* DECORSR - Deco Request Source */
 348         u32 rsvd11;
 349         u32 deco_rq;                    /* DECORR - DECO Request */
 350         struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
 351         u32 rsvd5[22];
 352
 353         /* DECO Availability/Reset Section                      120-3ff */
 354         u32 deco_avail;         /* DAR - DECO availability */
 355         u32 deco_reset;         /* DRR - DECO reset */
 356         u32 rsvd6[182];
 357
 358         /* Key Encryption/Decryption Configuration              400-5ff */
 359         /* Read/Writable only while in Non-secure mode                  */
 360         u32 kek[KEK_KEY_SIZE];  /* JDKEKR - Key Encryption Key */
 361         u32 tkek[TKEK_KEY_SIZE];        /* TDKEKR - Trusted Desc KEK */
 362         u32 tdsk[TDSK_KEY_SIZE];        /* TDSKR - Trusted Desc Signing Key */
 363         u32 rsvd7[32];
 364         u64 sknonce;                    /* SKNR - Secure Key Nonce */
 365         u32 rsvd8[70];
 366
 367         /* RNG Test/Verification/Debug Access                   600-7ff */
 368         /* (Useful in Test/Debug modes only...)                         */
 369         union {
 370                 struct rngtst rtst[2];
 371                 struct rng4tst r4tst[2];
 372         };
 373
 374         u32 rsvd9[448];
 375
 376         /* Performance Monitor                                  f00-fff */
 377         struct caam_perfmon perfmon;
 378 };
 379
 380 /*
 381  * Controller master config register defs
 382  */
 383 #define MCFGR_SWRESET           0x80000000 /* software reset */
 384 #define MCFGR_WDENABLE          0x40000000 /* DECO watchdog enable */
 385 #define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 386 #define MCFGR_DMA_RESET         0x10000000
 387 #define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
 388 #define SCFGR_RDBENABLE         0x00000400
 389 #define SCFGR_VIRT_EN           0x00008000
 390 #define DECORR_RQD0ENABLE       0x00000001 /* Enable DECO0 for direct access */
 391 #define DECORSR_JR0             0x00000001 /* JR to supply TZ, SDID, ICID */
 392 #define DECORSR_VALID           0x80000000
 393 #define DECORR_DEN0             0x00010000 /* DECO0 available for access*/
 394
 395 /* AXI read cache control */
 396 #define MCFGR_ARCACHE_SHIFT     12
 397 #define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
 398
 399 /* AXI write cache control */
 400 #define MCFGR_AWCACHE_SHIFT     8
 401 #define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
 402
 403 /* AXI pipeline depth */
 404 #define MCFGR_AXIPIPE_SHIFT     4
 405 #define MCFGR_AXIPIPE_MASK      (0xf << MCFGR_AXIPIPE_SHIFT)
 406
 407 #define MCFGR_AXIPRI            0x00000008 /* Assert AXI priority sideband */
 408 #define MCFGR_BURST_64          0x00000001 /* Max burst size */
 409
 410 /* JRSTART register offsets */
 411 #define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
 412 #define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
 413 #define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
 414 #define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
 415
 416 /*
 417  * caam_job_ring - direct job ring setup
 418  * 1-4 possible per instantiation, base + 1000/2000/3000/4000
 419  * Padded out to 0x1000
 420  */
 421 struct caam_job_ring {
 422         /* Input ring */
 423         u64 inpring_base;       /* IRBAx -  Input desc ring baseaddr */
 424         u32 rsvd1;
 425         u32 inpring_size;       /* IRSx - Input ring size */
 426         u32 rsvd2;
 427         u32 inpring_avail;      /* IRSAx - Input ring room remaining */
 428         u32 rsvd3;
 429         u32 inpring_jobadd;     /* IRJAx - Input ring jobs added */
 430
 431         /* Output Ring */
 432         u64 outring_base;       /* ORBAx - Output status ring base addr */
 433         u32 rsvd4;
 434         u32 outring_size;       /* ORSx - Output ring size */
 435         u32 rsvd5;
 436         u32 outring_rmvd;       /* ORJRx - Output ring jobs removed */
 437         u32 rsvd6;
 438         u32 outring_used;       /* ORSFx - Output ring slots full */
 439
 440         /* Status/Configuration */
 441         u32 rsvd7;
 442         u32 jroutstatus;        /* JRSTAx - JobR output status */
 443         u32 rsvd8;
 444         u32 jrintstatus;        /* JRINTx - JobR interrupt status */
 445         u32 rconfig_hi; /* JRxCFG - Ring configuration */
 446         u32 rconfig_lo;
 447
 448         /* Indices. CAAM maintains as "heads" of each queue */
 449         u32 rsvd9;
 450         u32 inp_rdidx;  /* IRRIx - Input ring read index */
 451         u32 rsvd10;
 452         u32 out_wtidx;  /* ORWIx - Output ring write index */
 453
 454         /* Command/control */
 455         u32 rsvd11;
 456         u32 jrcommand;  /* JRCRx - JobR command */
 457
 458         u32 rsvd12[932];
 459
 460         /* Performance Monitor                                  f00-fff */
 461         struct caam_perfmon perfmon;
 462 };
 463
 464 #define JR_RINGSIZE_MASK        0x03ff
 465 /*
 466  * jrstatus - Job Ring Output Status
 467  * All values in lo word
 468  * Also note, same values written out as status through QI
 469  * in the command/status field of a frame descriptor
 470  */
 471 #define JRSTA_SSRC_SHIFT            28
 472 #define JRSTA_SSRC_MASK             0xf0000000
 473
 474 #define JRSTA_SSRC_NONE             0x00000000
 475 #define JRSTA_SSRC_CCB_ERROR        0x20000000
 476 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
 477 #define JRSTA_SSRC_DECO             0x40000000
 478 #define JRSTA_SSRC_JRERROR          0x60000000
 479 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
 480
 481 #define JRSTA_DECOERR_JUMP          0x08000000
 482 #define JRSTA_DECOERR_INDEX_SHIFT   8
 483 #define JRSTA_DECOERR_INDEX_MASK    0xff00
 484 #define JRSTA_DECOERR_ERROR_MASK    0x00ff
 485
 486 #define JRSTA_DECOERR_NONE          0x00
 487 #define JRSTA_DECOERR_LINKLEN       0x01
 488 #define JRSTA_DECOERR_LINKPTR       0x02
 489 #define JRSTA_DECOERR_JRCTRL        0x03
 490 #define JRSTA_DECOERR_DESCCMD       0x04
 491 #define JRSTA_DECOERR_ORDER         0x05
 492 #define JRSTA_DECOERR_KEYCMD        0x06
 493 #define JRSTA_DECOERR_LOADCMD       0x07
 494 #define JRSTA_DECOERR_STORECMD      0x08
 495 #define JRSTA_DECOERR_OPCMD         0x09
 496 #define JRSTA_DECOERR_FIFOLDCMD     0x0a
 497 #define JRSTA_DECOERR_FIFOSTCMD     0x0b
 498 #define JRSTA_DECOERR_MOVECMD       0x0c
 499 #define JRSTA_DECOERR_JUMPCMD       0x0d
 500 #define JRSTA_DECOERR_MATHCMD       0x0e
 501 #define JRSTA_DECOERR_SHASHCMD      0x0f
 502 #define JRSTA_DECOERR_SEQCMD        0x10
 503 #define JRSTA_DECOERR_DECOINTERNAL  0x11
 504 #define JRSTA_DECOERR_SHDESCHDR     0x12
 505 #define JRSTA_DECOERR_HDRLEN        0x13
 506 #define JRSTA_DECOERR_BURSTER       0x14
 507 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
 508 #define JRSTA_DECOERR_DMA           0x16
 509 #define JRSTA_DECOERR_BURSTFIFO     0x17
 510 #define JRSTA_DECOERR_JRRESET       0x1a
 511 #define JRSTA_DECOERR_JOBFAIL       0x1b
 512 #define JRSTA_DECOERR_DNRERR        0x80
 513 #define JRSTA_DECOERR_UNDEFPCL      0x81
 514 #define JRSTA_DECOERR_PDBERR        0x82
 515 #define JRSTA_DECOERR_ANRPLY_LATE   0x83
 516 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
 517 #define JRSTA_DECOERR_SEQOVF        0x85
 518 #define JRSTA_DECOERR_INVSIGN       0x86
 519 #define JRSTA_DECOERR_DSASIGN       0x87
 520
 521 #define JRSTA_CCBERR_JUMP           0x08000000
 522 #define JRSTA_CCBERR_INDEX_MASK     0xff00
 523 #define JRSTA_CCBERR_INDEX_SHIFT    8
 524 #define JRSTA_CCBERR_CHAID_MASK     0x00f0
 525 #define JRSTA_CCBERR_CHAID_SHIFT    4
 526 #define JRSTA_CCBERR_ERRID_MASK     0x000f
 527
 528 #define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
 529 #define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
 530 #define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
 531 #define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
 532 #define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
 533 #define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
 534 #define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
 535 #define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
 536 #define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
 537
 538 #define JRSTA_CCBERR_ERRID_NONE     0x00
 539 #define JRSTA_CCBERR_ERRID_MODE     0x01
 540 #define JRSTA_CCBERR_ERRID_DATASIZ  0x02
 541 #define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
 542 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
 543 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
 544 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
 545 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
 546 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
 547 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
 548 #define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
 549 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
 550 #define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
 551 #define JRSTA_CCBERR_ERRID_INVCHA   0x0f
 552
 553 #define JRINT_ERR_INDEX_MASK        0x3fff0000
 554 #define JRINT_ERR_INDEX_SHIFT       16
 555 #define JRINT_ERR_TYPE_MASK         0xf00
 556 #define JRINT_ERR_TYPE_SHIFT        8
 557 #define JRINT_ERR_HALT_MASK         0xc
 558 #define JRINT_ERR_HALT_SHIFT        2
 559 #define JRINT_ERR_HALT_INPROGRESS   0x4
 560 #define JRINT_ERR_HALT_COMPLETE     0x8
 561 #define JRINT_JR_ERROR              0x02
 562 #define JRINT_JR_INT                0x01
 563
 564 #define JRINT_ERR_TYPE_WRITE        1
 565 #define JRINT_ERR_TYPE_BAD_INPADDR  3
 566 #define JRINT_ERR_TYPE_BAD_OUTADDR  4
 567 #define JRINT_ERR_TYPE_INV_INPWRT   5
 568 #define JRINT_ERR_TYPE_INV_OUTWRT   6
 569 #define JRINT_ERR_TYPE_RESET        7
 570 #define JRINT_ERR_TYPE_REMOVE_OFL   8
 571 #define JRINT_ERR_TYPE_ADD_OFL      9
 572
 573 #define JRCFG_SOE               0x04
 574 #define JRCFG_ICEN              0x02
 575 #define JRCFG_IMSK              0x01
 576 #define JRCFG_ICDCT_SHIFT       8
 577 #define JRCFG_ICTT_SHIFT        16
 578
 579 #define JRCR_RESET                  0x01
 580
 581 /*
 582  * caam_assurance - Assurance Controller View
 583  * base + 0x6000 padded out to 0x1000
 584  */
 585
 586 struct rtic_element {
 587         u64 address;
 588         u32 rsvd;
 589         u32 length;
 590 };
 591
 592 struct rtic_block {
 593         struct rtic_element element[2];
 594 };
 595
 596 struct rtic_memhash {
 597         u32 memhash_be[32];
 598         u32 memhash_le[32];
 599 };
 600
 601 struct caam_assurance {
 602     /* Status/Command/Watchdog */
 603         u32 rsvd1;
 604         u32 status;             /* RSTA - Status */
 605         u32 rsvd2;
 606         u32 cmd;                /* RCMD - Command */
 607         u32 rsvd3;
 608         u32 ctrl;               /* RCTL - Control */
 609         u32 rsvd4;
 610         u32 throttle;   /* RTHR - Throttle */
 611         u32 rsvd5[2];
 612         u64 watchdog;   /* RWDOG - Watchdog Timer */
 613         u32 rsvd6;
 614         u32 rend;               /* REND - Endian corrections */
 615         u32 rsvd7[50];
 616
 617         /* Block access/configuration @ 100/110/120/130 */
 618         struct rtic_block memblk[4];    /* Memory Blocks A-D */
 619         u32 rsvd8[32];
 620
 621         /* Block hashes @ 200/300/400/500 */
 622         struct rtic_memhash hash[4];    /* Block hash values A-D */
 623         u32 rsvd_3[640];
 624 };
 625
 626 /*
 627  * caam_queue_if - QI configuration and control
 628  * starts base + 0x7000, padded out to 0x1000 long
 629  */
 630
 631 struct caam_queue_if {
 632         u32 qi_control_hi;      /* QICTL  - QI Control */
 633         u32 qi_control_lo;
 634         u32 rsvd1;
 635         u32 qi_status;  /* QISTA  - QI Status */
 636         u32 qi_deq_cfg_hi;      /* QIDQC  - QI Dequeue Configuration */
 637         u32 qi_deq_cfg_lo;
 638         u32 qi_enq_cfg_hi;      /* QISEQC - QI Enqueue Command     */
 639         u32 qi_enq_cfg_lo;
 640         u32 rsvd2[1016];
 641 };
 642
 643 /* QI control bits - low word */
 644 #define QICTL_DQEN      0x01              /* Enable frame pop          */
 645 #define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
 646 #define QICTL_SOE       0x04              /* Stop on error             */
 647
 648 /* QI control bits - high word */
 649 #define QICTL_MBSI      0x01
 650 #define QICTL_MHWSI     0x02
 651 #define QICTL_MWSI      0x04
 652 #define QICTL_MDWSI     0x08
 653 #define QICTL_CBSI      0x10            /* CtrlDataByteSwapInput     */
 654 #define QICTL_CHWSI     0x20            /* CtrlDataHalfSwapInput     */
 655 #define QICTL_CWSI      0x40            /* CtrlDataWordSwapInput     */
 656 #define QICTL_CDWSI     0x80            /* CtrlDataDWordSwapInput    */
 657 #define QICTL_MBSO      0x0100
 658 #define QICTL_MHWSO     0x0200
 659 #define QICTL_MWSO      0x0400
 660 #define QICTL_MDWSO     0x0800
 661 #define QICTL_CBSO      0x1000          /* CtrlDataByteSwapOutput    */
 662 #define QICTL_CHWSO     0x2000          /* CtrlDataHalfSwapOutput    */
 663 #define QICTL_CWSO      0x4000          /* CtrlDataWordSwapOutput    */
 664 #define QICTL_CDWSO     0x8000          /* CtrlDataDWordSwapOutput   */
 665 #define QICTL_DMBS      0x010000
 666 #define QICTL_EPO       0x020000
 667
 668 /* QI status bits */
 669 #define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
 670 #define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
 671 #define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
 672 #define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
 673 #define QISTA_BTSERR    0x10              /* Buffer Undersize          */
 674 #define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
 675 #define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
 676
 677 /* deco_sg_table - DECO view of scatter/gather table */
 678 struct deco_sg_table {
 679         u64 addr;               /* Segment Address */
 680         u32 elen;               /* E, F bits + 30-bit length */
 681         u32 bpid_offset;        /* Buffer Pool ID + 16-bit length */
 682 };
 683
 684 /*
 685  * caam_deco - descriptor controller - CHA cluster block
 686  *
 687  * Only accessible when direct DECO access is turned on
 688  * (done in DECORR, via MID programmed in DECOxMID
 689  *
 690  * 5 typical, base + 0x8000/9000/a000/b000
 691  * Padded out to 0x1000 long
 692  */
 693 struct caam_deco {
 694         u32 rsvd1;
 695         u32 cls1_mode;  /* CxC1MR -  Class 1 Mode */
 696         u32 rsvd2;
 697         u32 cls1_keysize;       /* CxC1KSR - Class 1 Key Size */
 698         u32 cls1_datasize_hi;   /* CxC1DSR - Class 1 Data Size */
 699         u32 cls1_datasize_lo;
 700         u32 rsvd3;
 701         u32 cls1_icvsize;       /* CxC1ICVSR - Class 1 ICV size */
 702         u32 rsvd4[5];
 703         u32 cha_ctrl;   /* CCTLR - CHA control */
 704         u32 rsvd5;
 705         u32 irq_crtl;   /* CxCIRQ - CCB interrupt done/error/clear */
 706         u32 rsvd6;
 707         u32 clr_written;        /* CxCWR - Clear-Written */
 708         u32 ccb_status_hi;      /* CxCSTA - CCB Status/Error */
 709         u32 ccb_status_lo;
 710         u32 rsvd7[3];
 711         u32 aad_size;   /* CxAADSZR - Current AAD Size */
 712         u32 rsvd8;
 713         u32 cls1_iv_size;       /* CxC1IVSZR - Current Class 1 IV Size */
 714         u32 rsvd9[7];
 715         u32 pkha_a_size;        /* PKASZRx - Size of PKHA A */
 716         u32 rsvd10;
 717         u32 pkha_b_size;        /* PKBSZRx - Size of PKHA B */
 718         u32 rsvd11;
 719         u32 pkha_n_size;        /* PKNSZRx - Size of PKHA N */
 720         u32 rsvd12;
 721         u32 pkha_e_size;        /* PKESZRx - Size of PKHA E */
 722         u32 rsvd13[24];
 723         u32 cls1_ctx[16];       /* CxC1CTXR - Class 1 Context @100 */
 724         u32 rsvd14[48];
 725         u32 cls1_key[8];        /* CxC1KEYR - Class 1 Key @200 */
 726         u32 rsvd15[121];
 727         u32 cls2_mode;  /* CxC2MR - Class 2 Mode */
 728         u32 rsvd16;
 729         u32 cls2_keysize;       /* CxX2KSR - Class 2 Key Size */
 730         u32 cls2_datasize_hi;   /* CxC2DSR - Class 2 Data Size */
 731         u32 cls2_datasize_lo;
 732         u32 rsvd17;
 733         u32 cls2_icvsize;       /* CxC2ICVSZR - Class 2 ICV Size */
 734         u32 rsvd18[56];
 735         u32 cls2_ctx[18];       /* CxC2CTXR - Class 2 Context @500 */
 736         u32 rsvd19[46];
 737         u32 cls2_key[32];       /* CxC2KEYR - Class2 Key @600 */
 738         u32 rsvd20[84];
 739         u32 inp_infofifo_hi;    /* CxIFIFO - Input Info FIFO @7d0 */
 740         u32 inp_infofifo_lo;
 741         u32 rsvd21[2];
 742         u64 inp_datafifo;       /* CxDFIFO - Input Data FIFO */
 743         u32 rsvd22[2];
 744         u64 out_datafifo;       /* CxOFIFO - Output Data FIFO */
 745         u32 rsvd23[2];
 746         u32 jr_ctl_hi;  /* CxJRR - JobR Control Register      @800 */
 747         u32 jr_ctl_lo;
 748         u64 jr_descaddr;        /* CxDADR - JobR Descriptor Address */
 749 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
 750         u32 op_status_hi;       /* DxOPSTA - DECO Operation Status */
 751         u32 op_status_lo;
 752         u32 rsvd24[2];
 753         u32 liodn;              /* DxLSR - DECO LIODN Status - non-seq */
 754         u32 td_liodn;   /* DxLSR - DECO LIODN Status - trustdesc */
 755         u32 rsvd26[6];
 756         u64 math[4];            /* DxMTH - Math register */
 757         u32 rsvd27[8];
 758         struct deco_sg_table gthr_tbl[4];       /* DxGTR - Gather Tables */
 759         u32 rsvd28[16];
 760         struct deco_sg_table sctr_tbl[4];       /* DxSTR - Scatter Tables */
 761         u32 rsvd29[48];
 762         u32 descbuf[64];        /* DxDESB - Descriptor buffer */
 763         u32 rscvd30[193];
 764 #define DESC_DBG_DECO_STAT_HOST_ERR     0x00D00000
 765 #define DESC_DBG_DECO_STAT_VALID        0x80000000
 766 #define DESC_DBG_DECO_STAT_MASK         0x00F00000
 767         u32 desc_dbg;           /* DxDDR - DECO Debug Register */
 768         u32 rsvd31[126];
 769 };
 770
 771 #define DECO_JQCR_WHL           0x20000000
 772 #define DECO_JQCR_FOUR          0x10000000
 773
 774 #define JR_BLOCK_NUMBER         1
 775 #define ASSURE_BLOCK_NUMBER     6
 776 #define QI_BLOCK_NUMBER         7
 777 #define DECO_BLOCK_NUMBER       8
 778 #define PG_SIZE_4K              0x1000
 779 #define PG_SIZE_64K             0x10000
 780 #endif /* REGS_H */