drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_device.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/slab.h>
  35 #include <linux/basic_mmio_gpio.h>
  36 #include <linux/module.h>
  37
  38 #define MXS_SET         0x4
  39 #define MXS_CLR         0x8
  40
  41 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  42 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  43 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  44 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  45 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  46 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  47 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  48 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  49
  50 #define GPIO_INT_FALL_EDGE      0x0
  51 #define GPIO_INT_LOW_LEV        0x1
  52 #define GPIO_INT_RISE_EDGE      0x2
  53 #define GPIO_INT_HIGH_LEV       0x3
  54 #define GPIO_INT_LEV_MASK       (1 << 0)
  55 #define GPIO_INT_POL_MASK       (1 << 1)
  56
  57 enum mxs_gpio_id {
  58         IMX23_GPIO,
  59         IMX28_GPIO,
  60 };
  61
  62 struct mxs_gpio_port {
  63         void __iomem *base;
  64         int id;
  65         int irq;
  66         struct irq_domain *domain;
  67         struct bgpio_chip bgc;
  68         enum mxs_gpio_id devid;
  69         u32 both_edges;
  70 };
  71
  72 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  73 {
  74         return port->devid == IMX23_GPIO;
  75 }
  76
  77 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  78 {
  79         return port->devid == IMX28_GPIO;
  80 }
  81
  82 /* Note: This driver assumes 32 GPIOs are handled in one register */
  83
  84 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  85 {
  86         u32 val;
  87         u32 pin_mask = 1 << d->hwirq;
  88         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  89         struct mxs_gpio_port *port = gc->private;
  90         void __iomem *pin_addr;
  91         int edge;
  92
  93         port->both_edges &= ~pin_mask;
  94         switch (type) {
  95         case IRQ_TYPE_EDGE_BOTH:
  96                 val = gpio_get_value(port->bgc.gc.base + d->hwirq);
  97                 if (val)
  98                         edge = GPIO_INT_FALL_EDGE;
  99                 else
 100                         edge = GPIO_INT_RISE_EDGE;
 101                 port->both_edges |= pin_mask;
 102                 break;
 103         case IRQ_TYPE_EDGE_RISING:
 104                 edge = GPIO_INT_RISE_EDGE;
 105                 break;
 106         case IRQ_TYPE_EDGE_FALLING:
 107                 edge = GPIO_INT_FALL_EDGE;
 108                 break;
 109         case IRQ_TYPE_LEVEL_LOW:
 110                 edge = GPIO_INT_LOW_LEV;
 111                 break;
 112         case IRQ_TYPE_LEVEL_HIGH:
 113                 edge = GPIO_INT_HIGH_LEV;
 114                 break;
 115         default:
 116                 return -EINVAL;
 117         }
 118
 119         /* set level or edge */
 120         pin_addr = port->base + PINCTRL_IRQLEV(port);
 121         if (edge & GPIO_INT_LEV_MASK)
 122                 writel(pin_mask, pin_addr + MXS_SET);
 123         else
 124                 writel(pin_mask, pin_addr + MXS_CLR);
 125
 126         /* set polarity */
 127         pin_addr = port->base + PINCTRL_IRQPOL(port);
 128         if (edge & GPIO_INT_POL_MASK)
 129                 writel(pin_mask, pin_addr + MXS_SET);
 130         else
 131                 writel(pin_mask, pin_addr + MXS_CLR);
 132
 133         writel(pin_mask,
 134                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 135
 136         return 0;
 137 }
 138
 139 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
 140 {
 141         u32 bit, val, edge;
 142         void __iomem *pin_addr;
 143
 144         bit = 1 << gpio;
 145
 146         pin_addr = port->base + PINCTRL_IRQPOL(port);
 147         val = readl(pin_addr);
 148         edge = val & bit;
 149
 150         if (edge)
 151                 writel(bit, pin_addr + MXS_CLR);
 152         else
 153                 writel(bit, pin_addr + MXS_SET);
 154 }
 155
 156 /* MXS has one interrupt *per* gpio port */
 157 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 158 {
 159         u32 irq_stat;
 160         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 161
 162         desc->irq_data.chip->irq_ack(&desc->irq_data);
 163
 164         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 165                         readl(port->base + PINCTRL_IRQEN(port));
 166
 167         while (irq_stat != 0) {
 168                 int irqoffset = fls(irq_stat) - 1;
 169                 if (port->both_edges & (1 << irqoffset))
 170                         mxs_flip_edge(port, irqoffset);
 171
 172                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 173                 irq_stat &= ~(1 << irqoffset);
 174         }
 175 }
 176
 177 /*
 178  * Set interrupt number "irq" in the GPIO as a wake-up source.
 179  * While system is running, all registered GPIO interrupts need to have
 180  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 181  * need to have wake-up enabled.
 182  * @param  irq          interrupt source number
 183  * @param  enable       enable as wake-up if equal to non-zero
 184  * @return       This function returns 0 on success.
 185  */
 186 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 187 {
 188         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 189         struct mxs_gpio_port *port = gc->private;
 190
 191         if (enable)
 192                 enable_irq_wake(port->irq);
 193         else
 194                 disable_irq_wake(port->irq);
 195
 196         return 0;
 197 }
 198
 199 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 200 {
 201         struct irq_chip_generic *gc;
 202         struct irq_chip_type *ct;
 203
 204         gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
 205                                     port->base, handle_level_irq);
 206         gc->private = port;
 207
 208         ct = gc->chip_types;
 209         ct->chip.irq_ack = irq_gc_ack_set_bit;
 210         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 211         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 212         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 213         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 214         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 215         ct->regs.mask = PINCTRL_IRQEN(port);
 216
 217         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 218                                IRQ_NOREQUEST, 0);
 219 }
 220
 221 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 222 {
 223         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 224         struct mxs_gpio_port *port =
 225                 container_of(bgc, struct mxs_gpio_port, bgc);
 226
 227         return irq_find_mapping(port->domain, offset);
 228 }
 229
 230 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
 231 {
 232         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 233         struct mxs_gpio_port *port =
 234                 container_of(bgc, struct mxs_gpio_port, bgc);
 235         u32 mask = 1 << offset;
 236         u32 dir;
 237
 238         dir = readl(port->base + PINCTRL_DOE(port));
 239         return !(dir & mask);
 240 }
 241
 242 static struct platform_device_id mxs_gpio_ids[] = {
 243         {
 244                 .name = "imx23-gpio",
 245                 .driver_data = IMX23_GPIO,
 246         }, {
 247                 .name = "imx28-gpio",
 248                 .driver_data = IMX28_GPIO,
 249         }, {
 250                 /* sentinel */
 251         }
 252 };
 253 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 254
 255 static const struct of_device_id mxs_gpio_dt_ids[] = {
 256         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 257         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 258         { /* sentinel */ }
 259 };
 260 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 261
 262 static int mxs_gpio_probe(struct platform_device *pdev)
 263 {
 264         const struct of_device_id *of_id =
 265                         of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 266         struct device_node *np = pdev->dev.of_node;
 267         struct device_node *parent;
 268         static void __iomem *base;
 269         struct mxs_gpio_port *port;
 270         int irq_base;
 271         int err;
 272
 273         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 274         if (!port)
 275                 return -ENOMEM;
 276
 277         port->id = of_alias_get_id(np, "gpio");
 278         if (port->id < 0)
 279                 return port->id;
 280         port->devid = (enum mxs_gpio_id) of_id->data;
 281         port->irq = platform_get_irq(pdev, 0);
 282         if (port->irq < 0)
 283                 return port->irq;
 284
 285         /*
 286          * map memory region only once, as all the gpio ports
 287          * share the same one
 288          */
 289         if (!base) {
 290                 parent = of_get_parent(np);
 291                 base = of_iomap(parent, 0);
 292                 of_node_put(parent);
 293                 if (!base)
 294                         return -EADDRNOTAVAIL;
 295         }
 296         port->base = base;
 297
 298         /*
 299          * select the pin interrupt functionality but initially
 300          * disable the interrupts
 301          */
 302         writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
 303         writel(0, port->base + PINCTRL_IRQEN(port));
 304
 305         /* clear address has to be used to clear IRQSTAT bits */
 306         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 307
 308         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 309         if (irq_base < 0)
 310                 return irq_base;
 311
 312         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 313                                              &irq_domain_simple_ops, NULL);
 314         if (!port->domain) {
 315                 err = -ENODEV;
 316                 goto out_irqdesc_free;
 317         }
 318
 319         /* gpio-mxs can be a generic irq chip */
 320         mxs_gpio_init_gc(port, irq_base);
 321
 322         /* setup one handler for each entry */
 323         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 324         irq_set_handler_data(port->irq, port);
 325
 326         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 327                          port->base + PINCTRL_DIN(port),
 328                          port->base + PINCTRL_DOUT(port) + MXS_SET,
 329                          port->base + PINCTRL_DOUT(port) + MXS_CLR,
 330                          port->base + PINCTRL_DOE(port), NULL, 0);
 331         if (err)
 332                 goto out_irqdesc_free;
 333
 334         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 335         port->bgc.gc.get_direction = mxs_gpio_get_direction;
 336         port->bgc.gc.base = port->id * 32;
 337
 338         err = gpiochip_add(&port->bgc.gc);
 339         if (err)
 340                 goto out_bgpio_remove;
 341
 342         return 0;
 343
 344 out_bgpio_remove:
 345         bgpio_remove(&port->bgc);
 346 out_irqdesc_free:
 347         irq_free_descs(irq_base, 32);
 348         return err;
 349 }
 350
 351 static struct platform_driver mxs_gpio_driver = {
 352         .driver         = {
 353                 .name   = "gpio-mxs",
 354                 .of_match_table = mxs_gpio_dt_ids,
 355         },
 356         .probe          = mxs_gpio_probe,
 357         .id_table       = mxs_gpio_ids,
 358 };
 359
 360 static int __init mxs_gpio_init(void)
 361 {
 362         return platform_driver_register(&mxs_gpio_driver);
 363 }
 364 postcore_initcall(mxs_gpio_init);
 365
 366 MODULE_AUTHOR("Freescale Semiconductor, "
 367               "Daniel Mack <danielncaiaq.de>, "
 368               "Juergen Beisert <kernel@pengutronix.de>");
 369 MODULE_DESCRIPTION("Freescale MXS GPIO");
 370 MODULE_LICENSE("GPL");