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Linux 4.1.16
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_hdmi.c
blobbfbe07b6ddcedb3d00b724ad5691084c0621c2ef
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
82 return 0;
83 }
84 }
85
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
97 return 0;
98 }
99 }
100
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
112 return 0;
113 }
114 }
115
116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
117 enum transcoder cpu_transcoder,
118 struct drm_i915_private *dev_priv)
119 {
120 switch (type) {
121 case HDMI_INFOFRAME_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
123 case HDMI_INFOFRAME_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
125 case HDMI_INFOFRAME_TYPE_VENDOR:
126 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
127 default:
128 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
129 return 0;
130 }
131 }
132
133 static void g4x_write_infoframe(struct drm_encoder *encoder,
134 enum hdmi_infoframe_type type,
135 const void *frame, ssize_t len)
136 {
137 const uint32_t *data = frame;
138 struct drm_device *dev = encoder->dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 val = I915_READ(VIDEO_DIP_CTL);
141 int i;
142
143 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
144
145 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
146 val |= g4x_infoframe_index(type);
147
148 val &= ~g4x_infoframe_enable(type);
149
150 I915_WRITE(VIDEO_DIP_CTL, val);
151
152 mmiowb();
153 for (i = 0; i < len; i += 4) {
154 I915_WRITE(VIDEO_DIP_DATA, *data);
155 data++;
156 }
157 /* Write every possible data byte to force correct ECC calculation. */
158 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
159 I915_WRITE(VIDEO_DIP_DATA, 0);
160 mmiowb();
161
162 val |= g4x_infoframe_enable(type);
163 val &= ~VIDEO_DIP_FREQ_MASK;
164 val |= VIDEO_DIP_FREQ_VSYNC;
165
166 I915_WRITE(VIDEO_DIP_CTL, val);
167 POSTING_READ(VIDEO_DIP_CTL);
168 }
169
170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
171 {
172 struct drm_device *dev = encoder->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
175 u32 val = I915_READ(VIDEO_DIP_CTL);
176
177 if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
178 return val & VIDEO_DIP_ENABLE;
179
180 return false;
181 }
182
183 static void ibx_write_infoframe(struct drm_encoder *encoder,
184 enum hdmi_infoframe_type type,
185 const void *frame, ssize_t len)
186 {
187 const uint32_t *data = frame;
188 struct drm_device *dev = encoder->dev;
189 struct drm_i915_private *dev_priv = dev->dev_private;
190 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
191 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
192 u32 val = I915_READ(reg);
193
194 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
195
196 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
197 val |= g4x_infoframe_index(type);
198
199 val &= ~g4x_infoframe_enable(type);
200
201 I915_WRITE(reg, val);
202
203 mmiowb();
204 for (i = 0; i < len; i += 4) {
205 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
206 data++;
207 }
208 /* Write every possible data byte to force correct ECC calculation. */
209 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
211 mmiowb();
212
213 val |= g4x_infoframe_enable(type);
214 val &= ~VIDEO_DIP_FREQ_MASK;
215 val |= VIDEO_DIP_FREQ_VSYNC;
216
217 I915_WRITE(reg, val);
218 POSTING_READ(reg);
219 }
220
221 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
222 {
223 struct drm_device *dev = encoder->dev;
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
226 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
227 u32 val = I915_READ(reg);
228
229 return val & VIDEO_DIP_ENABLE;
230 }
231
232 static void cpt_write_infoframe(struct drm_encoder *encoder,
233 enum hdmi_infoframe_type type,
234 const void *frame, ssize_t len)
235 {
236 const uint32_t *data = frame;
237 struct drm_device *dev = encoder->dev;
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
240 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
241 u32 val = I915_READ(reg);
242
243 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
244
245 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
246 val |= g4x_infoframe_index(type);
247
248 /* The DIP control register spec says that we need to update the AVI
249 * infoframe without clearing its enable bit */
250 if (type != HDMI_INFOFRAME_TYPE_AVI)
251 val &= ~g4x_infoframe_enable(type);
252
253 I915_WRITE(reg, val);
254
255 mmiowb();
256 for (i = 0; i < len; i += 4) {
257 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
258 data++;
259 }
260 /* Write every possible data byte to force correct ECC calculation. */
261 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
262 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
263 mmiowb();
264
265 val |= g4x_infoframe_enable(type);
266 val &= ~VIDEO_DIP_FREQ_MASK;
267 val |= VIDEO_DIP_FREQ_VSYNC;
268
269 I915_WRITE(reg, val);
270 POSTING_READ(reg);
271 }
272
273 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
274 {
275 struct drm_device *dev = encoder->dev;
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
278 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
279 u32 val = I915_READ(reg);
280
281 return val & VIDEO_DIP_ENABLE;
282 }
283
284 static void vlv_write_infoframe(struct drm_encoder *encoder,
285 enum hdmi_infoframe_type type,
286 const void *frame, ssize_t len)
287 {
288 const uint32_t *data = frame;
289 struct drm_device *dev = encoder->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
292 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
293 u32 val = I915_READ(reg);
294
295 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
296
297 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
298 val |= g4x_infoframe_index(type);
299
300 val &= ~g4x_infoframe_enable(type);
301
302 I915_WRITE(reg, val);
303
304 mmiowb();
305 for (i = 0; i < len; i += 4) {
306 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
307 data++;
308 }
309 /* Write every possible data byte to force correct ECC calculation. */
310 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
311 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
312 mmiowb();
313
314 val |= g4x_infoframe_enable(type);
315 val &= ~VIDEO_DIP_FREQ_MASK;
316 val |= VIDEO_DIP_FREQ_VSYNC;
317
318 I915_WRITE(reg, val);
319 POSTING_READ(reg);
320 }
321
322 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
323 {
324 struct drm_device *dev = encoder->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
327 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
328 u32 val = I915_READ(reg);
329
330 return val & VIDEO_DIP_ENABLE;
331 }
332
333 static void hsw_write_infoframe(struct drm_encoder *encoder,
334 enum hdmi_infoframe_type type,
335 const void *frame, ssize_t len)
336 {
337 const uint32_t *data = frame;
338 struct drm_device *dev = encoder->dev;
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
341 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
342 u32 data_reg;
343 int i;
344 u32 val = I915_READ(ctl_reg);
345
346 data_reg = hsw_infoframe_data_reg(type,
347 intel_crtc->config->cpu_transcoder,
348 dev_priv);
349 if (data_reg == 0)
350 return;
351
352 val &= ~hsw_infoframe_enable(type);
353 I915_WRITE(ctl_reg, val);
354
355 mmiowb();
356 for (i = 0; i < len; i += 4) {
357 I915_WRITE(data_reg + i, *data);
358 data++;
359 }
360 /* Write every possible data byte to force correct ECC calculation. */
361 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
362 I915_WRITE(data_reg + i, 0);
363 mmiowb();
364
365 val |= hsw_infoframe_enable(type);
366 I915_WRITE(ctl_reg, val);
367 POSTING_READ(ctl_reg);
368 }
369
370 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
371 {
372 struct drm_device *dev = encoder->dev;
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
375 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
376 u32 val = I915_READ(ctl_reg);
377
378 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
379 VIDEO_DIP_ENABLE_VS_HSW);
380 }
381
382 /*
383 * The data we write to the DIP data buffer registers is 1 byte bigger than the
384 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
385 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
386 * used for both technologies.
387 *
388 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
389 * DW1: DB3 | DB2 | DB1 | DB0
390 * DW2: DB7 | DB6 | DB5 | DB4
391 * DW3: ...
392 *
393 * (HB is Header Byte, DB is Data Byte)
394 *
395 * The hdmi pack() functions don't know about that hardware specific hole so we
396 * trick them by giving an offset into the buffer and moving back the header
397 * bytes by one.
398 */
399 static void intel_write_infoframe(struct drm_encoder *encoder,
400 union hdmi_infoframe *frame)
401 {
402 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
403 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
404 ssize_t len;
405
406 /* see comment above for the reason for this offset */
407 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
408 if (len < 0)
409 return;
410
411 /* Insert the 'hole' (see big comment above) at position 3 */
412 buffer[0] = buffer[1];
413 buffer[1] = buffer[2];
414 buffer[2] = buffer[3];
415 buffer[3] = 0;
416 len++;
417
418 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
419 }
420
421 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
422 struct drm_display_mode *adjusted_mode)
423 {
424 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
425 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
426 union hdmi_infoframe frame;
427 int ret;
428
429 /* Set user selected PAR to incoming mode's member */
430 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
431
432 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
433 adjusted_mode);
434 if (ret < 0) {
435 DRM_ERROR("couldn't fill AVI infoframe\n");
436 return;
437 }
438
439 if (intel_hdmi->rgb_quant_range_selectable) {
440 if (intel_crtc->config->limited_color_range)
441 frame.avi.quantization_range =
442 HDMI_QUANTIZATION_RANGE_LIMITED;
443 else
444 frame.avi.quantization_range =
445 HDMI_QUANTIZATION_RANGE_FULL;
446 }
447
448 intel_write_infoframe(encoder, &frame);
449 }
450
451 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
452 {
453 union hdmi_infoframe frame;
454 int ret;
455
456 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
457 if (ret < 0) {
458 DRM_ERROR("couldn't fill SPD infoframe\n");
459 return;
460 }
461
462 frame.spd.sdi = HDMI_SPD_SDI_PC;
463
464 intel_write_infoframe(encoder, &frame);
465 }
466
467 static void
468 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
469 struct drm_display_mode *adjusted_mode)
470 {
471 union hdmi_infoframe frame;
472 int ret;
473
474 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
475 adjusted_mode);
476 if (ret < 0)
477 return;
478
479 intel_write_infoframe(encoder, &frame);
480 }
481
482 static void g4x_set_infoframes(struct drm_encoder *encoder,
483 bool enable,
484 struct drm_display_mode *adjusted_mode)
485 {
486 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
487 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
488 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
489 u32 reg = VIDEO_DIP_CTL;
490 u32 val = I915_READ(reg);
491 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
492
493 assert_hdmi_port_disabled(intel_hdmi);
494
495 /* If the registers were not initialized yet, they might be zeroes,
496 * which means we're selecting the AVI DIP and we're setting its
497 * frequency to once. This seems to really confuse the HW and make
498 * things stop working (the register spec says the AVI always needs to
499 * be sent every VSync). So here we avoid writing to the register more
500 * than we need and also explicitly select the AVI DIP and explicitly
501 * set its frequency to every VSync. Avoiding to write it twice seems to
502 * be enough to solve the problem, but being defensive shouldn't hurt us
503 * either. */
504 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
505
506 if (!enable) {
507 if (!(val & VIDEO_DIP_ENABLE))
508 return;
509 val &= ~VIDEO_DIP_ENABLE;
510 I915_WRITE(reg, val);
511 POSTING_READ(reg);
512 return;
513 }
514
515 if (port != (val & VIDEO_DIP_PORT_MASK)) {
516 if (val & VIDEO_DIP_ENABLE) {
517 val &= ~VIDEO_DIP_ENABLE;
518 I915_WRITE(reg, val);
519 POSTING_READ(reg);
520 }
521 val &= ~VIDEO_DIP_PORT_MASK;
522 val |= port;
523 }
524
525 val |= VIDEO_DIP_ENABLE;
526 val &= ~VIDEO_DIP_ENABLE_VENDOR;
527
528 I915_WRITE(reg, val);
529 POSTING_READ(reg);
530
531 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
532 intel_hdmi_set_spd_infoframe(encoder);
533 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
534 }
535
536 static void ibx_set_infoframes(struct drm_encoder *encoder,
537 bool enable,
538 struct drm_display_mode *adjusted_mode)
539 {
540 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
541 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
542 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
543 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
544 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
545 u32 val = I915_READ(reg);
546 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
547
548 assert_hdmi_port_disabled(intel_hdmi);
549
550 /* See the big comment in g4x_set_infoframes() */
551 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
552
553 if (!enable) {
554 if (!(val & VIDEO_DIP_ENABLE))
555 return;
556 val &= ~VIDEO_DIP_ENABLE;
557 I915_WRITE(reg, val);
558 POSTING_READ(reg);
559 return;
560 }
561
562 if (port != (val & VIDEO_DIP_PORT_MASK)) {
563 if (val & VIDEO_DIP_ENABLE) {
564 val &= ~VIDEO_DIP_ENABLE;
565 I915_WRITE(reg, val);
566 POSTING_READ(reg);
567 }
568 val &= ~VIDEO_DIP_PORT_MASK;
569 val |= port;
570 }
571
572 val |= VIDEO_DIP_ENABLE;
573 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
574 VIDEO_DIP_ENABLE_GCP);
575
576 I915_WRITE(reg, val);
577 POSTING_READ(reg);
578
579 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
580 intel_hdmi_set_spd_infoframe(encoder);
581 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
582 }
583
584 static void cpt_set_infoframes(struct drm_encoder *encoder,
585 bool enable,
586 struct drm_display_mode *adjusted_mode)
587 {
588 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
589 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
590 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
591 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
592 u32 val = I915_READ(reg);
593
594 assert_hdmi_port_disabled(intel_hdmi);
595
596 /* See the big comment in g4x_set_infoframes() */
597 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
598
599 if (!enable) {
600 if (!(val & VIDEO_DIP_ENABLE))
601 return;
602 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
603 I915_WRITE(reg, val);
604 POSTING_READ(reg);
605 return;
606 }
607
608 /* Set both together, unset both together: see the spec. */
609 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
610 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
611 VIDEO_DIP_ENABLE_GCP);
612
613 I915_WRITE(reg, val);
614 POSTING_READ(reg);
615
616 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
617 intel_hdmi_set_spd_infoframe(encoder);
618 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
619 }
620
621 static void vlv_set_infoframes(struct drm_encoder *encoder,
622 bool enable,
623 struct drm_display_mode *adjusted_mode)
624 {
625 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
626 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
627 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
628 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
629 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
630 u32 val = I915_READ(reg);
631 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
632
633 assert_hdmi_port_disabled(intel_hdmi);
634
635 /* See the big comment in g4x_set_infoframes() */
636 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
637
638 if (!enable) {
639 if (!(val & VIDEO_DIP_ENABLE))
640 return;
641 val &= ~VIDEO_DIP_ENABLE;
642 I915_WRITE(reg, val);
643 POSTING_READ(reg);
644 return;
645 }
646
647 if (port != (val & VIDEO_DIP_PORT_MASK)) {
648 if (val & VIDEO_DIP_ENABLE) {
649 val &= ~VIDEO_DIP_ENABLE;
650 I915_WRITE(reg, val);
651 POSTING_READ(reg);
652 }
653 val &= ~VIDEO_DIP_PORT_MASK;
654 val |= port;
655 }
656
657 val |= VIDEO_DIP_ENABLE;
658 val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
659 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
660
661 I915_WRITE(reg, val);
662 POSTING_READ(reg);
663
664 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
665 intel_hdmi_set_spd_infoframe(encoder);
666 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
667 }
668
669 static void hsw_set_infoframes(struct drm_encoder *encoder,
670 bool enable,
671 struct drm_display_mode *adjusted_mode)
672 {
673 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
674 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
675 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
676 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
677 u32 val = I915_READ(reg);
678
679 assert_hdmi_port_disabled(intel_hdmi);
680
681 if (!enable) {
682 I915_WRITE(reg, 0);
683 POSTING_READ(reg);
684 return;
685 }
686
687 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
688 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
689
690 I915_WRITE(reg, val);
691 POSTING_READ(reg);
692
693 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
694 intel_hdmi_set_spd_infoframe(encoder);
695 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
696 }
697
698 static void intel_hdmi_prepare(struct intel_encoder *encoder)
699 {
700 struct drm_device *dev = encoder->base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
703 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
704 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
705 u32 hdmi_val;
706
707 hdmi_val = SDVO_ENCODING_HDMI;
708 if (!HAS_PCH_SPLIT(dev))
709 hdmi_val |= intel_hdmi->color_range;
710 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
711 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
712 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
713 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
714
715 if (crtc->config->pipe_bpp > 24)
716 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
717 else
718 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
719
720 if (crtc->config->has_hdmi_sink)
721 hdmi_val |= HDMI_MODE_SELECT_HDMI;
722
723 if (HAS_PCH_CPT(dev))
724 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
725 else if (IS_CHERRYVIEW(dev))
726 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
727 else
728 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
729
730 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
731 POSTING_READ(intel_hdmi->hdmi_reg);
732 }
733
734 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
735 enum pipe *pipe)
736 {
737 struct drm_device *dev = encoder->base.dev;
738 struct drm_i915_private *dev_priv = dev->dev_private;
739 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
740 enum intel_display_power_domain power_domain;
741 u32 tmp;
742
743 power_domain = intel_display_port_power_domain(encoder);
744 if (!intel_display_power_is_enabled(dev_priv, power_domain))
745 return false;
746
747 tmp = I915_READ(intel_hdmi->hdmi_reg);
748
749 if (!(tmp & SDVO_ENABLE))
750 return false;
751
752 if (HAS_PCH_CPT(dev))
753 *pipe = PORT_TO_PIPE_CPT(tmp);
754 else if (IS_CHERRYVIEW(dev))
755 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
756 else
757 *pipe = PORT_TO_PIPE(tmp);
758
759 return true;
760 }
761
762 static void intel_hdmi_get_config(struct intel_encoder *encoder,
763 struct intel_crtc_state *pipe_config)
764 {
765 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
766 struct drm_device *dev = encoder->base.dev;
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 u32 tmp, flags = 0;
769 int dotclock;
770
771 tmp = I915_READ(intel_hdmi->hdmi_reg);
772
773 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
774 flags |= DRM_MODE_FLAG_PHSYNC;
775 else
776 flags |= DRM_MODE_FLAG_NHSYNC;
777
778 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
779 flags |= DRM_MODE_FLAG_PVSYNC;
780 else
781 flags |= DRM_MODE_FLAG_NVSYNC;
782
783 if (tmp & HDMI_MODE_SELECT_HDMI)
784 pipe_config->has_hdmi_sink = true;
785
786 if (intel_hdmi->infoframe_enabled(&encoder->base))
787 pipe_config->has_infoframe = true;
788
789 if (tmp & SDVO_AUDIO_ENABLE)
790 pipe_config->has_audio = true;
791
792 if (!HAS_PCH_SPLIT(dev) &&
793 tmp & HDMI_COLOR_RANGE_16_235)
794 pipe_config->limited_color_range = true;
795
796 pipe_config->base.adjusted_mode.flags |= flags;
797
798 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
799 dotclock = pipe_config->port_clock * 2 / 3;
800 else
801 dotclock = pipe_config->port_clock;
802
803 if (HAS_PCH_SPLIT(dev_priv->dev))
804 ironlake_check_encoder_dotclock(pipe_config, dotclock);
805
806 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
807 }
808
809 static void intel_enable_hdmi(struct intel_encoder *encoder)
810 {
811 struct drm_device *dev = encoder->base.dev;
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
814 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
815 u32 temp;
816 u32 enable_bits = SDVO_ENABLE;
817
818 if (intel_crtc->config->has_audio)
819 enable_bits |= SDVO_AUDIO_ENABLE;
820
821 temp = I915_READ(intel_hdmi->hdmi_reg);
822
823 /* HW workaround for IBX, we need to move the port to transcoder A
824 * before disabling it, so restore the transcoder select bit here. */
825 if (HAS_PCH_IBX(dev))
826 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
827
828 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
829 * we do this anyway which shows more stable in testing.
830 */
831 if (HAS_PCH_SPLIT(dev)) {
832 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
833 POSTING_READ(intel_hdmi->hdmi_reg);
834 }
835
836 temp |= enable_bits;
837
838 I915_WRITE(intel_hdmi->hdmi_reg, temp);
839 POSTING_READ(intel_hdmi->hdmi_reg);
840
841 /* HW workaround, need to write this twice for issue that may result
842 * in first write getting masked.
843 */
844 if (HAS_PCH_SPLIT(dev)) {
845 I915_WRITE(intel_hdmi->hdmi_reg, temp);
846 POSTING_READ(intel_hdmi->hdmi_reg);
847 }
848
849 if (intel_crtc->config->has_audio) {
850 WARN_ON(!intel_crtc->config->has_hdmi_sink);
851 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
852 pipe_name(intel_crtc->pipe));
853 intel_audio_codec_enable(encoder);
854 }
855 }
856
857 static void vlv_enable_hdmi(struct intel_encoder *encoder)
858 {
859 }
860
861 static void intel_disable_hdmi(struct intel_encoder *encoder)
862 {
863 struct drm_device *dev = encoder->base.dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
866 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
867 u32 temp;
868 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
869
870 if (crtc->config->has_audio)
871 intel_audio_codec_disable(encoder);
872
873 temp = I915_READ(intel_hdmi->hdmi_reg);
874
875 /* HW workaround for IBX, we need to move the port to transcoder A
876 * before disabling it. */
877 if (HAS_PCH_IBX(dev)) {
878 struct drm_crtc *crtc = encoder->base.crtc;
879 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
880
881 if (temp & SDVO_PIPE_B_SELECT) {
882 temp &= ~SDVO_PIPE_B_SELECT;
883 I915_WRITE(intel_hdmi->hdmi_reg, temp);
884 POSTING_READ(intel_hdmi->hdmi_reg);
885
886 /* Again we need to write this twice. */
887 I915_WRITE(intel_hdmi->hdmi_reg, temp);
888 POSTING_READ(intel_hdmi->hdmi_reg);
889
890 /* Transcoder selection bits only update
891 * effectively on vblank. */
892 if (crtc)
893 intel_wait_for_vblank(dev, pipe);
894 else
895 msleep(50);
896 }
897 }
898
899 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
900 * we do this anyway which shows more stable in testing.
901 */
902 if (HAS_PCH_SPLIT(dev)) {
903 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
904 POSTING_READ(intel_hdmi->hdmi_reg);
905 }
906
907 temp &= ~enable_bits;
908
909 I915_WRITE(intel_hdmi->hdmi_reg, temp);
910 POSTING_READ(intel_hdmi->hdmi_reg);
911
912 /* HW workaround, need to write this twice for issue that may result
913 * in first write getting masked.
914 */
915 if (HAS_PCH_SPLIT(dev)) {
916 I915_WRITE(intel_hdmi->hdmi_reg, temp);
917 POSTING_READ(intel_hdmi->hdmi_reg);
918 }
919 }
920
921 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
922 {
923 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
924
925 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
926 return 165000;
927 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
928 return 300000;
929 else
930 return 225000;
931 }
932
933 static enum drm_mode_status
934 intel_hdmi_mode_valid(struct drm_connector *connector,
935 struct drm_display_mode *mode)
936 {
937 int clock = mode->clock;
938
939 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
940 clock *= 2;
941
942 if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
943 true))
944 return MODE_CLOCK_HIGH;
945 if (clock < 20000)
946 return MODE_CLOCK_LOW;
947
948 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
949 return MODE_NO_DBLESCAN;
950
951 return MODE_OK;
952 }
953
954 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
955 {
956 struct drm_device *dev = crtc_state->base.crtc->dev;
957 struct drm_atomic_state *state;
958 struct intel_encoder *encoder;
959 struct drm_connector_state *connector_state;
960 int count = 0, count_hdmi = 0;
961 int i;
962
963 if (HAS_GMCH_DISPLAY(dev))
964 return false;
965
966 state = crtc_state->base.state;
967
968 for (i = 0; i < state->num_connector; i++) {
969 if (!state->connectors[i])
970 continue;
971
972 connector_state = state->connector_states[i];
973 if (connector_state->crtc != crtc_state->base.crtc)
974 continue;
975
976 encoder = to_intel_encoder(connector_state->best_encoder);
977
978 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
979 count++;
980 }
981
982 /*
983 * HDMI 12bpc affects the clocks, so it's only possible
984 * when not cloning with other encoder types.
985 */
986 return count_hdmi > 0 && count_hdmi == count;
987 }
988
989 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
990 struct intel_crtc_state *pipe_config)
991 {
992 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
993 struct drm_device *dev = encoder->base.dev;
994 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
995 int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
996 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
997 int desired_bpp;
998
999 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1000
1001 if (pipe_config->has_hdmi_sink)
1002 pipe_config->has_infoframe = true;
1003
1004 if (intel_hdmi->color_range_auto) {
1005 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1006 if (pipe_config->has_hdmi_sink &&
1007 drm_match_cea_mode(adjusted_mode) > 1)
1008 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1009 else
1010 intel_hdmi->color_range = 0;
1011 }
1012
1013 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1014 pipe_config->pixel_multiplier = 2;
1015 }
1016
1017 if (intel_hdmi->color_range)
1018 pipe_config->limited_color_range = true;
1019
1020 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1021 pipe_config->has_pch_encoder = true;
1022
1023 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1024 pipe_config->has_audio = true;
1025
1026 /*
1027 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1028 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1029 * outputs. We also need to check that the higher clock still fits
1030 * within limits.
1031 */
1032 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1033 clock_12bpc <= portclock_limit &&
1034 hdmi_12bpc_possible(pipe_config)) {
1035 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1036 desired_bpp = 12*3;
1037
1038 /* Need to adjust the port link by 1.5x for 12bpc. */
1039 pipe_config->port_clock = clock_12bpc;
1040 } else {
1041 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1042 desired_bpp = 8*3;
1043 }
1044
1045 if (!pipe_config->bw_constrained) {
1046 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1047 pipe_config->pipe_bpp = desired_bpp;
1048 }
1049
1050 if (adjusted_mode->crtc_clock > portclock_limit) {
1051 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1052 return false;
1053 }
1054
1055 return true;
1056 }
1057
1058 static void
1059 intel_hdmi_unset_edid(struct drm_connector *connector)
1060 {
1061 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1062
1063 intel_hdmi->has_hdmi_sink = false;
1064 intel_hdmi->has_audio = false;
1065 intel_hdmi->rgb_quant_range_selectable = false;
1066
1067 kfree(to_intel_connector(connector)->detect_edid);
1068 to_intel_connector(connector)->detect_edid = NULL;
1069 }
1070
1071 static bool
1072 intel_hdmi_set_edid(struct drm_connector *connector)
1073 {
1074 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1075 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1076 struct intel_encoder *intel_encoder =
1077 &hdmi_to_dig_port(intel_hdmi)->base;
1078 enum intel_display_power_domain power_domain;
1079 struct edid *edid;
1080 bool connected = false;
1081
1082 power_domain = intel_display_port_power_domain(intel_encoder);
1083 intel_display_power_get(dev_priv, power_domain);
1084
1085 edid = drm_get_edid(connector,
1086 intel_gmbus_get_adapter(dev_priv,
1087 intel_hdmi->ddc_bus));
1088
1089 intel_display_power_put(dev_priv, power_domain);
1090
1091 to_intel_connector(connector)->detect_edid = edid;
1092 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1093 intel_hdmi->rgb_quant_range_selectable =
1094 drm_rgb_quant_range_selectable(edid);
1095
1096 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1097 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1098 intel_hdmi->has_audio =
1099 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1100
1101 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1102 intel_hdmi->has_hdmi_sink =
1103 drm_detect_hdmi_monitor(edid);
1104
1105 connected = true;
1106 }
1107
1108 return connected;
1109 }
1110
1111 static enum drm_connector_status
1112 intel_hdmi_detect(struct drm_connector *connector, bool force)
1113 {
1114 enum drm_connector_status status;
1115
1116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1117 connector->base.id, connector->name);
1118
1119 intel_hdmi_unset_edid(connector);
1120
1121 if (intel_hdmi_set_edid(connector)) {
1122 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1123
1124 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1125 status = connector_status_connected;
1126 } else
1127 status = connector_status_disconnected;
1128
1129 return status;
1130 }
1131
1132 static void
1133 intel_hdmi_force(struct drm_connector *connector)
1134 {
1135 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1136
1137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1138 connector->base.id, connector->name);
1139
1140 intel_hdmi_unset_edid(connector);
1141
1142 if (connector->status != connector_status_connected)
1143 return;
1144
1145 intel_hdmi_set_edid(connector);
1146 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1147 }
1148
1149 static int intel_hdmi_get_modes(struct drm_connector *connector)
1150 {
1151 struct edid *edid;
1152
1153 edid = to_intel_connector(connector)->detect_edid;
1154 if (edid == NULL)
1155 return 0;
1156
1157 return intel_connector_update_modes(connector, edid);
1158 }
1159
1160 static bool
1161 intel_hdmi_detect_audio(struct drm_connector *connector)
1162 {
1163 bool has_audio = false;
1164 struct edid *edid;
1165
1166 edid = to_intel_connector(connector)->detect_edid;
1167 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1168 has_audio = drm_detect_monitor_audio(edid);
1169
1170 return has_audio;
1171 }
1172
1173 static int
1174 intel_hdmi_set_property(struct drm_connector *connector,
1175 struct drm_property *property,
1176 uint64_t val)
1177 {
1178 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1179 struct intel_digital_port *intel_dig_port =
1180 hdmi_to_dig_port(intel_hdmi);
1181 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1182 int ret;
1183
1184 ret = drm_object_property_set_value(&connector->base, property, val);
1185 if (ret)
1186 return ret;
1187
1188 if (property == dev_priv->force_audio_property) {
1189 enum hdmi_force_audio i = val;
1190 bool has_audio;
1191
1192 if (i == intel_hdmi->force_audio)
1193 return 0;
1194
1195 intel_hdmi->force_audio = i;
1196
1197 if (i == HDMI_AUDIO_AUTO)
1198 has_audio = intel_hdmi_detect_audio(connector);
1199 else
1200 has_audio = (i == HDMI_AUDIO_ON);
1201
1202 if (i == HDMI_AUDIO_OFF_DVI)
1203 intel_hdmi->has_hdmi_sink = 0;
1204
1205 intel_hdmi->has_audio = has_audio;
1206 goto done;
1207 }
1208
1209 if (property == dev_priv->broadcast_rgb_property) {
1210 bool old_auto = intel_hdmi->color_range_auto;
1211 uint32_t old_range = intel_hdmi->color_range;
1212
1213 switch (val) {
1214 case INTEL_BROADCAST_RGB_AUTO:
1215 intel_hdmi->color_range_auto = true;
1216 break;
1217 case INTEL_BROADCAST_RGB_FULL:
1218 intel_hdmi->color_range_auto = false;
1219 intel_hdmi->color_range = 0;
1220 break;
1221 case INTEL_BROADCAST_RGB_LIMITED:
1222 intel_hdmi->color_range_auto = false;
1223 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 if (old_auto == intel_hdmi->color_range_auto &&
1230 old_range == intel_hdmi->color_range)
1231 return 0;
1232
1233 goto done;
1234 }
1235
1236 if (property == connector->dev->mode_config.aspect_ratio_property) {
1237 switch (val) {
1238 case DRM_MODE_PICTURE_ASPECT_NONE:
1239 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1240 break;
1241 case DRM_MODE_PICTURE_ASPECT_4_3:
1242 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1243 break;
1244 case DRM_MODE_PICTURE_ASPECT_16_9:
1245 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1246 break;
1247 default:
1248 return -EINVAL;
1249 }
1250 goto done;
1251 }
1252
1253 return -EINVAL;
1254
1255 done:
1256 if (intel_dig_port->base.base.crtc)
1257 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1258
1259 return 0;
1260 }
1261
1262 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1263 {
1264 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1265 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1266 struct drm_display_mode *adjusted_mode =
1267 &intel_crtc->config->base.adjusted_mode;
1268
1269 intel_hdmi_prepare(encoder);
1270
1271 intel_hdmi->set_infoframes(&encoder->base,
1272 intel_crtc->config->has_hdmi_sink,
1273 adjusted_mode);
1274 }
1275
1276 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1277 {
1278 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1279 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1280 struct drm_device *dev = encoder->base.dev;
1281 struct drm_i915_private *dev_priv = dev->dev_private;
1282 struct intel_crtc *intel_crtc =
1283 to_intel_crtc(encoder->base.crtc);
1284 struct drm_display_mode *adjusted_mode =
1285 &intel_crtc->config->base.adjusted_mode;
1286 enum dpio_channel port = vlv_dport_to_channel(dport);
1287 int pipe = intel_crtc->pipe;
1288 u32 val;
1289
1290 /* Enable clock channels for this port */
1291 mutex_lock(&dev_priv->dpio_lock);
1292 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1293 val = 0;
1294 if (pipe)
1295 val |= (1<<21);
1296 else
1297 val &= ~(1<<21);
1298 val |= 0x001000c4;
1299 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1300
1301 /* HDMI 1.0V-2dB */
1302 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1303 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1304 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1305 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1306 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1307 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1308 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1309 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1310
1311 /* Program lane clock */
1312 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1313 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1314 mutex_unlock(&dev_priv->dpio_lock);
1315
1316 intel_hdmi->set_infoframes(&encoder->base,
1317 intel_crtc->config->has_hdmi_sink,
1318 adjusted_mode);
1319
1320 intel_enable_hdmi(encoder);
1321
1322 vlv_wait_port_ready(dev_priv, dport);
1323 }
1324
1325 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1326 {
1327 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1328 struct drm_device *dev = encoder->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 struct intel_crtc *intel_crtc =
1331 to_intel_crtc(encoder->base.crtc);
1332 enum dpio_channel port = vlv_dport_to_channel(dport);
1333 int pipe = intel_crtc->pipe;
1334
1335 intel_hdmi_prepare(encoder);
1336
1337 /* Program Tx lane resets to default */
1338 mutex_lock(&dev_priv->dpio_lock);
1339 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1340 DPIO_PCS_TX_LANE2_RESET |
1341 DPIO_PCS_TX_LANE1_RESET);
1342 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1343 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1344 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1345 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1346 DPIO_PCS_CLK_SOFT_RESET);
1347
1348 /* Fix up inter-pair skew failure */
1349 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1350 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1351 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1352
1353 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1354 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1355 mutex_unlock(&dev_priv->dpio_lock);
1356 }
1357
1358 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1359 {
1360 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1361 struct drm_device *dev = encoder->base.dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 struct intel_crtc *intel_crtc =
1364 to_intel_crtc(encoder->base.crtc);
1365 enum dpio_channel ch = vlv_dport_to_channel(dport);
1366 enum pipe pipe = intel_crtc->pipe;
1367 u32 val;
1368
1369 intel_hdmi_prepare(encoder);
1370
1371 mutex_lock(&dev_priv->dpio_lock);
1372
1373 /* program left/right clock distribution */
1374 if (pipe != PIPE_B) {
1375 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1376 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1377 if (ch == DPIO_CH0)
1378 val |= CHV_BUFLEFTENA1_FORCE;
1379 if (ch == DPIO_CH1)
1380 val |= CHV_BUFRIGHTENA1_FORCE;
1381 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1382 } else {
1383 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1384 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1385 if (ch == DPIO_CH0)
1386 val |= CHV_BUFLEFTENA2_FORCE;
1387 if (ch == DPIO_CH1)
1388 val |= CHV_BUFRIGHTENA2_FORCE;
1389 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1390 }
1391
1392 /* program clock channel usage */
1393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1394 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1395 if (pipe != PIPE_B)
1396 val &= ~CHV_PCS_USEDCLKCHANNEL;
1397 else
1398 val |= CHV_PCS_USEDCLKCHANNEL;
1399 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1400
1401 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1402 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1403 if (pipe != PIPE_B)
1404 val &= ~CHV_PCS_USEDCLKCHANNEL;
1405 else
1406 val |= CHV_PCS_USEDCLKCHANNEL;
1407 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1408
1409 /*
1410 * This a a bit weird since generally CL
1411 * matches the pipe, but here we need to
1412 * pick the CL based on the port.
1413 */
1414 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1415 if (pipe != PIPE_B)
1416 val &= ~CHV_CMN_USEDCLKCHANNEL;
1417 else
1418 val |= CHV_CMN_USEDCLKCHANNEL;
1419 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1420
1421 mutex_unlock(&dev_priv->dpio_lock);
1422 }
1423
1424 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1425 {
1426 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1427 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1428 struct intel_crtc *intel_crtc =
1429 to_intel_crtc(encoder->base.crtc);
1430 enum dpio_channel port = vlv_dport_to_channel(dport);
1431 int pipe = intel_crtc->pipe;
1432
1433 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1434 mutex_lock(&dev_priv->dpio_lock);
1435 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1436 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1437 mutex_unlock(&dev_priv->dpio_lock);
1438 }
1439
1440 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1441 {
1442 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1443 struct drm_device *dev = encoder->base.dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 struct intel_crtc *intel_crtc =
1446 to_intel_crtc(encoder->base.crtc);
1447 enum dpio_channel ch = vlv_dport_to_channel(dport);
1448 enum pipe pipe = intel_crtc->pipe;
1449 u32 val;
1450
1451 mutex_lock(&dev_priv->dpio_lock);
1452
1453 /* Propagate soft reset to data lane reset */
1454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1455 val |= CHV_PCS_REQ_SOFTRESET_EN;
1456 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1457
1458 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1459 val |= CHV_PCS_REQ_SOFTRESET_EN;
1460 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1461
1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1463 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1465
1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1467 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1468 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1469
1470 mutex_unlock(&dev_priv->dpio_lock);
1471 }
1472
1473 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1474 {
1475 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1476 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1477 struct drm_device *dev = encoder->base.dev;
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 struct intel_crtc *intel_crtc =
1480 to_intel_crtc(encoder->base.crtc);
1481 struct drm_display_mode *adjusted_mode =
1482 &intel_crtc->config->base.adjusted_mode;
1483 enum dpio_channel ch = vlv_dport_to_channel(dport);
1484 int pipe = intel_crtc->pipe;
1485 int data, i;
1486 u32 val;
1487
1488 mutex_lock(&dev_priv->dpio_lock);
1489
1490 /* allow hardware to manage TX FIFO reset source */
1491 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1492 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1493 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1494
1495 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1496 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1497 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1498
1499 /* Deassert soft data lane reset*/
1500 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1501 val |= CHV_PCS_REQ_SOFTRESET_EN;
1502 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1503
1504 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1505 val |= CHV_PCS_REQ_SOFTRESET_EN;
1506 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1507
1508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1509 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1510 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1511
1512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1513 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1514 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1515
1516 /* Program Tx latency optimal setting */
1517 for (i = 0; i < 4; i++) {
1518 /* Set the upar bit */
1519 data = (i == 1) ? 0x0 : 0x1;
1520 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1521 data << DPIO_UPAR_SHIFT);
1522 }
1523
1524 /* Data lane stagger programming */
1525 /* FIXME: Fix up value only after power analysis */
1526
1527 /* Clear calc init */
1528 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1529 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1530 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1531 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1532 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1533
1534 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1535 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1536 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1537 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1538 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1539
1540 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1541 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1542 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1543 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1544
1545 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1546 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1547 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1548 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1549
1550 /* FIXME: Program the support xxx V-dB */
1551 /* Use 800mV-0dB */
1552 for (i = 0; i < 4; i++) {
1553 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1554 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1555 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1556 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1557 }
1558
1559 for (i = 0; i < 4; i++) {
1560 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1561 val &= ~DPIO_SWING_MARGIN000_MASK;
1562 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1563 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1564 }
1565
1566 /* Disable unique transition scale */
1567 for (i = 0; i < 4; i++) {
1568 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1569 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1570 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1571 }
1572
1573 /* Additional steps for 1200mV-0dB */
1574 #if 0
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1576 if (ch)
1577 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1578 else
1579 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1580 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1581
1582 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1583 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1584 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1585 #endif
1586 /* Start swing calculation */
1587 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1588 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1589 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1590
1591 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1592 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1593 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1594
1595 /* LRC Bypass */
1596 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1597 val |= DPIO_LRC_BYPASS;
1598 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1599
1600 mutex_unlock(&dev_priv->dpio_lock);
1601
1602 intel_hdmi->set_infoframes(&encoder->base,
1603 intel_crtc->config->has_hdmi_sink,
1604 adjusted_mode);
1605
1606 intel_enable_hdmi(encoder);
1607
1608 vlv_wait_port_ready(dev_priv, dport);
1609 }
1610
1611 static void intel_hdmi_destroy(struct drm_connector *connector)
1612 {
1613 kfree(to_intel_connector(connector)->detect_edid);
1614 drm_connector_cleanup(connector);
1615 kfree(connector);
1616 }
1617
1618 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1619 .dpms = intel_connector_dpms,
1620 .detect = intel_hdmi_detect,
1621 .force = intel_hdmi_force,
1622 .fill_modes = drm_helper_probe_single_connector_modes,
1623 .set_property = intel_hdmi_set_property,
1624 .atomic_get_property = intel_connector_atomic_get_property,
1625 .destroy = intel_hdmi_destroy,
1626 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1627 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1628 };
1629
1630 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1631 .get_modes = intel_hdmi_get_modes,
1632 .mode_valid = intel_hdmi_mode_valid,
1633 .best_encoder = intel_best_encoder,
1634 };
1635
1636 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1637 .destroy = intel_encoder_destroy,
1638 };
1639
1640 static void
1641 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1642 {
1643 if (!drm_mode_create_aspect_ratio_property(connector->dev))
1644 drm_object_attach_property(&connector->base,
1645 connector->dev->mode_config.aspect_ratio_property,
1646 DRM_MODE_PICTURE_ASPECT_NONE);
1647 }
1648
1649 static void
1650 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1651 {
1652 intel_attach_force_audio_property(connector);
1653 intel_attach_broadcast_rgb_property(connector);
1654 intel_hdmi->color_range_auto = true;
1655 intel_attach_aspect_ratio_property(connector);
1656 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1657 }
1658
1659 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1660 struct intel_connector *intel_connector)
1661 {
1662 struct drm_connector *connector = &intel_connector->base;
1663 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1664 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1665 struct drm_device *dev = intel_encoder->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum port port = intel_dig_port->port;
1668
1669 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1670 DRM_MODE_CONNECTOR_HDMIA);
1671 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1672
1673 connector->interlace_allowed = 1;
1674 connector->doublescan_allowed = 0;
1675 connector->stereo_allowed = 1;
1676
1677 switch (port) {
1678 case PORT_B:
1679 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1680 intel_encoder->hpd_pin = HPD_PORT_B;
1681 break;
1682 case PORT_C:
1683 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1684 intel_encoder->hpd_pin = HPD_PORT_C;
1685 break;
1686 case PORT_D:
1687 if (IS_CHERRYVIEW(dev))
1688 intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1689 else
1690 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1691 intel_encoder->hpd_pin = HPD_PORT_D;
1692 break;
1693 case PORT_A:
1694 intel_encoder->hpd_pin = HPD_PORT_A;
1695 /* Internal port only for eDP. */
1696 default:
1697 BUG();
1698 }
1699
1700 if (IS_VALLEYVIEW(dev)) {
1701 intel_hdmi->write_infoframe = vlv_write_infoframe;
1702 intel_hdmi->set_infoframes = vlv_set_infoframes;
1703 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1704 } else if (IS_G4X(dev)) {
1705 intel_hdmi->write_infoframe = g4x_write_infoframe;
1706 intel_hdmi->set_infoframes = g4x_set_infoframes;
1707 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1708 } else if (HAS_DDI(dev)) {
1709 intel_hdmi->write_infoframe = hsw_write_infoframe;
1710 intel_hdmi->set_infoframes = hsw_set_infoframes;
1711 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1712 } else if (HAS_PCH_IBX(dev)) {
1713 intel_hdmi->write_infoframe = ibx_write_infoframe;
1714 intel_hdmi->set_infoframes = ibx_set_infoframes;
1715 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1716 } else {
1717 intel_hdmi->write_infoframe = cpt_write_infoframe;
1718 intel_hdmi->set_infoframes = cpt_set_infoframes;
1719 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1720 }
1721
1722 if (HAS_DDI(dev))
1723 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1724 else
1725 intel_connector->get_hw_state = intel_connector_get_hw_state;
1726 intel_connector->unregister = intel_connector_unregister;
1727
1728 intel_hdmi_add_properties(intel_hdmi, connector);
1729
1730 intel_connector_attach_encoder(intel_connector, intel_encoder);
1731 drm_connector_register(connector);
1732
1733 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1734 * 0xd. Failure to do so will result in spurious interrupts being
1735 * generated on the port when a cable is not attached.
1736 */
1737 if (IS_G4X(dev) && !IS_GM45(dev)) {
1738 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1739 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1740 }
1741 }
1742
1743 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1744 {
1745 struct intel_digital_port *intel_dig_port;
1746 struct intel_encoder *intel_encoder;
1747 struct intel_connector *intel_connector;
1748
1749 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1750 if (!intel_dig_port)
1751 return;
1752
1753 intel_connector = intel_connector_alloc();
1754 if (!intel_connector) {
1755 kfree(intel_dig_port);
1756 return;
1757 }
1758
1759 intel_encoder = &intel_dig_port->base;
1760
1761 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1762 DRM_MODE_ENCODER_TMDS);
1763
1764 intel_encoder->compute_config = intel_hdmi_compute_config;
1765 intel_encoder->disable = intel_disable_hdmi;
1766 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1767 intel_encoder->get_config = intel_hdmi_get_config;
1768 if (IS_CHERRYVIEW(dev)) {
1769 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1770 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1771 intel_encoder->enable = vlv_enable_hdmi;
1772 intel_encoder->post_disable = chv_hdmi_post_disable;
1773 } else if (IS_VALLEYVIEW(dev)) {
1774 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1775 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1776 intel_encoder->enable = vlv_enable_hdmi;
1777 intel_encoder->post_disable = vlv_hdmi_post_disable;
1778 } else {
1779 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1780 intel_encoder->enable = intel_enable_hdmi;
1781 }
1782
1783 intel_encoder->type = INTEL_OUTPUT_HDMI;
1784 if (IS_CHERRYVIEW(dev)) {
1785 if (port == PORT_D)
1786 intel_encoder->crtc_mask = 1 << 2;
1787 else
1788 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1789 } else {
1790 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1791 }
1792 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1793 /*
1794 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1795 * to work on real hardware. And since g4x can send infoframes to
1796 * only one port anyway, nothing is lost by allowing it.
1797 */
1798 if (IS_G4X(dev))
1799 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1800
1801 intel_dig_port->port = port;
1802 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1803 intel_dig_port->dp.output_reg = 0;
1804
1805 intel_hdmi_init_connector(intel_dig_port, intel_connector);
1806 }
Linux with added FPC-III support