drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67 #include <linux/interval_tree.h>
  68 #include <linux/hashtable.h>
  69 #include <linux/fence.h>
  70
  71 #include <ttm/ttm_bo_api.h>
  72 #include <ttm/ttm_bo_driver.h>
  73 #include <ttm/ttm_placement.h>
  74 #include <ttm/ttm_module.h>
  75 #include <ttm/ttm_execbuf_util.h>
  76
  77 #include <drm/drm_gem.h>
  78
  79 #include "radeon_family.h"
  80 #include "radeon_mode.h"
  81 #include "radeon_reg.h"
  82
  83 /*
  84  * Modules parameters.
  85  */
  86 extern int radeon_no_wb;
  87 extern int radeon_modeset;
  88 extern int radeon_dynclks;
  89 extern int radeon_r4xx_atom;
  90 extern int radeon_agpmode;
  91 extern int radeon_vram_limit;
  92 extern int radeon_gart_size;
  93 extern int radeon_benchmarking;
  94 extern int radeon_testing;
  95 extern int radeon_connector_table;
  96 extern int radeon_tv;
  97 extern int radeon_audio;
  98 extern int radeon_disp_priority;
  99 extern int radeon_hw_i2c;
 100 extern int radeon_pcie_gen2;
 101 extern int radeon_msi;
 102 extern int radeon_lockup_timeout;
 103 extern int radeon_fastfb;
 104 extern int radeon_dpm;
 105 extern int radeon_aspm;
 106 extern int radeon_runtime_pm;
 107 extern int radeon_hard_reset;
 108 extern int radeon_vm_size;
 109 extern int radeon_vm_block_size;
 110 extern int radeon_deep_color;
 111 extern int radeon_use_pflipirq;
 112 extern int radeon_bapm;
 113 extern int radeon_backlight;
 114 extern int radeon_auxch;
 115 extern int radeon_mst;
 116
 117 /*
 118  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 119  * symbol;
 120  */
 121 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 122 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 123 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 124 #define RADEON_IB_POOL_SIZE                     16
 125 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 126 #define RADEONFB_CONN_LIMIT                     4
 127 #define RADEON_BIOS_NUM_SCRATCH                 8
 128
 129 /* internal ring indices */
 130 /* r1xx+ has gfx CP ring */
 131 #define RADEON_RING_TYPE_GFX_INDEX              0
 132
 133 /* cayman has 2 compute CP rings */
 134 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 135 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 136
 137 /* R600+ has an async dma ring */
 138 #define R600_RING_TYPE_DMA_INDEX                3
 139 /* cayman add a second async dma ring */
 140 #define CAYMAN_RING_TYPE_DMA1_INDEX             4
 141
 142 /* R600+ */
 143 #define R600_RING_TYPE_UVD_INDEX                5
 144
 145 /* TN+ */
 146 #define TN_RING_TYPE_VCE1_INDEX                 6
 147 #define TN_RING_TYPE_VCE2_INDEX                 7
 148
 149 /* max number of rings */
 150 #define RADEON_NUM_RINGS                        8
 151
 152 /* number of hw syncs before falling back on blocking */
 153 #define RADEON_NUM_SYNCS                        4
 154
 155 /* hardcode those limit for now */
 156 #define RADEON_VA_IB_OFFSET                     (1 << 20)
 157 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 158 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 159
 160 /* hard reset data */
 161 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
 162
 163 /* reset flags */
 164 #define RADEON_RESET_GFX                        (1 << 0)
 165 #define RADEON_RESET_COMPUTE                    (1 << 1)
 166 #define RADEON_RESET_DMA                        (1 << 2)
 167 #define RADEON_RESET_CP                         (1 << 3)
 168 #define RADEON_RESET_GRBM                       (1 << 4)
 169 #define RADEON_RESET_DMA1                       (1 << 5)
 170 #define RADEON_RESET_RLC                        (1 << 6)
 171 #define RADEON_RESET_SEM                        (1 << 7)
 172 #define RADEON_RESET_IH                         (1 << 8)
 173 #define RADEON_RESET_VMC                        (1 << 9)
 174 #define RADEON_RESET_MC                         (1 << 10)
 175 #define RADEON_RESET_DISPLAY                    (1 << 11)
 176
 177 /* CG block flags */
 178 #define RADEON_CG_BLOCK_GFX                     (1 << 0)
 179 #define RADEON_CG_BLOCK_MC                      (1 << 1)
 180 #define RADEON_CG_BLOCK_SDMA                    (1 << 2)
 181 #define RADEON_CG_BLOCK_UVD                     (1 << 3)
 182 #define RADEON_CG_BLOCK_VCE                     (1 << 4)
 183 #define RADEON_CG_BLOCK_HDP                     (1 << 5)
 184 #define RADEON_CG_BLOCK_BIF                     (1 << 6)
 185
 186 /* CG flags */
 187 #define RADEON_CG_SUPPORT_GFX_MGCG              (1 << 0)
 188 #define RADEON_CG_SUPPORT_GFX_MGLS              (1 << 1)
 189 #define RADEON_CG_SUPPORT_GFX_CGCG              (1 << 2)
 190 #define RADEON_CG_SUPPORT_GFX_CGLS              (1 << 3)
 191 #define RADEON_CG_SUPPORT_GFX_CGTS              (1 << 4)
 192 #define RADEON_CG_SUPPORT_GFX_CGTS_LS           (1 << 5)
 193 #define RADEON_CG_SUPPORT_GFX_CP_LS             (1 << 6)
 194 #define RADEON_CG_SUPPORT_GFX_RLC_LS            (1 << 7)
 195 #define RADEON_CG_SUPPORT_MC_LS                 (1 << 8)
 196 #define RADEON_CG_SUPPORT_MC_MGCG               (1 << 9)
 197 #define RADEON_CG_SUPPORT_SDMA_LS               (1 << 10)
 198 #define RADEON_CG_SUPPORT_SDMA_MGCG             (1 << 11)
 199 #define RADEON_CG_SUPPORT_BIF_LS                (1 << 12)
 200 #define RADEON_CG_SUPPORT_UVD_MGCG              (1 << 13)
 201 #define RADEON_CG_SUPPORT_VCE_MGCG              (1 << 14)
 202 #define RADEON_CG_SUPPORT_HDP_LS                (1 << 15)
 203 #define RADEON_CG_SUPPORT_HDP_MGCG              (1 << 16)
 204
 205 /* PG flags */
 206 #define RADEON_PG_SUPPORT_GFX_PG                (1 << 0)
 207 #define RADEON_PG_SUPPORT_GFX_SMG               (1 << 1)
 208 #define RADEON_PG_SUPPORT_GFX_DMG               (1 << 2)
 209 #define RADEON_PG_SUPPORT_UVD                   (1 << 3)
 210 #define RADEON_PG_SUPPORT_VCE                   (1 << 4)
 211 #define RADEON_PG_SUPPORT_CP                    (1 << 5)
 212 #define RADEON_PG_SUPPORT_GDS                   (1 << 6)
 213 #define RADEON_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
 214 #define RADEON_PG_SUPPORT_SDMA                  (1 << 8)
 215 #define RADEON_PG_SUPPORT_ACP                   (1 << 9)
 216 #define RADEON_PG_SUPPORT_SAMU                  (1 << 10)
 217
 218 /* max cursor sizes (in pixels) */
 219 #define CURSOR_WIDTH 64
 220 #define CURSOR_HEIGHT 64
 221
 222 #define CIK_CURSOR_WIDTH 128
 223 #define CIK_CURSOR_HEIGHT 128
 224
 225 /*
 226  * Errata workarounds.
 227  */
 228 enum radeon_pll_errata {
 229         CHIP_ERRATA_R300_CG             = 0x00000001,
 230         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 231         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 232 };
 233
 234
 235 struct radeon_device;
 236
 237
 238 /*
 239  * BIOS.
 240  */
 241 bool radeon_get_bios(struct radeon_device *rdev);
 242
 243 /*
 244  * Dummy page
 245  */
 246 struct radeon_dummy_page {
 247         uint64_t        entry;
 248         struct page     *page;
 249         dma_addr_t      addr;
 250 };
 251 int radeon_dummy_page_init(struct radeon_device *rdev);
 252 void radeon_dummy_page_fini(struct radeon_device *rdev);
 253
 254
 255 /*
 256  * Clocks
 257  */
 258 struct radeon_clock {
 259         struct radeon_pll p1pll;
 260         struct radeon_pll p2pll;
 261         struct radeon_pll dcpll;
 262         struct radeon_pll spll;
 263         struct radeon_pll mpll;
 264         /* 10 Khz units */
 265         uint32_t default_mclk;
 266         uint32_t default_sclk;
 267         uint32_t default_dispclk;
 268         uint32_t current_dispclk;
 269         uint32_t dp_extclk;
 270         uint32_t max_pixel_clock;
 271 };
 272
 273 /*
 274  * Power management
 275  */
 276 int radeon_pm_init(struct radeon_device *rdev);
 277 int radeon_pm_late_init(struct radeon_device *rdev);
 278 void radeon_pm_fini(struct radeon_device *rdev);
 279 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 280 void radeon_pm_suspend(struct radeon_device *rdev);
 281 void radeon_pm_resume(struct radeon_device *rdev);
 282 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 283 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 284 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
 285                                    u8 clock_type,
 286                                    u32 clock,
 287                                    bool strobe_mode,
 288                                    struct atom_clock_dividers *dividers);
 289 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
 290                                         u32 clock,
 291                                         bool strobe_mode,
 292                                         struct atom_mpll_param *mpll_param);
 293 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 294 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
 295                                           u16 voltage_level, u8 voltage_type,
 296                                           u32 *gpio_value, u32 *gpio_mask);
 297 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
 298                                          u32 eng_clock, u32 mem_clock);
 299 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
 300                                  u8 voltage_type, u16 *voltage_step);
 301 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 302                              u16 voltage_id, u16 *voltage);
 303 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
 304                                                       u16 *voltage,
 305                                                       u16 leakage_idx);
 306 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
 307                                           u16 *leakage_id);
 308 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
 309                                                          u16 *vddc, u16 *vddci,
 310                                                          u16 virtual_voltage_id,
 311                                                          u16 vbios_voltage_id);
 312 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
 313                                 u16 virtual_voltage_id,
 314                                 u16 *voltage);
 315 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
 316                                       u8 voltage_type,
 317                                       u16 nominal_voltage,
 318                                       u16 *true_voltage);
 319 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
 320                                 u8 voltage_type, u16 *min_voltage);
 321 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
 322                                 u8 voltage_type, u16 *max_voltage);
 323 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
 324                                   u8 voltage_type, u8 voltage_mode,
 325                                   struct atom_voltage_table *voltage_table);
 326 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
 327                                  u8 voltage_type, u8 voltage_mode);
 328 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
 329                               u8 voltage_type,
 330                               u8 *svd_gpio_id, u8 *svc_gpio_id);
 331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
 332                                    u32 mem_clock);
 333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
 334                                u32 mem_clock);
 335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
 336                                   u8 module_index,
 337                                   struct atom_mc_reg_table *reg_table);
 338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
 339                                 u8 module_index, struct atom_memory_info *mem_info);
 340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
 341                                      bool gddr5, u8 module_index,
 342                                      struct atom_memory_clock_range_table *mclk_range_table);
 343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
 344                              u16 voltage_id, u16 *voltage);
 345 void rs690_pm_info(struct radeon_device *rdev);
 346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 347                                     unsigned *bankh, unsigned *mtaspect,
 348                                     unsigned *tile_split);
 349
 350 /*
 351  * Fences.
 352  */
 353 struct radeon_fence_driver {
 354         struct radeon_device            *rdev;
 355         uint32_t                        scratch_reg;
 356         uint64_t                        gpu_addr;
 357         volatile uint32_t               *cpu_addr;
 358         /* sync_seq is protected by ring emission lock */
 359         uint64_t                        sync_seq[RADEON_NUM_RINGS];
 360         atomic64_t                      last_seq;
 361         bool                            initialized, delayed_irq;
 362         struct delayed_work             lockup_work;
 363 };
 364
 365 struct radeon_fence {
 366         struct fence            base;
 367
 368         struct radeon_device    *rdev;
 369         uint64_t                seq;
 370         /* RB, DMA, etc. */
 371         unsigned                ring;
 372         bool                    is_vm_update;
 373
 374         wait_queue_t            fence_wake;
 375 };
 376
 377 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 378 int radeon_fence_driver_init(struct radeon_device *rdev);
 379 void radeon_fence_driver_fini(struct radeon_device *rdev);
 380 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
 381 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 382 void radeon_fence_process(struct radeon_device *rdev, int ring);
 383 bool radeon_fence_signaled(struct radeon_fence *fence);
 384 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 385 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 386 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
 387 int radeon_fence_wait_any(struct radeon_device *rdev,
 388                           struct radeon_fence **fences,
 389                           bool intr);
 390 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 391 void radeon_fence_unref(struct radeon_fence **fence);
 392 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 393 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
 394 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
 395 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
 396                                                       struct radeon_fence *b)
 397 {
 398         if (!a) {
 399                 return b;
 400         }
 401
 402         if (!b) {
 403                 return a;
 404         }
 405
 406         BUG_ON(a->ring != b->ring);
 407
 408         if (a->seq > b->seq) {
 409                 return a;
 410         } else {
 411                 return b;
 412         }
 413 }
 414
 415 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
 416                                            struct radeon_fence *b)
 417 {
 418         if (!a) {
 419                 return false;
 420         }
 421
 422         if (!b) {
 423                 return true;
 424         }
 425
 426         BUG_ON(a->ring != b->ring);
 427
 428         return a->seq < b->seq;
 429 }
 430
 431 /*
 432  * Tiling registers
 433  */
 434 struct radeon_surface_reg {
 435         struct radeon_bo *bo;
 436 };
 437
 438 #define RADEON_GEM_MAX_SURFACES 8
 439
 440 /*
 441  * TTM.
 442  */
 443 struct radeon_mman {
 444         struct ttm_bo_global_ref        bo_global_ref;
 445         struct drm_global_reference     mem_global_ref;
 446         struct ttm_bo_device            bdev;
 447         bool                            mem_global_referenced;
 448         bool                            initialized;
 449
 450 #if defined(CONFIG_DEBUG_FS)
 451         struct dentry                   *vram;
 452         struct dentry                   *gtt;
 453 #endif
 454 };
 455
 456 struct radeon_bo_list {
 457         struct radeon_bo                *robj;
 458         struct ttm_validate_buffer      tv;
 459         uint64_t                        gpu_offset;
 460         unsigned                        prefered_domains;
 461         unsigned                        allowed_domains;
 462         uint32_t                        tiling_flags;
 463 };
 464
 465 /* bo virtual address in a specific vm */
 466 struct radeon_bo_va {
 467         /* protected by bo being reserved */
 468         struct list_head                bo_list;
 469         uint32_t                        flags;
 470         uint64_t                        addr;
 471         struct radeon_fence             *last_pt_update;
 472         unsigned                        ref_count;
 473
 474         /* protected by vm mutex */
 475         struct interval_tree_node       it;
 476         struct list_head                vm_status;
 477
 478         /* constant after initialization */
 479         struct radeon_vm                *vm;
 480         struct radeon_bo                *bo;
 481 };
 482
 483 struct radeon_bo {
 484         /* Protected by gem.mutex */
 485         struct list_head                list;
 486         /* Protected by tbo.reserved */
 487         u32                             initial_domain;
 488         struct ttm_place                placements[4];
 489         struct ttm_placement            placement;
 490         struct ttm_buffer_object        tbo;
 491         struct ttm_bo_kmap_obj          kmap;
 492         u32                             flags;
 493         unsigned                        pin_count;
 494         void                            *kptr;
 495         u32                             tiling_flags;
 496         u32                             pitch;
 497         int                             surface_reg;
 498         /* list of all virtual address to which this bo
 499          * is associated to
 500          */
 501         struct list_head                va;
 502         /* Constant after initialization */
 503         struct radeon_device            *rdev;
 504         struct drm_gem_object           gem_base;
 505
 506         struct ttm_bo_kmap_obj          dma_buf_vmap;
 507         pid_t                           pid;
 508
 509         struct radeon_mn                *mn;
 510         struct list_head                mn_list;
 511 };
 512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 513
 514 int radeon_gem_debugfs_init(struct radeon_device *rdev);
 515
 516 /* sub-allocation manager, it has to be protected by another lock.
 517  * By conception this is an helper for other part of the driver
 518  * like the indirect buffer or semaphore, which both have their
 519  * locking.
 520  *
 521  * Principe is simple, we keep a list of sub allocation in offset
 522  * order (first entry has offset == 0, last entry has the highest
 523  * offset).
 524  *
 525  * When allocating new object we first check if there is room at
 526  * the end total_size - (last_object_offset + last_object_size) >=
 527  * alloc_size. If so we allocate new object there.
 528  *
 529  * When there is not enough room at the end, we start waiting for
 530  * each sub object until we reach object_offset+object_size >=
 531  * alloc_size, this object then become the sub object we return.
 532  *
 533  * Alignment can't be bigger than page size.
 534  *
 535  * Hole are not considered for allocation to keep things simple.
 536  * Assumption is that there won't be hole (all object on same
 537  * alignment).
 538  */
 539 struct radeon_sa_manager {
 540         wait_queue_head_t       wq;
 541         struct radeon_bo        *bo;
 542         struct list_head        *hole;
 543         struct list_head        flist[RADEON_NUM_RINGS];
 544         struct list_head        olist;
 545         unsigned                size;
 546         uint64_t                gpu_addr;
 547         void                    *cpu_ptr;
 548         uint32_t                domain;
 549         uint32_t                align;
 550 };
 551
 552 struct radeon_sa_bo;
 553
 554 /* sub-allocation buffer */
 555 struct radeon_sa_bo {
 556         struct list_head                olist;
 557         struct list_head                flist;
 558         struct radeon_sa_manager        *manager;
 559         unsigned                        soffset;
 560         unsigned                        eoffset;
 561         struct radeon_fence             *fence;
 562 };
 563
 564 /*
 565  * GEM objects.
 566  */
 567 struct radeon_gem {
 568         struct mutex            mutex;
 569         struct list_head        objects;
 570 };
 571
 572 int radeon_gem_init(struct radeon_device *rdev);
 573 void radeon_gem_fini(struct radeon_device *rdev);
 574 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
 575                                 int alignment, int initial_domain,
 576                                 u32 flags, bool kernel,
 577                                 struct drm_gem_object **obj);
 578
 579 int radeon_mode_dumb_create(struct drm_file *file_priv,
 580                             struct drm_device *dev,
 581                             struct drm_mode_create_dumb *args);
 582 int radeon_mode_dumb_mmap(struct drm_file *filp,
 583                           struct drm_device *dev,
 584                           uint32_t handle, uint64_t *offset_p);
 585
 586 /*
 587  * Semaphores.
 588  */
 589 struct radeon_semaphore {
 590         struct radeon_sa_bo     *sa_bo;
 591         signed                  waiters;
 592         uint64_t                gpu_addr;
 593 };
 594
 595 int radeon_semaphore_create(struct radeon_device *rdev,
 596                             struct radeon_semaphore **semaphore);
 597 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 598                                   struct radeon_semaphore *semaphore);
 599 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 600                                 struct radeon_semaphore *semaphore);
 601 void radeon_semaphore_free(struct radeon_device *rdev,
 602                            struct radeon_semaphore **semaphore,
 603                            struct radeon_fence *fence);
 604
 605 /*
 606  * Synchronization
 607  */
 608 struct radeon_sync {
 609         struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
 610         struct radeon_fence     *sync_to[RADEON_NUM_RINGS];
 611         struct radeon_fence     *last_vm_update;
 612 };
 613
 614 void radeon_sync_create(struct radeon_sync *sync);
 615 void radeon_sync_fence(struct radeon_sync *sync,
 616                        struct radeon_fence *fence);
 617 int radeon_sync_resv(struct radeon_device *rdev,
 618                      struct radeon_sync *sync,
 619                      struct reservation_object *resv,
 620                      bool shared);
 621 int radeon_sync_rings(struct radeon_device *rdev,
 622                       struct radeon_sync *sync,
 623                       int waiting_ring);
 624 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
 625                       struct radeon_fence *fence);
 626
 627 /*
 628  * GART structures, functions & helpers
 629  */
 630 struct radeon_mc;
 631
 632 #define RADEON_GPU_PAGE_SIZE 4096
 633 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 634 #define RADEON_GPU_PAGE_SHIFT 12
 635 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 636
 637 #define RADEON_GART_PAGE_DUMMY  0
 638 #define RADEON_GART_PAGE_VALID  (1 << 0)
 639 #define RADEON_GART_PAGE_READ   (1 << 1)
 640 #define RADEON_GART_PAGE_WRITE  (1 << 2)
 641 #define RADEON_GART_PAGE_SNOOP  (1 << 3)
 642
 643 struct radeon_gart {
 644         dma_addr_t                      table_addr;
 645         struct radeon_bo                *robj;
 646         void                            *ptr;
 647         unsigned                        num_gpu_pages;
 648         unsigned                        num_cpu_pages;
 649         unsigned                        table_size;
 650         struct page                     **pages;
 651         uint64_t                        *pages_entry;
 652         bool                            ready;
 653 };
 654
 655 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 656 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 657 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 658 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 659 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 660 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 661 int radeon_gart_init(struct radeon_device *rdev);
 662 void radeon_gart_fini(struct radeon_device *rdev);
 663 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 664                         int pages);
 665 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 666                      int pages, struct page **pagelist,
 667                      dma_addr_t *dma_addr, uint32_t flags);
 668
 669
 670 /*
 671  * GPU MC structures, functions & helpers
 672  */
 673 struct radeon_mc {
 674         resource_size_t         aper_size;
 675         resource_size_t         aper_base;
 676         resource_size_t         agp_base;
 677         /* for some chips with <= 32MB we need to lie
 678          * about vram size near mc fb location */
 679         u64                     mc_vram_size;
 680         u64                     visible_vram_size;
 681         u64                     gtt_size;
 682         u64                     gtt_start;
 683         u64                     gtt_end;
 684         u64                     vram_start;
 685         u64                     vram_end;
 686         unsigned                vram_width;
 687         u64                     real_vram_size;
 688         int                     vram_mtrr;
 689         bool                    vram_is_ddr;
 690         bool                    igp_sideport_enabled;
 691         u64                     gtt_base_align;
 692         u64                     mc_mask;
 693 };
 694
 695 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 696 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 697
 698 /*
 699  * GPU scratch registers structures, functions & helpers
 700  */
 701 struct radeon_scratch {
 702         unsigned                num_reg;
 703         uint32_t                reg_base;
 704         bool                    free[32];
 705         uint32_t                reg[32];
 706 };
 707
 708 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 709 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 710
 711 /*
 712  * GPU doorbell structures, functions & helpers
 713  */
 714 #define RADEON_MAX_DOORBELLS 1024       /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
 715
 716 struct radeon_doorbell {
 717         /* doorbell mmio */
 718         resource_size_t         base;
 719         resource_size_t         size;
 720         u32 __iomem             *ptr;
 721         u32                     num_doorbells;  /* Number of doorbells actually reserved for radeon. */
 722         unsigned long           used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
 723 };
 724
 725 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
 726 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
 727 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
 728                                   phys_addr_t *aperture_base,
 729                                   size_t *aperture_size,
 730                                   size_t *start_offset);
 731
 732 /*
 733  * IRQS.
 734  */
 735
 736 struct radeon_flip_work {
 737         struct work_struct              flip_work;
 738         struct work_struct              unpin_work;
 739         struct radeon_device            *rdev;
 740         int                             crtc_id;
 741         uint64_t                        base;
 742         struct drm_pending_vblank_event *event;
 743         struct radeon_bo                *old_rbo;
 744         struct fence                    *fence;
 745 };
 746
 747 struct r500_irq_stat_regs {
 748         u32 disp_int;
 749         u32 hdmi0_status;
 750 };
 751
 752 struct r600_irq_stat_regs {
 753         u32 disp_int;
 754         u32 disp_int_cont;
 755         u32 disp_int_cont2;
 756         u32 d1grph_int;
 757         u32 d2grph_int;
 758         u32 hdmi0_status;
 759         u32 hdmi1_status;
 760 };
 761
 762 struct evergreen_irq_stat_regs {
 763         u32 disp_int;
 764         u32 disp_int_cont;
 765         u32 disp_int_cont2;
 766         u32 disp_int_cont3;
 767         u32 disp_int_cont4;
 768         u32 disp_int_cont5;
 769         u32 d1grph_int;
 770         u32 d2grph_int;
 771         u32 d3grph_int;
 772         u32 d4grph_int;
 773         u32 d5grph_int;
 774         u32 d6grph_int;
 775         u32 afmt_status1;
 776         u32 afmt_status2;
 777         u32 afmt_status3;
 778         u32 afmt_status4;
 779         u32 afmt_status5;
 780         u32 afmt_status6;
 781 };
 782
 783 struct cik_irq_stat_regs {
 784         u32 disp_int;
 785         u32 disp_int_cont;
 786         u32 disp_int_cont2;
 787         u32 disp_int_cont3;
 788         u32 disp_int_cont4;
 789         u32 disp_int_cont5;
 790         u32 disp_int_cont6;
 791         u32 d1grph_int;
 792         u32 d2grph_int;
 793         u32 d3grph_int;
 794         u32 d4grph_int;
 795         u32 d5grph_int;
 796         u32 d6grph_int;
 797 };
 798
 799 union radeon_irq_stat_regs {
 800         struct r500_irq_stat_regs r500;
 801         struct r600_irq_stat_regs r600;
 802         struct evergreen_irq_stat_regs evergreen;
 803         struct cik_irq_stat_regs cik;
 804 };
 805
 806 struct radeon_irq {
 807         bool                            installed;
 808         spinlock_t                      lock;
 809         atomic_t                        ring_int[RADEON_NUM_RINGS];
 810         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
 811         atomic_t                        pflip[RADEON_MAX_CRTCS];
 812         wait_queue_head_t               vblank_queue;
 813         bool                            hpd[RADEON_MAX_HPD_PINS];
 814         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
 815         union radeon_irq_stat_regs      stat_regs;
 816         bool                            dpm_thermal;
 817 };
 818
 819 int radeon_irq_kms_init(struct radeon_device *rdev);
 820 void radeon_irq_kms_fini(struct radeon_device *rdev);
 821 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 822 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
 823 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 824 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 825 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 826 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
 827 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
 828 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 829 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
 830
 831 /*
 832  * CP & rings.
 833  */
 834
 835 struct radeon_ib {
 836         struct radeon_sa_bo             *sa_bo;
 837         uint32_t                        length_dw;
 838         uint64_t                        gpu_addr;
 839         uint32_t                        *ptr;
 840         int                             ring;
 841         struct radeon_fence             *fence;
 842         struct radeon_vm                *vm;
 843         bool                            is_const_ib;
 844         struct radeon_sync              sync;
 845 };
 846
 847 struct radeon_ring {
 848         struct radeon_bo        *ring_obj;
 849         volatile uint32_t       *ring;
 850         unsigned                rptr_offs;
 851         unsigned                rptr_save_reg;
 852         u64                     next_rptr_gpu_addr;
 853         volatile u32            *next_rptr_cpu_addr;
 854         unsigned                wptr;
 855         unsigned                wptr_old;
 856         unsigned                ring_size;
 857         unsigned                ring_free_dw;
 858         int                     count_dw;
 859         atomic_t                last_rptr;
 860         atomic64_t              last_activity;
 861         uint64_t                gpu_addr;
 862         uint32_t                align_mask;
 863         uint32_t                ptr_mask;
 864         bool                    ready;
 865         u32                     nop;
 866         u32                     idx;
 867         u64                     last_semaphore_signal_addr;
 868         u64                     last_semaphore_wait_addr;
 869         /* for CIK queues */
 870         u32 me;
 871         u32 pipe;
 872         u32 queue;
 873         struct radeon_bo        *mqd_obj;
 874         u32 doorbell_index;
 875         unsigned                wptr_offs;
 876 };
 877
 878 struct radeon_mec {
 879         struct radeon_bo        *hpd_eop_obj;
 880         u64                     hpd_eop_gpu_addr;
 881         u32 num_pipe;
 882         u32 num_mec;
 883         u32 num_queue;
 884 };
 885
 886 /*
 887  * VM
 888  */
 889
 890 /* maximum number of VMIDs */
 891 #define RADEON_NUM_VM   16
 892
 893 /* number of entries in page table */
 894 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
 895
 896 /* PTBs (Page Table Blocks) need to be aligned to 32K */
 897 #define RADEON_VM_PTB_ALIGN_SIZE   32768
 898 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
 899 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
 900
 901 #define R600_PTE_VALID          (1 << 0)
 902 #define R600_PTE_SYSTEM         (1 << 1)
 903 #define R600_PTE_SNOOPED        (1 << 2)
 904 #define R600_PTE_READABLE       (1 << 5)
 905 #define R600_PTE_WRITEABLE      (1 << 6)
 906
 907 /* PTE (Page Table Entry) fragment field for different page sizes */
 908 #define R600_PTE_FRAG_4KB       (0 << 7)
 909 #define R600_PTE_FRAG_64KB      (4 << 7)
 910 #define R600_PTE_FRAG_256KB     (6 << 7)
 911
 912 /* flags needed to be set so we can copy directly from the GART table */
 913 #define R600_PTE_GART_MASK      ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
 914                                   R600_PTE_SYSTEM | R600_PTE_VALID )
 915
 916 struct radeon_vm_pt {
 917         struct radeon_bo                *bo;
 918         uint64_t                        addr;
 919 };
 920
 921 struct radeon_vm_id {
 922         unsigned                id;
 923         uint64_t                pd_gpu_addr;
 924         /* last flushed PD/PT update */
 925         struct radeon_fence     *flushed_updates;
 926         /* last use of vmid */
 927         struct radeon_fence     *last_id_use;
 928 };
 929
 930 struct radeon_vm {
 931         struct mutex            mutex;
 932
 933         struct rb_root          va;
 934
 935         /* protecting invalidated and freed */
 936         spinlock_t              status_lock;
 937
 938         /* BOs moved, but not yet updated in the PT */
 939         struct list_head        invalidated;
 940
 941         /* BOs freed, but not yet updated in the PT */
 942         struct list_head        freed;
 943
 944         /* contains the page directory */
 945         struct radeon_bo        *page_directory;
 946         unsigned                max_pde_used;
 947
 948         /* array of page tables, one for each page directory entry */
 949         struct radeon_vm_pt     *page_tables;
 950
 951         struct radeon_bo_va     *ib_bo_va;
 952
 953         /* for id and flush management per ring */
 954         struct radeon_vm_id     ids[RADEON_NUM_RINGS];
 955 };
 956
 957 struct radeon_vm_manager {
 958         struct radeon_fence             *active[RADEON_NUM_VM];
 959         uint32_t                        max_pfn;
 960         /* number of VMIDs */
 961         unsigned                        nvm;
 962         /* vram base address for page table entry  */
 963         u64                             vram_base_offset;
 964         /* is vm enabled? */
 965         bool                            enabled;
 966         /* for hw to save the PD addr on suspend/resume */
 967         uint32_t                        saved_table_addr[RADEON_NUM_VM];
 968 };
 969
 970 /*
 971  * file private structure
 972  */
 973 struct radeon_fpriv {
 974         struct radeon_vm                vm;
 975 };
 976
 977 /*
 978  * R6xx+ IH ring
 979  */
 980 struct r600_ih {
 981         struct radeon_bo        *ring_obj;
 982         volatile uint32_t       *ring;
 983         unsigned                rptr;
 984         unsigned                ring_size;
 985         uint64_t                gpu_addr;
 986         uint32_t                ptr_mask;
 987         atomic_t                lock;
 988         bool                    enabled;
 989 };
 990
 991 /*
 992  * RLC stuff
 993  */
 994 #include "clearstate_defs.h"
 995
 996 struct radeon_rlc {
 997         /* for power gating */
 998         struct radeon_bo        *save_restore_obj;
 999         uint64_t                save_restore_gpu_addr;
1000         volatile uint32_t       *sr_ptr;
1001         const u32               *reg_list;
1002         u32                     reg_list_size;
1003         /* for clear state */
1004         struct radeon_bo        *clear_state_obj;
1005         uint64_t                clear_state_gpu_addr;
1006         volatile uint32_t       *cs_ptr;
1007         const struct cs_section_def   *cs_data;
1008         u32                     clear_state_size;
1009         /* for cp tables */
1010         struct radeon_bo        *cp_table_obj;
1011         uint64_t                cp_table_gpu_addr;
1012         volatile uint32_t       *cp_table_ptr;
1013         u32                     cp_table_size;
1014 };
1015
1016 int radeon_ib_get(struct radeon_device *rdev, int ring,
1017                   struct radeon_ib *ib, struct radeon_vm *vm,
1018                   unsigned size);
1019 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1020 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1021                        struct radeon_ib *const_ib, bool hdp_flush);
1022 int radeon_ib_pool_init(struct radeon_device *rdev);
1023 void radeon_ib_pool_fini(struct radeon_device *rdev);
1024 int radeon_ib_ring_tests(struct radeon_device *rdev);
1025 /* Ring access between begin & end cannot sleep */
1026 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1027                                       struct radeon_ring *ring);
1028 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1029 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1030 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1031 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1032                         bool hdp_flush);
1033 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1034                                bool hdp_flush);
1035 void radeon_ring_undo(struct radeon_ring *ring);
1036 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1037 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1038 void radeon_ring_lockup_update(struct radeon_device *rdev,
1039                                struct radeon_ring *ring);
1040 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1041 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1042                             uint32_t **data);
1043 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1044                         unsigned size, uint32_t *data);
1045 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1046                      unsigned rptr_offs, u32 nop);
1047 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1048
1049
1050 /* r600 async dma */
1051 void r600_dma_stop(struct radeon_device *rdev);
1052 int r600_dma_resume(struct radeon_device *rdev);
1053 void r600_dma_fini(struct radeon_device *rdev);
1054
1055 void cayman_dma_stop(struct radeon_device *rdev);
1056 int cayman_dma_resume(struct radeon_device *rdev);
1057 void cayman_dma_fini(struct radeon_device *rdev);
1058
1059 /*
1060  * CS.
1061  */
1062 struct radeon_cs_chunk {
1063         uint32_t                length_dw;
1064         uint32_t                *kdata;
1065         void __user             *user_ptr;
1066 };
1067
1068 struct radeon_cs_parser {
1069         struct device           *dev;
1070         struct radeon_device    *rdev;
1071         struct drm_file         *filp;
1072         /* chunks */
1073         unsigned                nchunks;
1074         struct radeon_cs_chunk  *chunks;
1075         uint64_t                *chunks_array;
1076         /* IB */
1077         unsigned                idx;
1078         /* relocations */
1079         unsigned                nrelocs;
1080         struct radeon_bo_list   *relocs;
1081         struct radeon_bo_list   *vm_bos;
1082         struct list_head        validated;
1083         unsigned                dma_reloc_idx;
1084         /* indices of various chunks */
1085         struct radeon_cs_chunk  *chunk_ib;
1086         struct radeon_cs_chunk  *chunk_relocs;
1087         struct radeon_cs_chunk  *chunk_flags;
1088         struct radeon_cs_chunk  *chunk_const_ib;
1089         struct radeon_ib        ib;
1090         struct radeon_ib        const_ib;
1091         void                    *track;
1092         unsigned                family;
1093         int                     parser_error;
1094         u32                     cs_flags;
1095         u32                     ring;
1096         s32                     priority;
1097         struct ww_acquire_ctx   ticket;
1098 };
1099
1100 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1101 {
1102         struct radeon_cs_chunk *ibc = p->chunk_ib;
1103
1104         if (ibc->kdata)
1105                 return ibc->kdata[idx];
1106         return p->ib.ptr[idx];
1107 }
1108
1109
1110 struct radeon_cs_packet {
1111         unsigned        idx;
1112         unsigned        type;
1113         unsigned        reg;
1114         unsigned        opcode;
1115         int             count;
1116         unsigned        one_reg_wr;
1117 };
1118
1119 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1120                                       struct radeon_cs_packet *pkt,
1121                                       unsigned idx, unsigned reg);
1122 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1123                                       struct radeon_cs_packet *pkt);
1124
1125
1126 /*
1127  * AGP
1128  */
1129 int radeon_agp_init(struct radeon_device *rdev);
1130 void radeon_agp_resume(struct radeon_device *rdev);
1131 void radeon_agp_suspend(struct radeon_device *rdev);
1132 void radeon_agp_fini(struct radeon_device *rdev);
1133
1134
1135 /*
1136  * Writeback
1137  */
1138 struct radeon_wb {
1139         struct radeon_bo        *wb_obj;
1140         volatile uint32_t       *wb;
1141         uint64_t                gpu_addr;
1142         bool                    enabled;
1143         bool                    use_event;
1144 };
1145
1146 #define RADEON_WB_SCRATCH_OFFSET 0
1147 #define RADEON_WB_RING0_NEXT_RPTR 256
1148 #define RADEON_WB_CP_RPTR_OFFSET 1024
1149 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1150 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1151 #define R600_WB_DMA_RPTR_OFFSET   1792
1152 #define R600_WB_IH_WPTR_OFFSET   2048
1153 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1154 #define R600_WB_EVENT_OFFSET     3072
1155 #define CIK_WB_CP1_WPTR_OFFSET     3328
1156 #define CIK_WB_CP2_WPTR_OFFSET     3584
1157 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1158 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1159
1160 /**
1161  * struct radeon_pm - power management datas
1162  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1163  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1164  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1165  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1166  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1167  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1168  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1169  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1170  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1171  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
1172  * @needed_bandwidth:   current bandwidth needs
1173  *
1174  * It keeps track of various data needed to take powermanagement decision.
1175  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1176  * Equation between gpu/memory clock and available bandwidth is hw dependent
1177  * (type of memory, bus size, efficiency, ...)
1178  */
1179
1180 enum radeon_pm_method {
1181         PM_METHOD_PROFILE,
1182         PM_METHOD_DYNPM,
1183         PM_METHOD_DPM,
1184 };
1185
1186 enum radeon_dynpm_state {
1187         DYNPM_STATE_DISABLED,
1188         DYNPM_STATE_MINIMUM,
1189         DYNPM_STATE_PAUSED,
1190         DYNPM_STATE_ACTIVE,
1191         DYNPM_STATE_SUSPENDED,
1192 };
1193 enum radeon_dynpm_action {
1194         DYNPM_ACTION_NONE,
1195         DYNPM_ACTION_MINIMUM,
1196         DYNPM_ACTION_DOWNCLOCK,
1197         DYNPM_ACTION_UPCLOCK,
1198         DYNPM_ACTION_DEFAULT
1199 };
1200
1201 enum radeon_voltage_type {
1202         VOLTAGE_NONE = 0,
1203         VOLTAGE_GPIO,
1204         VOLTAGE_VDDC,
1205         VOLTAGE_SW
1206 };
1207
1208 enum radeon_pm_state_type {
1209         /* not used for dpm */
1210         POWER_STATE_TYPE_DEFAULT,
1211         POWER_STATE_TYPE_POWERSAVE,
1212         /* user selectable states */
1213         POWER_STATE_TYPE_BATTERY,
1214         POWER_STATE_TYPE_BALANCED,
1215         POWER_STATE_TYPE_PERFORMANCE,
1216         /* internal states */
1217         POWER_STATE_TYPE_INTERNAL_UVD,
1218         POWER_STATE_TYPE_INTERNAL_UVD_SD,
1219         POWER_STATE_TYPE_INTERNAL_UVD_HD,
1220         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1221         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1222         POWER_STATE_TYPE_INTERNAL_BOOT,
1223         POWER_STATE_TYPE_INTERNAL_THERMAL,
1224         POWER_STATE_TYPE_INTERNAL_ACPI,
1225         POWER_STATE_TYPE_INTERNAL_ULV,
1226         POWER_STATE_TYPE_INTERNAL_3DPERF,
1227 };
1228
1229 enum radeon_pm_profile_type {
1230         PM_PROFILE_DEFAULT,
1231         PM_PROFILE_AUTO,
1232         PM_PROFILE_LOW,
1233         PM_PROFILE_MID,
1234         PM_PROFILE_HIGH,
1235 };
1236
1237 #define PM_PROFILE_DEFAULT_IDX 0
1238 #define PM_PROFILE_LOW_SH_IDX  1
1239 #define PM_PROFILE_MID_SH_IDX  2
1240 #define PM_PROFILE_HIGH_SH_IDX 3
1241 #define PM_PROFILE_LOW_MH_IDX  4
1242 #define PM_PROFILE_MID_MH_IDX  5
1243 #define PM_PROFILE_HIGH_MH_IDX 6
1244 #define PM_PROFILE_MAX         7
1245
1246 struct radeon_pm_profile {
1247         int dpms_off_ps_idx;
1248         int dpms_on_ps_idx;
1249         int dpms_off_cm_idx;
1250         int dpms_on_cm_idx;
1251 };
1252
1253 enum radeon_int_thermal_type {
1254         THERMAL_TYPE_NONE,
1255         THERMAL_TYPE_EXTERNAL,
1256         THERMAL_TYPE_EXTERNAL_GPIO,
1257         THERMAL_TYPE_RV6XX,
1258         THERMAL_TYPE_RV770,
1259         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1260         THERMAL_TYPE_EVERGREEN,
1261         THERMAL_TYPE_SUMO,
1262         THERMAL_TYPE_NI,
1263         THERMAL_TYPE_SI,
1264         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1265         THERMAL_TYPE_CI,
1266         THERMAL_TYPE_KV,
1267 };
1268
1269 struct radeon_voltage {
1270         enum radeon_voltage_type type;
1271         /* gpio voltage */
1272         struct radeon_gpio_rec gpio;
1273         u32 delay; /* delay in usec from voltage drop to sclk change */
1274         bool active_high; /* voltage drop is active when bit is high */
1275         /* VDDC voltage */
1276         u8 vddc_id; /* index into vddc voltage table */
1277         u8 vddci_id; /* index into vddci voltage table */
1278         bool vddci_enabled;
1279         /* r6xx+ sw */
1280         u16 voltage;
1281         /* evergreen+ vddci */
1282         u16 vddci;
1283 };
1284
1285 /* clock mode flags */
1286 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1287
1288 struct radeon_pm_clock_info {
1289         /* memory clock */
1290         u32 mclk;
1291         /* engine clock */
1292         u32 sclk;
1293         /* voltage info */
1294         struct radeon_voltage voltage;
1295         /* standardized clock flags */
1296         u32 flags;
1297 };
1298
1299 /* state flags */
1300 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1301
1302 struct radeon_power_state {
1303         enum radeon_pm_state_type type;
1304         struct radeon_pm_clock_info *clock_info;
1305         /* number of valid clock modes in this power state */
1306         int num_clock_modes;
1307         struct radeon_pm_clock_info *default_clock_mode;
1308         /* standardized state flags */
1309         u32 flags;
1310         u32 misc; /* vbios specific flags */
1311         u32 misc2; /* vbios specific flags */
1312         int pcie_lanes; /* pcie lanes */
1313 };
1314
1315 /*
1316  * Some modes are overclocked by very low value, accept them
1317  */
1318 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1319
1320 enum radeon_dpm_auto_throttle_src {
1321         RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1322         RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1323 };
1324
1325 enum radeon_dpm_event_src {
1326         RADEON_DPM_EVENT_SRC_ANALOG = 0,
1327         RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1328         RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1329         RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1330         RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1331 };
1332
1333 #define RADEON_MAX_VCE_LEVELS 6
1334
1335 enum radeon_vce_level {
1336         RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1337         RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1338         RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1339         RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1340         RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1341         RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1342 };
1343
1344 struct radeon_ps {
1345         u32 caps; /* vbios flags */
1346         u32 class; /* vbios flags */
1347         u32 class2; /* vbios flags */
1348         /* UVD clocks */
1349         u32 vclk;
1350         u32 dclk;
1351         /* VCE clocks */
1352         u32 evclk;
1353         u32 ecclk;
1354         bool vce_active;
1355         enum radeon_vce_level vce_level;
1356         /* asic priv */
1357         void *ps_priv;
1358 };
1359
1360 struct radeon_dpm_thermal {
1361         /* thermal interrupt work */
1362         struct work_struct work;
1363         /* low temperature threshold */
1364         int                min_temp;
1365         /* high temperature threshold */
1366         int                max_temp;
1367         /* was interrupt low to high or high to low */
1368         bool               high_to_low;
1369 };
1370
1371 enum radeon_clk_action
1372 {
1373         RADEON_SCLK_UP = 1,
1374         RADEON_SCLK_DOWN
1375 };
1376
1377 struct radeon_blacklist_clocks
1378 {
1379         u32 sclk;
1380         u32 mclk;
1381         enum radeon_clk_action action;
1382 };
1383
1384 struct radeon_clock_and_voltage_limits {
1385         u32 sclk;
1386         u32 mclk;
1387         u16 vddc;
1388         u16 vddci;
1389 };
1390
1391 struct radeon_clock_array {
1392         u32 count;
1393         u32 *values;
1394 };
1395
1396 struct radeon_clock_voltage_dependency_entry {
1397         u32 clk;
1398         u16 v;
1399 };
1400
1401 struct radeon_clock_voltage_dependency_table {
1402         u32 count;
1403         struct radeon_clock_voltage_dependency_entry *entries;
1404 };
1405
1406 union radeon_cac_leakage_entry {
1407         struct {
1408                 u16 vddc;
1409                 u32 leakage;
1410         };
1411         struct {
1412                 u16 vddc1;
1413                 u16 vddc2;
1414                 u16 vddc3;
1415         };
1416 };
1417
1418 struct radeon_cac_leakage_table {
1419         u32 count;
1420         union radeon_cac_leakage_entry *entries;
1421 };
1422
1423 struct radeon_phase_shedding_limits_entry {
1424         u16 voltage;
1425         u32 sclk;
1426         u32 mclk;
1427 };
1428
1429 struct radeon_phase_shedding_limits_table {
1430         u32 count;
1431         struct radeon_phase_shedding_limits_entry *entries;
1432 };
1433
1434 struct radeon_uvd_clock_voltage_dependency_entry {
1435         u32 vclk;
1436         u32 dclk;
1437         u16 v;
1438 };
1439
1440 struct radeon_uvd_clock_voltage_dependency_table {
1441         u8 count;
1442         struct radeon_uvd_clock_voltage_dependency_entry *entries;
1443 };
1444
1445 struct radeon_vce_clock_voltage_dependency_entry {
1446         u32 ecclk;
1447         u32 evclk;
1448         u16 v;
1449 };
1450
1451 struct radeon_vce_clock_voltage_dependency_table {
1452         u8 count;
1453         struct radeon_vce_clock_voltage_dependency_entry *entries;
1454 };
1455
1456 struct radeon_ppm_table {
1457         u8 ppm_design;
1458         u16 cpu_core_number;
1459         u32 platform_tdp;
1460         u32 small_ac_platform_tdp;
1461         u32 platform_tdc;
1462         u32 small_ac_platform_tdc;
1463         u32 apu_tdp;
1464         u32 dgpu_tdp;
1465         u32 dgpu_ulv_power;
1466         u32 tj_max;
1467 };
1468
1469 struct radeon_cac_tdp_table {
1470         u16 tdp;
1471         u16 configurable_tdp;
1472         u16 tdc;
1473         u16 battery_power_limit;
1474         u16 small_power_limit;
1475         u16 low_cac_leakage;
1476         u16 high_cac_leakage;
1477         u16 maximum_power_delivery_limit;
1478 };
1479
1480 struct radeon_dpm_dynamic_state {
1481         struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1482         struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1483         struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1484         struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1485         struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1486         struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1487         struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1488         struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1489         struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1490         struct radeon_clock_array valid_sclk_values;
1491         struct radeon_clock_array valid_mclk_values;
1492         struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1493         struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1494         u32 mclk_sclk_ratio;
1495         u32 sclk_mclk_delta;
1496         u16 vddc_vddci_delta;
1497         u16 min_vddc_for_pcie_gen2;
1498         struct radeon_cac_leakage_table cac_leakage_table;
1499         struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1500         struct radeon_ppm_table *ppm_table;
1501         struct radeon_cac_tdp_table *cac_tdp_table;
1502 };
1503
1504 struct radeon_dpm_fan {
1505         u16 t_min;
1506         u16 t_med;
1507         u16 t_high;
1508         u16 pwm_min;
1509         u16 pwm_med;
1510         u16 pwm_high;
1511         u8 t_hyst;
1512         u32 cycle_delay;
1513         u16 t_max;
1514         u8 control_mode;
1515         u16 default_max_fan_pwm;
1516         u16 default_fan_output_sensitivity;
1517         u16 fan_output_sensitivity;
1518         bool ucode_fan_control;
1519 };
1520
1521 enum radeon_pcie_gen {
1522         RADEON_PCIE_GEN1 = 0,
1523         RADEON_PCIE_GEN2 = 1,
1524         RADEON_PCIE_GEN3 = 2,
1525         RADEON_PCIE_GEN_INVALID = 0xffff
1526 };
1527
1528 enum radeon_dpm_forced_level {
1529         RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1530         RADEON_DPM_FORCED_LEVEL_LOW = 1,
1531         RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1532 };
1533
1534 struct radeon_vce_state {
1535         /* vce clocks */
1536         u32 evclk;
1537         u32 ecclk;
1538         /* gpu clocks */
1539         u32 sclk;
1540         u32 mclk;
1541         u8 clk_idx;
1542         u8 pstate;
1543 };
1544
1545 struct radeon_dpm {
1546         struct radeon_ps        *ps;
1547         /* number of valid power states */
1548         int                     num_ps;
1549         /* current power state that is active */
1550         struct radeon_ps        *current_ps;
1551         /* requested power state */
1552         struct radeon_ps        *requested_ps;
1553         /* boot up power state */
1554         struct radeon_ps        *boot_ps;
1555         /* default uvd power state */
1556         struct radeon_ps        *uvd_ps;
1557         /* vce requirements */
1558         struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1559         enum radeon_vce_level vce_level;
1560         enum radeon_pm_state_type state;
1561         enum radeon_pm_state_type user_state;
1562         u32                     platform_caps;
1563         u32                     voltage_response_time;
1564         u32                     backbias_response_time;
1565         void                    *priv;
1566         u32                     new_active_crtcs;
1567         int                     new_active_crtc_count;
1568         u32                     current_active_crtcs;
1569         int                     current_active_crtc_count;
1570         bool single_display;
1571         struct radeon_dpm_dynamic_state dyn_state;
1572         struct radeon_dpm_fan fan;
1573         u32 tdp_limit;
1574         u32 near_tdp_limit;
1575         u32 near_tdp_limit_adjusted;
1576         u32 sq_ramping_threshold;
1577         u32 cac_leakage;
1578         u16 tdp_od_limit;
1579         u32 tdp_adjustment;
1580         u16 load_line_slope;
1581         bool power_control;
1582         bool ac_power;
1583         /* special states active */
1584         bool                    thermal_active;
1585         bool                    uvd_active;
1586         bool                    vce_active;
1587         /* thermal handling */
1588         struct radeon_dpm_thermal thermal;
1589         /* forced levels */
1590         enum radeon_dpm_forced_level forced_level;
1591         /* track UVD streams */
1592         unsigned sd;
1593         unsigned hd;
1594 };
1595
1596 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1597 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1598
1599 struct radeon_pm {
1600         struct mutex            mutex;
1601         /* write locked while reprogramming mclk */
1602         struct rw_semaphore     mclk_lock;
1603         u32                     active_crtcs;
1604         int                     active_crtc_count;
1605         int                     req_vblank;
1606         bool                    vblank_sync;
1607         fixed20_12              max_bandwidth;
1608         fixed20_12              igp_sideport_mclk;
1609         fixed20_12              igp_system_mclk;
1610         fixed20_12              igp_ht_link_clk;
1611         fixed20_12              igp_ht_link_width;
1612         fixed20_12              k8_bandwidth;
1613         fixed20_12              sideport_bandwidth;
1614         fixed20_12              ht_bandwidth;
1615         fixed20_12              core_bandwidth;
1616         fixed20_12              sclk;
1617         fixed20_12              mclk;
1618         fixed20_12              needed_bandwidth;
1619         struct radeon_power_state *power_state;
1620         /* number of valid power states */
1621         int                     num_power_states;
1622         int                     current_power_state_index;
1623         int                     current_clock_mode_index;
1624         int                     requested_power_state_index;
1625         int                     requested_clock_mode_index;
1626         int                     default_power_state_index;
1627         u32                     current_sclk;
1628         u32                     current_mclk;
1629         u16                     current_vddc;
1630         u16                     current_vddci;
1631         u32                     default_sclk;
1632         u32                     default_mclk;
1633         u16                     default_vddc;
1634         u16                     default_vddci;
1635         struct radeon_i2c_chan *i2c_bus;
1636         /* selected pm method */
1637         enum radeon_pm_method     pm_method;
1638         /* dynpm power management */
1639         struct delayed_work     dynpm_idle_work;
1640         enum radeon_dynpm_state dynpm_state;
1641         enum radeon_dynpm_action        dynpm_planned_action;
1642         unsigned long           dynpm_action_timeout;
1643         bool                    dynpm_can_upclock;
1644         bool                    dynpm_can_downclock;
1645         /* profile-based power management */
1646         enum radeon_pm_profile_type profile;
1647         int                     profile_index;
1648         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1649         /* internal thermal controller on rv6xx+ */
1650         enum radeon_int_thermal_type int_thermal_type;
1651         struct device           *int_hwmon_dev;
1652         /* fan control parameters */
1653         bool                    no_fan;
1654         u8                      fan_pulses_per_revolution;
1655         u8                      fan_min_rpm;
1656         u8                      fan_max_rpm;
1657         /* dpm */
1658         bool                    dpm_enabled;
1659         bool                    sysfs_initialized;
1660         struct radeon_dpm       dpm;
1661 };
1662
1663 int radeon_pm_get_type_index(struct radeon_device *rdev,
1664                              enum radeon_pm_state_type ps_type,
1665                              int instance);
1666 /*
1667  * UVD
1668  */
1669 #define RADEON_MAX_UVD_HANDLES  10
1670 #define RADEON_UVD_STACK_SIZE   (1024*1024)
1671 #define RADEON_UVD_HEAP_SIZE    (1024*1024)
1672
1673 struct radeon_uvd {
1674         struct radeon_bo        *vcpu_bo;
1675         void                    *cpu_addr;
1676         uint64_t                gpu_addr;
1677         atomic_t                handles[RADEON_MAX_UVD_HANDLES];
1678         struct drm_file         *filp[RADEON_MAX_UVD_HANDLES];
1679         unsigned                img_size[RADEON_MAX_UVD_HANDLES];
1680         struct delayed_work     idle_work;
1681 };
1682
1683 int radeon_uvd_init(struct radeon_device *rdev);
1684 void radeon_uvd_fini(struct radeon_device *rdev);
1685 int radeon_uvd_suspend(struct radeon_device *rdev);
1686 int radeon_uvd_resume(struct radeon_device *rdev);
1687 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1688                               uint32_t handle, struct radeon_fence **fence);
1689 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1690                                uint32_t handle, struct radeon_fence **fence);
1691 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1692                                        uint32_t allowed_domains);
1693 void radeon_uvd_free_handles(struct radeon_device *rdev,
1694                              struct drm_file *filp);
1695 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1696 void radeon_uvd_note_usage(struct radeon_device *rdev);
1697 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1698                                   unsigned vclk, unsigned dclk,
1699                                   unsigned vco_min, unsigned vco_max,
1700                                   unsigned fb_factor, unsigned fb_mask,
1701                                   unsigned pd_min, unsigned pd_max,
1702                                   unsigned pd_even,
1703                                   unsigned *optimal_fb_div,
1704                                   unsigned *optimal_vclk_div,
1705                                   unsigned *optimal_dclk_div);
1706 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1707                                 unsigned cg_upll_func_cntl);
1708
1709 /*
1710  * VCE
1711  */
1712 #define RADEON_MAX_VCE_HANDLES  16
1713 #define RADEON_VCE_STACK_SIZE   (1024*1024)
1714 #define RADEON_VCE_HEAP_SIZE    (4*1024*1024)
1715
1716 struct radeon_vce {
1717         struct radeon_bo        *vcpu_bo;
1718         uint64_t                gpu_addr;
1719         unsigned                fw_version;
1720         unsigned                fb_version;
1721         atomic_t                handles[RADEON_MAX_VCE_HANDLES];
1722         struct drm_file         *filp[RADEON_MAX_VCE_HANDLES];
1723         unsigned                img_size[RADEON_MAX_VCE_HANDLES];
1724         struct delayed_work     idle_work;
1725 };
1726
1727 int radeon_vce_init(struct radeon_device *rdev);
1728 void radeon_vce_fini(struct radeon_device *rdev);
1729 int radeon_vce_suspend(struct radeon_device *rdev);
1730 int radeon_vce_resume(struct radeon_device *rdev);
1731 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1732                               uint32_t handle, struct radeon_fence **fence);
1733 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1734                                uint32_t handle, struct radeon_fence **fence);
1735 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1736 void radeon_vce_note_usage(struct radeon_device *rdev);
1737 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1738 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1739 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1740                                struct radeon_ring *ring,
1741                                struct radeon_semaphore *semaphore,
1742                                bool emit_wait);
1743 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1744 void radeon_vce_fence_emit(struct radeon_device *rdev,
1745                            struct radeon_fence *fence);
1746 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1747 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1748
1749 struct r600_audio_pin {
1750         int                     channels;
1751         int                     rate;
1752         int                     bits_per_sample;
1753         u8                      status_bits;
1754         u8                      category_code;
1755         u32                     offset;
1756         bool                    connected;
1757         u32                     id;
1758 };
1759
1760 struct r600_audio {
1761         bool enabled;
1762         struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1763         int num_pins;
1764         struct radeon_audio_funcs *hdmi_funcs;
1765         struct radeon_audio_funcs *dp_funcs;
1766         struct radeon_audio_basic_funcs *funcs;
1767 };
1768
1769 /*
1770  * Benchmarking
1771  */
1772 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1773
1774
1775 /*
1776  * Testing
1777  */
1778 void radeon_test_moves(struct radeon_device *rdev);
1779 void radeon_test_ring_sync(struct radeon_device *rdev,
1780                            struct radeon_ring *cpA,
1781                            struct radeon_ring *cpB);
1782 void radeon_test_syncing(struct radeon_device *rdev);
1783
1784 /*
1785  * MMU Notifier
1786  */
1787 #if defined(CONFIG_MMU_NOTIFIER)
1788 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1789 void radeon_mn_unregister(struct radeon_bo *bo);
1790 #else
1791 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1792 {
1793         return -ENODEV;
1794 }
1795 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1796 #endif
1797
1798 /*
1799  * Debugfs
1800  */
1801 struct radeon_debugfs {
1802         struct drm_info_list    *files;
1803         unsigned                num_files;
1804 };
1805
1806 int radeon_debugfs_add_files(struct radeon_device *rdev,
1807                              struct drm_info_list *files,
1808                              unsigned nfiles);
1809 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1810
1811 /*
1812  * ASIC ring specific functions.
1813  */
1814 struct radeon_asic_ring {
1815         /* ring read/write ptr handling */
1816         u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1817         u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1818         void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1819
1820         /* validating and patching of IBs */
1821         int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1822         int (*cs_parse)(struct radeon_cs_parser *p);
1823
1824         /* command emmit functions */
1825         void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1826         void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1827         void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1828         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1829                                struct radeon_semaphore *semaphore, bool emit_wait);
1830         void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1831                          unsigned vm_id, uint64_t pd_addr);
1832
1833         /* testing functions */
1834         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1835         int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1836         bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1837
1838         /* deprecated */
1839         void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 };
1841
1842 /*
1843  * ASIC specific functions.
1844  */
1845 struct radeon_asic {
1846         int (*init)(struct radeon_device *rdev);
1847         void (*fini)(struct radeon_device *rdev);
1848         int (*resume)(struct radeon_device *rdev);
1849         int (*suspend)(struct radeon_device *rdev);
1850         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1851         int (*asic_reset)(struct radeon_device *rdev);
1852         /* Flush the HDP cache via MMIO */
1853         void (*mmio_hdp_flush)(struct radeon_device *rdev);
1854         /* check if 3D engine is idle */
1855         bool (*gui_idle)(struct radeon_device *rdev);
1856         /* wait for mc_idle */
1857         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1858         /* get the reference clock */
1859         u32 (*get_xclk)(struct radeon_device *rdev);
1860         /* get the gpu clock counter */
1861         uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1862         /* get register for info ioctl */
1863         int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1864         /* gart */
1865         struct {
1866                 void (*tlb_flush)(struct radeon_device *rdev);
1867                 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1868                 void (*set_page)(struct radeon_device *rdev, unsigned i,
1869                                  uint64_t entry);
1870         } gart;
1871         struct {
1872                 int (*init)(struct radeon_device *rdev);
1873                 void (*fini)(struct radeon_device *rdev);
1874                 void (*copy_pages)(struct radeon_device *rdev,
1875                                    struct radeon_ib *ib,
1876                                    uint64_t pe, uint64_t src,
1877                                    unsigned count);
1878                 void (*write_pages)(struct radeon_device *rdev,
1879                                     struct radeon_ib *ib,
1880                                     uint64_t pe,
1881                                     uint64_t addr, unsigned count,
1882                                     uint32_t incr, uint32_t flags);
1883                 void (*set_pages)(struct radeon_device *rdev,
1884                                   struct radeon_ib *ib,
1885                                   uint64_t pe,
1886                                   uint64_t addr, unsigned count,
1887                                   uint32_t incr, uint32_t flags);
1888                 void (*pad_ib)(struct radeon_ib *ib);
1889         } vm;
1890         /* ring specific callbacks */
1891         struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1892         /* irqs */
1893         struct {
1894                 int (*set)(struct radeon_device *rdev);
1895                 int (*process)(struct radeon_device *rdev);
1896         } irq;
1897         /* displays */
1898         struct {
1899                 /* display watermarks */
1900                 void (*bandwidth_update)(struct radeon_device *rdev);
1901                 /* get frame count */
1902                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1903                 /* wait for vblank */
1904                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1905                 /* set backlight level */
1906                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1907                 /* get backlight level */
1908                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1909                 /* audio callbacks */
1910                 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1911                 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1912         } display;
1913         /* copy functions for bo handling */
1914         struct {
1915                 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1916                                              uint64_t src_offset,
1917                                              uint64_t dst_offset,
1918                                              unsigned num_gpu_pages,
1919                                              struct reservation_object *resv);
1920                 u32 blit_ring_index;
1921                 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1922                                             uint64_t src_offset,
1923                                             uint64_t dst_offset,
1924                                             unsigned num_gpu_pages,
1925                                             struct reservation_object *resv);
1926                 u32 dma_ring_index;
1927                 /* method used for bo copy */
1928                 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1929                                              uint64_t src_offset,
1930                                              uint64_t dst_offset,
1931                                              unsigned num_gpu_pages,
1932                                              struct reservation_object *resv);
1933                 /* ring used for bo copies */
1934                 u32 copy_ring_index;
1935         } copy;
1936         /* surfaces */
1937         struct {
1938                 int (*set_reg)(struct radeon_device *rdev, int reg,
1939                                        uint32_t tiling_flags, uint32_t pitch,
1940                                        uint32_t offset, uint32_t obj_size);
1941                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1942         } surface;
1943         /* hotplug detect */
1944         struct {
1945                 void (*init)(struct radeon_device *rdev);
1946                 void (*fini)(struct radeon_device *rdev);
1947                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1948                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1949         } hpd;
1950         /* static power management */
1951         struct {
1952                 void (*misc)(struct radeon_device *rdev);
1953                 void (*prepare)(struct radeon_device *rdev);
1954                 void (*finish)(struct radeon_device *rdev);
1955                 void (*init_profile)(struct radeon_device *rdev);
1956                 void (*get_dynpm_state)(struct radeon_device *rdev);
1957                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1958                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1959                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1960                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1961                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1962                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1963                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1964                 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1965                 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1966                 int (*get_temperature)(struct radeon_device *rdev);
1967         } pm;
1968         /* dynamic power management */
1969         struct {
1970                 int (*init)(struct radeon_device *rdev);
1971                 void (*setup_asic)(struct radeon_device *rdev);
1972                 int (*enable)(struct radeon_device *rdev);
1973                 int (*late_enable)(struct radeon_device *rdev);
1974                 void (*disable)(struct radeon_device *rdev);
1975                 int (*pre_set_power_state)(struct radeon_device *rdev);
1976                 int (*set_power_state)(struct radeon_device *rdev);
1977                 void (*post_set_power_state)(struct radeon_device *rdev);
1978                 void (*display_configuration_changed)(struct radeon_device *rdev);
1979                 void (*fini)(struct radeon_device *rdev);
1980                 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1981                 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1982                 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1983                 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1984                 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1985                 bool (*vblank_too_short)(struct radeon_device *rdev);
1986                 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1987                 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1988                 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1989                 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1990                 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1991                 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1992                 u32 (*get_current_sclk)(struct radeon_device *rdev);
1993                 u32 (*get_current_mclk)(struct radeon_device *rdev);
1994         } dpm;
1995         /* pageflipping */
1996         struct {
1997                 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1998                 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1999         } pflip;
2000 };
2001
2002 /*
2003  * Asic structures
2004  */
2005 struct r100_asic {
2006         const unsigned          *reg_safe_bm;
2007         unsigned                reg_safe_bm_size;
2008         u32                     hdp_cntl;
2009 };
2010
2011 struct r300_asic {
2012         const unsigned          *reg_safe_bm;
2013         unsigned                reg_safe_bm_size;
2014         u32                     resync_scratch;
2015         u32                     hdp_cntl;
2016 };
2017
2018 struct r600_asic {
2019         unsigned                max_pipes;
2020         unsigned                max_tile_pipes;
2021         unsigned                max_simds;
2022         unsigned                max_backends;
2023         unsigned                max_gprs;
2024         unsigned                max_threads;
2025         unsigned                max_stack_entries;
2026         unsigned                max_hw_contexts;
2027         unsigned                max_gs_threads;
2028         unsigned                sx_max_export_size;
2029         unsigned                sx_max_export_pos_size;
2030         unsigned                sx_max_export_smx_size;
2031         unsigned                sq_num_cf_insts;
2032         unsigned                tiling_nbanks;
2033         unsigned                tiling_npipes;
2034         unsigned                tiling_group_size;
2035         unsigned                tile_config;
2036         unsigned                backend_map;
2037         unsigned                active_simds;
2038 };
2039
2040 struct rv770_asic {
2041         unsigned                max_pipes;
2042         unsigned                max_tile_pipes;
2043         unsigned                max_simds;
2044         unsigned                max_backends;
2045         unsigned                max_gprs;
2046         unsigned                max_threads;
2047         unsigned                max_stack_entries;
2048         unsigned                max_hw_contexts;
2049         unsigned                max_gs_threads;
2050         unsigned                sx_max_export_size;
2051         unsigned                sx_max_export_pos_size;
2052         unsigned                sx_max_export_smx_size;
2053         unsigned                sq_num_cf_insts;
2054         unsigned                sx_num_of_sets;
2055         unsigned                sc_prim_fifo_size;
2056         unsigned                sc_hiz_tile_fifo_size;
2057         unsigned                sc_earlyz_tile_fifo_fize;
2058         unsigned                tiling_nbanks;
2059         unsigned                tiling_npipes;
2060         unsigned                tiling_group_size;
2061         unsigned                tile_config;
2062         unsigned                backend_map;
2063         unsigned                active_simds;
2064 };
2065
2066 struct evergreen_asic {
2067         unsigned num_ses;
2068         unsigned max_pipes;
2069         unsigned max_tile_pipes;
2070         unsigned max_simds;
2071         unsigned max_backends;
2072         unsigned max_gprs;
2073         unsigned max_threads;
2074         unsigned max_stack_entries;
2075         unsigned max_hw_contexts;
2076         unsigned max_gs_threads;
2077         unsigned sx_max_export_size;
2078         unsigned sx_max_export_pos_size;
2079         unsigned sx_max_export_smx_size;
2080         unsigned sq_num_cf_insts;
2081         unsigned sx_num_of_sets;
2082         unsigned sc_prim_fifo_size;
2083         unsigned sc_hiz_tile_fifo_size;
2084         unsigned sc_earlyz_tile_fifo_size;
2085         unsigned tiling_nbanks;
2086         unsigned tiling_npipes;
2087         unsigned tiling_group_size;
2088         unsigned tile_config;
2089         unsigned backend_map;
2090         unsigned active_simds;
2091 };
2092
2093 struct cayman_asic {
2094         unsigned max_shader_engines;
2095         unsigned max_pipes_per_simd;
2096         unsigned max_tile_pipes;
2097         unsigned max_simds_per_se;
2098         unsigned max_backends_per_se;
2099         unsigned max_texture_channel_caches;
2100         unsigned max_gprs;
2101         unsigned max_threads;
2102         unsigned max_gs_threads;
2103         unsigned max_stack_entries;
2104         unsigned sx_num_of_sets;
2105         unsigned sx_max_export_size;
2106         unsigned sx_max_export_pos_size;
2107         unsigned sx_max_export_smx_size;
2108         unsigned max_hw_contexts;
2109         unsigned sq_num_cf_insts;
2110         unsigned sc_prim_fifo_size;
2111         unsigned sc_hiz_tile_fifo_size;
2112         unsigned sc_earlyz_tile_fifo_size;
2113
2114         unsigned num_shader_engines;
2115         unsigned num_shader_pipes_per_simd;
2116         unsigned num_tile_pipes;
2117         unsigned num_simds_per_se;
2118         unsigned num_backends_per_se;
2119         unsigned backend_disable_mask_per_asic;
2120         unsigned backend_map;
2121         unsigned num_texture_channel_caches;
2122         unsigned mem_max_burst_length_bytes;
2123         unsigned mem_row_size_in_kb;
2124         unsigned shader_engine_tile_size;
2125         unsigned num_gpus;
2126         unsigned multi_gpu_tile_size;
2127
2128         unsigned tile_config;
2129         unsigned active_simds;
2130 };
2131
2132 struct si_asic {
2133         unsigned max_shader_engines;
2134         unsigned max_tile_pipes;
2135         unsigned max_cu_per_sh;
2136         unsigned max_sh_per_se;
2137         unsigned max_backends_per_se;
2138         unsigned max_texture_channel_caches;
2139         unsigned max_gprs;
2140         unsigned max_gs_threads;
2141         unsigned max_hw_contexts;
2142         unsigned sc_prim_fifo_size_frontend;
2143         unsigned sc_prim_fifo_size_backend;
2144         unsigned sc_hiz_tile_fifo_size;
2145         unsigned sc_earlyz_tile_fifo_size;
2146
2147         unsigned num_tile_pipes;
2148         unsigned backend_enable_mask;
2149         unsigned backend_disable_mask_per_asic;
2150         unsigned backend_map;
2151         unsigned num_texture_channel_caches;
2152         unsigned mem_max_burst_length_bytes;
2153         unsigned mem_row_size_in_kb;
2154         unsigned shader_engine_tile_size;
2155         unsigned num_gpus;
2156         unsigned multi_gpu_tile_size;
2157
2158         unsigned tile_config;
2159         uint32_t tile_mode_array[32];
2160         uint32_t active_cus;
2161 };
2162
2163 struct cik_asic {
2164         unsigned max_shader_engines;
2165         unsigned max_tile_pipes;
2166         unsigned max_cu_per_sh;
2167         unsigned max_sh_per_se;
2168         unsigned max_backends_per_se;
2169         unsigned max_texture_channel_caches;
2170         unsigned max_gprs;
2171         unsigned max_gs_threads;
2172         unsigned max_hw_contexts;
2173         unsigned sc_prim_fifo_size_frontend;
2174         unsigned sc_prim_fifo_size_backend;
2175         unsigned sc_hiz_tile_fifo_size;
2176         unsigned sc_earlyz_tile_fifo_size;
2177
2178         unsigned num_tile_pipes;
2179         unsigned backend_enable_mask;
2180         unsigned backend_disable_mask_per_asic;
2181         unsigned backend_map;
2182         unsigned num_texture_channel_caches;
2183         unsigned mem_max_burst_length_bytes;
2184         unsigned mem_row_size_in_kb;
2185         unsigned shader_engine_tile_size;
2186         unsigned num_gpus;
2187         unsigned multi_gpu_tile_size;
2188
2189         unsigned tile_config;
2190         uint32_t tile_mode_array[32];
2191         uint32_t macrotile_mode_array[16];
2192         uint32_t active_cus;
2193 };
2194
2195 union radeon_asic_config {
2196         struct r300_asic        r300;
2197         struct r100_asic        r100;
2198         struct r600_asic        r600;
2199         struct rv770_asic       rv770;
2200         struct evergreen_asic   evergreen;
2201         struct cayman_asic      cayman;
2202         struct si_asic          si;
2203         struct cik_asic         cik;
2204 };
2205
2206 /*
2207  * asic initizalization from radeon_asic.c
2208  */
2209 void radeon_agp_disable(struct radeon_device *rdev);
2210 int radeon_asic_init(struct radeon_device *rdev);
2211
2212
2213 /*
2214  * IOCTL.
2215  */
2216 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2217                           struct drm_file *filp);
2218 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2219                             struct drm_file *filp);
2220 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2221                              struct drm_file *filp);
2222 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2223                          struct drm_file *file_priv);
2224 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2225                            struct drm_file *file_priv);
2226 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2227                             struct drm_file *file_priv);
2228 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2229                            struct drm_file *file_priv);
2230 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2231                                 struct drm_file *filp);
2232 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2233                           struct drm_file *filp);
2234 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2235                           struct drm_file *filp);
2236 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2237                               struct drm_file *filp);
2238 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2239                           struct drm_file *filp);
2240 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2241                         struct drm_file *filp);
2242 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2243 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2244                                 struct drm_file *filp);
2245 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2246                                 struct drm_file *filp);
2247
2248 /* VRAM scratch page for HDP bug, default vram page */
2249 struct r600_vram_scratch {
2250         struct radeon_bo                *robj;
2251         volatile uint32_t               *ptr;
2252         u64                             gpu_addr;
2253 };
2254
2255 /*
2256  * ACPI
2257  */
2258 struct radeon_atif_notification_cfg {
2259         bool enabled;
2260         int command_code;
2261 };
2262
2263 struct radeon_atif_notifications {
2264         bool display_switch;
2265         bool expansion_mode_change;
2266         bool thermal_state;
2267         bool forced_power_state;
2268         bool system_power_state;
2269         bool display_conf_change;
2270         bool px_gfx_switch;
2271         bool brightness_change;
2272         bool dgpu_display_event;
2273 };
2274
2275 struct radeon_atif_functions {
2276         bool system_params;
2277         bool sbios_requests;
2278         bool select_active_disp;
2279         bool lid_state;
2280         bool get_tv_standard;
2281         bool set_tv_standard;
2282         bool get_panel_expansion_mode;
2283         bool set_panel_expansion_mode;
2284         bool temperature_change;
2285         bool graphics_device_types;
2286 };
2287
2288 struct radeon_atif {
2289         struct radeon_atif_notifications notifications;
2290         struct radeon_atif_functions functions;
2291         struct radeon_atif_notification_cfg notification_cfg;
2292         struct radeon_encoder *encoder_for_bl;
2293 };
2294
2295 struct radeon_atcs_functions {
2296         bool get_ext_state;
2297         bool pcie_perf_req;
2298         bool pcie_dev_rdy;
2299         bool pcie_bus_width;
2300 };
2301
2302 struct radeon_atcs {
2303         struct radeon_atcs_functions functions;
2304 };
2305
2306 /*
2307  * Core structure, functions and helpers.
2308  */
2309 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2310 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2311
2312 struct radeon_device {
2313         struct device                   *dev;
2314         struct drm_device               *ddev;
2315         struct pci_dev                  *pdev;
2316         struct rw_semaphore             exclusive_lock;
2317         /* ASIC */
2318         union radeon_asic_config        config;
2319         enum radeon_family              family;
2320         unsigned long                   flags;
2321         int                             usec_timeout;
2322         enum radeon_pll_errata          pll_errata;
2323         int                             num_gb_pipes;
2324         int                             num_z_pipes;
2325         int                             disp_priority;
2326         /* BIOS */
2327         uint8_t                         *bios;
2328         bool                            is_atom_bios;
2329         uint16_t                        bios_header_start;
2330         struct radeon_bo                *stollen_vga_memory;
2331         /* Register mmio */
2332         resource_size_t                 rmmio_base;
2333         resource_size_t                 rmmio_size;
2334         /* protects concurrent MM_INDEX/DATA based register access */
2335         spinlock_t mmio_idx_lock;
2336         /* protects concurrent SMC based register access */
2337         spinlock_t smc_idx_lock;
2338         /* protects concurrent PLL register access */
2339         spinlock_t pll_idx_lock;
2340         /* protects concurrent MC register access */
2341         spinlock_t mc_idx_lock;
2342         /* protects concurrent PCIE register access */
2343         spinlock_t pcie_idx_lock;
2344         /* protects concurrent PCIE_PORT register access */
2345         spinlock_t pciep_idx_lock;
2346         /* protects concurrent PIF register access */
2347         spinlock_t pif_idx_lock;
2348         /* protects concurrent CG register access */
2349         spinlock_t cg_idx_lock;
2350         /* protects concurrent UVD register access */
2351         spinlock_t uvd_idx_lock;
2352         /* protects concurrent RCU register access */
2353         spinlock_t rcu_idx_lock;
2354         /* protects concurrent DIDT register access */
2355         spinlock_t didt_idx_lock;
2356         /* protects concurrent ENDPOINT (audio) register access */
2357         spinlock_t end_idx_lock;
2358         void __iomem                    *rmmio;
2359         radeon_rreg_t                   mc_rreg;
2360         radeon_wreg_t                   mc_wreg;
2361         radeon_rreg_t                   pll_rreg;
2362         radeon_wreg_t                   pll_wreg;
2363         uint32_t                        pcie_reg_mask;
2364         radeon_rreg_t                   pciep_rreg;
2365         radeon_wreg_t                   pciep_wreg;
2366         /* io port */
2367         void __iomem                    *rio_mem;
2368         resource_size_t                 rio_mem_size;
2369         struct radeon_clock             clock;
2370         struct radeon_mc                mc;
2371         struct radeon_gart              gart;
2372         struct radeon_mode_info         mode_info;
2373         struct radeon_scratch           scratch;
2374         struct radeon_doorbell          doorbell;
2375         struct radeon_mman              mman;
2376         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
2377         wait_queue_head_t               fence_queue;
2378         unsigned                        fence_context;
2379         struct mutex                    ring_lock;
2380         struct radeon_ring              ring[RADEON_NUM_RINGS];
2381         bool                            ib_pool_ready;
2382         struct radeon_sa_manager        ring_tmp_bo;
2383         struct radeon_irq               irq;
2384         struct radeon_asic              *asic;
2385         struct radeon_gem               gem;
2386         struct radeon_pm                pm;
2387         struct radeon_uvd               uvd;
2388         struct radeon_vce               vce;
2389         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2390         struct radeon_wb                wb;
2391         struct radeon_dummy_page        dummy_page;
2392         bool                            shutdown;
2393         bool                            suspend;
2394         bool                            need_dma32;
2395         bool                            accel_working;
2396         bool                            fastfb_working; /* IGP feature*/
2397         bool                            needs_reset, in_reset;
2398         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2399         const struct firmware *me_fw;   /* all family ME firmware */
2400         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
2401         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
2402         const struct firmware *mc_fw;   /* NI MC firmware */
2403         const struct firmware *ce_fw;   /* SI CE firmware */
2404         const struct firmware *mec_fw;  /* CIK MEC firmware */
2405         const struct firmware *mec2_fw; /* KV MEC2 firmware */
2406         const struct firmware *sdma_fw; /* CIK SDMA firmware */
2407         const struct firmware *smc_fw;  /* SMC firmware */
2408         const struct firmware *uvd_fw;  /* UVD firmware */
2409         const struct firmware *vce_fw;  /* VCE firmware */
2410         bool new_fw;
2411         struct r600_vram_scratch vram_scratch;
2412         int msi_enabled; /* msi enabled */
2413         struct r600_ih ih; /* r6/700 interrupt ring */
2414         struct radeon_rlc rlc;
2415         struct radeon_mec mec;
2416         struct work_struct hotplug_work;
2417         struct work_struct dp_work;
2418         struct work_struct audio_work;
2419         int num_crtc; /* number of crtcs */
2420         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2421         bool has_uvd;
2422         struct r600_audio audio; /* audio stuff */
2423         struct notifier_block acpi_nb;
2424         /* only one userspace can use Hyperz features or CMASK at a time */
2425         struct drm_file *hyperz_filp;
2426         struct drm_file *cmask_filp;
2427         /* i2c buses */
2428         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2429         /* debugfs */
2430         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2431         unsigned                debugfs_count;
2432         /* virtual memory */
2433         struct radeon_vm_manager        vm_manager;
2434         struct mutex                    gpu_clock_mutex;
2435         /* memory stats */
2436         atomic64_t                      vram_usage;
2437         atomic64_t                      gtt_usage;
2438         atomic64_t                      num_bytes_moved;
2439         /* ACPI interface */
2440         struct radeon_atif              atif;
2441         struct radeon_atcs              atcs;
2442         /* srbm instance registers */
2443         struct mutex                    srbm_mutex;
2444         /* GRBM index mutex. Protects concurrents access to GRBM index */
2445         struct mutex                    grbm_idx_mutex;
2446         /* clock, powergating flags */
2447         u32 cg_flags;
2448         u32 pg_flags;
2449
2450         struct dev_pm_domain vga_pm_domain;
2451         bool have_disp_power_ref;
2452         u32 px_quirk_flags;
2453
2454         /* tracking pinned memory */
2455         u64 vram_pin_size;
2456         u64 gart_pin_size;
2457
2458         /* amdkfd interface */
2459         struct kfd_dev          *kfd;
2460         struct radeon_sa_manager        kfd_bo;
2461
2462         struct mutex    mn_lock;
2463         DECLARE_HASHTABLE(mn_hash, 7);
2464 };
2465
2466 bool radeon_is_px(struct drm_device *dev);
2467 int radeon_device_init(struct radeon_device *rdev,
2468                        struct drm_device *ddev,
2469                        struct pci_dev *pdev,
2470                        uint32_t flags);
2471 void radeon_device_fini(struct radeon_device *rdev);
2472 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2473
2474 #define RADEON_MIN_MMIO_SIZE 0x10000
2475
2476 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2477                                     bool always_indirect)
2478 {
2479         /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2480         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2481                 return readl(((void __iomem *)rdev->rmmio) + reg);
2482         else {
2483                 unsigned long flags;
2484                 uint32_t ret;
2485
2486                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2487                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2488                 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2489                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2490
2491                 return ret;
2492         }
2493 }
2494
2495 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2496                                 bool always_indirect)
2497 {
2498         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2499                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2500         else {
2501                 unsigned long flags;
2502
2503                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2504                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2505                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2506                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2507         }
2508 }
2509
2510 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2511 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2512
2513 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2514 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2515
2516 /*
2517  * Cast helper
2518  */
2519 extern const struct fence_ops radeon_fence_ops;
2520
2521 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2522 {
2523         struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2524
2525         if (__f->base.ops == &radeon_fence_ops)
2526                 return __f;
2527
2528         return NULL;
2529 }
2530
2531 /*
2532  * Registers read & write functions.
2533  */
2534 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2535 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2536 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2537 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2538 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2539 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2540 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2541 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2542 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2543 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2544 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2545 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2546 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2547 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2548 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2549 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2550 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2551 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2552 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2553 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2554 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2555 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2556 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2557 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2558 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2559 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2560 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2561 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2562 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2563 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2564 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2565 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2566 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2567 #define WREG32_P(reg, val, mask)                                \
2568         do {                                                    \
2569                 uint32_t tmp_ = RREG32(reg);                    \
2570                 tmp_ &= (mask);                                 \
2571                 tmp_ |= ((val) & ~(mask));                      \
2572                 WREG32(reg, tmp_);                              \
2573         } while (0)
2574 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2575 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2576 #define WREG32_PLL_P(reg, val, mask)                            \
2577         do {                                                    \
2578                 uint32_t tmp_ = RREG32_PLL(reg);                \
2579                 tmp_ &= (mask);                                 \
2580                 tmp_ |= ((val) & ~(mask));                      \
2581                 WREG32_PLL(reg, tmp_);                          \
2582         } while (0)
2583 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2584 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2585 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2586
2587 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2588 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2589
2590 /*
2591  * Indirect registers accessor
2592  */
2593 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2594 {
2595         unsigned long flags;
2596         uint32_t r;
2597
2598         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2599         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2600         r = RREG32(RADEON_PCIE_DATA);
2601         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2602         return r;
2603 }
2604
2605 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2606 {
2607         unsigned long flags;
2608
2609         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2610         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2611         WREG32(RADEON_PCIE_DATA, (v));
2612         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2613 }
2614
2615 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2616 {
2617         unsigned long flags;
2618         u32 r;
2619
2620         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2621         WREG32(TN_SMC_IND_INDEX_0, (reg));
2622         r = RREG32(TN_SMC_IND_DATA_0);
2623         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2624         return r;
2625 }
2626
2627 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2628 {
2629         unsigned long flags;
2630
2631         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2632         WREG32(TN_SMC_IND_INDEX_0, (reg));
2633         WREG32(TN_SMC_IND_DATA_0, (v));
2634         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2635 }
2636
2637 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2638 {
2639         unsigned long flags;
2640         u32 r;
2641
2642         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2643         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2644         r = RREG32(R600_RCU_DATA);
2645         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2646         return r;
2647 }
2648
2649 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2650 {
2651         unsigned long flags;
2652
2653         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2654         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2655         WREG32(R600_RCU_DATA, (v));
2656         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2657 }
2658
2659 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2660 {
2661         unsigned long flags;
2662         u32 r;
2663
2664         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2665         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2666         r = RREG32(EVERGREEN_CG_IND_DATA);
2667         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2668         return r;
2669 }
2670
2671 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2672 {
2673         unsigned long flags;
2674
2675         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2676         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2677         WREG32(EVERGREEN_CG_IND_DATA, (v));
2678         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2679 }
2680
2681 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2682 {
2683         unsigned long flags;
2684         u32 r;
2685
2686         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2687         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2688         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2689         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2690         return r;
2691 }
2692
2693 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2694 {
2695         unsigned long flags;
2696
2697         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2698         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2699         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2700         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2701 }
2702
2703 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2704 {
2705         unsigned long flags;
2706         u32 r;
2707
2708         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2709         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2710         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2711         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2712         return r;
2713 }
2714
2715 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2716 {
2717         unsigned long flags;
2718
2719         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2720         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2721         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2722         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2723 }
2724
2725 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2726 {
2727         unsigned long flags;
2728         u32 r;
2729
2730         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2731         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2732         r = RREG32(R600_UVD_CTX_DATA);
2733         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2734         return r;
2735 }
2736
2737 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2738 {
2739         unsigned long flags;
2740
2741         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2742         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2743         WREG32(R600_UVD_CTX_DATA, (v));
2744         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2745 }
2746
2747
2748 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2749 {
2750         unsigned long flags;
2751         u32 r;
2752
2753         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2754         WREG32(CIK_DIDT_IND_INDEX, (reg));
2755         r = RREG32(CIK_DIDT_IND_DATA);
2756         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2757         return r;
2758 }
2759
2760 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2761 {
2762         unsigned long flags;
2763
2764         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2765         WREG32(CIK_DIDT_IND_INDEX, (reg));
2766         WREG32(CIK_DIDT_IND_DATA, (v));
2767         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2768 }
2769
2770 void r100_pll_errata_after_index(struct radeon_device *rdev);
2771
2772
2773 /*
2774  * ASICs helpers.
2775  */
2776 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2777                             (rdev->pdev->device == 0x5969))
2778 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2779                 (rdev->family == CHIP_RV200) || \
2780                 (rdev->family == CHIP_RS100) || \
2781                 (rdev->family == CHIP_RS200) || \
2782                 (rdev->family == CHIP_RV250) || \
2783                 (rdev->family == CHIP_RV280) || \
2784                 (rdev->family == CHIP_RS300))
2785 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
2786                 (rdev->family == CHIP_RV350) ||                 \
2787                 (rdev->family == CHIP_R350)  ||                 \
2788                 (rdev->family == CHIP_RV380) ||                 \
2789                 (rdev->family == CHIP_R420)  ||                 \
2790                 (rdev->family == CHIP_R423)  ||                 \
2791                 (rdev->family == CHIP_RV410) ||                 \
2792                 (rdev->family == CHIP_RS400) ||                 \
2793                 (rdev->family == CHIP_RS480))
2794 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2795                 (rdev->ddev->pdev->device == 0x9443) || \
2796                 (rdev->ddev->pdev->device == 0x944B) || \
2797                 (rdev->ddev->pdev->device == 0x9506) || \
2798                 (rdev->ddev->pdev->device == 0x9509) || \
2799                 (rdev->ddev->pdev->device == 0x950F) || \
2800                 (rdev->ddev->pdev->device == 0x689C) || \
2801                 (rdev->ddev->pdev->device == 0x689D))
2802 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2803 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
2804                             (rdev->family == CHIP_RS690)  ||    \
2805                             (rdev->family == CHIP_RS740)  ||    \
2806                             (rdev->family >= CHIP_R600))
2807 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2808 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2809 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2810 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2811                              (rdev->flags & RADEON_IS_IGP))
2812 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2813 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2814 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2815                              (rdev->flags & RADEON_IS_IGP))
2816 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2817 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2818 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2819 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2820 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2821 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2822                              (rdev->family == CHIP_MULLINS))
2823
2824 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2825                               (rdev->ddev->pdev->device == 0x6850) || \
2826                               (rdev->ddev->pdev->device == 0x6858) || \
2827                               (rdev->ddev->pdev->device == 0x6859) || \
2828                               (rdev->ddev->pdev->device == 0x6840) || \
2829                               (rdev->ddev->pdev->device == 0x6841) || \
2830                               (rdev->ddev->pdev->device == 0x6842) || \
2831                               (rdev->ddev->pdev->device == 0x6843))
2832
2833 /*
2834  * BIOS helpers.
2835  */
2836 #define RBIOS8(i) (rdev->bios[i])
2837 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2838 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2839
2840 int radeon_combios_init(struct radeon_device *rdev);
2841 void radeon_combios_fini(struct radeon_device *rdev);
2842 int radeon_atombios_init(struct radeon_device *rdev);
2843 void radeon_atombios_fini(struct radeon_device *rdev);
2844
2845
2846 /*
2847  * RING helpers.
2848  */
2849
2850 /**
2851  * radeon_ring_write - write a value to the ring
2852  *
2853  * @ring: radeon_ring structure holding ring information
2854  * @v: dword (dw) value to write
2855  *
2856  * Write a value to the requested ring buffer (all asics).
2857  */
2858 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2859 {
2860         if (ring->count_dw <= 0)
2861                 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2862
2863         ring->ring[ring->wptr++] = v;
2864         ring->wptr &= ring->ptr_mask;
2865         ring->count_dw--;
2866         ring->ring_free_dw--;
2867 }
2868
2869 /*
2870  * ASICs macro.
2871  */
2872 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2873 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2874 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2875 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2876 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2877 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2878 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2879 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2880 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2881 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2882 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2883 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2884 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2885 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2886 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2887 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2888 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2889 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2890 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2891 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2892 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2893 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2894 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2895 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2896 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2897 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2898 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2899 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2900 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2901 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2902 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2903 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2904 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2905 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2906 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2907 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2908 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2909 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2910 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2911 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2912 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2913 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2914 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2915 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2916 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2917 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2918 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2919 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2920 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2921 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2922 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2923 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2924 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2925 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2926 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2927 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2928 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2929 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2930 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2931 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2932 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2933 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2934 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2935 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2936 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2937 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2938 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2939 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2940 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2941 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2942 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2943 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2944 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2945 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2946 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2947 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2948 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2949 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2950 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2951 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2952 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2953 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2954 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2955 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2956 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2957 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2958 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2959 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2960 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2961 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2962 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2963
2964 /* Common functions */
2965 /* AGP */
2966 extern int radeon_gpu_reset(struct radeon_device *rdev);
2967 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2968 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2969 extern void radeon_agp_disable(struct radeon_device *rdev);
2970 extern int radeon_modeset_init(struct radeon_device *rdev);
2971 extern void radeon_modeset_fini(struct radeon_device *rdev);
2972 extern bool radeon_card_posted(struct radeon_device *rdev);
2973 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2974 extern void radeon_update_display_priority(struct radeon_device *rdev);
2975 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2976 extern void radeon_scratch_init(struct radeon_device *rdev);
2977 extern void radeon_wb_fini(struct radeon_device *rdev);
2978 extern int radeon_wb_init(struct radeon_device *rdev);
2979 extern void radeon_wb_disable(struct radeon_device *rdev);
2980 extern void radeon_surface_init(struct radeon_device *rdev);
2981 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2982 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2983 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2984 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2985 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2986 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2987                                      uint32_t flags);
2988 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2989 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2990 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2991 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2992 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2993 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2994 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2995 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2996                                              const u32 *registers,
2997                                              const u32 array_size);
2998
2999 /*
3000  * vm
3001  */
3002 int radeon_vm_manager_init(struct radeon_device *rdev);
3003 void radeon_vm_manager_fini(struct radeon_device *rdev);
3004 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
3005 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
3006 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
3007                                           struct radeon_vm *vm,
3008                                           struct list_head *head);
3009 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
3010                                        struct radeon_vm *vm, int ring);
3011 void radeon_vm_flush(struct radeon_device *rdev,
3012                      struct radeon_vm *vm,
3013                      int ring, struct radeon_fence *fence);
3014 void radeon_vm_fence(struct radeon_device *rdev,
3015                      struct radeon_vm *vm,
3016                      struct radeon_fence *fence);
3017 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
3018 int radeon_vm_update_page_directory(struct radeon_device *rdev,
3019                                     struct radeon_vm *vm);
3020 int radeon_vm_clear_freed(struct radeon_device *rdev,
3021                           struct radeon_vm *vm);
3022 int radeon_vm_clear_invalids(struct radeon_device *rdev,
3023                              struct radeon_vm *vm);
3024 int radeon_vm_bo_update(struct radeon_device *rdev,
3025                         struct radeon_bo_va *bo_va,
3026                         struct ttm_mem_reg *mem);
3027 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
3028                              struct radeon_bo *bo);
3029 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
3030                                        struct radeon_bo *bo);
3031 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
3032                                       struct radeon_vm *vm,
3033                                       struct radeon_bo *bo);
3034 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3035                           struct radeon_bo_va *bo_va,
3036                           uint64_t offset,
3037                           uint32_t flags);
3038 void radeon_vm_bo_rmv(struct radeon_device *rdev,
3039                       struct radeon_bo_va *bo_va);
3040
3041 /* audio */
3042 void r600_audio_update_hdmi(struct work_struct *work);
3043 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3044 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
3045 void r600_audio_enable(struct radeon_device *rdev,
3046                        struct r600_audio_pin *pin,
3047                        u8 enable_mask);
3048 void dce6_audio_enable(struct radeon_device *rdev,
3049                        struct r600_audio_pin *pin,
3050                        u8 enable_mask);
3051
3052 /*
3053  * R600 vram scratch functions
3054  */
3055 int r600_vram_scratch_init(struct radeon_device *rdev);
3056 void r600_vram_scratch_fini(struct radeon_device *rdev);
3057
3058 /*
3059  * r600 cs checking helper
3060  */
3061 unsigned r600_mip_minify(unsigned size, unsigned level);
3062 bool r600_fmt_is_valid_color(u32 format);
3063 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3064 int r600_fmt_get_blocksize(u32 format);
3065 int r600_fmt_get_nblocksx(u32 format, u32 w);
3066 int r600_fmt_get_nblocksy(u32 format, u32 h);
3067
3068 /*
3069  * r600 functions used by radeon_encoder.c
3070  */
3071 struct radeon_hdmi_acr {
3072         u32 clock;
3073
3074         int n_32khz;
3075         int cts_32khz;
3076
3077         int n_44_1khz;
3078         int cts_44_1khz;
3079
3080         int n_48khz;
3081         int cts_48khz;
3082
3083 };
3084
3085 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3086
3087 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3088                                      u32 tiling_pipe_num,
3089                                      u32 max_rb_num,
3090                                      u32 total_max_rb_num,
3091                                      u32 enabled_rb_mask);
3092
3093 /*
3094  * evergreen functions used by radeon_encoder.c
3095  */
3096
3097 extern int ni_init_microcode(struct radeon_device *rdev);
3098 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3099
3100 /* radeon_acpi.c */
3101 #if defined(CONFIG_ACPI)
3102 extern int radeon_acpi_init(struct radeon_device *rdev);
3103 extern void radeon_acpi_fini(struct radeon_device *rdev);
3104 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3105 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3106                                                 u8 perf_req, bool advertise);
3107 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3108 #else
3109 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3110 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3111 #endif
3112
3113 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3114                            struct radeon_cs_packet *pkt,
3115                            unsigned idx);
3116 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3117 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3118                            struct radeon_cs_packet *pkt);
3119 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3120                                 struct radeon_bo_list **cs_reloc,
3121                                 int nomm);
3122 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3123                                uint32_t *vline_start_end,
3124                                uint32_t *vline_status);
3125
3126 #include "radeon_object.h"
3127
3128 #endif