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Linux 4.1.16
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob8f285244c839a8c85ad186a1b877f94749776a58
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 extern void
34 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
35 uint32_t supported_device, u16 caps);
36
37 /* from radeon_legacy_encoder.c */
38 extern void
39 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42 union atom_supported_devices {
43 struct _ATOM_SUPPORTED_DEVICES_INFO info;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46 };
47
48 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
49 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 u8 index)
51 {
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
59 gpio->ucClkMaskShift = 0x19;
60 gpio->ucDataMaskShift = 0x18;
61 }
62 }
63
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev)) {
66 if ((index == 7) &&
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
68 (gpio->sucI2cId.ucAccess == 0)) {
69 gpio->sucI2cId.ucAccess = 0x97;
70 gpio->ucDataMaskShift = 8;
71 gpio->ucDataEnShift = 8;
72 gpio->ucDataY_Shift = 8;
73 gpio->ucDataA_Shift = 8;
74 }
75 }
76
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev)) {
79 if ((index == 4) &&
80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
81 (gpio->sucI2cId.ucAccess == 0x94))
82 gpio->sucI2cId.ucAccess = 0x14;
83 }
84 }
85
86 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
87 {
88 struct radeon_i2c_bus_rec i2c;
89
90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
91
92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
103 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
108
109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
110 i2c.hw_capable = true;
111 else
112 i2c.hw_capable = false;
113
114 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.mm_i2c = true;
116 else
117 i2c.mm_i2c = false;
118
119 i2c.i2c_id = gpio->sucI2cId.ucAccess;
120
121 if (i2c.mask_clk_reg)
122 i2c.valid = true;
123 else
124 i2c.valid = false;
125
126 return i2c;
127 }
128
129 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 uint8_t id)
131 {
132 struct atom_context *ctx = rdev->mode_info.atom_context;
133 ATOM_GPIO_I2C_ASSIGMENT *gpio;
134 struct radeon_i2c_bus_rec i2c;
135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
136 struct _ATOM_GPIO_I2C_INFO *i2c_info;
137 uint16_t data_offset, size;
138 int i, num_indices;
139
140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 i2c.valid = false;
142
143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
145
146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
148
149 gpio = &i2c_info->asGPIO_Info[0];
150 for (i = 0; i < num_indices; i++) {
151
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
153
154 if (gpio->sucI2cId.ucAccess == id) {
155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 break;
157 }
158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
160 }
161 }
162
163 return i2c;
164 }
165
166 void radeon_atombios_i2c_init(struct radeon_device *rdev)
167 {
168 struct atom_context *ctx = rdev->mode_info.atom_context;
169 ATOM_GPIO_I2C_ASSIGMENT *gpio;
170 struct radeon_i2c_bus_rec i2c;
171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
172 struct _ATOM_GPIO_I2C_INFO *i2c_info;
173 uint16_t data_offset, size;
174 int i, num_indices;
175 char stmp[32];
176
177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
179
180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
181 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
182
183 gpio = &i2c_info->asGPIO_Info[0];
184 for (i = 0; i < num_indices; i++) {
185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
186
187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
188
189 if (i2c.valid) {
190 sprintf(stmp, "0x%x", i2c.i2c_id);
191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
192 }
193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
195 }
196 }
197 }
198
199 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
200 u8 id)
201 {
202 struct atom_context *ctx = rdev->mode_info.atom_context;
203 struct radeon_gpio_rec gpio;
204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
205 struct _ATOM_GPIO_PIN_LUT *gpio_info;
206 ATOM_GPIO_PIN_ASSIGNMENT *pin;
207 u16 data_offset, size;
208 int i, num_indices;
209
210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
211 gpio.valid = false;
212
213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
215
216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
218
219 pin = gpio_info->asGPIO_Pin;
220 for (i = 0; i < num_indices; i++) {
221 if (id == pin->ucGPIO_ID) {
222 gpio.id = pin->ucGPIO_ID;
223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
224 gpio.shift = pin->ucGpioPinBitShift;
225 gpio.mask = (1 << pin->ucGpioPinBitShift);
226 gpio.valid = true;
227 break;
228 }
229 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
230 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
231 }
232 }
233
234 return gpio;
235 }
236
237 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
238 struct radeon_gpio_rec *gpio)
239 {
240 struct radeon_hpd hpd;
241 u32 reg;
242
243 memset(&hpd, 0, sizeof(struct radeon_hpd));
244
245 if (ASIC_IS_DCE6(rdev))
246 reg = SI_DC_GPIO_HPD_A;
247 else if (ASIC_IS_DCE4(rdev))
248 reg = EVERGREEN_DC_GPIO_HPD_A;
249 else
250 reg = AVIVO_DC_GPIO_HPD_A;
251
252 hpd.gpio = *gpio;
253 if (gpio->reg == reg) {
254 switch(gpio->mask) {
255 case (1 << 0):
256 hpd.hpd = RADEON_HPD_1;
257 break;
258 case (1 << 8):
259 hpd.hpd = RADEON_HPD_2;
260 break;
261 case (1 << 16):
262 hpd.hpd = RADEON_HPD_3;
263 break;
264 case (1 << 24):
265 hpd.hpd = RADEON_HPD_4;
266 break;
267 case (1 << 26):
268 hpd.hpd = RADEON_HPD_5;
269 break;
270 case (1 << 28):
271 hpd.hpd = RADEON_HPD_6;
272 break;
273 default:
274 hpd.hpd = RADEON_HPD_NONE;
275 break;
276 }
277 } else
278 hpd.hpd = RADEON_HPD_NONE;
279 return hpd;
280 }
281
282 static bool radeon_atom_apply_quirks(struct drm_device *dev,
283 uint32_t supported_device,
284 int *connector_type,
285 struct radeon_i2c_bus_rec *i2c_bus,
286 uint16_t *line_mux,
287 struct radeon_hpd *hpd)
288 {
289
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((dev->pdev->device == 0x791e) &&
292 (dev->pdev->subsystem_vendor == 0x1043) &&
293 (dev->pdev->subsystem_device == 0x826d)) {
294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
296 *connector_type = DRM_MODE_CONNECTOR_DVID;
297 }
298
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((dev->pdev->device == 0x7941) &&
301 (dev->pdev->subsystem_vendor == 0x1849) &&
302 (dev->pdev->subsystem_device == 0x7941)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((dev->pdev->device == 0x796e) &&
310 (dev->pdev->subsystem_vendor == 0x1462) &&
311 (dev->pdev->subsystem_device == 0x7302)) {
312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 return false;
315 }
316
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((dev->pdev->device == 0x7941) &&
319 (dev->pdev->subsystem_vendor == 0x147b) &&
320 (dev->pdev->subsystem_device == 0x2412)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
322 return false;
323 }
324
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((dev->pdev->device == 0x5653) &&
327 (dev->pdev->subsystem_vendor == 0x1462) &&
328 (dev->pdev->subsystem_device == 0x0291)) {
329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
330 i2c_bus->valid = false;
331 *line_mux = 53;
332 }
333 }
334
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((dev->pdev->device == 0x7146) &&
337 (dev->pdev->subsystem_vendor == 0x17af) &&
338 (dev->pdev->subsystem_device == 0x2058)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((dev->pdev->device == 0x7142) &&
345 (dev->pdev->subsystem_vendor == 0x1458) &&
346 (dev->pdev->subsystem_device == 0x2134)) {
347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
348 return false;
349 }
350
351
352 /* Funky macbooks */
353 if ((dev->pdev->device == 0x71C5) &&
354 (dev->pdev->subsystem_vendor == 0x106b) &&
355 (dev->pdev->subsystem_device == 0x0080)) {
356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 return false;
359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
360 *line_mux = 0x90;
361 }
362
363 /* mac rv630, rv730, others */
364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
368 }
369
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((dev->pdev->device == 0x9598) &&
372 (dev->pdev->subsystem_vendor == 0x1043) &&
373 (dev->pdev->subsystem_device == 0x01da)) {
374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
375 *connector_type = DRM_MODE_CONNECTOR_DVII;
376 }
377 }
378
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((dev->pdev->device == 0x9598) &&
381 (dev->pdev->subsystem_vendor == 0x1043) &&
382 (dev->pdev->subsystem_device == 0x01e4)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((dev->pdev->device == 0x95C5) &&
390 (dev->pdev->subsystem_vendor == 0x1043) &&
391 (dev->pdev->subsystem_device == 0x01e2)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
399 */
400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
402 *connector_type = DRM_MODE_CONNECTOR_VGA;
403 *line_mux = 0;
404 }
405 }
406
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
415 */
416 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
417 (dev->pdev->subsystem_vendor == 0x1025) &&
418 (dev->pdev->subsystem_device == 0x013c)) {
419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 return false;
424 }
425 }
426
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
429 */
430 if ((dev->pdev->device == 0x9498) &&
431 (dev->pdev->subsystem_vendor == 0x1682) &&
432 (dev->pdev->subsystem_device == 0x2452) &&
433 (i2c_bus->valid == false) &&
434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
435 struct radeon_device *rdev = dev->dev_private;
436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
437 }
438
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
441 (dev->pdev->subsystem_vendor == 0x1734) &&
442 (dev->pdev->subsystem_device == 0x11bd)) {
443 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
444 *connector_type = DRM_MODE_CONNECTOR_DVII;
445 *line_mux = 0x3103;
446 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
447 *connector_type = DRM_MODE_CONNECTOR_DVII;
448 }
449 }
450
451 /* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
452 if ((dev->pdev->device == 0x9805) &&
453 (dev->pdev->subsystem_vendor == 0x1734) &&
454 (dev->pdev->subsystem_device == 0x11bd)) {
455 if (*connector_type == DRM_MODE_CONNECTOR_VGA)
456 return false;
457 }
458
459 return true;
460 }
461
462 static const int supported_devices_connector_convert[] = {
463 DRM_MODE_CONNECTOR_Unknown,
464 DRM_MODE_CONNECTOR_VGA,
465 DRM_MODE_CONNECTOR_DVII,
466 DRM_MODE_CONNECTOR_DVID,
467 DRM_MODE_CONNECTOR_DVIA,
468 DRM_MODE_CONNECTOR_SVIDEO,
469 DRM_MODE_CONNECTOR_Composite,
470 DRM_MODE_CONNECTOR_LVDS,
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_Unknown,
473 DRM_MODE_CONNECTOR_HDMIA,
474 DRM_MODE_CONNECTOR_HDMIB,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_9PinDIN,
478 DRM_MODE_CONNECTOR_DisplayPort
479 };
480
481 static const uint16_t supported_devices_connector_object_id_convert[] = {
482 CONNECTOR_OBJECT_ID_NONE,
483 CONNECTOR_OBJECT_ID_VGA,
484 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
485 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
486 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
487 CONNECTOR_OBJECT_ID_COMPOSITE,
488 CONNECTOR_OBJECT_ID_SVIDEO,
489 CONNECTOR_OBJECT_ID_LVDS,
490 CONNECTOR_OBJECT_ID_9PIN_DIN,
491 CONNECTOR_OBJECT_ID_9PIN_DIN,
492 CONNECTOR_OBJECT_ID_DISPLAYPORT,
493 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
494 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
495 CONNECTOR_OBJECT_ID_SVIDEO
496 };
497
498 static const int object_connector_convert[] = {
499 DRM_MODE_CONNECTOR_Unknown,
500 DRM_MODE_CONNECTOR_DVII,
501 DRM_MODE_CONNECTOR_DVII,
502 DRM_MODE_CONNECTOR_DVID,
503 DRM_MODE_CONNECTOR_DVID,
504 DRM_MODE_CONNECTOR_VGA,
505 DRM_MODE_CONNECTOR_Composite,
506 DRM_MODE_CONNECTOR_SVIDEO,
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_9PinDIN,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_HDMIA,
512 DRM_MODE_CONNECTOR_HDMIB,
513 DRM_MODE_CONNECTOR_LVDS,
514 DRM_MODE_CONNECTOR_9PinDIN,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_Unknown,
518 DRM_MODE_CONNECTOR_DisplayPort,
519 DRM_MODE_CONNECTOR_eDP,
520 DRM_MODE_CONNECTOR_Unknown
521 };
522
523 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
524 {
525 struct radeon_device *rdev = dev->dev_private;
526 struct radeon_mode_info *mode_info = &rdev->mode_info;
527 struct atom_context *ctx = mode_info->atom_context;
528 int index = GetIndexIntoMasterTable(DATA, Object_Header);
529 u16 size, data_offset;
530 u8 frev, crev;
531 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
532 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
533 ATOM_OBJECT_TABLE *router_obj;
534 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
535 ATOM_OBJECT_HEADER *obj_header;
536 int i, j, k, path_size, device_support;
537 int connector_type;
538 u16 igp_lane_info, conn_id, connector_object_id;
539 struct radeon_i2c_bus_rec ddc_bus;
540 struct radeon_router router;
541 struct radeon_gpio_rec gpio;
542 struct radeon_hpd hpd;
543
544 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
545 return false;
546
547 if (crev < 2)
548 return false;
549
550 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
551 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usDisplayPathTableOffset));
554 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
557 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
558 (ctx->bios + data_offset +
559 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
560 router_obj = (ATOM_OBJECT_TABLE *)
561 (ctx->bios + data_offset +
562 le16_to_cpu(obj_header->usRouterObjectTableOffset));
563 device_support = le16_to_cpu(obj_header->usDeviceSupport);
564
565 path_size = 0;
566 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
567 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
568 ATOM_DISPLAY_OBJECT_PATH *path;
569 addr += path_size;
570 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
571 path_size += le16_to_cpu(path->usSize);
572
573 if (device_support & le16_to_cpu(path->usDeviceTag)) {
574 uint8_t con_obj_id, con_obj_num, con_obj_type;
575
576 con_obj_id =
577 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
578 >> OBJECT_ID_SHIFT;
579 con_obj_num =
580 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
581 >> ENUM_ID_SHIFT;
582 con_obj_type =
583 (le16_to_cpu(path->usConnObjectId) &
584 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
585
586 /* TODO CV support */
587 if (le16_to_cpu(path->usDeviceTag) ==
588 ATOM_DEVICE_CV_SUPPORT)
589 continue;
590
591 /* IGP chips */
592 if ((rdev->flags & RADEON_IS_IGP) &&
593 (con_obj_id ==
594 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
595 uint16_t igp_offset = 0;
596 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
597
598 index =
599 GetIndexIntoMasterTable(DATA,
600 IntegratedSystemInfo);
601
602 if (atom_parse_data_header(ctx, index, &size, &frev,
603 &crev, &igp_offset)) {
604
605 if (crev >= 2) {
606 igp_obj =
607 (ATOM_INTEGRATED_SYSTEM_INFO_V2
608 *) (ctx->bios + igp_offset);
609
610 if (igp_obj) {
611 uint32_t slot_config, ct;
612
613 if (con_obj_num == 1)
614 slot_config =
615 igp_obj->
616 ulDDISlot1Config;
617 else
618 slot_config =
619 igp_obj->
620 ulDDISlot2Config;
621
622 ct = (slot_config >> 16) & 0xff;
623 connector_type =
624 object_connector_convert
625 [ct];
626 connector_object_id = ct;
627 igp_lane_info =
628 slot_config & 0xffff;
629 } else
630 continue;
631 } else
632 continue;
633 } else {
634 igp_lane_info = 0;
635 connector_type =
636 object_connector_convert[con_obj_id];
637 connector_object_id = con_obj_id;
638 }
639 } else {
640 igp_lane_info = 0;
641 connector_type =
642 object_connector_convert[con_obj_id];
643 connector_object_id = con_obj_id;
644 }
645
646 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
647 continue;
648
649 router.ddc_valid = false;
650 router.cd_valid = false;
651 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
652 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
653
654 grph_obj_id =
655 (le16_to_cpu(path->usGraphicObjIds[j]) &
656 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
657 grph_obj_num =
658 (le16_to_cpu(path->usGraphicObjIds[j]) &
659 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
660 grph_obj_type =
661 (le16_to_cpu(path->usGraphicObjIds[j]) &
662 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
663
664 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
665 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
666 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
667 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
668 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
669 (ctx->bios + data_offset +
670 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
671 ATOM_ENCODER_CAP_RECORD *cap_record;
672 u16 caps = 0;
673
674 while (record->ucRecordSize > 0 &&
675 record->ucRecordType > 0 &&
676 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
677 switch (record->ucRecordType) {
678 case ATOM_ENCODER_CAP_RECORD_TYPE:
679 cap_record =(ATOM_ENCODER_CAP_RECORD *)
680 record;
681 caps = le16_to_cpu(cap_record->usEncoderCap);
682 break;
683 }
684 record = (ATOM_COMMON_RECORD_HEADER *)
685 ((char *)record + record->ucRecordSize);
686 }
687 radeon_add_atom_encoder(dev,
688 encoder_obj,
689 le16_to_cpu
690 (path->
691 usDeviceTag),
692 caps);
693 }
694 }
695 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
696 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
697 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
698 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
699 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
700 (ctx->bios + data_offset +
701 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
702 ATOM_I2C_RECORD *i2c_record;
703 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
704 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
705 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
706 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
707 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
708 (ctx->bios + data_offset +
709 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
710 u8 *num_dst_objs = (u8 *)
711 ((u8 *)router_src_dst_table + 1 +
712 (router_src_dst_table->ucNumberOfSrc * 2));
713 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
718 if (le16_to_cpu(path->usConnObjectId) ==
719 le16_to_cpu(dst_objs[enum_id]))
720 break;
721 }
722
723 while (record->ucRecordSize > 0 &&
724 record->ucRecordType > 0 &&
725 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
726 switch (record->ucRecordType) {
727 case ATOM_I2C_RECORD_TYPE:
728 i2c_record =
729 (ATOM_I2C_RECORD *)
730 record;
731 i2c_config =
732 (ATOM_I2C_ID_CONFIG_ACCESS *)
733 &i2c_record->sucI2cId;
734 router.i2c_info =
735 radeon_lookup_i2c_gpio(rdev,
736 i2c_config->
737 ucAccess);
738 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
739 break;
740 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
741 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
742 record;
743 router.ddc_valid = true;
744 router.ddc_mux_type = ddc_path->ucMuxType;
745 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
746 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
747 break;
748 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
749 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
750 record;
751 router.cd_valid = true;
752 router.cd_mux_type = cd_path->ucMuxType;
753 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
754 router.cd_mux_state = cd_path->ucMuxState[enum_id];
755 break;
756 }
757 record = (ATOM_COMMON_RECORD_HEADER *)
758 ((char *)record + record->ucRecordSize);
759 }
760 }
761 }
762 }
763 }
764
765 /* look up gpio for ddc, hpd */
766 ddc_bus.valid = false;
767 hpd.hpd = RADEON_HPD_NONE;
768 if ((le16_to_cpu(path->usDeviceTag) &
769 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
770 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
771 if (le16_to_cpu(path->usConnObjectId) ==
772 le16_to_cpu(con_obj->asObjects[j].
773 usObjectID)) {
774 ATOM_COMMON_RECORD_HEADER
775 *record =
776 (ATOM_COMMON_RECORD_HEADER
777 *)
778 (ctx->bios + data_offset +
779 le16_to_cpu(con_obj->
780 asObjects[j].
781 usRecordOffset));
782 ATOM_I2C_RECORD *i2c_record;
783 ATOM_HPD_INT_RECORD *hpd_record;
784 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
785
786 while (record->ucRecordSize > 0 &&
787 record->ucRecordType > 0 &&
788 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
789 switch (record->ucRecordType) {
790 case ATOM_I2C_RECORD_TYPE:
791 i2c_record =
792 (ATOM_I2C_RECORD *)
793 record;
794 i2c_config =
795 (ATOM_I2C_ID_CONFIG_ACCESS *)
796 &i2c_record->sucI2cId;
797 ddc_bus = radeon_lookup_i2c_gpio(rdev,
798 i2c_config->
799 ucAccess);
800 break;
801 case ATOM_HPD_INT_RECORD_TYPE:
802 hpd_record =
803 (ATOM_HPD_INT_RECORD *)
804 record;
805 gpio = radeon_atombios_lookup_gpio(rdev,
806 hpd_record->ucHPDIntGPIOID);
807 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
808 hpd.plugged_state = hpd_record->ucPlugged_PinState;
809 break;
810 }
811 record =
812 (ATOM_COMMON_RECORD_HEADER
813 *) ((char *)record
814 +
815 record->
816 ucRecordSize);
817 }
818 break;
819 }
820 }
821 }
822
823 /* needed for aux chan transactions */
824 ddc_bus.hpd = hpd.hpd;
825
826 conn_id = le16_to_cpu(path->usConnObjectId);
827
828 if (!radeon_atom_apply_quirks
829 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
830 &ddc_bus, &conn_id, &hpd))
831 continue;
832
833 radeon_add_atom_connector(dev,
834 conn_id,
835 le16_to_cpu(path->
836 usDeviceTag),
837 connector_type, &ddc_bus,
838 igp_lane_info,
839 connector_object_id,
840 &hpd,
841 &router);
842
843 }
844 }
845
846 radeon_link_encoder_connector(dev);
847
848 radeon_setup_mst_connector(dev);
849 return true;
850 }
851
852 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
873
874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892 }
893
894 struct bios_connector {
895 bool valid;
896 uint16_t line_mux;
897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
900 struct radeon_hpd hpd;
901 };
902
903 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906 {
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
916 int i, j, max_device;
917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
919 struct radeon_router router;
920
921 router.ddc_valid = false;
922 router.cd_valid = false;
923
924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
931 return false;
932 }
933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
955 DRM_DEBUG_KMS("Skipping Component Video\n");
956 continue;
957 }
958
959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i),
1033 0);
1034 else
1035 radeon_add_legacy_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
1043 for (i = 0; i < max_device; i++) {
1044 if (bios_connectors[i].valid) {
1045 for (j = 0; j < max_device; j++) {
1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
1072 bios_connectors[j].valid = false;
1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
1081 for (i = 0; i < max_device; i++) {
1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
1093 0,
1094 connector_object_id,
1095 &bios_connectors[i].hpd,
1096 &router);
1097 }
1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
1102 kfree(bios_connectors);
1103 return true;
1104 }
1105
1106 union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
1113 };
1114
1115 bool radeon_atom_get_clock_info(struct drm_device *dev)
1116 {
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE6(rdev))
1240 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1241 else if (ASIC_IS_DCE5(rdev))
1242 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1243 else
1244 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1245 }
1246 /* set a reasonable default for DP */
1247 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1248 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1249 rdev->clock.default_dispclk / 100);
1250 rdev->clock.default_dispclk = 60000;
1251 }
1252 rdev->clock.dp_extclk =
1253 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1254 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1255 }
1256 *dcpll = *p1pll;
1257
1258 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1259 if (rdev->clock.max_pixel_clock == 0)
1260 rdev->clock.max_pixel_clock = 40000;
1261
1262 /* not technically a clock, but... */
1263 rdev->mode_info.firmware_flags =
1264 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1265
1266 return true;
1267 }
1268
1269 return false;
1270 }
1271
1272 union igp_info {
1273 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1274 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1275 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1276 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1277 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1278 };
1279
1280 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1281 {
1282 struct radeon_mode_info *mode_info = &rdev->mode_info;
1283 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1284 union igp_info *igp_info;
1285 u8 frev, crev;
1286 u16 data_offset;
1287
1288 /* sideport is AMD only */
1289 if (rdev->family == CHIP_RS600)
1290 return false;
1291
1292 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1293 &frev, &crev, &data_offset)) {
1294 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1295 data_offset);
1296 switch (crev) {
1297 case 1:
1298 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1299 return true;
1300 break;
1301 case 2:
1302 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1303 return true;
1304 break;
1305 default:
1306 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1307 break;
1308 }
1309 }
1310 return false;
1311 }
1312
1313 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1314 struct radeon_encoder_int_tmds *tmds)
1315 {
1316 struct drm_device *dev = encoder->base.dev;
1317 struct radeon_device *rdev = dev->dev_private;
1318 struct radeon_mode_info *mode_info = &rdev->mode_info;
1319 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1320 uint16_t data_offset;
1321 struct _ATOM_TMDS_INFO *tmds_info;
1322 uint8_t frev, crev;
1323 uint16_t maxfreq;
1324 int i;
1325
1326 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1327 &frev, &crev, &data_offset)) {
1328 tmds_info =
1329 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1330 data_offset);
1331
1332 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1333 for (i = 0; i < 4; i++) {
1334 tmds->tmds_pll[i].freq =
1335 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1336 tmds->tmds_pll[i].value =
1337 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1338 tmds->tmds_pll[i].value |=
1339 (tmds_info->asMiscInfo[i].
1340 ucPLL_VCO_Gain & 0x3f) << 6;
1341 tmds->tmds_pll[i].value |=
1342 (tmds_info->asMiscInfo[i].
1343 ucPLL_DutyCycle & 0xf) << 12;
1344 tmds->tmds_pll[i].value |=
1345 (tmds_info->asMiscInfo[i].
1346 ucPLL_VoltageSwing & 0xf) << 16;
1347
1348 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1349 tmds->tmds_pll[i].freq,
1350 tmds->tmds_pll[i].value);
1351
1352 if (maxfreq == tmds->tmds_pll[i].freq) {
1353 tmds->tmds_pll[i].freq = 0xffffffff;
1354 break;
1355 }
1356 }
1357 return true;
1358 }
1359 return false;
1360 }
1361
1362 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1363 struct radeon_atom_ss *ss,
1364 int id)
1365 {
1366 struct radeon_mode_info *mode_info = &rdev->mode_info;
1367 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1368 uint16_t data_offset, size;
1369 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1370 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1371 uint8_t frev, crev;
1372 int i, num_indices;
1373
1374 memset(ss, 0, sizeof(struct radeon_atom_ss));
1375 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1376 &frev, &crev, &data_offset)) {
1377 ss_info =
1378 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1379
1380 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1381 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1382 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1383 ((u8 *)&ss_info->asSS_Info[0]);
1384 for (i = 0; i < num_indices; i++) {
1385 if (ss_assign->ucSS_Id == id) {
1386 ss->percentage =
1387 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1388 ss->type = ss_assign->ucSpreadSpectrumType;
1389 ss->step = ss_assign->ucSS_Step;
1390 ss->delay = ss_assign->ucSS_Delay;
1391 ss->range = ss_assign->ucSS_Range;
1392 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1393 return true;
1394 }
1395 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1396 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1397 }
1398 }
1399 return false;
1400 }
1401
1402 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1403 struct radeon_atom_ss *ss,
1404 int id)
1405 {
1406 struct radeon_mode_info *mode_info = &rdev->mode_info;
1407 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1408 u16 data_offset, size;
1409 union igp_info *igp_info;
1410 u8 frev, crev;
1411 u16 percentage = 0, rate = 0;
1412
1413 /* get any igp specific overrides */
1414 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1415 &frev, &crev, &data_offset)) {
1416 igp_info = (union igp_info *)
1417 (mode_info->atom_context->bios + data_offset);
1418 switch (crev) {
1419 case 6:
1420 switch (id) {
1421 case ASIC_INTERNAL_SS_ON_TMDS:
1422 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1423 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1424 break;
1425 case ASIC_INTERNAL_SS_ON_HDMI:
1426 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1427 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1428 break;
1429 case ASIC_INTERNAL_SS_ON_LVDS:
1430 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1431 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1432 break;
1433 }
1434 break;
1435 case 7:
1436 switch (id) {
1437 case ASIC_INTERNAL_SS_ON_TMDS:
1438 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1439 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1440 break;
1441 case ASIC_INTERNAL_SS_ON_HDMI:
1442 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1443 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1444 break;
1445 case ASIC_INTERNAL_SS_ON_LVDS:
1446 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1447 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1448 break;
1449 }
1450 break;
1451 case 8:
1452 switch (id) {
1453 case ASIC_INTERNAL_SS_ON_TMDS:
1454 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1455 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1456 break;
1457 case ASIC_INTERNAL_SS_ON_HDMI:
1458 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1459 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1460 break;
1461 case ASIC_INTERNAL_SS_ON_LVDS:
1462 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1463 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1464 break;
1465 }
1466 break;
1467 default:
1468 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1469 break;
1470 }
1471 if (percentage)
1472 ss->percentage = percentage;
1473 if (rate)
1474 ss->rate = rate;
1475 }
1476 }
1477
1478 union asic_ss_info {
1479 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1480 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1481 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1482 };
1483
1484 union asic_ss_assignment {
1485 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1486 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1487 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1488 };
1489
1490 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1491 struct radeon_atom_ss *ss,
1492 int id, u32 clock)
1493 {
1494 struct radeon_mode_info *mode_info = &rdev->mode_info;
1495 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1496 uint16_t data_offset, size;
1497 union asic_ss_info *ss_info;
1498 union asic_ss_assignment *ss_assign;
1499 uint8_t frev, crev;
1500 int i, num_indices;
1501
1502 if (id == ASIC_INTERNAL_MEMORY_SS) {
1503 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1504 return false;
1505 }
1506 if (id == ASIC_INTERNAL_ENGINE_SS) {
1507 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1508 return false;
1509 }
1510
1511 memset(ss, 0, sizeof(struct radeon_atom_ss));
1512 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1513 &frev, &crev, &data_offset)) {
1514
1515 ss_info =
1516 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1517
1518 switch (frev) {
1519 case 1:
1520 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1521 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1522
1523 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1524 for (i = 0; i < num_indices; i++) {
1525 if ((ss_assign->v1.ucClockIndication == id) &&
1526 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1527 ss->percentage =
1528 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1529 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1530 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1531 ss->percentage_divider = 100;
1532 return true;
1533 }
1534 ss_assign = (union asic_ss_assignment *)
1535 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1536 }
1537 break;
1538 case 2:
1539 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1540 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1541 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1542 for (i = 0; i < num_indices; i++) {
1543 if ((ss_assign->v2.ucClockIndication == id) &&
1544 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1545 ss->percentage =
1546 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1547 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1548 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1549 ss->percentage_divider = 100;
1550 if ((crev == 2) &&
1551 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1552 (id == ASIC_INTERNAL_MEMORY_SS)))
1553 ss->rate /= 100;
1554 return true;
1555 }
1556 ss_assign = (union asic_ss_assignment *)
1557 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1558 }
1559 break;
1560 case 3:
1561 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1562 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1563 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1564 for (i = 0; i < num_indices; i++) {
1565 if ((ss_assign->v3.ucClockIndication == id) &&
1566 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1567 ss->percentage =
1568 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1569 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1570 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1571 if (ss_assign->v3.ucSpreadSpectrumMode &
1572 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1573 ss->percentage_divider = 1000;
1574 else
1575 ss->percentage_divider = 100;
1576 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1577 (id == ASIC_INTERNAL_MEMORY_SS))
1578 ss->rate /= 100;
1579 if (rdev->flags & RADEON_IS_IGP)
1580 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1581 return true;
1582 }
1583 ss_assign = (union asic_ss_assignment *)
1584 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1585 }
1586 break;
1587 default:
1588 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1589 break;
1590 }
1591
1592 }
1593 return false;
1594 }
1595
1596 union lvds_info {
1597 struct _ATOM_LVDS_INFO info;
1598 struct _ATOM_LVDS_INFO_V12 info_12;
1599 };
1600
1601 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1602 radeon_encoder
1603 *encoder)
1604 {
1605 struct drm_device *dev = encoder->base.dev;
1606 struct radeon_device *rdev = dev->dev_private;
1607 struct radeon_mode_info *mode_info = &rdev->mode_info;
1608 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1609 uint16_t data_offset, misc;
1610 union lvds_info *lvds_info;
1611 uint8_t frev, crev;
1612 struct radeon_encoder_atom_dig *lvds = NULL;
1613 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1614
1615 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1616 &frev, &crev, &data_offset)) {
1617 lvds_info =
1618 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1619 lvds =
1620 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1621
1622 if (!lvds)
1623 return NULL;
1624
1625 lvds->native_mode.clock =
1626 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1627 lvds->native_mode.hdisplay =
1628 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1629 lvds->native_mode.vdisplay =
1630 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1631 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1632 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1633 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1634 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1635 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1636 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1637 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1638 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1639 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1640 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1641 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1642 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1643 lvds->panel_pwr_delay =
1644 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1645 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1646
1647 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1648 if (misc & ATOM_VSYNC_POLARITY)
1649 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1650 if (misc & ATOM_HSYNC_POLARITY)
1651 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1652 if (misc & ATOM_COMPOSITESYNC)
1653 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1654 if (misc & ATOM_INTERLACE)
1655 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1656 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1657 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1658
1659 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1660 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1661
1662 /* set crtc values */
1663 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1664
1665 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1666
1667 encoder->native_mode = lvds->native_mode;
1668
1669 if (encoder_enum == 2)
1670 lvds->linkb = true;
1671 else
1672 lvds->linkb = false;
1673
1674 /* parse the lcd record table */
1675 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1676 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1677 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1678 bool bad_record = false;
1679 u8 *record;
1680
1681 if ((frev == 1) && (crev < 2))
1682 /* absolute */
1683 record = (u8 *)(mode_info->atom_context->bios +
1684 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1685 else
1686 /* relative */
1687 record = (u8 *)(mode_info->atom_context->bios +
1688 data_offset +
1689 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1690 while (*record != ATOM_RECORD_END_TYPE) {
1691 switch (*record) {
1692 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1693 record += sizeof(ATOM_PATCH_RECORD_MODE);
1694 break;
1695 case LCD_RTS_RECORD_TYPE:
1696 record += sizeof(ATOM_LCD_RTS_RECORD);
1697 break;
1698 case LCD_CAP_RECORD_TYPE:
1699 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1700 break;
1701 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1702 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1703 if (fake_edid_record->ucFakeEDIDLength) {
1704 struct edid *edid;
1705 int edid_size =
1706 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1707 edid = kmalloc(edid_size, GFP_KERNEL);
1708 if (edid) {
1709 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1710 fake_edid_record->ucFakeEDIDLength);
1711
1712 if (drm_edid_is_valid(edid)) {
1713 rdev->mode_info.bios_hardcoded_edid = edid;
1714 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1715 } else
1716 kfree(edid);
1717 }
1718 }
1719 record += fake_edid_record->ucFakeEDIDLength ?
1720 fake_edid_record->ucFakeEDIDLength + 2 :
1721 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1722 break;
1723 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1724 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1725 lvds->native_mode.width_mm = panel_res_record->usHSize;
1726 lvds->native_mode.height_mm = panel_res_record->usVSize;
1727 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1728 break;
1729 default:
1730 DRM_ERROR("Bad LCD record %d\n", *record);
1731 bad_record = true;
1732 break;
1733 }
1734 if (bad_record)
1735 break;
1736 }
1737 }
1738 }
1739 return lvds;
1740 }
1741
1742 struct radeon_encoder_primary_dac *
1743 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1744 {
1745 struct drm_device *dev = encoder->base.dev;
1746 struct radeon_device *rdev = dev->dev_private;
1747 struct radeon_mode_info *mode_info = &rdev->mode_info;
1748 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1749 uint16_t data_offset;
1750 struct _COMPASSIONATE_DATA *dac_info;
1751 uint8_t frev, crev;
1752 uint8_t bg, dac;
1753 struct radeon_encoder_primary_dac *p_dac = NULL;
1754
1755 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1756 &frev, &crev, &data_offset)) {
1757 dac_info = (struct _COMPASSIONATE_DATA *)
1758 (mode_info->atom_context->bios + data_offset);
1759
1760 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1761
1762 if (!p_dac)
1763 return NULL;
1764
1765 bg = dac_info->ucDAC1_BG_Adjustment;
1766 dac = dac_info->ucDAC1_DAC_Adjustment;
1767 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1768
1769 }
1770 return p_dac;
1771 }
1772
1773 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1774 struct drm_display_mode *mode)
1775 {
1776 struct radeon_mode_info *mode_info = &rdev->mode_info;
1777 ATOM_ANALOG_TV_INFO *tv_info;
1778 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1779 ATOM_DTD_FORMAT *dtd_timings;
1780 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1781 u8 frev, crev;
1782 u16 data_offset, misc;
1783
1784 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1785 &frev, &crev, &data_offset))
1786 return false;
1787
1788 switch (crev) {
1789 case 1:
1790 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1791 if (index >= MAX_SUPPORTED_TV_TIMING)
1792 return false;
1793
1794 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1795 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1796 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1797 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1798 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1799
1800 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1801 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1802 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1803 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1804 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1805
1806 mode->flags = 0;
1807 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1808 if (misc & ATOM_VSYNC_POLARITY)
1809 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1810 if (misc & ATOM_HSYNC_POLARITY)
1811 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1812 if (misc & ATOM_COMPOSITESYNC)
1813 mode->flags |= DRM_MODE_FLAG_CSYNC;
1814 if (misc & ATOM_INTERLACE)
1815 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1816 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1817 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1818
1819 mode->crtc_clock = mode->clock =
1820 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1821
1822 if (index == 1) {
1823 /* PAL timings appear to have wrong values for totals */
1824 mode->crtc_htotal -= 1;
1825 mode->crtc_vtotal -= 1;
1826 }
1827 break;
1828 case 2:
1829 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1830 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1831 return false;
1832
1833 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1834 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1835 le16_to_cpu(dtd_timings->usHBlanking_Time);
1836 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1837 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1838 le16_to_cpu(dtd_timings->usHSyncOffset);
1839 mode->crtc_hsync_end = mode->crtc_hsync_start +
1840 le16_to_cpu(dtd_timings->usHSyncWidth);
1841
1842 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1843 le16_to_cpu(dtd_timings->usVBlanking_Time);
1844 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1845 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1846 le16_to_cpu(dtd_timings->usVSyncOffset);
1847 mode->crtc_vsync_end = mode->crtc_vsync_start +
1848 le16_to_cpu(dtd_timings->usVSyncWidth);
1849
1850 mode->flags = 0;
1851 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1852 if (misc & ATOM_VSYNC_POLARITY)
1853 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1854 if (misc & ATOM_HSYNC_POLARITY)
1855 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1856 if (misc & ATOM_COMPOSITESYNC)
1857 mode->flags |= DRM_MODE_FLAG_CSYNC;
1858 if (misc & ATOM_INTERLACE)
1859 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1860 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1861 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1862
1863 mode->crtc_clock = mode->clock =
1864 le16_to_cpu(dtd_timings->usPixClk) * 10;
1865 break;
1866 }
1867 return true;
1868 }
1869
1870 enum radeon_tv_std
1871 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1872 {
1873 struct radeon_mode_info *mode_info = &rdev->mode_info;
1874 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1875 uint16_t data_offset;
1876 uint8_t frev, crev;
1877 struct _ATOM_ANALOG_TV_INFO *tv_info;
1878 enum radeon_tv_std tv_std = TV_STD_NTSC;
1879
1880 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1881 &frev, &crev, &data_offset)) {
1882
1883 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1884 (mode_info->atom_context->bios + data_offset);
1885
1886 switch (tv_info->ucTV_BootUpDefaultStandard) {
1887 case ATOM_TV_NTSC:
1888 tv_std = TV_STD_NTSC;
1889 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1890 break;
1891 case ATOM_TV_NTSCJ:
1892 tv_std = TV_STD_NTSC_J;
1893 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1894 break;
1895 case ATOM_TV_PAL:
1896 tv_std = TV_STD_PAL;
1897 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1898 break;
1899 case ATOM_TV_PALM:
1900 tv_std = TV_STD_PAL_M;
1901 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1902 break;
1903 case ATOM_TV_PALN:
1904 tv_std = TV_STD_PAL_N;
1905 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1906 break;
1907 case ATOM_TV_PALCN:
1908 tv_std = TV_STD_PAL_CN;
1909 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1910 break;
1911 case ATOM_TV_PAL60:
1912 tv_std = TV_STD_PAL_60;
1913 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1914 break;
1915 case ATOM_TV_SECAM:
1916 tv_std = TV_STD_SECAM;
1917 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1918 break;
1919 default:
1920 tv_std = TV_STD_NTSC;
1921 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1922 break;
1923 }
1924 }
1925 return tv_std;
1926 }
1927
1928 struct radeon_encoder_tv_dac *
1929 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1930 {
1931 struct drm_device *dev = encoder->base.dev;
1932 struct radeon_device *rdev = dev->dev_private;
1933 struct radeon_mode_info *mode_info = &rdev->mode_info;
1934 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1935 uint16_t data_offset;
1936 struct _COMPASSIONATE_DATA *dac_info;
1937 uint8_t frev, crev;
1938 uint8_t bg, dac;
1939 struct radeon_encoder_tv_dac *tv_dac = NULL;
1940
1941 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1942 &frev, &crev, &data_offset)) {
1943
1944 dac_info = (struct _COMPASSIONATE_DATA *)
1945 (mode_info->atom_context->bios + data_offset);
1946
1947 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1948
1949 if (!tv_dac)
1950 return NULL;
1951
1952 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1953 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1954 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1955
1956 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1957 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1958 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1959
1960 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1961 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1962 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1963
1964 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1965 }
1966 return tv_dac;
1967 }
1968
1969 static const char *thermal_controller_names[] = {
1970 "NONE",
1971 "lm63",
1972 "adm1032",
1973 "adm1030",
1974 "max6649",
1975 "lm63", /* lm64 */
1976 "f75375",
1977 "asc7xxx",
1978 };
1979
1980 static const char *pp_lib_thermal_controller_names[] = {
1981 "NONE",
1982 "lm63",
1983 "adm1032",
1984 "adm1030",
1985 "max6649",
1986 "lm63", /* lm64 */
1987 "f75375",
1988 "RV6xx",
1989 "RV770",
1990 "adt7473",
1991 "NONE",
1992 "External GPIO",
1993 "Evergreen",
1994 "emc2103",
1995 "Sumo",
1996 "Northern Islands",
1997 "Southern Islands",
1998 "lm96163",
1999 "Sea Islands",
2000 };
2001
2002 union power_info {
2003 struct _ATOM_POWERPLAY_INFO info;
2004 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2005 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2006 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2007 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2008 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2009 };
2010
2011 union pplib_clock_info {
2012 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2013 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2014 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2015 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2016 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2017 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2018 };
2019
2020 union pplib_power_state {
2021 struct _ATOM_PPLIB_STATE v1;
2022 struct _ATOM_PPLIB_STATE_V2 v2;
2023 };
2024
2025 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2026 int state_index,
2027 u32 misc, u32 misc2)
2028 {
2029 rdev->pm.power_state[state_index].misc = misc;
2030 rdev->pm.power_state[state_index].misc2 = misc2;
2031 /* order matters! */
2032 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2033 rdev->pm.power_state[state_index].type =
2034 POWER_STATE_TYPE_POWERSAVE;
2035 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2036 rdev->pm.power_state[state_index].type =
2037 POWER_STATE_TYPE_BATTERY;
2038 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2039 rdev->pm.power_state[state_index].type =
2040 POWER_STATE_TYPE_BATTERY;
2041 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2042 rdev->pm.power_state[state_index].type =
2043 POWER_STATE_TYPE_BALANCED;
2044 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2045 rdev->pm.power_state[state_index].type =
2046 POWER_STATE_TYPE_PERFORMANCE;
2047 rdev->pm.power_state[state_index].flags &=
2048 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2049 }
2050 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2051 rdev->pm.power_state[state_index].type =
2052 POWER_STATE_TYPE_BALANCED;
2053 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2054 rdev->pm.power_state[state_index].type =
2055 POWER_STATE_TYPE_DEFAULT;
2056 rdev->pm.default_power_state_index = state_index;
2057 rdev->pm.power_state[state_index].default_clock_mode =
2058 &rdev->pm.power_state[state_index].clock_info[0];
2059 } else if (state_index == 0) {
2060 rdev->pm.power_state[state_index].clock_info[0].flags |=
2061 RADEON_PM_MODE_NO_DISPLAY;
2062 }
2063 }
2064
2065 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2066 {
2067 struct radeon_mode_info *mode_info = &rdev->mode_info;
2068 u32 misc, misc2 = 0;
2069 int num_modes = 0, i;
2070 int state_index = 0;
2071 struct radeon_i2c_bus_rec i2c_bus;
2072 union power_info *power_info;
2073 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2074 u16 data_offset;
2075 u8 frev, crev;
2076
2077 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2078 &frev, &crev, &data_offset))
2079 return state_index;
2080 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2081
2082 /* add the i2c bus for thermal/fan chip */
2083 if ((power_info->info.ucOverdriveThermalController > 0) &&
2084 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2085 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2086 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2087 power_info->info.ucOverdriveControllerAddress >> 1);
2088 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2089 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2090 if (rdev->pm.i2c_bus) {
2091 struct i2c_board_info info = { };
2092 const char *name = thermal_controller_names[power_info->info.
2093 ucOverdriveThermalController];
2094 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2095 strlcpy(info.type, name, sizeof(info.type));
2096 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2097 }
2098 }
2099 num_modes = power_info->info.ucNumOfPowerModeEntries;
2100 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2101 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2102 if (num_modes == 0)
2103 return state_index;
2104 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2105 if (!rdev->pm.power_state)
2106 return state_index;
2107 /* last mode is usually default, array is low to high */
2108 for (i = 0; i < num_modes; i++) {
2109 rdev->pm.power_state[state_index].clock_info =
2110 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2111 if (!rdev->pm.power_state[state_index].clock_info)
2112 return state_index;
2113 rdev->pm.power_state[state_index].num_clock_modes = 1;
2114 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2115 switch (frev) {
2116 case 1:
2117 rdev->pm.power_state[state_index].clock_info[0].mclk =
2118 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2119 rdev->pm.power_state[state_index].clock_info[0].sclk =
2120 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2121 /* skip invalid modes */
2122 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2123 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2124 continue;
2125 rdev->pm.power_state[state_index].pcie_lanes =
2126 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2127 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2128 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2129 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2130 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2131 VOLTAGE_GPIO;
2132 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2133 radeon_atombios_lookup_gpio(rdev,
2134 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2135 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2136 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2137 true;
2138 else
2139 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2140 false;
2141 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2142 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2143 VOLTAGE_VDDC;
2144 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2145 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2146 }
2147 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2148 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2149 state_index++;
2150 break;
2151 case 2:
2152 rdev->pm.power_state[state_index].clock_info[0].mclk =
2153 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2154 rdev->pm.power_state[state_index].clock_info[0].sclk =
2155 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2156 /* skip invalid modes */
2157 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2158 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2159 continue;
2160 rdev->pm.power_state[state_index].pcie_lanes =
2161 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2162 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2163 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2164 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2165 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2167 VOLTAGE_GPIO;
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2169 radeon_atombios_lookup_gpio(rdev,
2170 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2171 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2172 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2173 true;
2174 else
2175 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2176 false;
2177 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2178 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2179 VOLTAGE_VDDC;
2180 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2181 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2182 }
2183 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2184 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2185 state_index++;
2186 break;
2187 case 3:
2188 rdev->pm.power_state[state_index].clock_info[0].mclk =
2189 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2190 rdev->pm.power_state[state_index].clock_info[0].sclk =
2191 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2192 /* skip invalid modes */
2193 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2194 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2195 continue;
2196 rdev->pm.power_state[state_index].pcie_lanes =
2197 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2198 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2199 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2200 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2201 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2203 VOLTAGE_GPIO;
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2205 radeon_atombios_lookup_gpio(rdev,
2206 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2207 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2208 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2209 true;
2210 else
2211 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2212 false;
2213 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2214 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2215 VOLTAGE_VDDC;
2216 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2217 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2218 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2219 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2220 true;
2221 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2222 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2223 }
2224 }
2225 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2226 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2227 state_index++;
2228 break;
2229 }
2230 }
2231 /* last mode is usually default */
2232 if (rdev->pm.default_power_state_index == -1) {
2233 rdev->pm.power_state[state_index - 1].type =
2234 POWER_STATE_TYPE_DEFAULT;
2235 rdev->pm.default_power_state_index = state_index - 1;
2236 rdev->pm.power_state[state_index - 1].default_clock_mode =
2237 &rdev->pm.power_state[state_index - 1].clock_info[0];
2238 rdev->pm.power_state[state_index].flags &=
2239 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2240 rdev->pm.power_state[state_index].misc = 0;
2241 rdev->pm.power_state[state_index].misc2 = 0;
2242 }
2243 return state_index;
2244 }
2245
2246 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2247 ATOM_PPLIB_THERMALCONTROLLER *controller)
2248 {
2249 struct radeon_i2c_bus_rec i2c_bus;
2250
2251 /* add the i2c bus for thermal/fan chip */
2252 if (controller->ucType > 0) {
2253 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2254 rdev->pm.no_fan = true;
2255 rdev->pm.fan_pulses_per_revolution =
2256 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2257 if (rdev->pm.fan_pulses_per_revolution) {
2258 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2259 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2260 }
2261 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2262 DRM_INFO("Internal thermal controller %s fan control\n",
2263 (controller->ucFanParameters &
2264 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2265 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2266 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2267 DRM_INFO("Internal thermal controller %s fan control\n",
2268 (controller->ucFanParameters &
2269 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2270 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2271 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2272 DRM_INFO("Internal thermal controller %s fan control\n",
2273 (controller->ucFanParameters &
2274 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2275 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2276 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2277 DRM_INFO("Internal thermal controller %s fan control\n",
2278 (controller->ucFanParameters &
2279 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2280 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2281 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2282 DRM_INFO("Internal thermal controller %s fan control\n",
2283 (controller->ucFanParameters &
2284 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2285 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2286 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2287 DRM_INFO("Internal thermal controller %s fan control\n",
2288 (controller->ucFanParameters &
2289 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2291 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2292 DRM_INFO("Internal thermal controller %s fan control\n",
2293 (controller->ucFanParameters &
2294 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2296 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2297 DRM_INFO("Internal thermal controller %s fan control\n",
2298 (controller->ucFanParameters &
2299 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2301 } else if (controller->ucType ==
2302 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2303 DRM_INFO("External GPIO thermal controller %s fan control\n",
2304 (controller->ucFanParameters &
2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2307 } else if (controller->ucType ==
2308 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2309 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2310 (controller->ucFanParameters &
2311 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2312 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2313 } else if (controller->ucType ==
2314 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2315 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2316 (controller->ucFanParameters &
2317 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2318 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2319 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2320 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2321 pp_lib_thermal_controller_names[controller->ucType],
2322 controller->ucI2cAddress >> 1,
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2326 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2327 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2328 if (rdev->pm.i2c_bus) {
2329 struct i2c_board_info info = { };
2330 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2331 info.addr = controller->ucI2cAddress >> 1;
2332 strlcpy(info.type, name, sizeof(info.type));
2333 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2334 }
2335 } else {
2336 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2337 controller->ucType,
2338 controller->ucI2cAddress >> 1,
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 }
2342 }
2343 }
2344
2345 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2346 u16 *vddc, u16 *vddci, u16 *mvdd)
2347 {
2348 struct radeon_mode_info *mode_info = &rdev->mode_info;
2349 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2350 u8 frev, crev;
2351 u16 data_offset;
2352 union firmware_info *firmware_info;
2353
2354 *vddc = 0;
2355 *vddci = 0;
2356 *mvdd = 0;
2357
2358 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2359 &frev, &crev, &data_offset)) {
2360 firmware_info =
2361 (union firmware_info *)(mode_info->atom_context->bios +
2362 data_offset);
2363 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2364 if ((frev == 2) && (crev >= 2)) {
2365 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2366 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2367 }
2368 }
2369 }
2370
2371 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2372 int state_index, int mode_index,
2373 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2374 {
2375 int j;
2376 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2377 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2378 u16 vddc, vddci, mvdd;
2379
2380 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2381
2382 rdev->pm.power_state[state_index].misc = misc;
2383 rdev->pm.power_state[state_index].misc2 = misc2;
2384 rdev->pm.power_state[state_index].pcie_lanes =
2385 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2386 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2387 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2388 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2389 rdev->pm.power_state[state_index].type =
2390 POWER_STATE_TYPE_BATTERY;
2391 break;
2392 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2393 rdev->pm.power_state[state_index].type =
2394 POWER_STATE_TYPE_BALANCED;
2395 break;
2396 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2397 rdev->pm.power_state[state_index].type =
2398 POWER_STATE_TYPE_PERFORMANCE;
2399 break;
2400 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2401 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2402 rdev->pm.power_state[state_index].type =
2403 POWER_STATE_TYPE_PERFORMANCE;
2404 break;
2405 }
2406 rdev->pm.power_state[state_index].flags = 0;
2407 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2408 rdev->pm.power_state[state_index].flags |=
2409 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2410 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2411 rdev->pm.power_state[state_index].type =
2412 POWER_STATE_TYPE_DEFAULT;
2413 rdev->pm.default_power_state_index = state_index;
2414 rdev->pm.power_state[state_index].default_clock_mode =
2415 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2416 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2417 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2418 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2419 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2420 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2421 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2422 } else {
2423 u16 max_vddci = 0;
2424
2425 if (ASIC_IS_DCE4(rdev))
2426 radeon_atom_get_max_voltage(rdev,
2427 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2428 &max_vddci);
2429 /* patch the table values with the default sclk/mclk from firmware info */
2430 for (j = 0; j < mode_index; j++) {
2431 rdev->pm.power_state[state_index].clock_info[j].mclk =
2432 rdev->clock.default_mclk;
2433 rdev->pm.power_state[state_index].clock_info[j].sclk =
2434 rdev->clock.default_sclk;
2435 if (vddc)
2436 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2437 vddc;
2438 if (max_vddci)
2439 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2440 max_vddci;
2441 }
2442 }
2443 }
2444 }
2445
2446 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2447 int state_index, int mode_index,
2448 union pplib_clock_info *clock_info)
2449 {
2450 u32 sclk, mclk;
2451 u16 vddc;
2452
2453 if (rdev->flags & RADEON_IS_IGP) {
2454 if (rdev->family >= CHIP_PALM) {
2455 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2456 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2457 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2458 } else {
2459 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2460 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2461 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2462 }
2463 } else if (rdev->family >= CHIP_BONAIRE) {
2464 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2465 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2466 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2467 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2468 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2469 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2470 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2471 VOLTAGE_NONE;
2472 } else if (rdev->family >= CHIP_TAHITI) {
2473 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2474 sclk |= clock_info->si.ucEngineClockHigh << 16;
2475 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2476 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2477 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2478 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2479 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2480 VOLTAGE_SW;
2481 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2482 le16_to_cpu(clock_info->si.usVDDC);
2483 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2484 le16_to_cpu(clock_info->si.usVDDCI);
2485 } else if (rdev->family >= CHIP_CEDAR) {
2486 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2487 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2488 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2489 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2490 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2491 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2492 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2493 VOLTAGE_SW;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2495 le16_to_cpu(clock_info->evergreen.usVDDC);
2496 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2497 le16_to_cpu(clock_info->evergreen.usVDDCI);
2498 } else {
2499 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2500 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2501 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2502 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2506 VOLTAGE_SW;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2508 le16_to_cpu(clock_info->r600.usVDDC);
2509 }
2510
2511 /* patch up vddc if necessary */
2512 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2513 case ATOM_VIRTUAL_VOLTAGE_ID0:
2514 case ATOM_VIRTUAL_VOLTAGE_ID1:
2515 case ATOM_VIRTUAL_VOLTAGE_ID2:
2516 case ATOM_VIRTUAL_VOLTAGE_ID3:
2517 case ATOM_VIRTUAL_VOLTAGE_ID4:
2518 case ATOM_VIRTUAL_VOLTAGE_ID5:
2519 case ATOM_VIRTUAL_VOLTAGE_ID6:
2520 case ATOM_VIRTUAL_VOLTAGE_ID7:
2521 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2523 &vddc) == 0)
2524 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2525 break;
2526 default:
2527 break;
2528 }
2529
2530 if (rdev->flags & RADEON_IS_IGP) {
2531 /* skip invalid modes */
2532 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2533 return false;
2534 } else {
2535 /* skip invalid modes */
2536 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2537 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2538 return false;
2539 }
2540 return true;
2541 }
2542
2543 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2544 {
2545 struct radeon_mode_info *mode_info = &rdev->mode_info;
2546 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2547 union pplib_power_state *power_state;
2548 int i, j;
2549 int state_index = 0, mode_index = 0;
2550 union pplib_clock_info *clock_info;
2551 bool valid;
2552 union power_info *power_info;
2553 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2554 u16 data_offset;
2555 u8 frev, crev;
2556
2557 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2558 &frev, &crev, &data_offset))
2559 return state_index;
2560 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2561
2562 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2563 if (power_info->pplib.ucNumStates == 0)
2564 return state_index;
2565 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2566 power_info->pplib.ucNumStates, GFP_KERNEL);
2567 if (!rdev->pm.power_state)
2568 return state_index;
2569 /* first mode is usually default, followed by low to high */
2570 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2571 mode_index = 0;
2572 power_state = (union pplib_power_state *)
2573 (mode_info->atom_context->bios + data_offset +
2574 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2575 i * power_info->pplib.ucStateEntrySize);
2576 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2577 (mode_info->atom_context->bios + data_offset +
2578 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2579 (power_state->v1.ucNonClockStateIndex *
2580 power_info->pplib.ucNonClockSize));
2581 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2582 ((power_info->pplib.ucStateEntrySize - 1) ?
2583 (power_info->pplib.ucStateEntrySize - 1) : 1),
2584 GFP_KERNEL);
2585 if (!rdev->pm.power_state[i].clock_info)
2586 return state_index;
2587 if (power_info->pplib.ucStateEntrySize - 1) {
2588 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2589 clock_info = (union pplib_clock_info *)
2590 (mode_info->atom_context->bios + data_offset +
2591 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2592 (power_state->v1.ucClockStateIndices[j] *
2593 power_info->pplib.ucClockInfoSize));
2594 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2595 state_index, mode_index,
2596 clock_info);
2597 if (valid)
2598 mode_index++;
2599 }
2600 } else {
2601 rdev->pm.power_state[state_index].clock_info[0].mclk =
2602 rdev->clock.default_mclk;
2603 rdev->pm.power_state[state_index].clock_info[0].sclk =
2604 rdev->clock.default_sclk;
2605 mode_index++;
2606 }
2607 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2608 if (mode_index) {
2609 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2610 non_clock_info);
2611 state_index++;
2612 }
2613 }
2614 /* if multiple clock modes, mark the lowest as no display */
2615 for (i = 0; i < state_index; i++) {
2616 if (rdev->pm.power_state[i].num_clock_modes > 1)
2617 rdev->pm.power_state[i].clock_info[0].flags |=
2618 RADEON_PM_MODE_NO_DISPLAY;
2619 }
2620 /* first mode is usually default */
2621 if (rdev->pm.default_power_state_index == -1) {
2622 rdev->pm.power_state[0].type =
2623 POWER_STATE_TYPE_DEFAULT;
2624 rdev->pm.default_power_state_index = 0;
2625 rdev->pm.power_state[0].default_clock_mode =
2626 &rdev->pm.power_state[0].clock_info[0];
2627 }
2628 return state_index;
2629 }
2630
2631 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2632 {
2633 struct radeon_mode_info *mode_info = &rdev->mode_info;
2634 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2635 union pplib_power_state *power_state;
2636 int i, j, non_clock_array_index, clock_array_index;
2637 int state_index = 0, mode_index = 0;
2638 union pplib_clock_info *clock_info;
2639 struct _StateArray *state_array;
2640 struct _ClockInfoArray *clock_info_array;
2641 struct _NonClockInfoArray *non_clock_info_array;
2642 bool valid;
2643 union power_info *power_info;
2644 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2645 u16 data_offset;
2646 u8 frev, crev;
2647 u8 *power_state_offset;
2648
2649 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2650 &frev, &crev, &data_offset))
2651 return state_index;
2652 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2653
2654 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2655 state_array = (struct _StateArray *)
2656 (mode_info->atom_context->bios + data_offset +
2657 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2658 clock_info_array = (struct _ClockInfoArray *)
2659 (mode_info->atom_context->bios + data_offset +
2660 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2661 non_clock_info_array = (struct _NonClockInfoArray *)
2662 (mode_info->atom_context->bios + data_offset +
2663 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2664 if (state_array->ucNumEntries == 0)
2665 return state_index;
2666 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2667 state_array->ucNumEntries, GFP_KERNEL);
2668 if (!rdev->pm.power_state)
2669 return state_index;
2670 power_state_offset = (u8 *)state_array->states;
2671 for (i = 0; i < state_array->ucNumEntries; i++) {
2672 mode_index = 0;
2673 power_state = (union pplib_power_state *)power_state_offset;
2674 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2675 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2676 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2677 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2678 (power_state->v2.ucNumDPMLevels ?
2679 power_state->v2.ucNumDPMLevels : 1),
2680 GFP_KERNEL);
2681 if (!rdev->pm.power_state[i].clock_info)
2682 return state_index;
2683 if (power_state->v2.ucNumDPMLevels) {
2684 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2685 clock_array_index = power_state->v2.clockInfoIndex[j];
2686 clock_info = (union pplib_clock_info *)
2687 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2688 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2689 state_index, mode_index,
2690 clock_info);
2691 if (valid)
2692 mode_index++;
2693 }
2694 } else {
2695 rdev->pm.power_state[state_index].clock_info[0].mclk =
2696 rdev->clock.default_mclk;
2697 rdev->pm.power_state[state_index].clock_info[0].sclk =
2698 rdev->clock.default_sclk;
2699 mode_index++;
2700 }
2701 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2702 if (mode_index) {
2703 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2704 non_clock_info);
2705 state_index++;
2706 }
2707 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2708 }
2709 /* if multiple clock modes, mark the lowest as no display */
2710 for (i = 0; i < state_index; i++) {
2711 if (rdev->pm.power_state[i].num_clock_modes > 1)
2712 rdev->pm.power_state[i].clock_info[0].flags |=
2713 RADEON_PM_MODE_NO_DISPLAY;
2714 }
2715 /* first mode is usually default */
2716 if (rdev->pm.default_power_state_index == -1) {
2717 rdev->pm.power_state[0].type =
2718 POWER_STATE_TYPE_DEFAULT;
2719 rdev->pm.default_power_state_index = 0;
2720 rdev->pm.power_state[0].default_clock_mode =
2721 &rdev->pm.power_state[0].clock_info[0];
2722 }
2723 return state_index;
2724 }
2725
2726 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2727 {
2728 struct radeon_mode_info *mode_info = &rdev->mode_info;
2729 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2730 u16 data_offset;
2731 u8 frev, crev;
2732 int state_index = 0;
2733
2734 rdev->pm.default_power_state_index = -1;
2735
2736 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2737 &frev, &crev, &data_offset)) {
2738 switch (frev) {
2739 case 1:
2740 case 2:
2741 case 3:
2742 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2743 break;
2744 case 4:
2745 case 5:
2746 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2747 break;
2748 case 6:
2749 state_index = radeon_atombios_parse_power_table_6(rdev);
2750 break;
2751 default:
2752 break;
2753 }
2754 }
2755
2756 if (state_index == 0) {
2757 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2758 if (rdev->pm.power_state) {
2759 rdev->pm.power_state[0].clock_info =
2760 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2761 if (rdev->pm.power_state[0].clock_info) {
2762 /* add the default mode */
2763 rdev->pm.power_state[state_index].type =
2764 POWER_STATE_TYPE_DEFAULT;
2765 rdev->pm.power_state[state_index].num_clock_modes = 1;
2766 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2767 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2768 rdev->pm.power_state[state_index].default_clock_mode =
2769 &rdev->pm.power_state[state_index].clock_info[0];
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2771 rdev->pm.power_state[state_index].pcie_lanes = 16;
2772 rdev->pm.default_power_state_index = state_index;
2773 rdev->pm.power_state[state_index].flags = 0;
2774 state_index++;
2775 }
2776 }
2777 }
2778
2779 rdev->pm.num_power_states = state_index;
2780
2781 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2782 rdev->pm.current_clock_mode_index = 0;
2783 if (rdev->pm.default_power_state_index >= 0)
2784 rdev->pm.current_vddc =
2785 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2786 else
2787 rdev->pm.current_vddc = 0;
2788 }
2789
2790 union get_clock_dividers {
2791 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2792 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2793 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2794 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2795 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2796 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2797 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2798 };
2799
2800 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2801 u8 clock_type,
2802 u32 clock,
2803 bool strobe_mode,
2804 struct atom_clock_dividers *dividers)
2805 {
2806 union get_clock_dividers args;
2807 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2808 u8 frev, crev;
2809
2810 memset(&args, 0, sizeof(args));
2811 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2812
2813 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2814 return -EINVAL;
2815
2816 switch (crev) {
2817 case 1:
2818 /* r4xx, r5xx */
2819 args.v1.ucAction = clock_type;
2820 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2821
2822 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2823
2824 dividers->post_div = args.v1.ucPostDiv;
2825 dividers->fb_div = args.v1.ucFbDiv;
2826 dividers->enable_post_div = true;
2827 break;
2828 case 2:
2829 case 3:
2830 case 5:
2831 /* r6xx, r7xx, evergreen, ni, si */
2832 if (rdev->family <= CHIP_RV770) {
2833 args.v2.ucAction = clock_type;
2834 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2835
2836 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2837
2838 dividers->post_div = args.v2.ucPostDiv;
2839 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2840 dividers->ref_div = args.v2.ucAction;
2841 if (rdev->family == CHIP_RV770) {
2842 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2843 true : false;
2844 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2845 } else
2846 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2847 } else {
2848 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2849 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2850
2851 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2852
2853 dividers->post_div = args.v3.ucPostDiv;
2854 dividers->enable_post_div = (args.v3.ucCntlFlag &
2855 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2856 dividers->enable_dithen = (args.v3.ucCntlFlag &
2857 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2858 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2859 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2860 dividers->ref_div = args.v3.ucRefDiv;
2861 dividers->vco_mode = (args.v3.ucCntlFlag &
2862 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2863 } else {
2864 /* for SI we use ComputeMemoryClockParam for memory plls */
2865 if (rdev->family >= CHIP_TAHITI)
2866 return -EINVAL;
2867 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2868 if (strobe_mode)
2869 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2870
2871 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2872
2873 dividers->post_div = args.v5.ucPostDiv;
2874 dividers->enable_post_div = (args.v5.ucCntlFlag &
2875 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2876 dividers->enable_dithen = (args.v5.ucCntlFlag &
2877 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2878 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2879 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2880 dividers->ref_div = args.v5.ucRefDiv;
2881 dividers->vco_mode = (args.v5.ucCntlFlag &
2882 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2883 }
2884 }
2885 break;
2886 case 4:
2887 /* fusion */
2888 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2889
2890 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2891
2892 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2893 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2894 break;
2895 case 6:
2896 /* CI */
2897 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2898 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2899 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2900
2901 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2902
2903 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2904 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2905 dividers->ref_div = args.v6_out.ucPllRefDiv;
2906 dividers->post_div = args.v6_out.ucPllPostDiv;
2907 dividers->flags = args.v6_out.ucPllCntlFlag;
2908 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2909 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2910 break;
2911 default:
2912 return -EINVAL;
2913 }
2914 return 0;
2915 }
2916
2917 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2918 u32 clock,
2919 bool strobe_mode,
2920 struct atom_mpll_param *mpll_param)
2921 {
2922 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2923 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2924 u8 frev, crev;
2925
2926 memset(&args, 0, sizeof(args));
2927 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2928
2929 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2930 return -EINVAL;
2931
2932 switch (frev) {
2933 case 2:
2934 switch (crev) {
2935 case 1:
2936 /* SI */
2937 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2938 args.ucInputFlag = 0;
2939 if (strobe_mode)
2940 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2941
2942 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2943
2944 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2945 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2946 mpll_param->post_div = args.ucPostDiv;
2947 mpll_param->dll_speed = args.ucDllSpeed;
2948 mpll_param->bwcntl = args.ucBWCntl;
2949 mpll_param->vco_mode =
2950 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2951 mpll_param->yclk_sel =
2952 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2953 mpll_param->qdr =
2954 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2955 mpll_param->half_rate =
2956 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2957 break;
2958 default:
2959 return -EINVAL;
2960 }
2961 break;
2962 default:
2963 return -EINVAL;
2964 }
2965 return 0;
2966 }
2967
2968 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2969 {
2970 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2971 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2972
2973 args.ucEnable = enable;
2974
2975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2976 }
2977
2978 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2979 {
2980 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2981 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2982
2983 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2984 return le32_to_cpu(args.ulReturnEngineClock);
2985 }
2986
2987 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2988 {
2989 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2990 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2991
2992 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2993 return le32_to_cpu(args.ulReturnMemoryClock);
2994 }
2995
2996 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2997 uint32_t eng_clock)
2998 {
2999 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3000 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3001
3002 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3003
3004 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3005 }
3006
3007 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3008 uint32_t mem_clock)
3009 {
3010 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3011 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3012
3013 if (rdev->flags & RADEON_IS_IGP)
3014 return;
3015
3016 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3017
3018 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3019 }
3020
3021 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3022 u32 eng_clock, u32 mem_clock)
3023 {
3024 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3026 u32 tmp;
3027
3028 memset(&args, 0, sizeof(args));
3029
3030 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3031 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3032
3033 args.ulTargetEngineClock = cpu_to_le32(tmp);
3034 if (mem_clock)
3035 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3036
3037 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3038 }
3039
3040 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3041 u32 mem_clock)
3042 {
3043 u32 args;
3044 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3045
3046 args = cpu_to_le32(mem_clock); /* 10 khz */
3047
3048 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3049 }
3050
3051 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3052 u32 mem_clock)
3053 {
3054 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3055 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3056 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3057
3058 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3059
3060 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3061 }
3062
3063 union set_voltage {
3064 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3065 struct _SET_VOLTAGE_PARAMETERS v1;
3066 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3067 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3068 };
3069
3070 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3071 {
3072 union set_voltage args;
3073 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3074 u8 frev, crev, volt_index = voltage_level;
3075
3076 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3077 return;
3078
3079 /* 0xff01 is a flag rather then an actual voltage */
3080 if (voltage_level == 0xff01)
3081 return;
3082
3083 switch (crev) {
3084 case 1:
3085 args.v1.ucVoltageType = voltage_type;
3086 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3087 args.v1.ucVoltageIndex = volt_index;
3088 break;
3089 case 2:
3090 args.v2.ucVoltageType = voltage_type;
3091 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3092 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3093 break;
3094 case 3:
3095 args.v3.ucVoltageType = voltage_type;
3096 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3097 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3098 break;
3099 default:
3100 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3101 return;
3102 }
3103
3104 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3105 }
3106
3107 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3108 u16 voltage_id, u16 *voltage)
3109 {
3110 union set_voltage args;
3111 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3112 u8 frev, crev;
3113
3114 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3115 return -EINVAL;
3116
3117 switch (crev) {
3118 case 1:
3119 return -EINVAL;
3120 case 2:
3121 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3122 args.v2.ucVoltageMode = 0;
3123 args.v2.usVoltageLevel = 0;
3124
3125 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3126
3127 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3128 break;
3129 case 3:
3130 args.v3.ucVoltageType = voltage_type;
3131 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3132 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3133
3134 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3135
3136 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3137 break;
3138 default:
3139 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3140 return -EINVAL;
3141 }
3142
3143 return 0;
3144 }
3145
3146 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3147 u16 *voltage,
3148 u16 leakage_idx)
3149 {
3150 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3151 }
3152
3153 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3154 u16 *leakage_id)
3155 {
3156 union set_voltage args;
3157 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3158 u8 frev, crev;
3159
3160 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3161 return -EINVAL;
3162
3163 switch (crev) {
3164 case 3:
3165 case 4:
3166 args.v3.ucVoltageType = 0;
3167 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3168 args.v3.usVoltageLevel = 0;
3169
3170 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3171
3172 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3173 break;
3174 default:
3175 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3176 return -EINVAL;
3177 }
3178
3179 return 0;
3180 }
3181
3182 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3183 u16 *vddc, u16 *vddci,
3184 u16 virtual_voltage_id,
3185 u16 vbios_voltage_id)
3186 {
3187 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3188 u8 frev, crev;
3189 u16 data_offset, size;
3190 int i, j;
3191 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3192 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3193
3194 *vddc = 0;
3195 *vddci = 0;
3196
3197 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3198 &frev, &crev, &data_offset))
3199 return -EINVAL;
3200
3201 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3202 (rdev->mode_info.atom_context->bios + data_offset);
3203
3204 switch (frev) {
3205 case 1:
3206 return -EINVAL;
3207 case 2:
3208 switch (crev) {
3209 case 1:
3210 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3211 return -EINVAL;
3212 leakage_bin = (u16 *)
3213 (rdev->mode_info.atom_context->bios + data_offset +
3214 le16_to_cpu(profile->usLeakageBinArrayOffset));
3215 vddc_id_buf = (u16 *)
3216 (rdev->mode_info.atom_context->bios + data_offset +
3217 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3218 vddc_buf = (u16 *)
3219 (rdev->mode_info.atom_context->bios + data_offset +
3220 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3221 vddci_id_buf = (u16 *)
3222 (rdev->mode_info.atom_context->bios + data_offset +
3223 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3224 vddci_buf = (u16 *)
3225 (rdev->mode_info.atom_context->bios + data_offset +
3226 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3227
3228 if (profile->ucElbVDDC_Num > 0) {
3229 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3230 if (vddc_id_buf[i] == virtual_voltage_id) {
3231 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3232 if (vbios_voltage_id <= leakage_bin[j]) {
3233 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3234 break;
3235 }
3236 }
3237 break;
3238 }
3239 }
3240 }
3241 if (profile->ucElbVDDCI_Num > 0) {
3242 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3243 if (vddci_id_buf[i] == virtual_voltage_id) {
3244 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3245 if (vbios_voltage_id <= leakage_bin[j]) {
3246 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3247 break;
3248 }
3249 }
3250 break;
3251 }
3252 }
3253 }
3254 break;
3255 default:
3256 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3257 return -EINVAL;
3258 }
3259 break;
3260 default:
3261 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3262 return -EINVAL;
3263 }
3264
3265 return 0;
3266 }
3267
3268 union get_voltage_info {
3269 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3270 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3271 };
3272
3273 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3274 u16 virtual_voltage_id,
3275 u16 *voltage)
3276 {
3277 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3278 u32 entry_id;
3279 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3280 union get_voltage_info args;
3281
3282 for (entry_id = 0; entry_id < count; entry_id++) {
3283 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3284 virtual_voltage_id)
3285 break;
3286 }
3287
3288 if (entry_id >= count)
3289 return -EINVAL;
3290
3291 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3292 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3293 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3294 args.in.ulSCLKFreq =
3295 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3296
3297 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3298
3299 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3300
3301 return 0;
3302 }
3303
3304 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3305 u16 voltage_level, u8 voltage_type,
3306 u32 *gpio_value, u32 *gpio_mask)
3307 {
3308 union set_voltage args;
3309 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3310 u8 frev, crev;
3311
3312 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3313 return -EINVAL;
3314
3315 switch (crev) {
3316 case 1:
3317 return -EINVAL;
3318 case 2:
3319 args.v2.ucVoltageType = voltage_type;
3320 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3321 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3322
3323 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3324
3325 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3326
3327 args.v2.ucVoltageType = voltage_type;
3328 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3329 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3330
3331 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3332
3333 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3334 break;
3335 default:
3336 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3337 return -EINVAL;
3338 }
3339
3340 return 0;
3341 }
3342
3343 union voltage_object_info {
3344 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3345 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3346 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3347 };
3348
3349 union voltage_object {
3350 struct _ATOM_VOLTAGE_OBJECT v1;
3351 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3352 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3353 };
3354
3355 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3356 u8 voltage_type)
3357 {
3358 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3359 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3360 u8 *start = (u8 *)v1;
3361
3362 while (offset < size) {
3363 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3364 if (vo->ucVoltageType == voltage_type)
3365 return vo;
3366 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3367 vo->asFormula.ucNumOfVoltageEntries;
3368 }
3369 return NULL;
3370 }
3371
3372 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3373 u8 voltage_type)
3374 {
3375 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3376 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3377 u8 *start = (u8*)v2;
3378
3379 while (offset < size) {
3380 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3381 if (vo->ucVoltageType == voltage_type)
3382 return vo;
3383 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3384 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3385 }
3386 return NULL;
3387 }
3388
3389 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3390 u8 voltage_type, u8 voltage_mode)
3391 {
3392 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3393 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3394 u8 *start = (u8*)v3;
3395
3396 while (offset < size) {
3397 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3398 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3399 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3400 return vo;
3401 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3402 }
3403 return NULL;
3404 }
3405
3406 bool
3407 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3408 u8 voltage_type, u8 voltage_mode)
3409 {
3410 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3411 u8 frev, crev;
3412 u16 data_offset, size;
3413 union voltage_object_info *voltage_info;
3414 union voltage_object *voltage_object = NULL;
3415
3416 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3417 &frev, &crev, &data_offset)) {
3418 voltage_info = (union voltage_object_info *)
3419 (rdev->mode_info.atom_context->bios + data_offset);
3420
3421 switch (frev) {
3422 case 1:
3423 case 2:
3424 switch (crev) {
3425 case 1:
3426 voltage_object = (union voltage_object *)
3427 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3428 if (voltage_object &&
3429 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3430 return true;
3431 break;
3432 case 2:
3433 voltage_object = (union voltage_object *)
3434 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3435 if (voltage_object &&
3436 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3437 return true;
3438 break;
3439 default:
3440 DRM_ERROR("unknown voltage object table\n");
3441 return false;
3442 }
3443 break;
3444 case 3:
3445 switch (crev) {
3446 case 1:
3447 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3448 voltage_type, voltage_mode))
3449 return true;
3450 break;
3451 default:
3452 DRM_ERROR("unknown voltage object table\n");
3453 return false;
3454 }
3455 break;
3456 default:
3457 DRM_ERROR("unknown voltage object table\n");
3458 return false;
3459 }
3460
3461 }
3462 return false;
3463 }
3464
3465 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3466 u8 voltage_type,
3467 u8 *svd_gpio_id, u8 *svc_gpio_id)
3468 {
3469 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3470 u8 frev, crev;
3471 u16 data_offset, size;
3472 union voltage_object_info *voltage_info;
3473 union voltage_object *voltage_object = NULL;
3474
3475 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3476 &frev, &crev, &data_offset)) {
3477 voltage_info = (union voltage_object_info *)
3478 (rdev->mode_info.atom_context->bios + data_offset);
3479
3480 switch (frev) {
3481 case 3:
3482 switch (crev) {
3483 case 1:
3484 voltage_object = (union voltage_object *)
3485 atom_lookup_voltage_object_v3(&voltage_info->v3,
3486 voltage_type,
3487 VOLTAGE_OBJ_SVID2);
3488 if (voltage_object) {
3489 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3490 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3491 } else {
3492 return -EINVAL;
3493 }
3494 break;
3495 default:
3496 DRM_ERROR("unknown voltage object table\n");
3497 return -EINVAL;
3498 }
3499 break;
3500 default:
3501 DRM_ERROR("unknown voltage object table\n");
3502 return -EINVAL;
3503 }
3504
3505 }
3506 return 0;
3507 }
3508
3509 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3510 u8 voltage_type, u16 *max_voltage)
3511 {
3512 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3513 u8 frev, crev;
3514 u16 data_offset, size;
3515 union voltage_object_info *voltage_info;
3516 union voltage_object *voltage_object = NULL;
3517
3518 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3519 &frev, &crev, &data_offset)) {
3520 voltage_info = (union voltage_object_info *)
3521 (rdev->mode_info.atom_context->bios + data_offset);
3522
3523 switch (crev) {
3524 case 1:
3525 voltage_object = (union voltage_object *)
3526 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3527 if (voltage_object) {
3528 ATOM_VOLTAGE_FORMULA *formula =
3529 &voltage_object->v1.asFormula;
3530 if (formula->ucFlag & 1)
3531 *max_voltage =
3532 le16_to_cpu(formula->usVoltageBaseLevel) +
3533 formula->ucNumOfVoltageEntries / 2 *
3534 le16_to_cpu(formula->usVoltageStep);
3535 else
3536 *max_voltage =
3537 le16_to_cpu(formula->usVoltageBaseLevel) +
3538 (formula->ucNumOfVoltageEntries - 1) *
3539 le16_to_cpu(formula->usVoltageStep);
3540 return 0;
3541 }
3542 break;
3543 case 2:
3544 voltage_object = (union voltage_object *)
3545 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3546 if (voltage_object) {
3547 ATOM_VOLTAGE_FORMULA_V2 *formula =
3548 &voltage_object->v2.asFormula;
3549 if (formula->ucNumOfVoltageEntries) {
3550 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3551 ((u8 *)&formula->asVIDAdjustEntries[0] +
3552 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3553 *max_voltage =
3554 le16_to_cpu(lut->usVoltageValue);
3555 return 0;
3556 }
3557 }
3558 break;
3559 default:
3560 DRM_ERROR("unknown voltage object table\n");
3561 return -EINVAL;
3562 }
3563
3564 }
3565 return -EINVAL;
3566 }
3567
3568 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3569 u8 voltage_type, u16 *min_voltage)
3570 {
3571 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3572 u8 frev, crev;
3573 u16 data_offset, size;
3574 union voltage_object_info *voltage_info;
3575 union voltage_object *voltage_object = NULL;
3576
3577 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3578 &frev, &crev, &data_offset)) {
3579 voltage_info = (union voltage_object_info *)
3580 (rdev->mode_info.atom_context->bios + data_offset);
3581
3582 switch (crev) {
3583 case 1:
3584 voltage_object = (union voltage_object *)
3585 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3586 if (voltage_object) {
3587 ATOM_VOLTAGE_FORMULA *formula =
3588 &voltage_object->v1.asFormula;
3589 *min_voltage =
3590 le16_to_cpu(formula->usVoltageBaseLevel);
3591 return 0;
3592 }
3593 break;
3594 case 2:
3595 voltage_object = (union voltage_object *)
3596 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3597 if (voltage_object) {
3598 ATOM_VOLTAGE_FORMULA_V2 *formula =
3599 &voltage_object->v2.asFormula;
3600 if (formula->ucNumOfVoltageEntries) {
3601 *min_voltage =
3602 le16_to_cpu(formula->asVIDAdjustEntries[
3603 0
3604 ].usVoltageValue);
3605 return 0;
3606 }
3607 }
3608 break;
3609 default:
3610 DRM_ERROR("unknown voltage object table\n");
3611 return -EINVAL;
3612 }
3613
3614 }
3615 return -EINVAL;
3616 }
3617
3618 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3619 u8 voltage_type, u16 *voltage_step)
3620 {
3621 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3622 u8 frev, crev;
3623 u16 data_offset, size;
3624 union voltage_object_info *voltage_info;
3625 union voltage_object *voltage_object = NULL;
3626
3627 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3628 &frev, &crev, &data_offset)) {
3629 voltage_info = (union voltage_object_info *)
3630 (rdev->mode_info.atom_context->bios + data_offset);
3631
3632 switch (crev) {
3633 case 1:
3634 voltage_object = (union voltage_object *)
3635 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3636 if (voltage_object) {
3637 ATOM_VOLTAGE_FORMULA *formula =
3638 &voltage_object->v1.asFormula;
3639 if (formula->ucFlag & 1)
3640 *voltage_step =
3641 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3642 else
3643 *voltage_step =
3644 le16_to_cpu(formula->usVoltageStep);
3645 return 0;
3646 }
3647 break;
3648 case 2:
3649 return -EINVAL;
3650 default:
3651 DRM_ERROR("unknown voltage object table\n");
3652 return -EINVAL;
3653 }
3654
3655 }
3656 return -EINVAL;
3657 }
3658
3659 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3660 u8 voltage_type,
3661 u16 nominal_voltage,
3662 u16 *true_voltage)
3663 {
3664 u16 min_voltage, max_voltage, voltage_step;
3665
3666 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3667 return -EINVAL;
3668 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3669 return -EINVAL;
3670 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3671 return -EINVAL;
3672
3673 if (nominal_voltage <= min_voltage)
3674 *true_voltage = min_voltage;
3675 else if (nominal_voltage >= max_voltage)
3676 *true_voltage = max_voltage;
3677 else
3678 *true_voltage = min_voltage +
3679 ((nominal_voltage - min_voltage) / voltage_step) *
3680 voltage_step;
3681
3682 return 0;
3683 }
3684
3685 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3686 u8 voltage_type, u8 voltage_mode,
3687 struct atom_voltage_table *voltage_table)
3688 {
3689 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3690 u8 frev, crev;
3691 u16 data_offset, size;
3692 int i, ret;
3693 union voltage_object_info *voltage_info;
3694 union voltage_object *voltage_object = NULL;
3695
3696 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3697 &frev, &crev, &data_offset)) {
3698 voltage_info = (union voltage_object_info *)
3699 (rdev->mode_info.atom_context->bios + data_offset);
3700
3701 switch (frev) {
3702 case 1:
3703 case 2:
3704 switch (crev) {
3705 case 1:
3706 DRM_ERROR("old table version %d, %d\n", frev, crev);
3707 return -EINVAL;
3708 case 2:
3709 voltage_object = (union voltage_object *)
3710 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3711 if (voltage_object) {
3712 ATOM_VOLTAGE_FORMULA_V2 *formula =
3713 &voltage_object->v2.asFormula;
3714 VOLTAGE_LUT_ENTRY *lut;
3715 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3716 return -EINVAL;
3717 lut = &formula->asVIDAdjustEntries[0];
3718 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3719 voltage_table->entries[i].value =
3720 le16_to_cpu(lut->usVoltageValue);
3721 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3722 voltage_table->entries[i].value,
3723 voltage_type,
3724 &voltage_table->entries[i].smio_low,
3725 &voltage_table->mask_low);
3726 if (ret)
3727 return ret;
3728 lut = (VOLTAGE_LUT_ENTRY *)
3729 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3730 }
3731 voltage_table->count = formula->ucNumOfVoltageEntries;
3732 return 0;
3733 }
3734 break;
3735 default:
3736 DRM_ERROR("unknown voltage object table\n");
3737 return -EINVAL;
3738 }
3739 break;
3740 case 3:
3741 switch (crev) {
3742 case 1:
3743 voltage_object = (union voltage_object *)
3744 atom_lookup_voltage_object_v3(&voltage_info->v3,
3745 voltage_type, voltage_mode);
3746 if (voltage_object) {
3747 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3748 &voltage_object->v3.asGpioVoltageObj;
3749 VOLTAGE_LUT_ENTRY_V2 *lut;
3750 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3751 return -EINVAL;
3752 lut = &gpio->asVolGpioLut[0];
3753 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3754 voltage_table->entries[i].value =
3755 le16_to_cpu(lut->usVoltageValue);
3756 voltage_table->entries[i].smio_low =
3757 le32_to_cpu(lut->ulVoltageId);
3758 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3759 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3760 }
3761 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3762 voltage_table->count = gpio->ucGpioEntryNum;
3763 voltage_table->phase_delay = gpio->ucPhaseDelay;
3764 return 0;
3765 }
3766 break;
3767 default:
3768 DRM_ERROR("unknown voltage object table\n");
3769 return -EINVAL;
3770 }
3771 break;
3772 default:
3773 DRM_ERROR("unknown voltage object table\n");
3774 return -EINVAL;
3775 }
3776 }
3777 return -EINVAL;
3778 }
3779
3780 union vram_info {
3781 struct _ATOM_VRAM_INFO_V3 v1_3;
3782 struct _ATOM_VRAM_INFO_V4 v1_4;
3783 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3784 };
3785
3786 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3787 u8 module_index, struct atom_memory_info *mem_info)
3788 {
3789 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3790 u8 frev, crev, i;
3791 u16 data_offset, size;
3792 union vram_info *vram_info;
3793
3794 memset(mem_info, 0, sizeof(struct atom_memory_info));
3795
3796 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3797 &frev, &crev, &data_offset)) {
3798 vram_info = (union vram_info *)
3799 (rdev->mode_info.atom_context->bios + data_offset);
3800 switch (frev) {
3801 case 1:
3802 switch (crev) {
3803 case 3:
3804 /* r6xx */
3805 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3806 ATOM_VRAM_MODULE_V3 *vram_module =
3807 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3808
3809 for (i = 0; i < module_index; i++) {
3810 if (le16_to_cpu(vram_module->usSize) == 0)
3811 return -EINVAL;
3812 vram_module = (ATOM_VRAM_MODULE_V3 *)
3813 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3814 }
3815 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3816 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3817 } else
3818 return -EINVAL;
3819 break;
3820 case 4:
3821 /* r7xx, evergreen */
3822 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3823 ATOM_VRAM_MODULE_V4 *vram_module =
3824 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3825
3826 for (i = 0; i < module_index; i++) {
3827 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3828 return -EINVAL;
3829 vram_module = (ATOM_VRAM_MODULE_V4 *)
3830 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3831 }
3832 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3833 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3834 } else
3835 return -EINVAL;
3836 break;
3837 default:
3838 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3839 return -EINVAL;
3840 }
3841 break;
3842 case 2:
3843 switch (crev) {
3844 case 1:
3845 /* ni */
3846 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3847 ATOM_VRAM_MODULE_V7 *vram_module =
3848 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3849
3850 for (i = 0; i < module_index; i++) {
3851 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3852 return -EINVAL;
3853 vram_module = (ATOM_VRAM_MODULE_V7 *)
3854 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3855 }
3856 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3857 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3858 } else
3859 return -EINVAL;
3860 break;
3861 default:
3862 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3863 return -EINVAL;
3864 }
3865 break;
3866 default:
3867 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3868 return -EINVAL;
3869 }
3870 return 0;
3871 }
3872 return -EINVAL;
3873 }
3874
3875 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3876 bool gddr5, u8 module_index,
3877 struct atom_memory_clock_range_table *mclk_range_table)
3878 {
3879 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3880 u8 frev, crev, i;
3881 u16 data_offset, size;
3882 union vram_info *vram_info;
3883 u32 mem_timing_size = gddr5 ?
3884 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3885
3886 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3887
3888 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3889 &frev, &crev, &data_offset)) {
3890 vram_info = (union vram_info *)
3891 (rdev->mode_info.atom_context->bios + data_offset);
3892 switch (frev) {
3893 case 1:
3894 switch (crev) {
3895 case 3:
3896 DRM_ERROR("old table version %d, %d\n", frev, crev);
3897 return -EINVAL;
3898 case 4:
3899 /* r7xx, evergreen */
3900 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3901 ATOM_VRAM_MODULE_V4 *vram_module =
3902 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3903 ATOM_MEMORY_TIMING_FORMAT *format;
3904
3905 for (i = 0; i < module_index; i++) {
3906 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3907 return -EINVAL;
3908 vram_module = (ATOM_VRAM_MODULE_V4 *)
3909 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3910 }
3911 mclk_range_table->num_entries = (u8)
3912 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3913 mem_timing_size);
3914 format = &vram_module->asMemTiming[0];
3915 for (i = 0; i < mclk_range_table->num_entries; i++) {
3916 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3917 format = (ATOM_MEMORY_TIMING_FORMAT *)
3918 ((u8 *)format + mem_timing_size);
3919 }
3920 } else
3921 return -EINVAL;
3922 break;
3923 default:
3924 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3925 return -EINVAL;
3926 }
3927 break;
3928 case 2:
3929 DRM_ERROR("new table version %d, %d\n", frev, crev);
3930 return -EINVAL;
3931 default:
3932 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3933 return -EINVAL;
3934 }
3935 return 0;
3936 }
3937 return -EINVAL;
3938 }
3939
3940 #define MEM_ID_MASK 0xff000000
3941 #define MEM_ID_SHIFT 24
3942 #define CLOCK_RANGE_MASK 0x00ffffff
3943 #define CLOCK_RANGE_SHIFT 0
3944 #define LOW_NIBBLE_MASK 0xf
3945 #define DATA_EQU_PREV 0
3946 #define DATA_FROM_TABLE 4
3947
3948 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3949 u8 module_index,
3950 struct atom_mc_reg_table *reg_table)
3951 {
3952 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3953 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3954 u32 i = 0, j;
3955 u16 data_offset, size;
3956 union vram_info *vram_info;
3957
3958 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3959
3960 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3961 &frev, &crev, &data_offset)) {
3962 vram_info = (union vram_info *)
3963 (rdev->mode_info.atom_context->bios + data_offset);
3964 switch (frev) {
3965 case 1:
3966 DRM_ERROR("old table version %d, %d\n", frev, crev);
3967 return -EINVAL;
3968 case 2:
3969 switch (crev) {
3970 case 1:
3971 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3972 ATOM_INIT_REG_BLOCK *reg_block =
3973 (ATOM_INIT_REG_BLOCK *)
3974 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3975 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
3976 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
3977 ((u8 *)reg_block + (2 * sizeof(u16)) +
3978 le16_to_cpu(reg_block->usRegIndexTblSize));
3979 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
3980 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
3981 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
3982 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
3983 return -EINVAL;
3984 while (i < num_entries) {
3985 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
3986 break;
3987 reg_table->mc_reg_address[i].s1 =
3988 (u16)(le16_to_cpu(format->usRegIndex));
3989 reg_table->mc_reg_address[i].pre_reg_data =
3990 (u8)(format->ucPreRegDataLength);
3991 i++;
3992 format = (ATOM_INIT_REG_INDEX_FORMAT *)
3993 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
3994 }
3995 reg_table->last = i;
3996 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
3997 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
3998 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
3999 >> MEM_ID_SHIFT);
4000 if (module_index == t_mem_id) {
4001 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4002 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4003 >> CLOCK_RANGE_SHIFT);
4004 for (i = 0, j = 1; i < reg_table->last; i++) {
4005 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4006 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4007 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4008 j++;
4009 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4010 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4011 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4012 }
4013 }
4014 num_ranges++;
4015 }
4016 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4017 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4018 }
4019 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4020 return -EINVAL;
4021 reg_table->num_entries = num_ranges;
4022 } else
4023 return -EINVAL;
4024 break;
4025 default:
4026 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4027 return -EINVAL;
4028 }
4029 break;
4030 default:
4031 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4032 return -EINVAL;
4033 }
4034 return 0;
4035 }
4036 return -EINVAL;
4037 }
4038
4039 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4040 {
4041 struct radeon_device *rdev = dev->dev_private;
4042 uint32_t bios_2_scratch, bios_6_scratch;
4043
4044 if (rdev->family >= CHIP_R600) {
4045 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4046 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4047 } else {
4048 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4049 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4050 }
4051
4052 /* let the bios control the backlight */
4053 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4054
4055 /* tell the bios not to handle mode switching */
4056 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4057
4058 /* clear the vbios dpms state */
4059 if (ASIC_IS_DCE4(rdev))
4060 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4061
4062 if (rdev->family >= CHIP_R600) {
4063 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4064 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4065 } else {
4066 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4067 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4068 }
4069
4070 }
4071
4072 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4073 {
4074 uint32_t scratch_reg;
4075 int i;
4076
4077 if (rdev->family >= CHIP_R600)
4078 scratch_reg = R600_BIOS_0_SCRATCH;
4079 else
4080 scratch_reg = RADEON_BIOS_0_SCRATCH;
4081
4082 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4083 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4084 }
4085
4086 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4087 {
4088 uint32_t scratch_reg;
4089 int i;
4090
4091 if (rdev->family >= CHIP_R600)
4092 scratch_reg = R600_BIOS_0_SCRATCH;
4093 else
4094 scratch_reg = RADEON_BIOS_0_SCRATCH;
4095
4096 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4097 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4098 }
4099
4100 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4101 {
4102 struct drm_device *dev = encoder->dev;
4103 struct radeon_device *rdev = dev->dev_private;
4104 uint32_t bios_6_scratch;
4105
4106 if (rdev->family >= CHIP_R600)
4107 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4108 else
4109 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4110
4111 if (lock) {
4112 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4113 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4114 } else {
4115 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4116 bios_6_scratch |= ATOM_S6_ACC_MODE;
4117 }
4118
4119 if (rdev->family >= CHIP_R600)
4120 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4121 else
4122 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4123 }
4124
4125 /* at some point we may want to break this out into individual functions */
4126 void
4127 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4128 struct drm_encoder *encoder,
4129 bool connected)
4130 {
4131 struct drm_device *dev = connector->dev;
4132 struct radeon_device *rdev = dev->dev_private;
4133 struct radeon_connector *radeon_connector =
4134 to_radeon_connector(connector);
4135 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4136 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4137
4138 if (rdev->family >= CHIP_R600) {
4139 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4140 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4141 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4142 } else {
4143 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4144 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4145 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4146 }
4147
4148 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4149 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4150 if (connected) {
4151 DRM_DEBUG_KMS("TV1 connected\n");
4152 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4153 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4154 } else {
4155 DRM_DEBUG_KMS("TV1 disconnected\n");
4156 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4157 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4158 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4159 }
4160 }
4161 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4162 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4163 if (connected) {
4164 DRM_DEBUG_KMS("CV connected\n");
4165 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4166 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4167 } else {
4168 DRM_DEBUG_KMS("CV disconnected\n");
4169 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4170 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4171 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4172 }
4173 }
4174 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4175 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4176 if (connected) {
4177 DRM_DEBUG_KMS("LCD1 connected\n");
4178 bios_0_scratch |= ATOM_S0_LCD1;
4179 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4180 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4181 } else {
4182 DRM_DEBUG_KMS("LCD1 disconnected\n");
4183 bios_0_scratch &= ~ATOM_S0_LCD1;
4184 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4185 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4186 }
4187 }
4188 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4189 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4190 if (connected) {
4191 DRM_DEBUG_KMS("CRT1 connected\n");
4192 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4193 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4194 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4195 } else {
4196 DRM_DEBUG_KMS("CRT1 disconnected\n");
4197 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4198 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4199 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4200 }
4201 }
4202 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4203 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4204 if (connected) {
4205 DRM_DEBUG_KMS("CRT2 connected\n");
4206 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4207 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4208 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4209 } else {
4210 DRM_DEBUG_KMS("CRT2 disconnected\n");
4211 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4212 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4213 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4214 }
4215 }
4216 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4217 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4218 if (connected) {
4219 DRM_DEBUG_KMS("DFP1 connected\n");
4220 bios_0_scratch |= ATOM_S0_DFP1;
4221 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4222 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4223 } else {
4224 DRM_DEBUG_KMS("DFP1 disconnected\n");
4225 bios_0_scratch &= ~ATOM_S0_DFP1;
4226 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4227 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4228 }
4229 }
4230 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4231 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4232 if (connected) {
4233 DRM_DEBUG_KMS("DFP2 connected\n");
4234 bios_0_scratch |= ATOM_S0_DFP2;
4235 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4236 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4237 } else {
4238 DRM_DEBUG_KMS("DFP2 disconnected\n");
4239 bios_0_scratch &= ~ATOM_S0_DFP2;
4240 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4241 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4242 }
4243 }
4244 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4245 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4246 if (connected) {
4247 DRM_DEBUG_KMS("DFP3 connected\n");
4248 bios_0_scratch |= ATOM_S0_DFP3;
4249 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4250 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4251 } else {
4252 DRM_DEBUG_KMS("DFP3 disconnected\n");
4253 bios_0_scratch &= ~ATOM_S0_DFP3;
4254 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4255 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4256 }
4257 }
4258 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4259 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4260 if (connected) {
4261 DRM_DEBUG_KMS("DFP4 connected\n");
4262 bios_0_scratch |= ATOM_S0_DFP4;
4263 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4264 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4265 } else {
4266 DRM_DEBUG_KMS("DFP4 disconnected\n");
4267 bios_0_scratch &= ~ATOM_S0_DFP4;
4268 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4269 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4270 }
4271 }
4272 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4273 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4274 if (connected) {
4275 DRM_DEBUG_KMS("DFP5 connected\n");
4276 bios_0_scratch |= ATOM_S0_DFP5;
4277 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4278 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4279 } else {
4280 DRM_DEBUG_KMS("DFP5 disconnected\n");
4281 bios_0_scratch &= ~ATOM_S0_DFP5;
4282 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4283 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4284 }
4285 }
4286 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4287 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4288 if (connected) {
4289 DRM_DEBUG_KMS("DFP6 connected\n");
4290 bios_0_scratch |= ATOM_S0_DFP6;
4291 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4292 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4293 } else {
4294 DRM_DEBUG_KMS("DFP6 disconnected\n");
4295 bios_0_scratch &= ~ATOM_S0_DFP6;
4296 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4297 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4298 }
4299 }
4300
4301 if (rdev->family >= CHIP_R600) {
4302 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4303 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4304 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4305 } else {
4306 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4307 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4308 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4309 }
4310 }
4311
4312 void
4313 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4314 {
4315 struct drm_device *dev = encoder->dev;
4316 struct radeon_device *rdev = dev->dev_private;
4317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4318 uint32_t bios_3_scratch;
4319
4320 if (ASIC_IS_DCE4(rdev))
4321 return;
4322
4323 if (rdev->family >= CHIP_R600)
4324 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4325 else
4326 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4327
4328 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4329 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4330 bios_3_scratch |= (crtc << 18);
4331 }
4332 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4333 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4334 bios_3_scratch |= (crtc << 24);
4335 }
4336 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4337 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4338 bios_3_scratch |= (crtc << 16);
4339 }
4340 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4341 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4342 bios_3_scratch |= (crtc << 20);
4343 }
4344 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4345 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4346 bios_3_scratch |= (crtc << 17);
4347 }
4348 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4349 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4350 bios_3_scratch |= (crtc << 19);
4351 }
4352 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4353 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4354 bios_3_scratch |= (crtc << 23);
4355 }
4356 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4357 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4358 bios_3_scratch |= (crtc << 25);
4359 }
4360
4361 if (rdev->family >= CHIP_R600)
4362 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4363 else
4364 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4365 }
4366
4367 void
4368 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4369 {
4370 struct drm_device *dev = encoder->dev;
4371 struct radeon_device *rdev = dev->dev_private;
4372 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4373 uint32_t bios_2_scratch;
4374
4375 if (ASIC_IS_DCE4(rdev))
4376 return;
4377
4378 if (rdev->family >= CHIP_R600)
4379 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4380 else
4381 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4382
4383 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4384 if (on)
4385 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4386 else
4387 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4388 }
4389 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4390 if (on)
4391 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4392 else
4393 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4394 }
4395 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4396 if (on)
4397 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4398 else
4399 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4400 }
4401 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4402 if (on)
4403 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4404 else
4405 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4406 }
4407 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4408 if (on)
4409 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4410 else
4411 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4412 }
4413 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4414 if (on)
4415 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4416 else
4417 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4418 }
4419 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4420 if (on)
4421 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4422 else
4423 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4424 }
4425 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4426 if (on)
4427 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4428 else
4429 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4430 }
4431 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4432 if (on)
4433 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4434 else
4435 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4436 }
4437 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4438 if (on)
4439 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4440 else
4441 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4442 }
4443
4444 if (rdev->family >= CHIP_R600)
4445 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4446 else
4447 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4448 }
Linux with added FPC-III support