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Linux 4.1.16
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / rs690.c
blob516ca27cfa12847e904bd9f8ecb8047db53bdba5
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <drm/drmP.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "radeon_audio.h"
32 #include "atom.h"
33 #include "rs690d.h"
34
35 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
36 {
37 unsigned i;
38 uint32_t tmp;
39
40 for (i = 0; i < rdev->usec_timeout; i++) {
41 /* read MC_STATUS */
42 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
43 if (G_000090_MC_SYSTEM_IDLE(tmp))
44 return 0;
45 udelay(1);
46 }
47 return -1;
48 }
49
50 static void rs690_gpu_init(struct radeon_device *rdev)
51 {
52 /* FIXME: is this correct ? */
53 r420_pipes_init(rdev);
54 if (rs690_mc_wait_for_idle(rdev)) {
55 printk(KERN_WARNING "Failed to wait MC idle while "
56 "programming pipes. Bad things might happen.\n");
57 }
58 }
59
60 union igp_info {
61 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
62 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
63 };
64
65 void rs690_pm_info(struct radeon_device *rdev)
66 {
67 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
68 union igp_info *info;
69 uint16_t data_offset;
70 uint8_t frev, crev;
71 fixed20_12 tmp;
72
73 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
74 &frev, &crev, &data_offset)) {
75 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
76
77 /* Get various system informations from bios */
78 switch (crev) {
79 case 1:
80 tmp.full = dfixed_const(100);
81 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
82 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
83 if (le16_to_cpu(info->info.usK8MemoryClock))
84 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
85 else if (rdev->clock.default_mclk) {
86 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
87 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
88 } else
89 rdev->pm.igp_system_mclk.full = dfixed_const(400);
90 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
91 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
92 break;
93 case 2:
94 tmp.full = dfixed_const(100);
95 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
96 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
97 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
98 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
99 else if (rdev->clock.default_mclk)
100 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
101 else
102 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
105 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
106 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
107 break;
108 default:
109 /* We assume the slower possible clock ie worst case */
110 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
111 rdev->pm.igp_system_mclk.full = dfixed_const(200);
112 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
113 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
114 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
115 break;
116 }
117 } else {
118 /* We assume the slower possible clock ie worst case */
119 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
120 rdev->pm.igp_system_mclk.full = dfixed_const(200);
121 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
122 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
123 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
124 }
125 /* Compute various bandwidth */
126 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
127 tmp.full = dfixed_const(4);
128 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
129 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
130 * = ht_clk * ht_width / 5
131 */
132 tmp.full = dfixed_const(5);
133 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
134 rdev->pm.igp_ht_link_width);
135 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
136 if (tmp.full < rdev->pm.max_bandwidth.full) {
137 /* HT link is a limiting factor */
138 rdev->pm.max_bandwidth.full = tmp.full;
139 }
140 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
141 * = (sideport_clk * 14) / 10
142 */
143 tmp.full = dfixed_const(14);
144 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
145 tmp.full = dfixed_const(10);
146 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
147 }
148
149 static void rs690_mc_init(struct radeon_device *rdev)
150 {
151 u64 base;
152 uint32_t h_addr, l_addr;
153 unsigned long long k8_addr;
154
155 rs400_gart_adjust_size(rdev);
156 rdev->mc.vram_is_ddr = true;
157 rdev->mc.vram_width = 128;
158 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
159 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
160 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
161 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
162 rdev->mc.visible_vram_size = rdev->mc.aper_size;
163 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
164 base = G_000100_MC_FB_START(base) << 16;
165 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
166 /* Some boards seem to be configured for 128MB of sideport memory,
167 * but really only have 64MB. Just skip the sideport and use
168 * UMA memory.
169 */
170 if (rdev->mc.igp_sideport_enabled &&
171 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
172 base += 128 * 1024 * 1024;
173 rdev->mc.real_vram_size -= 128 * 1024 * 1024;
174 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
175 }
176
177 /* Use K8 direct mapping for fast fb access. */
178 rdev->fastfb_working = false;
179 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
180 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
181 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
182 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
183 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
184 #endif
185 {
186 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
187 * memory is present.
188 */
189 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
190 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
191 (unsigned long long)rdev->mc.aper_base, k8_addr);
192 rdev->mc.aper_base = (resource_size_t)k8_addr;
193 rdev->fastfb_working = true;
194 }
195 }
196
197 rs690_pm_info(rdev);
198 radeon_vram_location(rdev, &rdev->mc, base);
199 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
200 radeon_gtt_location(rdev, &rdev->mc);
201 radeon_update_bandwidth_info(rdev);
202 }
203
204 void rs690_line_buffer_adjust(struct radeon_device *rdev,
205 struct drm_display_mode *mode1,
206 struct drm_display_mode *mode2)
207 {
208 u32 tmp;
209
210 /*
211 * Line Buffer Setup
212 * There is a single line buffer shared by both display controllers.
213 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
214 * the display controllers. The paritioning can either be done
215 * manually or via one of four preset allocations specified in bits 1:0:
216 * 0 - line buffer is divided in half and shared between crtc
217 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
218 * 2 - D1 gets the whole buffer
219 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
220 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
221 * allocation mode. In manual allocation mode, D1 always starts at 0,
222 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
223 */
224 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
225 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
226 /* auto */
227 if (mode1 && mode2) {
228 if (mode1->hdisplay > mode2->hdisplay) {
229 if (mode1->hdisplay > 2560)
230 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
231 else
232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
233 } else if (mode2->hdisplay > mode1->hdisplay) {
234 if (mode2->hdisplay > 2560)
235 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
236 else
237 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
238 } else
239 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
240 } else if (mode1) {
241 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
242 } else if (mode2) {
243 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
244 }
245 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
246 }
247
248 struct rs690_watermark {
249 u32 lb_request_fifo_depth;
250 fixed20_12 num_line_pair;
251 fixed20_12 estimated_width;
252 fixed20_12 worst_case_latency;
253 fixed20_12 consumption_rate;
254 fixed20_12 active_time;
255 fixed20_12 dbpp;
256 fixed20_12 priority_mark_max;
257 fixed20_12 priority_mark;
258 fixed20_12 sclk;
259 };
260
261 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
262 struct radeon_crtc *crtc,
263 struct rs690_watermark *wm,
264 bool low)
265 {
266 struct drm_display_mode *mode = &crtc->base.mode;
267 fixed20_12 a, b, c;
268 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
269 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
270 fixed20_12 sclk, core_bandwidth, max_bandwidth;
271 u32 selected_sclk;
272
273 if (!crtc->base.enabled) {
274 /* FIXME: wouldn't it better to set priority mark to maximum */
275 wm->lb_request_fifo_depth = 4;
276 return;
277 }
278
279 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
280 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
281 selected_sclk = radeon_dpm_get_sclk(rdev, low);
282 else
283 selected_sclk = rdev->pm.current_sclk;
284
285 /* sclk in Mhz */
286 a.full = dfixed_const(100);
287 sclk.full = dfixed_const(selected_sclk);
288 sclk.full = dfixed_div(sclk, a);
289
290 /* core_bandwidth = sclk(Mhz) * 16 */
291 a.full = dfixed_const(16);
292 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
293
294 if (crtc->vsc.full > dfixed_const(2))
295 wm->num_line_pair.full = dfixed_const(2);
296 else
297 wm->num_line_pair.full = dfixed_const(1);
298
299 b.full = dfixed_const(mode->crtc_hdisplay);
300 c.full = dfixed_const(256);
301 a.full = dfixed_div(b, c);
302 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
303 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
304 if (a.full < dfixed_const(4)) {
305 wm->lb_request_fifo_depth = 4;
306 } else {
307 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
308 }
309
310 /* Determine consumption rate
311 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
312 * vtaps = number of vertical taps,
313 * vsc = vertical scaling ratio, defined as source/destination
314 * hsc = horizontal scaling ration, defined as source/destination
315 */
316 a.full = dfixed_const(mode->clock);
317 b.full = dfixed_const(1000);
318 a.full = dfixed_div(a, b);
319 pclk.full = dfixed_div(b, a);
320 if (crtc->rmx_type != RMX_OFF) {
321 b.full = dfixed_const(2);
322 if (crtc->vsc.full > b.full)
323 b.full = crtc->vsc.full;
324 b.full = dfixed_mul(b, crtc->hsc);
325 c.full = dfixed_const(2);
326 b.full = dfixed_div(b, c);
327 consumption_time.full = dfixed_div(pclk, b);
328 } else {
329 consumption_time.full = pclk.full;
330 }
331 a.full = dfixed_const(1);
332 wm->consumption_rate.full = dfixed_div(a, consumption_time);
333
334
335 /* Determine line time
336 * LineTime = total time for one line of displayhtotal
337 * LineTime = total number of horizontal pixels
338 * pclk = pixel clock period(ns)
339 */
340 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
341 line_time.full = dfixed_mul(a, pclk);
342
343 /* Determine active time
344 * ActiveTime = time of active region of display within one line,
345 * hactive = total number of horizontal active pixels
346 * htotal = total number of horizontal pixels
347 */
348 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
349 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
350 wm->active_time.full = dfixed_mul(line_time, b);
351 wm->active_time.full = dfixed_div(wm->active_time, a);
352
353 /* Maximun bandwidth is the minimun bandwidth of all component */
354 max_bandwidth = core_bandwidth;
355 if (rdev->mc.igp_sideport_enabled) {
356 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
357 rdev->pm.sideport_bandwidth.full)
358 max_bandwidth = rdev->pm.sideport_bandwidth;
359 read_delay_latency.full = dfixed_const(370 * 800);
360 a.full = dfixed_const(1000);
361 b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
362 read_delay_latency.full = dfixed_div(read_delay_latency, b);
363 read_delay_latency.full = dfixed_mul(read_delay_latency, a);
364 } else {
365 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
366 rdev->pm.k8_bandwidth.full)
367 max_bandwidth = rdev->pm.k8_bandwidth;
368 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
369 rdev->pm.ht_bandwidth.full)
370 max_bandwidth = rdev->pm.ht_bandwidth;
371 read_delay_latency.full = dfixed_const(5000);
372 }
373
374 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
375 a.full = dfixed_const(16);
376 sclk.full = dfixed_mul(max_bandwidth, a);
377 a.full = dfixed_const(1000);
378 sclk.full = dfixed_div(a, sclk);
379 /* Determine chunk time
380 * ChunkTime = the time it takes the DCP to send one chunk of data
381 * to the LB which consists of pipeline delay and inter chunk gap
382 * sclk = system clock(ns)
383 */
384 a.full = dfixed_const(256 * 13);
385 chunk_time.full = dfixed_mul(sclk, a);
386 a.full = dfixed_const(10);
387 chunk_time.full = dfixed_div(chunk_time, a);
388
389 /* Determine the worst case latency
390 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
391 * WorstCaseLatency = worst case time from urgent to when the MC starts
392 * to return data
393 * READ_DELAY_IDLE_MAX = constant of 1us
394 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
395 * which consists of pipeline delay and inter chunk gap
396 */
397 if (dfixed_trunc(wm->num_line_pair) > 1) {
398 a.full = dfixed_const(3);
399 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
400 wm->worst_case_latency.full += read_delay_latency.full;
401 } else {
402 a.full = dfixed_const(2);
403 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
404 wm->worst_case_latency.full += read_delay_latency.full;
405 }
406
407 /* Determine the tolerable latency
408 * TolerableLatency = Any given request has only 1 line time
409 * for the data to be returned
410 * LBRequestFifoDepth = Number of chunk requests the LB can
411 * put into the request FIFO for a display
412 * LineTime = total time for one line of display
413 * ChunkTime = the time it takes the DCP to send one chunk
414 * of data to the LB which consists of
415 * pipeline delay and inter chunk gap
416 */
417 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
418 tolerable_latency.full = line_time.full;
419 } else {
420 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
421 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
422 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
423 tolerable_latency.full = line_time.full - tolerable_latency.full;
424 }
425 /* We assume worst case 32bits (4 bytes) */
426 wm->dbpp.full = dfixed_const(4 * 8);
427
428 /* Determine the maximum priority mark
429 * width = viewport width in pixels
430 */
431 a.full = dfixed_const(16);
432 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
433 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
434 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
435
436 /* Determine estimated width */
437 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
438 estimated_width.full = dfixed_div(estimated_width, consumption_time);
439 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
440 wm->priority_mark.full = dfixed_const(10);
441 } else {
442 a.full = dfixed_const(16);
443 wm->priority_mark.full = dfixed_div(estimated_width, a);
444 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
445 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
446 }
447 }
448
449 static void rs690_compute_mode_priority(struct radeon_device *rdev,
450 struct rs690_watermark *wm0,
451 struct rs690_watermark *wm1,
452 struct drm_display_mode *mode0,
453 struct drm_display_mode *mode1,
454 u32 *d1mode_priority_a_cnt,
455 u32 *d2mode_priority_a_cnt)
456 {
457 fixed20_12 priority_mark02, priority_mark12, fill_rate;
458 fixed20_12 a, b;
459
460 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
461 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
462
463 if (mode0 && mode1) {
464 if (dfixed_trunc(wm0->dbpp) > 64)
465 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
466 else
467 a.full = wm0->num_line_pair.full;
468 if (dfixed_trunc(wm1->dbpp) > 64)
469 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
470 else
471 b.full = wm1->num_line_pair.full;
472 a.full += b.full;
473 fill_rate.full = dfixed_div(wm0->sclk, a);
474 if (wm0->consumption_rate.full > fill_rate.full) {
475 b.full = wm0->consumption_rate.full - fill_rate.full;
476 b.full = dfixed_mul(b, wm0->active_time);
477 a.full = dfixed_mul(wm0->worst_case_latency,
478 wm0->consumption_rate);
479 a.full = a.full + b.full;
480 b.full = dfixed_const(16 * 1000);
481 priority_mark02.full = dfixed_div(a, b);
482 } else {
483 a.full = dfixed_mul(wm0->worst_case_latency,
484 wm0->consumption_rate);
485 b.full = dfixed_const(16 * 1000);
486 priority_mark02.full = dfixed_div(a, b);
487 }
488 if (wm1->consumption_rate.full > fill_rate.full) {
489 b.full = wm1->consumption_rate.full - fill_rate.full;
490 b.full = dfixed_mul(b, wm1->active_time);
491 a.full = dfixed_mul(wm1->worst_case_latency,
492 wm1->consumption_rate);
493 a.full = a.full + b.full;
494 b.full = dfixed_const(16 * 1000);
495 priority_mark12.full = dfixed_div(a, b);
496 } else {
497 a.full = dfixed_mul(wm1->worst_case_latency,
498 wm1->consumption_rate);
499 b.full = dfixed_const(16 * 1000);
500 priority_mark12.full = dfixed_div(a, b);
501 }
502 if (wm0->priority_mark.full > priority_mark02.full)
503 priority_mark02.full = wm0->priority_mark.full;
504 if (wm0->priority_mark_max.full > priority_mark02.full)
505 priority_mark02.full = wm0->priority_mark_max.full;
506 if (wm1->priority_mark.full > priority_mark12.full)
507 priority_mark12.full = wm1->priority_mark.full;
508 if (wm1->priority_mark_max.full > priority_mark12.full)
509 priority_mark12.full = wm1->priority_mark_max.full;
510 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
511 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
512 if (rdev->disp_priority == 2) {
513 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
514 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
515 }
516 } else if (mode0) {
517 if (dfixed_trunc(wm0->dbpp) > 64)
518 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
519 else
520 a.full = wm0->num_line_pair.full;
521 fill_rate.full = dfixed_div(wm0->sclk, a);
522 if (wm0->consumption_rate.full > fill_rate.full) {
523 b.full = wm0->consumption_rate.full - fill_rate.full;
524 b.full = dfixed_mul(b, wm0->active_time);
525 a.full = dfixed_mul(wm0->worst_case_latency,
526 wm0->consumption_rate);
527 a.full = a.full + b.full;
528 b.full = dfixed_const(16 * 1000);
529 priority_mark02.full = dfixed_div(a, b);
530 } else {
531 a.full = dfixed_mul(wm0->worst_case_latency,
532 wm0->consumption_rate);
533 b.full = dfixed_const(16 * 1000);
534 priority_mark02.full = dfixed_div(a, b);
535 }
536 if (wm0->priority_mark.full > priority_mark02.full)
537 priority_mark02.full = wm0->priority_mark.full;
538 if (wm0->priority_mark_max.full > priority_mark02.full)
539 priority_mark02.full = wm0->priority_mark_max.full;
540 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
541 if (rdev->disp_priority == 2)
542 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
543 } else if (mode1) {
544 if (dfixed_trunc(wm1->dbpp) > 64)
545 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
546 else
547 a.full = wm1->num_line_pair.full;
548 fill_rate.full = dfixed_div(wm1->sclk, a);
549 if (wm1->consumption_rate.full > fill_rate.full) {
550 b.full = wm1->consumption_rate.full - fill_rate.full;
551 b.full = dfixed_mul(b, wm1->active_time);
552 a.full = dfixed_mul(wm1->worst_case_latency,
553 wm1->consumption_rate);
554 a.full = a.full + b.full;
555 b.full = dfixed_const(16 * 1000);
556 priority_mark12.full = dfixed_div(a, b);
557 } else {
558 a.full = dfixed_mul(wm1->worst_case_latency,
559 wm1->consumption_rate);
560 b.full = dfixed_const(16 * 1000);
561 priority_mark12.full = dfixed_div(a, b);
562 }
563 if (wm1->priority_mark.full > priority_mark12.full)
564 priority_mark12.full = wm1->priority_mark.full;
565 if (wm1->priority_mark_max.full > priority_mark12.full)
566 priority_mark12.full = wm1->priority_mark_max.full;
567 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
568 if (rdev->disp_priority == 2)
569 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
570 }
571 }
572
573 void rs690_bandwidth_update(struct radeon_device *rdev)
574 {
575 struct drm_display_mode *mode0 = NULL;
576 struct drm_display_mode *mode1 = NULL;
577 struct rs690_watermark wm0_high, wm0_low;
578 struct rs690_watermark wm1_high, wm1_low;
579 u32 tmp;
580 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
581 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
582
583 if (!rdev->mode_info.mode_config_initialized)
584 return;
585
586 radeon_update_display_priority(rdev);
587
588 if (rdev->mode_info.crtcs[0]->base.enabled)
589 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
590 if (rdev->mode_info.crtcs[1]->base.enabled)
591 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
592 /*
593 * Set display0/1 priority up in the memory controller for
594 * modes if the user specifies HIGH for displaypriority
595 * option.
596 */
597 if ((rdev->disp_priority == 2) &&
598 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
599 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
600 tmp &= C_000104_MC_DISP0R_INIT_LAT;
601 tmp &= C_000104_MC_DISP1R_INIT_LAT;
602 if (mode0)
603 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
604 if (mode1)
605 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
606 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
607 }
608 rs690_line_buffer_adjust(rdev, mode0, mode1);
609
610 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
611 WREG32(R_006C9C_DCP_CONTROL, 0);
612 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
613 WREG32(R_006C9C_DCP_CONTROL, 2);
614
615 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
616 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
617
618 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
619 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
620
621 tmp = (wm0_high.lb_request_fifo_depth - 1);
622 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
623 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
624
625 rs690_compute_mode_priority(rdev,
626 &wm0_high, &wm1_high,
627 mode0, mode1,
628 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
629 rs690_compute_mode_priority(rdev,
630 &wm0_low, &wm1_low,
631 mode0, mode1,
632 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
633
634 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
635 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
636 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
637 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
638 }
639
640 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
641 {
642 unsigned long flags;
643 uint32_t r;
644
645 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
646 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
647 r = RREG32(R_00007C_MC_DATA);
648 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
649 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
650 return r;
651 }
652
653 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
654 {
655 unsigned long flags;
656
657 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
658 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
659 S_000078_MC_IND_WR_EN(1));
660 WREG32(R_00007C_MC_DATA, v);
661 WREG32(R_000078_MC_INDEX, 0x7F);
662 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
663 }
664
665 static void rs690_mc_program(struct radeon_device *rdev)
666 {
667 struct rv515_mc_save save;
668
669 /* Stops all mc clients */
670 rv515_mc_stop(rdev, &save);
671
672 /* Wait for mc idle */
673 if (rs690_mc_wait_for_idle(rdev))
674 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
675 /* Program MC, should be a 32bits limited address space */
676 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
677 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
678 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
679 WREG32(R_000134_HDP_FB_LOCATION,
680 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
681
682 rv515_mc_resume(rdev, &save);
683 }
684
685 static int rs690_startup(struct radeon_device *rdev)
686 {
687 int r;
688
689 rs690_mc_program(rdev);
690 /* Resume clock */
691 rv515_clock_startup(rdev);
692 /* Initialize GPU configuration (# pipes, ...) */
693 rs690_gpu_init(rdev);
694 /* Initialize GART (initialize after TTM so we can allocate
695 * memory through TTM but finalize after TTM) */
696 r = rs400_gart_enable(rdev);
697 if (r)
698 return r;
699
700 /* allocate wb buffer */
701 r = radeon_wb_init(rdev);
702 if (r)
703 return r;
704
705 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
706 if (r) {
707 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
708 return r;
709 }
710
711 /* Enable IRQ */
712 if (!rdev->irq.installed) {
713 r = radeon_irq_kms_init(rdev);
714 if (r)
715 return r;
716 }
717
718 rs600_irq_set(rdev);
719 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
720 /* 1M ring buffer */
721 r = r100_cp_init(rdev, 1024 * 1024);
722 if (r) {
723 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
724 return r;
725 }
726
727 r = radeon_ib_pool_init(rdev);
728 if (r) {
729 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
730 return r;
731 }
732
733 r = radeon_audio_init(rdev);
734 if (r) {
735 dev_err(rdev->dev, "failed initializing audio\n");
736 return r;
737 }
738
739 return 0;
740 }
741
742 int rs690_resume(struct radeon_device *rdev)
743 {
744 int r;
745
746 /* Make sur GART are not working */
747 rs400_gart_disable(rdev);
748 /* Resume clock before doing reset */
749 rv515_clock_startup(rdev);
750 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
751 if (radeon_asic_reset(rdev)) {
752 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
753 RREG32(R_000E40_RBBM_STATUS),
754 RREG32(R_0007C0_CP_STAT));
755 }
756 /* post */
757 atom_asic_init(rdev->mode_info.atom_context);
758 /* Resume clock after posting */
759 rv515_clock_startup(rdev);
760 /* Initialize surface registers */
761 radeon_surface_init(rdev);
762
763 rdev->accel_working = true;
764 r = rs690_startup(rdev);
765 if (r) {
766 rdev->accel_working = false;
767 }
768 return r;
769 }
770
771 int rs690_suspend(struct radeon_device *rdev)
772 {
773 radeon_pm_suspend(rdev);
774 radeon_audio_fini(rdev);
775 r100_cp_disable(rdev);
776 radeon_wb_disable(rdev);
777 rs600_irq_disable(rdev);
778 rs400_gart_disable(rdev);
779 return 0;
780 }
781
782 void rs690_fini(struct radeon_device *rdev)
783 {
784 radeon_pm_fini(rdev);
785 radeon_audio_fini(rdev);
786 r100_cp_fini(rdev);
787 radeon_wb_fini(rdev);
788 radeon_ib_pool_fini(rdev);
789 radeon_gem_fini(rdev);
790 rs400_gart_fini(rdev);
791 radeon_irq_kms_fini(rdev);
792 radeon_fence_driver_fini(rdev);
793 radeon_bo_fini(rdev);
794 radeon_atombios_fini(rdev);
795 kfree(rdev->bios);
796 rdev->bios = NULL;
797 }
798
799 int rs690_init(struct radeon_device *rdev)
800 {
801 int r;
802
803 /* Disable VGA */
804 rv515_vga_render_disable(rdev);
805 /* Initialize scratch registers */
806 radeon_scratch_init(rdev);
807 /* Initialize surface registers */
808 radeon_surface_init(rdev);
809 /* restore some register to sane defaults */
810 r100_restore_sanity(rdev);
811 /* TODO: disable VGA need to use VGA request */
812 /* BIOS*/
813 if (!radeon_get_bios(rdev)) {
814 if (ASIC_IS_AVIVO(rdev))
815 return -EINVAL;
816 }
817 if (rdev->is_atom_bios) {
818 r = radeon_atombios_init(rdev);
819 if (r)
820 return r;
821 } else {
822 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
823 return -EINVAL;
824 }
825 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
826 if (radeon_asic_reset(rdev)) {
827 dev_warn(rdev->dev,
828 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
829 RREG32(R_000E40_RBBM_STATUS),
830 RREG32(R_0007C0_CP_STAT));
831 }
832 /* check if cards are posted or not */
833 if (radeon_boot_test_post_card(rdev) == false)
834 return -EINVAL;
835
836 /* Initialize clocks */
837 radeon_get_clock_info(rdev->ddev);
838 /* initialize memory controller */
839 rs690_mc_init(rdev);
840 rv515_debugfs(rdev);
841 /* Fence driver */
842 r = radeon_fence_driver_init(rdev);
843 if (r)
844 return r;
845 /* Memory manager */
846 r = radeon_bo_init(rdev);
847 if (r)
848 return r;
849 r = rs400_gart_init(rdev);
850 if (r)
851 return r;
852 rs600_set_safe_registers(rdev);
853
854 /* Initialize power management */
855 radeon_pm_init(rdev);
856
857 rdev->accel_working = true;
858 r = rs690_startup(rdev);
859 if (r) {
860 /* Somethings want wront with the accel init stop accel */
861 dev_err(rdev->dev, "Disabling GPU acceleration\n");
862 r100_cp_fini(rdev);
863 radeon_wb_fini(rdev);
864 radeon_ib_pool_fini(rdev);
865 rs400_gart_fini(rdev);
866 radeon_irq_kms_fini(rdev);
867 rdev->accel_working = false;
868 }
869 return 0;
870 }
Linux with added FPC-III support