2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
53 #define MII_M1145_PHY_EXT_SR 0x1b
54 #define MII_M1145_PHY_EXT_CR 0x14
55 #define MII_M1145_RGMII_RX_DELAY 0x0080
56 #define MII_M1145_RGMII_TX_DELAY 0x0002
57 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
58 #define MII_M1145_HWCFG_MODE_MASK 0xf
59 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
61 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
62 #define MII_M1145_HWCFG_MODE_MASK 0xf
63 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
65 #define MII_M1111_PHY_LED_CONTROL 0x18
66 #define MII_M1111_PHY_LED_DIRECT 0x4100
67 #define MII_M1111_PHY_LED_COMBINE 0x411c
68 #define MII_M1111_PHY_EXT_CR 0x14
69 #define MII_M1111_RX_DELAY 0x80
70 #define MII_M1111_TX_DELAY 0x2
71 #define MII_M1111_PHY_EXT_SR 0x1b
73 #define MII_M1111_HWCFG_MODE_MASK 0xf
74 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
75 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
76 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
77 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
78 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
79 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
81 #define MII_M1111_COPPER 0
82 #define MII_M1111_FIBER 1
84 #define MII_88E1121_PHY_MSCR_PAGE 2
85 #define MII_88E1121_PHY_MSCR_REG 21
86 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
87 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
88 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
90 #define MII_88E1318S_PHY_MSCR1_REG 16
91 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
93 /* Copper Specific Interrupt Enable Register */
94 #define MII_88E1318S_PHY_CSIER 0x12
95 /* WOL Event Interrupt Enable */
96 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
98 /* LED Timer Control Register */
99 #define MII_88E1318S_PHY_LED_PAGE 0x03
100 #define MII_88E1318S_PHY_LED_TCR 0x12
101 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
102 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
103 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
105 /* Magic Packet MAC address registers */
106 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
107 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
108 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
110 #define MII_88E1318S_PHY_WOL_PAGE 0x11
111 #define MII_88E1318S_PHY_WOL_CTRL 0x10
112 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
113 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
115 #define MII_88E1121_PHY_LED_CTRL 16
116 #define MII_88E1121_PHY_LED_PAGE 3
117 #define MII_88E1121_PHY_LED_DEF 0x0030
119 #define MII_M1011_PHY_STATUS 0x11
120 #define MII_M1011_PHY_STATUS_1000 0x8000
121 #define MII_M1011_PHY_STATUS_100 0x4000
122 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
123 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
124 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
125 #define MII_M1011_PHY_STATUS_LINK 0x0400
127 #define MII_M1116R_CONTROL_REG_MAC 21
129 #define MII_88E3016_PHY_SPEC_CTRL 0x10
130 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
131 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
133 MODULE_DESCRIPTION("Marvell PHY driver");
134 MODULE_AUTHOR("Andy Fleming");
135 MODULE_LICENSE("GPL");
137 static int marvell_ack_interrupt(struct phy_device
*phydev
)
141 /* Clear the interrupts by reading the reg */
142 err
= phy_read(phydev
, MII_M1011_IEVENT
);
150 static int marvell_config_intr(struct phy_device
*phydev
)
154 if (phydev
->interrupts
== PHY_INTERRUPT_ENABLED
)
155 err
= phy_write(phydev
, MII_M1011_IMASK
, MII_M1011_IMASK_INIT
);
157 err
= phy_write(phydev
, MII_M1011_IMASK
, MII_M1011_IMASK_CLEAR
);
162 static int marvell_config_aneg(struct phy_device
*phydev
)
166 /* The Marvell PHY has an errata which requires
167 * that certain registers get written in order
168 * to restart autonegotiation */
169 err
= phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
174 err
= phy_write(phydev
, 0x1d, 0x1f);
178 err
= phy_write(phydev
, 0x1e, 0x200c);
182 err
= phy_write(phydev
, 0x1d, 0x5);
186 err
= phy_write(phydev
, 0x1e, 0);
190 err
= phy_write(phydev
, 0x1e, 0x100);
194 err
= phy_write(phydev
, MII_M1011_PHY_SCR
,
195 MII_M1011_PHY_SCR_AUTO_CROSS
);
199 err
= phy_write(phydev
, MII_M1111_PHY_LED_CONTROL
,
200 MII_M1111_PHY_LED_DIRECT
);
204 err
= genphy_config_aneg(phydev
);
208 if (phydev
->autoneg
!= AUTONEG_ENABLE
) {
212 * A write to speed/duplex bits (that is performed by
213 * genphy_config_aneg() call above) must be followed by
214 * a software reset. Otherwise, the write has no effect.
216 bmcr
= phy_read(phydev
, MII_BMCR
);
220 err
= phy_write(phydev
, MII_BMCR
, bmcr
| BMCR_RESET
);
228 #ifdef CONFIG_OF_MDIO
230 * Set and/or override some configuration registers based on the
231 * marvell,reg-init property stored in the of_node for the phydev.
233 * marvell,reg-init = <reg-page reg mask value>,...;
235 * There may be one or more sets of <reg-page reg mask value>:
237 * reg-page: which register bank to use.
239 * mask: if non-zero, ANDed with existing register value.
240 * value: ORed with the masked value and written to the regiser.
243 static int marvell_of_reg_init(struct phy_device
*phydev
)
246 int len
, i
, saved_page
, current_page
, page_changed
, ret
;
248 if (!phydev
->dev
.of_node
)
251 paddr
= of_get_property(phydev
->dev
.of_node
, "marvell,reg-init", &len
);
252 if (!paddr
|| len
< (4 * sizeof(*paddr
)))
255 saved_page
= phy_read(phydev
, MII_MARVELL_PHY_PAGE
);
259 current_page
= saved_page
;
262 len
/= sizeof(*paddr
);
263 for (i
= 0; i
< len
- 3; i
+= 4) {
264 u16 reg_page
= be32_to_cpup(paddr
+ i
);
265 u16 reg
= be32_to_cpup(paddr
+ i
+ 1);
266 u16 mask
= be32_to_cpup(paddr
+ i
+ 2);
267 u16 val_bits
= be32_to_cpup(paddr
+ i
+ 3);
270 if (reg_page
!= current_page
) {
271 current_page
= reg_page
;
273 ret
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, reg_page
);
280 val
= phy_read(phydev
, reg
);
289 ret
= phy_write(phydev
, reg
, val
);
296 i
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, saved_page
);
303 static int marvell_of_reg_init(struct phy_device
*phydev
)
307 #endif /* CONFIG_OF_MDIO */
309 static int m88e1121_config_aneg(struct phy_device
*phydev
)
311 int err
, oldpage
, mscr
;
313 oldpage
= phy_read(phydev
, MII_MARVELL_PHY_PAGE
);
315 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
316 MII_88E1121_PHY_MSCR_PAGE
);
320 if ((phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
321 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
322 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
323 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
325 mscr
= phy_read(phydev
, MII_88E1121_PHY_MSCR_REG
) &
326 MII_88E1121_PHY_MSCR_DELAY_MASK
;
328 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
329 mscr
|= (MII_88E1121_PHY_MSCR_RX_DELAY
|
330 MII_88E1121_PHY_MSCR_TX_DELAY
);
331 else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
332 mscr
|= MII_88E1121_PHY_MSCR_RX_DELAY
;
333 else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
334 mscr
|= MII_88E1121_PHY_MSCR_TX_DELAY
;
336 err
= phy_write(phydev
, MII_88E1121_PHY_MSCR_REG
, mscr
);
341 phy_write(phydev
, MII_MARVELL_PHY_PAGE
, oldpage
);
343 err
= phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
347 err
= phy_write(phydev
, MII_M1011_PHY_SCR
,
348 MII_M1011_PHY_SCR_AUTO_CROSS
);
352 oldpage
= phy_read(phydev
, MII_MARVELL_PHY_PAGE
);
354 phy_write(phydev
, MII_MARVELL_PHY_PAGE
, MII_88E1121_PHY_LED_PAGE
);
355 phy_write(phydev
, MII_88E1121_PHY_LED_CTRL
, MII_88E1121_PHY_LED_DEF
);
356 phy_write(phydev
, MII_MARVELL_PHY_PAGE
, oldpage
);
358 err
= genphy_config_aneg(phydev
);
363 static int m88e1318_config_aneg(struct phy_device
*phydev
)
365 int err
, oldpage
, mscr
;
367 oldpage
= phy_read(phydev
, MII_MARVELL_PHY_PAGE
);
369 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
370 MII_88E1121_PHY_MSCR_PAGE
);
374 mscr
= phy_read(phydev
, MII_88E1318S_PHY_MSCR1_REG
);
375 mscr
|= MII_88E1318S_PHY_MSCR1_PAD_ODD
;
377 err
= phy_write(phydev
, MII_88E1318S_PHY_MSCR1_REG
, mscr
);
381 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, oldpage
);
385 return m88e1121_config_aneg(phydev
);
388 static int m88e1510_config_aneg(struct phy_device
*phydev
)
392 err
= m88e1318_config_aneg(phydev
);
396 return marvell_of_reg_init(phydev
);
399 static int m88e1116r_config_init(struct phy_device
*phydev
)
404 temp
= phy_read(phydev
, MII_BMCR
);
406 err
= phy_write(phydev
, MII_BMCR
, temp
);
412 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0);
416 temp
= phy_read(phydev
, MII_M1011_PHY_SCR
);
417 temp
|= (7 << 12); /* max number of gigabit attempts */
418 temp
|= (1 << 11); /* enable downshift */
419 temp
|= MII_M1011_PHY_SCR_AUTO_CROSS
;
420 err
= phy_write(phydev
, MII_M1011_PHY_SCR
, temp
);
424 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 2);
427 temp
= phy_read(phydev
, MII_M1116R_CONTROL_REG_MAC
);
430 err
= phy_write(phydev
, MII_M1116R_CONTROL_REG_MAC
, temp
);
433 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0);
437 temp
= phy_read(phydev
, MII_BMCR
);
439 err
= phy_write(phydev
, MII_BMCR
, temp
);
448 static int m88e3016_config_init(struct phy_device
*phydev
)
452 /* Enable Scrambler and Auto-Crossover */
453 reg
= phy_read(phydev
, MII_88E3016_PHY_SPEC_CTRL
);
457 reg
&= ~MII_88E3016_DISABLE_SCRAMBLER
;
458 reg
|= MII_88E3016_AUTO_MDIX_CROSSOVER
;
460 reg
= phy_write(phydev
, MII_88E3016_PHY_SPEC_CTRL
, reg
);
467 static int m88e1111_config_init(struct phy_device
*phydev
)
472 if ((phydev
->interface
== PHY_INTERFACE_MODE_RGMII
) ||
473 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
474 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
475 (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
477 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_CR
);
481 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
) {
482 temp
|= (MII_M1111_RX_DELAY
| MII_M1111_TX_DELAY
);
483 } else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
) {
484 temp
&= ~MII_M1111_TX_DELAY
;
485 temp
|= MII_M1111_RX_DELAY
;
486 } else if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
) {
487 temp
&= ~MII_M1111_RX_DELAY
;
488 temp
|= MII_M1111_TX_DELAY
;
491 err
= phy_write(phydev
, MII_M1111_PHY_EXT_CR
, temp
);
495 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_SR
);
499 temp
&= ~(MII_M1111_HWCFG_MODE_MASK
);
501 if (temp
& MII_M1111_HWCFG_FIBER_COPPER_RES
)
502 temp
|= MII_M1111_HWCFG_MODE_FIBER_RGMII
;
504 temp
|= MII_M1111_HWCFG_MODE_COPPER_RGMII
;
506 err
= phy_write(phydev
, MII_M1111_PHY_EXT_SR
, temp
);
511 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
) {
512 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_SR
);
516 temp
&= ~(MII_M1111_HWCFG_MODE_MASK
);
517 temp
|= MII_M1111_HWCFG_MODE_SGMII_NO_CLK
;
518 temp
|= MII_M1111_HWCFG_FIBER_COPPER_AUTO
;
520 err
= phy_write(phydev
, MII_M1111_PHY_EXT_SR
, temp
);
525 if (phydev
->interface
== PHY_INTERFACE_MODE_RTBI
) {
526 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_CR
);
529 temp
|= (MII_M1111_RX_DELAY
| MII_M1111_TX_DELAY
);
530 err
= phy_write(phydev
, MII_M1111_PHY_EXT_CR
, temp
);
534 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_SR
);
537 temp
&= ~(MII_M1111_HWCFG_MODE_MASK
| MII_M1111_HWCFG_FIBER_COPPER_RES
);
538 temp
|= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO
;
539 err
= phy_write(phydev
, MII_M1111_PHY_EXT_SR
, temp
);
544 err
= phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
548 temp
= phy_read(phydev
, MII_BMCR
);
549 while (temp
& BMCR_RESET
);
551 temp
= phy_read(phydev
, MII_M1111_PHY_EXT_SR
);
554 temp
&= ~(MII_M1111_HWCFG_MODE_MASK
| MII_M1111_HWCFG_FIBER_COPPER_RES
);
555 temp
|= MII_M1111_HWCFG_MODE_COPPER_RTBI
| MII_M1111_HWCFG_FIBER_COPPER_AUTO
;
556 err
= phy_write(phydev
, MII_M1111_PHY_EXT_SR
, temp
);
561 err
= marvell_of_reg_init(phydev
);
565 return phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
568 static int m88e1118_config_aneg(struct phy_device
*phydev
)
572 err
= phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
576 err
= phy_write(phydev
, MII_M1011_PHY_SCR
,
577 MII_M1011_PHY_SCR_AUTO_CROSS
);
581 err
= genphy_config_aneg(phydev
);
585 static int m88e1118_config_init(struct phy_device
*phydev
)
590 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x0002);
594 /* Enable 1000 Mbit */
595 err
= phy_write(phydev
, 0x15, 0x1070);
600 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x0003);
604 /* Adjust LED Control */
605 if (phydev
->dev_flags
& MARVELL_PHY_M1118_DNS323_LEDS
)
606 err
= phy_write(phydev
, 0x10, 0x1100);
608 err
= phy_write(phydev
, 0x10, 0x021e);
612 err
= marvell_of_reg_init(phydev
);
617 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x0);
621 return phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
624 static int m88e1149_config_init(struct phy_device
*phydev
)
629 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x0002);
633 /* Enable 1000 Mbit */
634 err
= phy_write(phydev
, 0x15, 0x1048);
638 err
= marvell_of_reg_init(phydev
);
643 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x0);
647 return phy_write(phydev
, MII_BMCR
, BMCR_RESET
);
650 static int m88e1145_config_init(struct phy_device
*phydev
)
655 /* Take care of errata E0 & E1 */
656 err
= phy_write(phydev
, 0x1d, 0x001b);
660 err
= phy_write(phydev
, 0x1e, 0x418f);
664 err
= phy_write(phydev
, 0x1d, 0x0016);
668 err
= phy_write(phydev
, 0x1e, 0xa2da);
672 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
) {
673 int temp
= phy_read(phydev
, MII_M1145_PHY_EXT_CR
);
677 temp
|= (MII_M1145_RGMII_RX_DELAY
| MII_M1145_RGMII_TX_DELAY
);
679 err
= phy_write(phydev
, MII_M1145_PHY_EXT_CR
, temp
);
683 if (phydev
->dev_flags
& MARVELL_PHY_M1145_FLAGS_RESISTANCE
) {
684 err
= phy_write(phydev
, 0x1d, 0x0012);
688 temp
= phy_read(phydev
, 0x1e);
693 temp
|= 2 << 9; /* 36 ohm */
694 temp
|= 2 << 6; /* 39 ohm */
696 err
= phy_write(phydev
, 0x1e, temp
);
700 err
= phy_write(phydev
, 0x1d, 0x3);
704 err
= phy_write(phydev
, 0x1e, 0x8000);
710 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
) {
711 temp
= phy_read(phydev
, MII_M1145_PHY_EXT_SR
);
715 temp
&= ~MII_M1145_HWCFG_MODE_MASK
;
716 temp
|= MII_M1145_HWCFG_MODE_SGMII_NO_CLK
;
717 temp
|= MII_M1145_HWCFG_FIBER_COPPER_AUTO
;
719 err
= phy_write(phydev
, MII_M1145_PHY_EXT_SR
, temp
);
724 err
= marvell_of_reg_init(phydev
);
731 /* marvell_read_status
733 * Generic status code does not detect Fiber correctly!
735 * Check the link, then figure out the current state
736 * by comparing what we advertise with what the link partner
737 * advertises. Start by checking the gigabit possibilities,
738 * then move on to 10/100.
740 static int marvell_read_status(struct phy_device
*phydev
)
747 /* Update the link, but return if there
749 err
= genphy_update_link(phydev
);
753 if (AUTONEG_ENABLE
== phydev
->autoneg
) {
754 status
= phy_read(phydev
, MII_M1011_PHY_STATUS
);
758 lpa
= phy_read(phydev
, MII_LPA
);
762 adv
= phy_read(phydev
, MII_ADVERTISE
);
768 if (status
& MII_M1011_PHY_STATUS_FULLDUPLEX
)
769 phydev
->duplex
= DUPLEX_FULL
;
771 phydev
->duplex
= DUPLEX_HALF
;
773 status
= status
& MII_M1011_PHY_STATUS_SPD_MASK
;
774 phydev
->pause
= phydev
->asym_pause
= 0;
777 case MII_M1011_PHY_STATUS_1000
:
778 phydev
->speed
= SPEED_1000
;
781 case MII_M1011_PHY_STATUS_100
:
782 phydev
->speed
= SPEED_100
;
786 phydev
->speed
= SPEED_10
;
790 if (phydev
->duplex
== DUPLEX_FULL
) {
791 phydev
->pause
= lpa
& LPA_PAUSE_CAP
? 1 : 0;
792 phydev
->asym_pause
= lpa
& LPA_PAUSE_ASYM
? 1 : 0;
795 int bmcr
= phy_read(phydev
, MII_BMCR
);
800 if (bmcr
& BMCR_FULLDPLX
)
801 phydev
->duplex
= DUPLEX_FULL
;
803 phydev
->duplex
= DUPLEX_HALF
;
805 if (bmcr
& BMCR_SPEED1000
)
806 phydev
->speed
= SPEED_1000
;
807 else if (bmcr
& BMCR_SPEED100
)
808 phydev
->speed
= SPEED_100
;
810 phydev
->speed
= SPEED_10
;
812 phydev
->pause
= phydev
->asym_pause
= 0;
818 static int marvell_aneg_done(struct phy_device
*phydev
)
820 int retval
= phy_read(phydev
, MII_M1011_PHY_STATUS
);
821 return (retval
< 0) ? retval
: (retval
& MII_M1011_PHY_STATUS_RESOLVED
);
824 static int m88e1121_did_interrupt(struct phy_device
*phydev
)
828 imask
= phy_read(phydev
, MII_M1011_IEVENT
);
830 if (imask
& MII_M1011_IMASK_INIT
)
836 static void m88e1318_get_wol(struct phy_device
*phydev
, struct ethtool_wolinfo
*wol
)
838 wol
->supported
= WAKE_MAGIC
;
841 if (phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
842 MII_88E1318S_PHY_WOL_PAGE
) < 0)
845 if (phy_read(phydev
, MII_88E1318S_PHY_WOL_CTRL
) &
846 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE
)
847 wol
->wolopts
|= WAKE_MAGIC
;
849 if (phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x00) < 0)
853 static int m88e1318_set_wol(struct phy_device
*phydev
, struct ethtool_wolinfo
*wol
)
855 int err
, oldpage
, temp
;
857 oldpage
= phy_read(phydev
, MII_MARVELL_PHY_PAGE
);
859 if (wol
->wolopts
& WAKE_MAGIC
) {
860 /* Explicitly switch to page 0x00, just to be sure */
861 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, 0x00);
865 /* Enable the WOL interrupt */
866 temp
= phy_read(phydev
, MII_88E1318S_PHY_CSIER
);
867 temp
|= MII_88E1318S_PHY_CSIER_WOL_EIE
;
868 err
= phy_write(phydev
, MII_88E1318S_PHY_CSIER
, temp
);
872 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
873 MII_88E1318S_PHY_LED_PAGE
);
877 /* Setup LED[2] as interrupt pin (active low) */
878 temp
= phy_read(phydev
, MII_88E1318S_PHY_LED_TCR
);
879 temp
&= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT
;
880 temp
|= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE
;
881 temp
|= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW
;
882 err
= phy_write(phydev
, MII_88E1318S_PHY_LED_TCR
, temp
);
886 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
887 MII_88E1318S_PHY_WOL_PAGE
);
891 /* Store the device address for the magic packet */
892 err
= phy_write(phydev
, MII_88E1318S_PHY_MAGIC_PACKET_WORD2
,
893 ((phydev
->attached_dev
->dev_addr
[5] << 8) |
894 phydev
->attached_dev
->dev_addr
[4]));
897 err
= phy_write(phydev
, MII_88E1318S_PHY_MAGIC_PACKET_WORD1
,
898 ((phydev
->attached_dev
->dev_addr
[3] << 8) |
899 phydev
->attached_dev
->dev_addr
[2]));
902 err
= phy_write(phydev
, MII_88E1318S_PHY_MAGIC_PACKET_WORD0
,
903 ((phydev
->attached_dev
->dev_addr
[1] << 8) |
904 phydev
->attached_dev
->dev_addr
[0]));
908 /* Clear WOL status and enable magic packet matching */
909 temp
= phy_read(phydev
, MII_88E1318S_PHY_WOL_CTRL
);
910 temp
|= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS
;
911 temp
|= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE
;
912 err
= phy_write(phydev
, MII_88E1318S_PHY_WOL_CTRL
, temp
);
916 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
,
917 MII_88E1318S_PHY_WOL_PAGE
);
921 /* Clear WOL status and disable magic packet matching */
922 temp
= phy_read(phydev
, MII_88E1318S_PHY_WOL_CTRL
);
923 temp
|= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS
;
924 temp
&= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE
;
925 err
= phy_write(phydev
, MII_88E1318S_PHY_WOL_CTRL
, temp
);
930 err
= phy_write(phydev
, MII_MARVELL_PHY_PAGE
, oldpage
);
937 static struct phy_driver marvell_drivers
[] = {
939 .phy_id
= MARVELL_PHY_ID_88E1101
,
940 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
941 .name
= "Marvell 88E1101",
942 .features
= PHY_GBIT_FEATURES
,
943 .flags
= PHY_HAS_INTERRUPT
,
944 .config_aneg
= &marvell_config_aneg
,
945 .read_status
= &genphy_read_status
,
946 .ack_interrupt
= &marvell_ack_interrupt
,
947 .config_intr
= &marvell_config_intr
,
948 .resume
= &genphy_resume
,
949 .suspend
= &genphy_suspend
,
950 .driver
= { .owner
= THIS_MODULE
},
953 .phy_id
= MARVELL_PHY_ID_88E1112
,
954 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
955 .name
= "Marvell 88E1112",
956 .features
= PHY_GBIT_FEATURES
,
957 .flags
= PHY_HAS_INTERRUPT
,
958 .config_init
= &m88e1111_config_init
,
959 .config_aneg
= &marvell_config_aneg
,
960 .read_status
= &genphy_read_status
,
961 .ack_interrupt
= &marvell_ack_interrupt
,
962 .config_intr
= &marvell_config_intr
,
963 .resume
= &genphy_resume
,
964 .suspend
= &genphy_suspend
,
965 .driver
= { .owner
= THIS_MODULE
},
968 .phy_id
= MARVELL_PHY_ID_88E1111
,
969 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
970 .name
= "Marvell 88E1111",
971 .features
= PHY_GBIT_FEATURES
,
972 .flags
= PHY_HAS_INTERRUPT
,
973 .config_init
= &m88e1111_config_init
,
974 .config_aneg
= &marvell_config_aneg
,
975 .read_status
= &marvell_read_status
,
976 .ack_interrupt
= &marvell_ack_interrupt
,
977 .config_intr
= &marvell_config_intr
,
978 .resume
= &genphy_resume
,
979 .suspend
= &genphy_suspend
,
980 .driver
= { .owner
= THIS_MODULE
},
983 .phy_id
= MARVELL_PHY_ID_88E1118
,
984 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
985 .name
= "Marvell 88E1118",
986 .features
= PHY_GBIT_FEATURES
,
987 .flags
= PHY_HAS_INTERRUPT
,
988 .config_init
= &m88e1118_config_init
,
989 .config_aneg
= &m88e1118_config_aneg
,
990 .read_status
= &genphy_read_status
,
991 .ack_interrupt
= &marvell_ack_interrupt
,
992 .config_intr
= &marvell_config_intr
,
993 .resume
= &genphy_resume
,
994 .suspend
= &genphy_suspend
,
995 .driver
= {.owner
= THIS_MODULE
,},
998 .phy_id
= MARVELL_PHY_ID_88E1121R
,
999 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1000 .name
= "Marvell 88E1121R",
1001 .features
= PHY_GBIT_FEATURES
,
1002 .flags
= PHY_HAS_INTERRUPT
,
1003 .config_aneg
= &m88e1121_config_aneg
,
1004 .read_status
= &marvell_read_status
,
1005 .ack_interrupt
= &marvell_ack_interrupt
,
1006 .config_intr
= &marvell_config_intr
,
1007 .did_interrupt
= &m88e1121_did_interrupt
,
1008 .resume
= &genphy_resume
,
1009 .suspend
= &genphy_suspend
,
1010 .driver
= { .owner
= THIS_MODULE
},
1013 .phy_id
= MARVELL_PHY_ID_88E1318S
,
1014 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1015 .name
= "Marvell 88E1318S",
1016 .features
= PHY_GBIT_FEATURES
,
1017 .flags
= PHY_HAS_INTERRUPT
,
1018 .config_aneg
= &m88e1318_config_aneg
,
1019 .read_status
= &marvell_read_status
,
1020 .ack_interrupt
= &marvell_ack_interrupt
,
1021 .config_intr
= &marvell_config_intr
,
1022 .did_interrupt
= &m88e1121_did_interrupt
,
1023 .get_wol
= &m88e1318_get_wol
,
1024 .set_wol
= &m88e1318_set_wol
,
1025 .resume
= &genphy_resume
,
1026 .suspend
= &genphy_suspend
,
1027 .driver
= { .owner
= THIS_MODULE
},
1030 .phy_id
= MARVELL_PHY_ID_88E1145
,
1031 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1032 .name
= "Marvell 88E1145",
1033 .features
= PHY_GBIT_FEATURES
,
1034 .flags
= PHY_HAS_INTERRUPT
,
1035 .config_init
= &m88e1145_config_init
,
1036 .config_aneg
= &marvell_config_aneg
,
1037 .read_status
= &genphy_read_status
,
1038 .ack_interrupt
= &marvell_ack_interrupt
,
1039 .config_intr
= &marvell_config_intr
,
1040 .resume
= &genphy_resume
,
1041 .suspend
= &genphy_suspend
,
1042 .driver
= { .owner
= THIS_MODULE
},
1045 .phy_id
= MARVELL_PHY_ID_88E1149R
,
1046 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1047 .name
= "Marvell 88E1149R",
1048 .features
= PHY_GBIT_FEATURES
,
1049 .flags
= PHY_HAS_INTERRUPT
,
1050 .config_init
= &m88e1149_config_init
,
1051 .config_aneg
= &m88e1118_config_aneg
,
1052 .read_status
= &genphy_read_status
,
1053 .ack_interrupt
= &marvell_ack_interrupt
,
1054 .config_intr
= &marvell_config_intr
,
1055 .resume
= &genphy_resume
,
1056 .suspend
= &genphy_suspend
,
1057 .driver
= { .owner
= THIS_MODULE
},
1060 .phy_id
= MARVELL_PHY_ID_88E1240
,
1061 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1062 .name
= "Marvell 88E1240",
1063 .features
= PHY_GBIT_FEATURES
,
1064 .flags
= PHY_HAS_INTERRUPT
,
1065 .config_init
= &m88e1111_config_init
,
1066 .config_aneg
= &marvell_config_aneg
,
1067 .read_status
= &genphy_read_status
,
1068 .ack_interrupt
= &marvell_ack_interrupt
,
1069 .config_intr
= &marvell_config_intr
,
1070 .resume
= &genphy_resume
,
1071 .suspend
= &genphy_suspend
,
1072 .driver
= { .owner
= THIS_MODULE
},
1075 .phy_id
= MARVELL_PHY_ID_88E1116R
,
1076 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1077 .name
= "Marvell 88E1116R",
1078 .features
= PHY_GBIT_FEATURES
,
1079 .flags
= PHY_HAS_INTERRUPT
,
1080 .config_init
= &m88e1116r_config_init
,
1081 .config_aneg
= &genphy_config_aneg
,
1082 .read_status
= &genphy_read_status
,
1083 .ack_interrupt
= &marvell_ack_interrupt
,
1084 .config_intr
= &marvell_config_intr
,
1085 .resume
= &genphy_resume
,
1086 .suspend
= &genphy_suspend
,
1087 .driver
= { .owner
= THIS_MODULE
},
1090 .phy_id
= MARVELL_PHY_ID_88E1510
,
1091 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1092 .name
= "Marvell 88E1510",
1093 .features
= PHY_GBIT_FEATURES
,
1094 .flags
= PHY_HAS_INTERRUPT
,
1095 .config_aneg
= &m88e1510_config_aneg
,
1096 .read_status
= &marvell_read_status
,
1097 .ack_interrupt
= &marvell_ack_interrupt
,
1098 .config_intr
= &marvell_config_intr
,
1099 .did_interrupt
= &m88e1121_did_interrupt
,
1100 .resume
= &genphy_resume
,
1101 .suspend
= &genphy_suspend
,
1102 .driver
= { .owner
= THIS_MODULE
},
1105 .phy_id
= MARVELL_PHY_ID_88E3016
,
1106 .phy_id_mask
= MARVELL_PHY_ID_MASK
,
1107 .name
= "Marvell 88E3016",
1108 .features
= PHY_BASIC_FEATURES
,
1109 .flags
= PHY_HAS_INTERRUPT
,
1110 .config_aneg
= &genphy_config_aneg
,
1111 .config_init
= &m88e3016_config_init
,
1112 .aneg_done
= &marvell_aneg_done
,
1113 .read_status
= &marvell_read_status
,
1114 .ack_interrupt
= &marvell_ack_interrupt
,
1115 .config_intr
= &marvell_config_intr
,
1116 .did_interrupt
= &m88e1121_did_interrupt
,
1117 .resume
= &genphy_resume
,
1118 .suspend
= &genphy_suspend
,
1119 .driver
= { .owner
= THIS_MODULE
},
1123 module_phy_driver(marvell_drivers
);
1125 static struct mdio_device_id __maybe_unused marvell_tbl
[] = {
1126 { MARVELL_PHY_ID_88E1101
, MARVELL_PHY_ID_MASK
},
1127 { MARVELL_PHY_ID_88E1112
, MARVELL_PHY_ID_MASK
},
1128 { MARVELL_PHY_ID_88E1111
, MARVELL_PHY_ID_MASK
},
1129 { MARVELL_PHY_ID_88E1118
, MARVELL_PHY_ID_MASK
},
1130 { MARVELL_PHY_ID_88E1121R
, MARVELL_PHY_ID_MASK
},
1131 { MARVELL_PHY_ID_88E1145
, MARVELL_PHY_ID_MASK
},
1132 { MARVELL_PHY_ID_88E1149R
, MARVELL_PHY_ID_MASK
},
1133 { MARVELL_PHY_ID_88E1240
, MARVELL_PHY_ID_MASK
},
1134 { MARVELL_PHY_ID_88E1318S
, MARVELL_PHY_ID_MASK
},
1135 { MARVELL_PHY_ID_88E1116R
, MARVELL_PHY_ID_MASK
},
1136 { MARVELL_PHY_ID_88E1510
, MARVELL_PHY_ID_MASK
},
1137 { MARVELL_PHY_ID_88E3016
, MARVELL_PHY_ID_MASK
},
1141 MODULE_DEVICE_TABLE(mdio
, marvell_tbl
);