Linux 4.1.16
[linux/fpc-iii.git] / drivers / net / phy / vitesse.c
blob76cad712ddb2c7c6bc2794389380e4e0a862d5f5
1 /*
2 * Driver for Vitesse PHYs
4 * Author: Kriston Carson
6 * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/mii.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
21 /* Vitesse Extended Page Magic Register(s) */
22 #define MII_VSC82X4_EXT_PAGE_16E 0x10
23 #define MII_VSC82X4_EXT_PAGE_17E 0x11
24 #define MII_VSC82X4_EXT_PAGE_18E 0x12
26 /* Vitesse Extended Control Register 1 */
27 #define MII_VSC8244_EXT_CON1 0x17
28 #define MII_VSC8244_EXTCON1_INIT 0x0000
29 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
30 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
31 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
32 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
34 /* Vitesse Interrupt Mask Register */
35 #define MII_VSC8244_IMASK 0x19
36 #define MII_VSC8244_IMASK_IEN 0x8000
37 #define MII_VSC8244_IMASK_SPEED 0x4000
38 #define MII_VSC8244_IMASK_LINK 0x2000
39 #define MII_VSC8244_IMASK_DUPLEX 0x1000
40 #define MII_VSC8244_IMASK_MASK 0xf000
42 #define MII_VSC8221_IMASK_MASK 0xa000
44 /* Vitesse Interrupt Status Register */
45 #define MII_VSC8244_ISTAT 0x1a
46 #define MII_VSC8244_ISTAT_STATUS 0x8000
47 #define MII_VSC8244_ISTAT_SPEED 0x4000
48 #define MII_VSC8244_ISTAT_LINK 0x2000
49 #define MII_VSC8244_ISTAT_DUPLEX 0x1000
51 /* Vitesse Auxiliary Control/Status Register */
52 #define MII_VSC8244_AUX_CONSTAT 0x1c
53 #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
54 #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
55 #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
56 #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
57 #define MII_VSC8244_AUXCONSTAT_100 0x0008
59 #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
60 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
62 /* Vitesse Extended Page Access Register */
63 #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
65 #define PHY_ID_VSC8234 0x000fc620
66 #define PHY_ID_VSC8244 0x000fc6c0
67 #define PHY_ID_VSC8514 0x00070670
68 #define PHY_ID_VSC8574 0x000704a0
69 #define PHY_ID_VSC8662 0x00070660
70 #define PHY_ID_VSC8221 0x000fc550
71 #define PHY_ID_VSC8211 0x000fc4b0
73 MODULE_DESCRIPTION("Vitesse PHY driver");
74 MODULE_AUTHOR("Kriston Carson");
75 MODULE_LICENSE("GPL");
77 static int vsc824x_add_skew(struct phy_device *phydev)
79 int err;
80 int extcon;
82 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
84 if (extcon < 0)
85 return extcon;
87 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
88 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
90 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
91 MII_VSC8244_EXTCON1_RX_SKEW);
93 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
95 return err;
98 static int vsc824x_config_init(struct phy_device *phydev)
100 int err;
102 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
103 MII_VSC8244_AUXCONSTAT_INIT);
104 if (err < 0)
105 return err;
107 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
108 err = vsc824x_add_skew(phydev);
110 return err;
113 static int vsc824x_ack_interrupt(struct phy_device *phydev)
115 int err = 0;
117 /* Don't bother to ACK the interrupts if interrupts
118 * are disabled. The 824x cannot clear the interrupts
119 * if they are disabled.
121 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
122 err = phy_read(phydev, MII_VSC8244_ISTAT);
124 return (err < 0) ? err : 0;
127 static int vsc82xx_config_intr(struct phy_device *phydev)
129 int err;
131 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
132 err = phy_write(phydev, MII_VSC8244_IMASK,
133 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
134 phydev->drv->phy_id == PHY_ID_VSC8244 ||
135 phydev->drv->phy_id == PHY_ID_VSC8514 ||
136 phydev->drv->phy_id == PHY_ID_VSC8574) ?
137 MII_VSC8244_IMASK_MASK :
138 MII_VSC8221_IMASK_MASK);
139 else {
140 /* The Vitesse PHY cannot clear the interrupt
141 * once it has disabled them, so we clear them first
143 err = phy_read(phydev, MII_VSC8244_ISTAT);
145 if (err < 0)
146 return err;
148 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
151 return err;
154 static int vsc8221_config_init(struct phy_device *phydev)
156 int err;
158 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
159 MII_VSC8221_AUXCONSTAT_INIT);
160 return err;
162 /* Perhaps we should set EXT_CON1 based on the interface?
163 * Options are 802.3Z SerDes or SGMII
167 /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
168 * @phydev: target phy_device struct
170 * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
171 * special values in the VSC8234/VSC8244 extended reserved registers
173 static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
175 int ret;
177 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
178 return 0;
180 /* map extended registers set 0x10 - 0x1e */
181 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
182 if (ret >= 0)
183 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
184 if (ret >= 0)
185 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
186 if (ret >= 0)
187 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
188 /* map standard registers set 0x10 - 0x1e */
189 if (ret >= 0)
190 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
191 else
192 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
194 return ret;
197 /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
198 * @phydev: target phy_device struct
200 * Description: If auto-negotiation is enabled, we configure the
201 * advertising, and then restart auto-negotiation. If it is not
202 * enabled, then we write the BMCR and also start the auto
203 * MDI/MDI-X feature
205 static int vsc82x4_config_aneg(struct phy_device *phydev)
207 int ret;
209 /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
210 * writing special values in the VSC8234 extended reserved registers
212 if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
213 ret = genphy_setup_forced(phydev);
215 if (ret < 0) /* error */
216 return ret;
218 return vsc82x4_config_autocross_enable(phydev);
221 return genphy_config_aneg(phydev);
224 /* Vitesse 82xx */
225 static struct phy_driver vsc82xx_driver[] = {
227 .phy_id = PHY_ID_VSC8234,
228 .name = "Vitesse VSC8234",
229 .phy_id_mask = 0x000ffff0,
230 .features = PHY_GBIT_FEATURES,
231 .flags = PHY_HAS_INTERRUPT,
232 .config_init = &vsc824x_config_init,
233 .config_aneg = &vsc82x4_config_aneg,
234 .read_status = &genphy_read_status,
235 .ack_interrupt = &vsc824x_ack_interrupt,
236 .config_intr = &vsc82xx_config_intr,
237 .driver = { .owner = THIS_MODULE,},
238 }, {
239 .phy_id = PHY_ID_VSC8244,
240 .name = "Vitesse VSC8244",
241 .phy_id_mask = 0x000fffc0,
242 .features = PHY_GBIT_FEATURES,
243 .flags = PHY_HAS_INTERRUPT,
244 .config_init = &vsc824x_config_init,
245 .config_aneg = &vsc82x4_config_aneg,
246 .read_status = &genphy_read_status,
247 .ack_interrupt = &vsc824x_ack_interrupt,
248 .config_intr = &vsc82xx_config_intr,
249 .driver = { .owner = THIS_MODULE,},
250 }, {
251 .phy_id = PHY_ID_VSC8514,
252 .name = "Vitesse VSC8514",
253 .phy_id_mask = 0x000ffff0,
254 .features = PHY_GBIT_FEATURES,
255 .flags = PHY_HAS_INTERRUPT,
256 .config_init = &vsc824x_config_init,
257 .config_aneg = &vsc82x4_config_aneg,
258 .read_status = &genphy_read_status,
259 .ack_interrupt = &vsc824x_ack_interrupt,
260 .config_intr = &vsc82xx_config_intr,
261 .driver = { .owner = THIS_MODULE,},
262 }, {
263 .phy_id = PHY_ID_VSC8574,
264 .name = "Vitesse VSC8574",
265 .phy_id_mask = 0x000ffff0,
266 .features = PHY_GBIT_FEATURES,
267 .flags = PHY_HAS_INTERRUPT,
268 .config_init = &vsc824x_config_init,
269 .config_aneg = &vsc82x4_config_aneg,
270 .read_status = &genphy_read_status,
271 .ack_interrupt = &vsc824x_ack_interrupt,
272 .config_intr = &vsc82xx_config_intr,
273 .driver = { .owner = THIS_MODULE,},
274 }, {
275 .phy_id = PHY_ID_VSC8662,
276 .name = "Vitesse VSC8662",
277 .phy_id_mask = 0x000ffff0,
278 .features = PHY_GBIT_FEATURES,
279 .flags = PHY_HAS_INTERRUPT,
280 .config_init = &vsc824x_config_init,
281 .config_aneg = &vsc82x4_config_aneg,
282 .read_status = &genphy_read_status,
283 .ack_interrupt = &vsc824x_ack_interrupt,
284 .config_intr = &vsc82xx_config_intr,
285 .driver = { .owner = THIS_MODULE,},
286 }, {
287 /* Vitesse 8221 */
288 .phy_id = PHY_ID_VSC8221,
289 .phy_id_mask = 0x000ffff0,
290 .name = "Vitesse VSC8221",
291 .features = PHY_GBIT_FEATURES,
292 .flags = PHY_HAS_INTERRUPT,
293 .config_init = &vsc8221_config_init,
294 .config_aneg = &genphy_config_aneg,
295 .read_status = &genphy_read_status,
296 .ack_interrupt = &vsc824x_ack_interrupt,
297 .config_intr = &vsc82xx_config_intr,
298 .driver = { .owner = THIS_MODULE,},
299 }, {
300 /* Vitesse 8211 */
301 .phy_id = PHY_ID_VSC8211,
302 .phy_id_mask = 0x000ffff0,
303 .name = "Vitesse VSC8211",
304 .features = PHY_GBIT_FEATURES,
305 .flags = PHY_HAS_INTERRUPT,
306 .config_init = &vsc8221_config_init,
307 .config_aneg = &genphy_config_aneg,
308 .read_status = &genphy_read_status,
309 .ack_interrupt = &vsc824x_ack_interrupt,
310 .config_intr = &vsc82xx_config_intr,
311 .driver = { .owner = THIS_MODULE,},
312 } };
314 module_phy_driver(vsc82xx_driver);
316 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
317 { PHY_ID_VSC8234, 0x000ffff0 },
318 { PHY_ID_VSC8244, 0x000fffc0 },
319 { PHY_ID_VSC8514, 0x000ffff0 },
320 { PHY_ID_VSC8574, 0x000ffff0 },
321 { PHY_ID_VSC8662, 0x000ffff0 },
322 { PHY_ID_VSC8221, 0x000ffff0 },
323 { PHY_ID_VSC8211, 0x000ffff0 },
327 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);