1 /*======================================================================
3 Device driver for the PCMCIA control functionality of PXA2xx
6 The contents of this file may be used under the
7 terms of the GNU Public License version 2 (the "GPL")
9 (c) Ian Molton (spyro@f2s.com) 2003
10 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
12 derived from sa11xx_base.c
14 Portions created by John G. Dorsey are
15 Copyright (C) 1999 John G. Dorsey.
17 ======================================================================*/
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/init.h>
22 #include <linux/cpufreq.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_device.h>
28 #include <mach/hardware.h>
29 #include <mach/smemc.h>
32 #include <mach/pxa2xx-regs.h>
33 #include <asm/mach-types.h>
35 #include <pcmcia/ss.h>
36 #include <pcmcia/cistpl.h>
38 #include "soc_common.h"
39 #include "pxa2xx_base.h"
42 * Personal Computer Memory Card International Association (PCMCIA) sockets
45 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
46 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
47 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
48 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
49 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
51 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
52 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
53 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
54 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
56 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
57 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
58 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
59 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
61 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
62 (0x20000000 + (Nb) * PCMCIASp)
63 #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
64 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
65 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
66 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
67 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
69 #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
70 #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
71 #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
72 #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
74 #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
75 #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
76 #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
77 #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
80 #define MCXX_SETUP_MASK (0x7f)
81 #define MCXX_ASST_MASK (0x1f)
82 #define MCXX_HOLD_MASK (0x3f)
83 #define MCXX_SETUP_SHIFT (0)
84 #define MCXX_ASST_SHIFT (7)
85 #define MCXX_HOLD_SHIFT (14)
87 static inline u_int
pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns
,
90 u_int code
= pcmcia_cycle_ns
* mem_clk_10khz
;
91 return (code
/ 300000) + ((code
% 300000) ? 1 : 0) - 1;
94 static inline u_int
pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns
,
97 u_int code
= pcmcia_cycle_ns
* mem_clk_10khz
;
98 return (code
/ 300000) + ((code
% 300000) ? 1 : 0) + 1;
101 static inline u_int
pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns
,
104 u_int code
= pcmcia_cycle_ns
* mem_clk_10khz
;
105 return (code
/ 100000) + ((code
% 100000) ? 1 : 0) - 1;
108 /* This function returns the (approximate) command assertion period, in
109 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
111 static inline u_int
pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz
,
112 u_int pcmcia_mcxx_asst
)
114 return (300000 * (pcmcia_mcxx_asst
+ 1) / mem_clk_10khz
);
117 static int pxa2xx_pcmcia_set_mcmem( int sock
, int speed
, int clock
)
121 val
= ((pxa2xx_mcxx_setup(speed
, clock
)
122 & MCXX_SETUP_MASK
) << MCXX_SETUP_SHIFT
)
123 | ((pxa2xx_mcxx_asst(speed
, clock
)
124 & MCXX_ASST_MASK
) << MCXX_ASST_SHIFT
)
125 | ((pxa2xx_mcxx_hold(speed
, clock
)
126 & MCXX_HOLD_MASK
) << MCXX_HOLD_SHIFT
);
128 __raw_writel(val
, MCMEM(sock
));
133 static int pxa2xx_pcmcia_set_mcio( int sock
, int speed
, int clock
)
137 val
= ((pxa2xx_mcxx_setup(speed
, clock
)
138 & MCXX_SETUP_MASK
) << MCXX_SETUP_SHIFT
)
139 | ((pxa2xx_mcxx_asst(speed
, clock
)
140 & MCXX_ASST_MASK
) << MCXX_ASST_SHIFT
)
141 | ((pxa2xx_mcxx_hold(speed
, clock
)
142 & MCXX_HOLD_MASK
) << MCXX_HOLD_SHIFT
);
144 __raw_writel(val
, MCIO(sock
));
149 static int pxa2xx_pcmcia_set_mcatt( int sock
, int speed
, int clock
)
153 val
= ((pxa2xx_mcxx_setup(speed
, clock
)
154 & MCXX_SETUP_MASK
) << MCXX_SETUP_SHIFT
)
155 | ((pxa2xx_mcxx_asst(speed
, clock
)
156 & MCXX_ASST_MASK
) << MCXX_ASST_SHIFT
)
157 | ((pxa2xx_mcxx_hold(speed
, clock
)
158 & MCXX_HOLD_MASK
) << MCXX_HOLD_SHIFT
);
160 __raw_writel(val
, MCATT(sock
));
165 static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket
*skt
, unsigned int clk
)
167 struct soc_pcmcia_timing timing
;
170 soc_common_pcmcia_get_timing(skt
, &timing
);
172 pxa2xx_pcmcia_set_mcmem(sock
, timing
.mem
, clk
);
173 pxa2xx_pcmcia_set_mcatt(sock
, timing
.attr
, clk
);
174 pxa2xx_pcmcia_set_mcio(sock
, timing
.io
, clk
);
179 static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket
*skt
)
181 unsigned long clk
= clk_get_rate(skt
->clk
);
182 return pxa2xx_pcmcia_set_mcxx(skt
, clk
/ 10000);
185 #ifdef CONFIG_CPU_FREQ
188 pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket
*skt
,
190 struct cpufreq_freqs
*freqs
)
193 case CPUFREQ_PRECHANGE
:
194 if (freqs
->new > freqs
->old
) {
195 debug(skt
, 2, "new frequency %u.%uMHz > %u.%uMHz, "
197 freqs
->new / 1000, (freqs
->new / 100) % 10,
198 freqs
->old
/ 1000, (freqs
->old
/ 100) % 10);
199 pxa2xx_pcmcia_set_timing(skt
);
203 case CPUFREQ_POSTCHANGE
:
204 if (freqs
->new < freqs
->old
) {
205 debug(skt
, 2, "new frequency %u.%uMHz < %u.%uMHz, "
207 freqs
->new / 1000, (freqs
->new / 100) % 10,
208 freqs
->old
/ 1000, (freqs
->old
/ 100) % 10);
209 pxa2xx_pcmcia_set_timing(skt
);
217 void pxa2xx_configure_sockets(struct device
*dev
)
219 struct pcmcia_low_level
*ops
= dev
->platform_data
;
221 * We have at least one socket, so set MECR:CIT
224 uint32_t mecr
= MECR_CIT
;
226 /* Set MECR:NOS (Number Of Sockets) */
227 if ((ops
->first
+ ops
->nr
) > 1 ||
228 machine_is_viper() || machine_is_arcom_zeus())
231 __raw_writel(mecr
, MECR
);
233 EXPORT_SYMBOL(pxa2xx_configure_sockets
);
235 static const char *skt_names
[] = {
240 #define SKT_DEV_INFO_SIZE(n) \
241 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
243 int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket
*skt
)
245 skt
->res_skt
.start
= _PCMCIA(skt
->nr
);
246 skt
->res_skt
.end
= _PCMCIA(skt
->nr
) + PCMCIASp
- 1;
247 skt
->res_skt
.name
= skt_names
[skt
->nr
];
248 skt
->res_skt
.flags
= IORESOURCE_MEM
;
250 skt
->res_io
.start
= _PCMCIAIO(skt
->nr
);
251 skt
->res_io
.end
= _PCMCIAIO(skt
->nr
) + PCMCIAIOSp
- 1;
252 skt
->res_io
.name
= "io";
253 skt
->res_io
.flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
255 skt
->res_mem
.start
= _PCMCIAMem(skt
->nr
);
256 skt
->res_mem
.end
= _PCMCIAMem(skt
->nr
) + PCMCIAMemSp
- 1;
257 skt
->res_mem
.name
= "memory";
258 skt
->res_mem
.flags
= IORESOURCE_MEM
;
260 skt
->res_attr
.start
= _PCMCIAAttr(skt
->nr
);
261 skt
->res_attr
.end
= _PCMCIAAttr(skt
->nr
) + PCMCIAAttrSp
- 1;
262 skt
->res_attr
.name
= "attribute";
263 skt
->res_attr
.flags
= IORESOURCE_MEM
;
265 return soc_pcmcia_add_one(skt
);
267 EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one
);
269 void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level
*ops
)
271 /* Provide our PXA2xx specific timing routines. */
272 ops
->set_timing
= pxa2xx_pcmcia_set_timing
;
273 #ifdef CONFIG_CPU_FREQ
274 ops
->frequency_change
= pxa2xx_pcmcia_frequency_change
;
277 EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops
);
279 static int pxa2xx_drv_pcmcia_probe(struct platform_device
*dev
)
282 struct pcmcia_low_level
*ops
;
283 struct skt_dev_info
*sinfo
;
284 struct soc_pcmcia_socket
*skt
;
287 ops
= (struct pcmcia_low_level
*)dev
->dev
.platform_data
;
293 if (cpu_is_pxa320() && ops
->nr
> 1) {
294 dev_err(&dev
->dev
, "pxa320 supports only one pcmcia slot");
299 clk
= clk_get(&dev
->dev
, NULL
);
303 pxa2xx_drv_pcmcia_ops(ops
);
305 sinfo
= kzalloc(SKT_DEV_INFO_SIZE(ops
->nr
), GFP_KERNEL
);
311 sinfo
->nskt
= ops
->nr
;
314 /* Initialize processor specific parameters */
315 for (i
= 0; i
< ops
->nr
; i
++) {
316 skt
= &sinfo
->skt
[i
];
318 skt
->nr
= ops
->first
+ i
;
320 soc_pcmcia_init_one(skt
, ops
, &dev
->dev
);
322 ret
= pxa2xx_drv_pcmcia_add_one(skt
);
327 pxa2xx_configure_sockets(&dev
->dev
);
328 dev_set_drvdata(&dev
->dev
, sinfo
);
334 soc_pcmcia_remove_one(&sinfo
->skt
[i
]);
341 static int pxa2xx_drv_pcmcia_remove(struct platform_device
*dev
)
343 struct skt_dev_info
*sinfo
= platform_get_drvdata(dev
);
346 platform_set_drvdata(dev
, NULL
);
348 for (i
= 0; i
< sinfo
->nskt
; i
++)
349 soc_pcmcia_remove_one(&sinfo
->skt
[i
]);
356 static int pxa2xx_drv_pcmcia_resume(struct device
*dev
)
358 pxa2xx_configure_sockets(dev
);
362 static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops
= {
363 .resume
= pxa2xx_drv_pcmcia_resume
,
366 static struct platform_driver pxa2xx_pcmcia_driver
= {
367 .probe
= pxa2xx_drv_pcmcia_probe
,
368 .remove
= pxa2xx_drv_pcmcia_remove
,
370 .name
= "pxa2xx-pcmcia",
371 .pm
= &pxa2xx_drv_pcmcia_pm_ops
,
375 static int __init
pxa2xx_pcmcia_init(void)
377 return platform_driver_register(&pxa2xx_pcmcia_driver
);
380 static void __exit
pxa2xx_pcmcia_exit(void)
382 platform_driver_unregister(&pxa2xx_pcmcia_driver
);
385 fs_initcall(pxa2xx_pcmcia_init
);
386 module_exit(pxa2xx_pcmcia_exit
);
388 MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
389 MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
390 MODULE_LICENSE("GPL");
391 MODULE_ALIAS("platform:pxa2xx-pcmcia");