drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/platform_data/gpio-rcar.h>
  24
  25 #include "sh_pfc.h"
  26
  27 #define PORT_GP_9(bank, fn, sfx)                                        \
  28         PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),       \
  29         PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),       \
  30         PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),       \
  31         PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),       \
  32         PORT_GP_1(bank, 8, fn, sfx)
  33
  34 #define CPU_ALL_PORT(fn, sfx)                                           \
  35         PORT_GP_32(0, fn, sfx),                                         \
  36         PORT_GP_32(1, fn, sfx),                                         \
  37         PORT_GP_32(2, fn, sfx),                                         \
  38         PORT_GP_32(3, fn, sfx),                                         \
  39         PORT_GP_32(4, fn, sfx),                                         \
  40         PORT_GP_32(5, fn, sfx),                                         \
  41         PORT_GP_9(6, fn, sfx)
  42
  43 enum {
  44         PINMUX_RESERVED = 0,
  45
  46         PINMUX_DATA_BEGIN,
  47         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
  48         PINMUX_DATA_END,
  49
  50         PINMUX_FUNCTION_BEGIN,
  51         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
  52
  53         /* GPSR0 */
  54         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
  55         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
  56         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
  57         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
  58         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
  59         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
  60         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
  61         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
  62
  63         /* GPSR1 */
  64         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
  65         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
  66         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
  67         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
  68         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
  69         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
  70         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
  71         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
  72
  73         /* GPSR2 */
  74         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
  75         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
  76         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
  77         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
  78         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
  79         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  80         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  81         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
  82
  83         /* GPSR3 */
  84         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  85         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
  86         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  87         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
  88         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
  89         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
  90         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
  91         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
  92
  93         /* GPSR4 */
  94         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
  95         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
  96         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
  97         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
  98         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
  99         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
 100         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 101         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 102
 103         /* GPSR5 */
 104         FN_A1, FN_A2, FN_A3, FN_A4,
 105         FN_A5, FN_A6, FN_A7, FN_A8,
 106         FN_A9, FN_A10, FN_A11, FN_A12,
 107         FN_A13, FN_A14, FN_A15, FN_A16,
 108         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 109         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 110         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 111         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 112
 113         /* GPSR6 */
 114         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 115         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 116         FN_IP3_20,
 117
 118         /* IPSR0 */
 119         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 120         FN_HRTS1, FN_RX4_C,
 121         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 122         FN_CS0, FN_HSPI_CS2_B,
 123         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 124         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 125         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 126         FN_CTS0_B,
 127         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 128         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 129         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 130         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 131         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 132         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 133         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 134         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 135         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 136         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 137         FN_SCIF_CLK, FN_TCLK0_C,
 138
 139         /* IPSR1 */
 140         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 141         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 142         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 143         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 144         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 145         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 146         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 147         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 148         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 149         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 150         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 151         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 152         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 153         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 154         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 155         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 156
 157         /* IPSR2 */
 158         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 159         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 160         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 161         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 162         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 163         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 164         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 165         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 166         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 167         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 168         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 169         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 170         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 171         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 172         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 173         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 174         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 175         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 176
 177         /* IPSR3 */
 178         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 179         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 180         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 181         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 182         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 183         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 184         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 185         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 186         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 187         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 188         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 189         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 190         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 191         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 192         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 193         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 194         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 195
 196         /* IPSR4 */
 197         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 198         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 199         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 200         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 201         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 202         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 203         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 204         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 205         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 206         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 207         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 208         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 209         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 210         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 211         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 212         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 213         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 214         FN_SCK0_D,
 215
 216         /* IPSR5 */
 217         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 218         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 219         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 220         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 221         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 222         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 223         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 224         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 225         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 226         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 227         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 228         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 229         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 230         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 231         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 232         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 233         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 234         FN_CAN_DEBUGOUT0, FN_MOUT0,
 235
 236         /* IPSR6 */
 237         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 238         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 239         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 240         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 241         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 242         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 243         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 244         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 245         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 246         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 247         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 248         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 249         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 250
 251         /* IPSR7 */
 252         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 253         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 254         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 255         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 256         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 257         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 258         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 259         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 260         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 261         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 262         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 263         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 264         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 265         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 266
 267         /* IPSR8 */
 268         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 269         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 270         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 271         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 272         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 273         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 274         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 275         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 276         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 277         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 278         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 279         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 280         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 281         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 282         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 283         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 284
 285         /* IPSR9 */
 286         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 287         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 288         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 289         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 290         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 291         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 292         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 293         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 294         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 295         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 296         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 297         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 298         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 299         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 300
 301         /* IPSR10 */
 302         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 303         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 304         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 305         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 306         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 307         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 308         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 309         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 310         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 311         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 312         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 313         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 314         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 315         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 316         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 317         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 318
 319         /* IPSR11 */
 320         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 321         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 322         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 323         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 324         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 325         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 326         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 327         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 328         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 329         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 330         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 331         FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 332         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 333         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 334
 335         /* IPSR12 */
 336         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 337         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 338         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 339         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 340         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 341         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 342         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 343         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 344         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 345
 346         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 347         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 348         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 349         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 350         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 351         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 352         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 353         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 354         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 355         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 356         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 357         FN_SEL_VI0_0, FN_SEL_VI0_1,
 358         FN_SEL_SD2_0, FN_SEL_SD2_1,
 359         FN_SEL_INT3_0, FN_SEL_INT3_1,
 360         FN_SEL_INT2_0, FN_SEL_INT2_1,
 361         FN_SEL_INT1_0, FN_SEL_INT1_1,
 362         FN_SEL_INT0_0, FN_SEL_INT0_1,
 363         FN_SEL_IE_0, FN_SEL_IE_1,
 364         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 365         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 366         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 367
 368         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 369         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 370         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 371         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 372         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 373         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 374         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 375         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 376         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 377         FN_SEL_ADI_0, FN_SEL_ADI_1,
 378         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 379         FN_SEL_SIM_0, FN_SEL_SIM_1,
 380         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 381         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 382         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 383         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 384         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 385         PINMUX_FUNCTION_END,
 386
 387         PINMUX_MARK_BEGIN,
 388         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 389         A19_MARK,
 390
 391         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 392         HRTS1_MARK, RX4_C_MARK,
 393         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 394         CS0_MARK, HSPI_CS2_B_MARK,
 395         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 396         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 397         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 398         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 399         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 400         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 401         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 402         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 403         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 404         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 405         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 406         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 407         USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
 408         SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 409         SCIF_CLK_MARK, TCLK0_C_MARK,
 410
 411         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 412         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 413         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 414         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 415         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 416         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 417         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 418         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 419         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 420         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 421         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 422         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 423         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 424         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 425         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 426         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 427
 428         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 429         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 430         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 431         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 432         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 433         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 434         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 435         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 436         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 437         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 438         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 439         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 440         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 441         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 442         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 443         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 444         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 445         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 446
 447         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 448         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 449         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 450         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 451         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 452         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 453         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 454         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 455         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 456         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 457         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 458         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 459         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 460         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 461         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 462         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 463         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 464
 465         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 466         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 467         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 468         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 469         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 470         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 471         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 472         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 473         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 474         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 475         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 476         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 477         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 478         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 479         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 480         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 481         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 482         SCK0_D_MARK,
 483
 484         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 485         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 486         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 487         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 488         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 489         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 490         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 491         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 492         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 493         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 494         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 495         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 496         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 497         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 498         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 499         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 500         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 501         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 502
 503         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 504         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 505         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 506         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 507         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 508         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 509         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 510         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 511         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 512         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 513         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 514         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 515         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 516
 517         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 518         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 519         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 520         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 521         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 522         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 523         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 524         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 525         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 526         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 527         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 528         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 529         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 530         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 531
 532         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 533         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 534         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 535         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 536         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 537         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 538         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 539         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 540         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 541         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 542         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 543         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 544         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 545         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 546         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 547         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 548
 549         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 550         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 551         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 552         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 553         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 554         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 555         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 556         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 557         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 558         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 559         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 560         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 561         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 562         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 563         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 564
 565         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 566         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 567         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 568         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 569         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 570         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 571         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 572         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 573         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 574         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 575         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 576         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 577         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 578         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 579         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 580         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 581
 582         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 583         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 584         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 585         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 586         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 587         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 588         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 589         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 590         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 591         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 592         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 593         VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
 594         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 595         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 596         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 597
 598         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 599         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 600         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 601         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 602         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 603         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 604         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 605         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 606         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 607         PINMUX_MARK_END,
 608 };
 609
 610 static const u16 pinmux_data[] = {
 611         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 612
 613         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 614         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 615         PINMUX_DATA(A17_MARK, FN_A17),
 616         PINMUX_DATA(A18_MARK, FN_A18),
 617         PINMUX_DATA(A19_MARK, FN_A19),
 618
 619         PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
 620         PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
 621
 622         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 623         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 624         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 625         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 626         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 627         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 628         PINMUX_IPSR_DATA(IP0_5_3, BS),
 629         PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
 630         PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
 631         PINMUX_IPSR_DATA(IP0_5_3, FD2),
 632         PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
 633         PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
 634         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 635         PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
 636         PINMUX_IPSR_DATA(IP0_7_6, A0),
 637         PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
 638         PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
 639         PINMUX_IPSR_DATA(IP0_7_6, FD3),
 640         PINMUX_IPSR_DATA(IP0_9_8, A20),
 641         PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
 642         PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
 643         PINMUX_IPSR_DATA(IP0_11_10, A21),
 644         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 645         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 646         PINMUX_IPSR_DATA(IP0_13_12, A22),
 647         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
 648         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 649         PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
 650         PINMUX_IPSR_DATA(IP0_15_14, A23),
 651         PINMUX_IPSR_DATA(IP0_15_14, FCLE),
 652         PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 653         PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
 654         PINMUX_IPSR_DATA(IP0_18_16, A24),
 655         PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
 656         PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
 657         PINMUX_IPSR_DATA(IP0_18_16, FD4),
 658         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 659         PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
 660         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 661         PINMUX_IPSR_DATA(IP0_22_19, A25),
 662         PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
 663         PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
 664         PINMUX_IPSR_DATA(IP0_22_19, FD5),
 665         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 666         PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
 667         PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
 668         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 669         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 670         PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
 671         PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
 672         PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
 673         PINMUX_IPSR_DATA(IP0_25, CS0),
 674         PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 675         PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
 676         PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
 677         PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
 678         PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
 679         PINMUX_IPSR_DATA(IP0_30_28, FWE),
 680         PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
 681         PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
 682         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 683         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
 684
 685         PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
 686         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 687         PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
 688         PINMUX_IPSR_DATA(IP1_1_0, FD6),
 689         PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
 690         PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
 691         PINMUX_IPSR_DATA(IP1_3_2, FD7),
 692         PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
 693         PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
 694         PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
 695         PINMUX_IPSR_DATA(IP1_6_4, FALE),
 696         PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
 697         PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
 698         PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
 699         PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
 700         PINMUX_IPSR_DATA(IP1_10_7, FRE),
 701         PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
 702         PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
 703         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
 704         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 705         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 706         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 707         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 708         PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
 709         PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
 710         PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
 711         PINMUX_IPSR_DATA(IP1_14_11, FD0),
 712         PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
 713         PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
 714         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 715         PINMUX_IPSR_DATA(IP1_14_11, HTX1),
 716         PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
 717         PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
 718         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 719         PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
 720         PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
 721         PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
 722         PINMUX_IPSR_DATA(IP1_18_15, FD1),
 723         PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
 724         PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
 725         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
 726         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
 727         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
 728         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 729         PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
 730         PINMUX_IPSR_DATA(IP1_20_19, PWM2),
 731         PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
 732         PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
 733         PINMUX_IPSR_DATA(IP1_22_21, PWM3),
 734         PINMUX_IPSR_DATA(IP1_22_21, TX4),
 735         PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
 736         PINMUX_IPSR_DATA(IP1_24_23, PWM4),
 737         PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
 738         PINMUX_IPSR_DATA(IP1_28_25, HTX0),
 739         PINMUX_IPSR_DATA(IP1_28_25, TX1),
 740         PINMUX_IPSR_DATA(IP1_28_25, SDATA),
 741         PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 742         PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
 743         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
 744         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
 745         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
 746         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
 747         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
 748
 749         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
 750         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
 751         PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
 752         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 753         PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
 754         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
 755         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
 756         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
 757         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
 758         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
 759         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 760         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
 761         PINMUX_IPSR_DATA(IP2_7_4, MTS),
 762         PINMUX_IPSR_DATA(IP2_7_4, PWM5),
 763         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 764         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 765         PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
 766         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
 767         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
 768         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
 769         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
 770         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
 771         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 772         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
 773         PINMUX_IPSR_DATA(IP2_11_8, STM),
 774         PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
 775         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
 776         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 777         PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
 778         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 779         PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
 780         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 781         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 782         PINMUX_IPSR_DATA(IP2_15_12, MDATA),
 783         PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
 784         PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
 785         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
 786         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
 787         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
 788         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
 789         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
 790         PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
 791         PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
 792         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 793         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 794         PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
 795         PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
 796         PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
 797         PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
 798         PINMUX_IPSR_DATA(IP2_21_19, DACK0),
 799         PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
 800         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 801         PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
 802         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
 803         PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
 804         PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
 805         PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
 806         PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
 807         PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
 808         PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
 809         PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
 810         PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
 811         PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
 812         PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
 813         PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
 814         PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
 815         PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
 816         PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
 817         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 818         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
 819         PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
 820
 821         PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
 822         PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
 823         PINMUX_IPSR_DATA(IP3_2_0, DACK1),
 824         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
 825         PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
 826         PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
 827         PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
 828         PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
 829         PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
 830         PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
 831         PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
 832         PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
 833         PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
 834         PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
 835         PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
 836         PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
 837         PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
 838         PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
 839         PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
 840         PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
 841         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
 842         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
 843         PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
 844         PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
 845         PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
 846         PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
 847         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
 848         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 849         PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
 850         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 851         PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
 852         PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
 853         PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
 854         PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
 855         PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
 856         PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
 857         PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
 858         PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
 859         PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
 860         PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
 861         PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
 862         PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
 863         PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
 864         PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
 865         PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
 866         PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
 867         PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
 868         PINMUX_IPSR_DATA(IP3_23, QCLK),
 869         PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
 870         PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
 871         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 872         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
 873         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
 874         PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
 875         PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
 876         PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 877         PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
 878         PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 879         PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
 880         PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 881         PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
 882         PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
 883         PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
 884         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
 885         PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
 886
 887         PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
 888         PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
 889         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 890         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 891         PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
 892         PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
 893         PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
 894         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
 895         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 896         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 897         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 898         PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
 899         PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
 900         PINMUX_IPSR_DATA(IP4_7_5, PWM6),
 901         PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
 902         PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
 903         PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
 904         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 905         PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
 906         PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
 907         PINMUX_IPSR_DATA(IP4_10_8, PWM0),
 908         PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
 909         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 910         PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
 911         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 912         PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
 913         PINMUX_IPSR_DATA(IP4_11, VI2_G0),
 914         PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
 915         PINMUX_IPSR_DATA(IP4_12, VI2_G1),
 916         PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
 917         PINMUX_IPSR_DATA(IP4_13, VI2_G2),
 918         PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
 919         PINMUX_IPSR_DATA(IP4_14, VI2_G3),
 920         PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
 921         PINMUX_IPSR_DATA(IP4_15, VI2_G4),
 922         PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
 923         PINMUX_IPSR_DATA(IP4_16, VI2_G5),
 924         PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
 925         PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
 926         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
 927         PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
 928         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 929         PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
 930         PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
 931         PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
 932         PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
 933         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
 934         PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
 935         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
 936         PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
 937         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
 938         PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
 939         PINMUX_IPSR_DATA(IP4_23, VI2_G6),
 940         PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
 941         PINMUX_IPSR_DATA(IP4_24, VI2_G7),
 942         PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
 943         PINMUX_IPSR_DATA(IP4_25, VI2_R0),
 944         PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
 945         PINMUX_IPSR_DATA(IP4_26, VI2_R1),
 946         PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
 947         PINMUX_IPSR_DATA(IP4_27, VI2_R2),
 948         PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
 949         PINMUX_IPSR_DATA(IP4_28, VI2_R3),
 950         PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
 951         PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
 952         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
 953         PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
 954         PINMUX_IPSR_DATA(IP4_31_29, TX5),
 955         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
 956
 957         PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
 958         PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
 959         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
 960         PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
 961         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
 962         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
 963         PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
 964         PINMUX_IPSR_DATA(IP5_3, VI2_R4),
 965         PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
 966         PINMUX_IPSR_DATA(IP5_4, VI2_R5),
 967         PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
 968         PINMUX_IPSR_DATA(IP5_5, VI2_R6),
 969         PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
 970         PINMUX_IPSR_DATA(IP5_6, VI2_R7),
 971         PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
 972         PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
 973         PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
 974         PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
 975         PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
 976         PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
 977         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
 978         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
 979         PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
 980         PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
 981         PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
 982         PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
 983         PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
 984         PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
 985         PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
 986         PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
 987         PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
 988         PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
 989         PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
 990         PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
 991         PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
 992         PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
 993         PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
 994         PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
 995         PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
 996         PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
 997         PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
 998         PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
 999         PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1000         PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1001         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1002         PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1003         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1004         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1005         PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1006         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1007         PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1008         PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1009         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1010         PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1011         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1012         PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1013         PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1014         PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1015         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1016         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1017         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1018         PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1019         PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1020         PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1021         PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1022         PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1023         PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1024
1025         PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1026         PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1027         PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1028         PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1029         PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1030         PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1031         PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1032         PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1033         PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1034         PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1035         PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1036         PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1037         PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1038         PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1039         PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1040         PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1041         PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1042         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1043         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1044         PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1045         PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1046         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1047         PINMUX_IPSR_DATA(IP6_14_12, IETX),
1048         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1049         PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1050         PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1051         PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1052         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1053         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1055         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1056         PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1057         PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1058         PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1059         PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1060         PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1061         PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1062         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1063         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1064         PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1065         PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1066         PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1067         PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1068         PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1069         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1070         PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1071         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1072         PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1073         PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1074         PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1075         PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1076
1077         PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1078         PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1079         PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1080         PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1081         PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1082         PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1083         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1084         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1085         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1086         PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1087         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1088         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1089         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1090         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1091         PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1092         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1093         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1094         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1095         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1096         PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1097         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1098         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1099         PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1100         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1101         PINMUX_IPSR_DATA(IP7_14_13, VSP),
1102         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1103         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1104         PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1105         PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1106         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1107         PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1108         PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1109         PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1110         PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1111         PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1112         PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1113         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1114         PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1115         PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1116         PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1117         PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1118         PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1119         PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1120         PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1121         PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1122         PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1123         PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1124         PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1125         PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1126         PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1127         PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1128         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1129         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1130         PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1131         PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1132         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1133
1134         PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1135         PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1136         PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1137         PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1138         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1139         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1140         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1141         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1142         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1143         PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1144         PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1145         PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1146         PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1147         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1148         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1149         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1150         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1151         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1152         PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1153         PINMUX_IPSR_DATA(IP8_11_8, TX0),
1154         PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1155         PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1156         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1157         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1158         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1159         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1160         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1161         PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1162         PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1163         PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1164         PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1165         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1166         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1167         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1168         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1169         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1170         PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1171         PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1172         PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1173         PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1174         PINMUX_IPSR_DATA(IP8_18, PCMWE),
1175         PINMUX_IPSR_DATA(IP8_19, FMIN),
1176         PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1177         PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1178         PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1179         PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1180         PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1181         PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1182         PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1183         PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1184         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1185         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1186         PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1187         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1188         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1189         PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1190         PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1191         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1192         PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1193         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1194         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1195         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1196         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1197
1198         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1199         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1200         PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1201         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1202         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1203         PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1204         PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1205         PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1206         PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1207         PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1208         PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1209         PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1210         PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1211         PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1212         PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1213         PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1214         PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1215         PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1216         PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1217         PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1218         PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1219         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1220         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1221         PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1222         PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1223         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1224         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1225         PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1226         PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1227         PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1228         PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1229         PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1230         PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1231         PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1232         PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1233         PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1234         PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1235         PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1236         PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1237         PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1238         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1239         PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1240         PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1241         PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1242         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1243         PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1244         PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1245         PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1246         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1247         PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1248         PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1249         PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1250         PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1251         PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1252
1253         PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1254         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1255         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1256         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1257         PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1258         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1259         PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1260         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1261         PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1262         PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1263         PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1264         PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1265         PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1266         PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1267         PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1268         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1269         PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1270         PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1271         PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1272         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1273         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1274         PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1275         PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1276         PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1277         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1278         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1279         PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1280         PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1281         PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1282         PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1283         PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1284         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1285         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1286         PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1287         PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1288         PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1289         PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1290         PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1291         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1292         PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1293         PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1294         PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1295         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1296         PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1297         PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1298         PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1299         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1300         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1301         PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1302         PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1303         PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1304         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1305         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1306         PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1307         PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1308         PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1311         PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1312         PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1313         PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1314         PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1315         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1316         PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1318
1319         PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1320         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1321         PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1322         PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1323         PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1324         PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1325         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1326         PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1327         PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1328         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1329         PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1330         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1331         PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1332         PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1333         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1334         PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1335         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1336         PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1337         PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1338         PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1339         PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1340         PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1341         PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1342         PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1343         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1344         PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1345         PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1346         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1347         PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1348         PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1349         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1350         PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1351         PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1352         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1353         PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1354         PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1355         PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1356         PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1357         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1358         PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1359         PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1360         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1361         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1362         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1363         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1364         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1365         PINMUX_IPSR_DATA(IP11_26_24, TX2),
1366         PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1367         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1368         PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1369         PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1370         PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1371         PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1372         PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1373         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1374         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1375
1376         PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1377         PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1378         PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1379         PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1380         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1381         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1382         PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1383         PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1384         PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1385         PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1386         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1387         PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1388         PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1389         PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1390         PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1391         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1392         PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1393         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1394         PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1395         PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1396         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1397         PINMUX_IPSR_DATA(IP12_11_9, FSE),
1398         PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1399         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1400         PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1401         PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1402         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1403         PINMUX_IPSR_DATA(IP12_14_12, FRB),
1404         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1405         PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1406         PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1407         PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1408         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1409         PINMUX_IPSR_DATA(IP12_17_15, FCE),
1410         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1411 };
1412
1413 static const struct sh_pfc_pin pinmux_pins[] = {
1414         PINMUX_GPIO_GP_ALL(),
1415 };
1416
1417 /* - DU0 -------------------------------------------------------------------- */
1418 static const unsigned int du0_rgb666_pins[] = {
1419         /* R[7:2], G[7:2], B[7:2] */
1420         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1421         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1422         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
1423         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1424         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
1425         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
1426 };
1427 static const unsigned int du0_rgb666_mux[] = {
1428         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1429         DU0_DR3_MARK, DU0_DR2_MARK,
1430         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1431         DU0_DG3_MARK, DU0_DG2_MARK,
1432         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1433         DU0_DB3_MARK, DU0_DB2_MARK,
1434 };
1435 static const unsigned int du0_rgb888_pins[] = {
1436         /* R[7:0], G[7:0], B[7:0] */
1437         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1438         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1439         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1440         RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
1441         RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1442         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
1443         RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
1444         RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1445 };
1446 static const unsigned int du0_rgb888_mux[] = {
1447         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1448         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1449         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1450         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1451         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1452         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1453 };
1454 static const unsigned int du0_clk_in_pins[] = {
1455         /* CLKIN */
1456         RCAR_GP_PIN(0, 29),
1457 };
1458 static const unsigned int du0_clk_in_mux[] = {
1459         DU0_DOTCLKIN_MARK,
1460 };
1461 static const unsigned int du0_clk_out_0_pins[] = {
1462         /* CLKOUT */
1463         RCAR_GP_PIN(5, 20),
1464 };
1465 static const unsigned int du0_clk_out_0_mux[] = {
1466         DU0_DOTCLKOUT0_MARK,
1467 };
1468 static const unsigned int du0_clk_out_1_pins[] = {
1469         /* CLKOUT */
1470         RCAR_GP_PIN(0, 30),
1471 };
1472 static const unsigned int du0_clk_out_1_mux[] = {
1473         DU0_DOTCLKOUT1_MARK,
1474 };
1475 static const unsigned int du0_sync_0_pins[] = {
1476         /* VSYNC, HSYNC, DISP */
1477         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1478 };
1479 static const unsigned int du0_sync_0_mux[] = {
1480         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1481         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1482 };
1483 static const unsigned int du0_sync_1_pins[] = {
1484         /* VSYNC, HSYNC, DISP */
1485         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1486 };
1487 static const unsigned int du0_sync_1_mux[] = {
1488         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1489         DU0_DISP_MARK
1490 };
1491 static const unsigned int du0_oddf_pins[] = {
1492         /* ODDF */
1493         RCAR_GP_PIN(0, 31),
1494 };
1495 static const unsigned int du0_oddf_mux[] = {
1496         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1497 };
1498 static const unsigned int du0_cde_pins[] = {
1499         /* CDE */
1500         RCAR_GP_PIN(1, 1),
1501 };
1502 static const unsigned int du0_cde_mux[] = {
1503         DU0_CDE_MARK
1504 };
1505 /* - DU1 -------------------------------------------------------------------- */
1506 static const unsigned int du1_rgb666_pins[] = {
1507         /* R[7:2], G[7:2], B[7:2] */
1508         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1509         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1510         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1511         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1512         RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1513         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1514 };
1515 static const unsigned int du1_rgb666_mux[] = {
1516         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1517         DU1_DR3_MARK, DU1_DR2_MARK,
1518         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1519         DU1_DG3_MARK, DU1_DG2_MARK,
1520         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1521         DU1_DB3_MARK, DU1_DB2_MARK,
1522 };
1523 static const unsigned int du1_rgb888_pins[] = {
1524         /* R[7:0], G[7:0], B[7:0] */
1525         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1526         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1527         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
1528         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1529         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1530         RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1531         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1532         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1533 };
1534 static const unsigned int du1_rgb888_mux[] = {
1535         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1536         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1537         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1538         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1539         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1540         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1541 };
1542 static const unsigned int du1_clk_in_pins[] = {
1543         /* CLKIN */
1544         RCAR_GP_PIN(1, 26),
1545 };
1546 static const unsigned int du1_clk_in_mux[] = {
1547         DU1_DOTCLKIN_MARK,
1548 };
1549 static const unsigned int du1_clk_out_pins[] = {
1550         /* CLKOUT */
1551         RCAR_GP_PIN(1, 27),
1552 };
1553 static const unsigned int du1_clk_out_mux[] = {
1554         DU1_DOTCLKOUT_MARK,
1555 };
1556 static const unsigned int du1_sync_0_pins[] = {
1557         /* VSYNC, HSYNC, DISP */
1558         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1559 };
1560 static const unsigned int du1_sync_0_mux[] = {
1561         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1562         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1563 };
1564 static const unsigned int du1_sync_1_pins[] = {
1565         /* VSYNC, HSYNC, DISP */
1566         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1567 };
1568 static const unsigned int du1_sync_1_mux[] = {
1569         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1570         DU1_DISP_MARK
1571 };
1572 static const unsigned int du1_oddf_pins[] = {
1573         /* ODDF */
1574         RCAR_GP_PIN(1, 30),
1575 };
1576 static const unsigned int du1_oddf_mux[] = {
1577         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1578 };
1579 static const unsigned int du1_cde_pins[] = {
1580         /* CDE */
1581         RCAR_GP_PIN(2, 0),
1582 };
1583 static const unsigned int du1_cde_mux[] = {
1584         DU1_CDE_MARK
1585 };
1586 /* - Ether ------------------------------------------------------------------ */
1587 static const unsigned int ether_rmii_pins[] = {
1588         /*
1589          * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
1590          * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1591          * ETH_MDIO, ETH_MDC
1592          */
1593         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1594         RCAR_GP_PIN(2, 26),
1595         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1596         RCAR_GP_PIN(2, 19),
1597         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1598 };
1599 static const unsigned int ether_rmii_mux[] = {
1600         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
1601         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1602         ETH_MDIO_MARK, ETH_MDC_MARK,
1603 };
1604 static const unsigned int ether_link_pins[] = {
1605         /* ETH_LINK */
1606         RCAR_GP_PIN(2, 24),
1607 };
1608 static const unsigned int ether_link_mux[] = {
1609         ETH_LINK_MARK,
1610 };
1611 static const unsigned int ether_magic_pins[] = {
1612         /* ETH_MAGIC */
1613         RCAR_GP_PIN(2, 25),
1614 };
1615 static const unsigned int ether_magic_mux[] = {
1616         ETH_MAGIC_MARK,
1617 };
1618 /* - HSPI0 ------------------------------------------------------------------ */
1619 static const unsigned int hspi0_pins[] = {
1620         /* CLK, CS, RX, TX */
1621         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1622         RCAR_GP_PIN(4, 24),
1623 };
1624 static const unsigned int hspi0_mux[] = {
1625         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1626 };
1627 /* - HSPI1 ------------------------------------------------------------------ */
1628 static const unsigned int hspi1_pins[] = {
1629         /* CLK, CS, RX, TX */
1630         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1631         RCAR_GP_PIN(1, 30),
1632 };
1633 static const unsigned int hspi1_mux[] = {
1634         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1635 };
1636 static const unsigned int hspi1_b_pins[] = {
1637         /* CLK, CS, RX, TX */
1638         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1639         RCAR_GP_PIN(2, 28),
1640 };
1641 static const unsigned int hspi1_b_mux[] = {
1642         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1643 };
1644 static const unsigned int hspi1_c_pins[] = {
1645         /* CLK, CS, RX, TX */
1646         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1647         RCAR_GP_PIN(4, 15),
1648 };
1649 static const unsigned int hspi1_c_mux[] = {
1650         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1651 };
1652 static const unsigned int hspi1_d_pins[] = {
1653         /* CLK, CS, RX, TX */
1654         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1655         RCAR_GP_PIN(3, 7),
1656 };
1657 static const unsigned int hspi1_d_mux[] = {
1658         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1659 };
1660 /* - HSPI2 ------------------------------------------------------------------ */
1661 static const unsigned int hspi2_pins[] = {
1662         /* CLK, CS, RX, TX */
1663         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1664         RCAR_GP_PIN(0, 14),
1665 };
1666 static const unsigned int hspi2_mux[] = {
1667         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1668 };
1669 static const unsigned int hspi2_b_pins[] = {
1670         /* CLK, CS, RX, TX */
1671         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1672         RCAR_GP_PIN(0, 6),
1673 };
1674 static const unsigned int hspi2_b_mux[] = {
1675         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1676 };
1677 /* - I2C1 ------------------------------------------------------------------ */
1678 static const unsigned int i2c1_pins[] = {
1679         /* SCL, SDA, */
1680         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1681 };
1682 static const unsigned int i2c1_mux[] = {
1683         SCL1_MARK, SDA1_MARK,
1684 };
1685 static const unsigned int i2c1_b_pins[] = {
1686         /* SCL, SDA, */
1687         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1688 };
1689 static const unsigned int i2c1_b_mux[] = {
1690         SCL1_B_MARK, SDA1_B_MARK,
1691 };
1692 static const unsigned int i2c1_c_pins[] = {
1693         /* SCL, SDA, */
1694         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1695 };
1696 static const unsigned int i2c1_c_mux[] = {
1697         SCL1_C_MARK, SDA1_C_MARK,
1698 };
1699 static const unsigned int i2c1_d_pins[] = {
1700         /* SCL, SDA, */
1701         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1702 };
1703 static const unsigned int i2c1_d_mux[] = {
1704         SCL1_D_MARK, SDA1_D_MARK,
1705 };
1706 /* - I2C2 ------------------------------------------------------------------ */
1707 static const unsigned int i2c2_pins[] = {
1708         /* SCL, SDA, */
1709         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
1710 };
1711 static const unsigned int i2c2_mux[] = {
1712         SCL2_MARK, SDA2_MARK,
1713 };
1714 static const unsigned int i2c2_b_pins[] = {
1715         /* SCL, SDA, */
1716         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1717 };
1718 static const unsigned int i2c2_b_mux[] = {
1719         SCL2_B_MARK, SDA2_B_MARK,
1720 };
1721 static const unsigned int i2c2_c_pins[] = {
1722         /* SCL, SDA */
1723         RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
1724 };
1725 static const unsigned int i2c2_c_mux[] = {
1726         SCL2_C_MARK, SDA2_C_MARK,
1727 };
1728 static const unsigned int i2c2_d_pins[] = {
1729         /* SCL, SDA */
1730         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
1731 };
1732 static const unsigned int i2c2_d_mux[] = {
1733         SCL2_D_MARK, SDA2_D_MARK,
1734 };
1735 /* - I2C3 ------------------------------------------------------------------ */
1736 static const unsigned int i2c3_pins[] = {
1737         /* SCL, SDA, */
1738         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
1739 };
1740 static const unsigned int i2c3_mux[] = {
1741         SCL3_MARK, SDA3_MARK,
1742 };
1743 static const unsigned int i2c3_b_pins[] = {
1744         /* SCL, SDA, */
1745         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
1746 };
1747 static const unsigned int i2c3_b_mux[] = {
1748         SCL3_B_MARK, SDA3_B_MARK,
1749 };
1750 /* - INTC ------------------------------------------------------------------- */
1751 static const unsigned int intc_irq0_pins[] = {
1752         /* IRQ */
1753         RCAR_GP_PIN(2, 14),
1754 };
1755 static const unsigned int intc_irq0_mux[] = {
1756         IRQ0_MARK,
1757 };
1758 static const unsigned int intc_irq0_b_pins[] = {
1759         /* IRQ */
1760         RCAR_GP_PIN(4, 13),
1761 };
1762 static const unsigned int intc_irq0_b_mux[] = {
1763         IRQ0_B_MARK,
1764 };
1765 static const unsigned int intc_irq1_pins[] = {
1766         /* IRQ */
1767         RCAR_GP_PIN(2, 15),
1768 };
1769 static const unsigned int intc_irq1_mux[] = {
1770         IRQ1_MARK,
1771 };
1772 static const unsigned int intc_irq1_b_pins[] = {
1773         /* IRQ */
1774         RCAR_GP_PIN(4, 14),
1775 };
1776 static const unsigned int intc_irq1_b_mux[] = {
1777         IRQ1_B_MARK,
1778 };
1779 static const unsigned int intc_irq2_pins[] = {
1780         /* IRQ */
1781         RCAR_GP_PIN(2, 24),
1782 };
1783 static const unsigned int intc_irq2_mux[] = {
1784         IRQ2_MARK,
1785 };
1786 static const unsigned int intc_irq2_b_pins[] = {
1787         /* IRQ */
1788         RCAR_GP_PIN(4, 15),
1789 };
1790 static const unsigned int intc_irq2_b_mux[] = {
1791         IRQ2_B_MARK,
1792 };
1793 static const unsigned int intc_irq3_pins[] = {
1794         /* IRQ */
1795         RCAR_GP_PIN(2, 25),
1796 };
1797 static const unsigned int intc_irq3_mux[] = {
1798         IRQ3_MARK,
1799 };
1800 static const unsigned int intc_irq3_b_pins[] = {
1801         /* IRQ */
1802         RCAR_GP_PIN(4, 16),
1803 };
1804 static const unsigned int intc_irq3_b_mux[] = {
1805         IRQ3_B_MARK,
1806 };
1807 /* - LSBC ------------------------------------------------------------------- */
1808 static const unsigned int lbsc_cs0_pins[] = {
1809         /* CS */
1810         RCAR_GP_PIN(0, 13),
1811 };
1812 static const unsigned int lbsc_cs0_mux[] = {
1813         CS0_MARK,
1814 };
1815 static const unsigned int lbsc_cs1_pins[] = {
1816         /* CS */
1817         RCAR_GP_PIN(0, 14),
1818 };
1819 static const unsigned int lbsc_cs1_mux[] = {
1820         CS1_A26_MARK,
1821 };
1822 static const unsigned int lbsc_ex_cs0_pins[] = {
1823         /* CS */
1824         RCAR_GP_PIN(0, 15),
1825 };
1826 static const unsigned int lbsc_ex_cs0_mux[] = {
1827         EX_CS0_MARK,
1828 };
1829 static const unsigned int lbsc_ex_cs1_pins[] = {
1830         /* CS */
1831         RCAR_GP_PIN(0, 16),
1832 };
1833 static const unsigned int lbsc_ex_cs1_mux[] = {
1834         EX_CS1_MARK,
1835 };
1836 static const unsigned int lbsc_ex_cs2_pins[] = {
1837         /* CS */
1838         RCAR_GP_PIN(0, 17),
1839 };
1840 static const unsigned int lbsc_ex_cs2_mux[] = {
1841         EX_CS2_MARK,
1842 };
1843 static const unsigned int lbsc_ex_cs3_pins[] = {
1844         /* CS */
1845         RCAR_GP_PIN(0, 18),
1846 };
1847 static const unsigned int lbsc_ex_cs3_mux[] = {
1848         EX_CS3_MARK,
1849 };
1850 static const unsigned int lbsc_ex_cs4_pins[] = {
1851         /* CS */
1852         RCAR_GP_PIN(0, 19),
1853 };
1854 static const unsigned int lbsc_ex_cs4_mux[] = {
1855         EX_CS4_MARK,
1856 };
1857 static const unsigned int lbsc_ex_cs5_pins[] = {
1858         /* CS */
1859         RCAR_GP_PIN(0, 20),
1860 };
1861 static const unsigned int lbsc_ex_cs5_mux[] = {
1862         EX_CS5_MARK,
1863 };
1864 /* - MMCIF ------------------------------------------------------------------ */
1865 static const unsigned int mmc0_data1_pins[] = {
1866         /* D[0] */
1867         RCAR_GP_PIN(0, 19),
1868 };
1869 static const unsigned int mmc0_data1_mux[] = {
1870         MMC0_D0_MARK,
1871 };
1872 static const unsigned int mmc0_data4_pins[] = {
1873         /* D[0:3] */
1874         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1875         RCAR_GP_PIN(0, 2),
1876 };
1877 static const unsigned int mmc0_data4_mux[] = {
1878         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1879 };
1880 static const unsigned int mmc0_data8_pins[] = {
1881         /* D[0:7] */
1882         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1883         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1884         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1885 };
1886 static const unsigned int mmc0_data8_mux[] = {
1887         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1888         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1889 };
1890 static const unsigned int mmc0_ctrl_pins[] = {
1891         /* CMD, CLK */
1892         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1893 };
1894 static const unsigned int mmc0_ctrl_mux[] = {
1895         MMC0_CMD_MARK, MMC0_CLK_MARK,
1896 };
1897 static const unsigned int mmc1_data1_pins[] = {
1898         /* D[0] */
1899         RCAR_GP_PIN(2, 8),
1900 };
1901 static const unsigned int mmc1_data1_mux[] = {
1902         MMC1_D0_MARK,
1903 };
1904 static const unsigned int mmc1_data4_pins[] = {
1905         /* D[0:3] */
1906         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1907         RCAR_GP_PIN(2, 11),
1908 };
1909 static const unsigned int mmc1_data4_mux[] = {
1910         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1911 };
1912 static const unsigned int mmc1_data8_pins[] = {
1913         /* D[0:7] */
1914         RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
1915         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1916         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1917 };
1918 static const unsigned int mmc1_data8_mux[] = {
1919         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1920         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1921 };
1922 static const unsigned int mmc1_ctrl_pins[] = {
1923         /* CMD, CLK */
1924         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1925 };
1926 static const unsigned int mmc1_ctrl_mux[] = {
1927         MMC1_CMD_MARK, MMC1_CLK_MARK,
1928 };
1929 /* - SCIF0 ------------------------------------------------------------------ */
1930 static const unsigned int scif0_data_pins[] = {
1931         /* RXD, TXD */
1932         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1933 };
1934 static const unsigned int scif0_data_mux[] = {
1935         RX0_MARK, TX0_MARK,
1936 };
1937 static const unsigned int scif0_clk_pins[] = {
1938         /* SCK */
1939         RCAR_GP_PIN(4, 28),
1940 };
1941 static const unsigned int scif0_clk_mux[] = {
1942         SCK0_MARK,
1943 };
1944 static const unsigned int scif0_ctrl_pins[] = {
1945         /* RTS, CTS */
1946         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1947 };
1948 static const unsigned int scif0_ctrl_mux[] = {
1949         RTS0_TANS_MARK, CTS0_MARK,
1950 };
1951 static const unsigned int scif0_data_b_pins[] = {
1952         /* RXD, TXD */
1953         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1954 };
1955 static const unsigned int scif0_data_b_mux[] = {
1956         RX0_B_MARK, TX0_B_MARK,
1957 };
1958 static const unsigned int scif0_clk_b_pins[] = {
1959         /* SCK */
1960         RCAR_GP_PIN(1, 1),
1961 };
1962 static const unsigned int scif0_clk_b_mux[] = {
1963         SCK0_B_MARK,
1964 };
1965 static const unsigned int scif0_ctrl_b_pins[] = {
1966         /* RTS, CTS */
1967         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
1968 };
1969 static const unsigned int scif0_ctrl_b_mux[] = {
1970         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1971 };
1972 static const unsigned int scif0_data_c_pins[] = {
1973         /* RXD, TXD */
1974         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1975 };
1976 static const unsigned int scif0_data_c_mux[] = {
1977         RX0_C_MARK, TX0_C_MARK,
1978 };
1979 static const unsigned int scif0_clk_c_pins[] = {
1980         /* SCK */
1981         RCAR_GP_PIN(4, 17),
1982 };
1983 static const unsigned int scif0_clk_c_mux[] = {
1984         SCK0_C_MARK,
1985 };
1986 static const unsigned int scif0_ctrl_c_pins[] = {
1987         /* RTS, CTS */
1988         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1989 };
1990 static const unsigned int scif0_ctrl_c_mux[] = {
1991         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1992 };
1993 static const unsigned int scif0_data_d_pins[] = {
1994         /* RXD, TXD */
1995         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1996 };
1997 static const unsigned int scif0_data_d_mux[] = {
1998         RX0_D_MARK, TX0_D_MARK,
1999 };
2000 static const unsigned int scif0_clk_d_pins[] = {
2001         /* SCK */
2002         RCAR_GP_PIN(1, 18),
2003 };
2004 static const unsigned int scif0_clk_d_mux[] = {
2005         SCK0_D_MARK,
2006 };
2007 static const unsigned int scif0_ctrl_d_pins[] = {
2008         /* RTS, CTS */
2009         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
2010 };
2011 static const unsigned int scif0_ctrl_d_mux[] = {
2012         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
2013 };
2014 /* - SCIF1 ------------------------------------------------------------------ */
2015 static const unsigned int scif1_data_pins[] = {
2016         /* RXD, TXD */
2017         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2018 };
2019 static const unsigned int scif1_data_mux[] = {
2020         RX1_MARK, TX1_MARK,
2021 };
2022 static const unsigned int scif1_clk_pins[] = {
2023         /* SCK */
2024         RCAR_GP_PIN(4, 17),
2025 };
2026 static const unsigned int scif1_clk_mux[] = {
2027         SCK1_MARK,
2028 };
2029 static const unsigned int scif1_ctrl_pins[] = {
2030         /* RTS, CTS */
2031         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2032 };
2033 static const unsigned int scif1_ctrl_mux[] = {
2034         RTS1_TANS_MARK, CTS1_MARK,
2035 };
2036 static const unsigned int scif1_data_b_pins[] = {
2037         /* RXD, TXD */
2038         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
2039 };
2040 static const unsigned int scif1_data_b_mux[] = {
2041         RX1_B_MARK, TX1_B_MARK,
2042 };
2043 static const unsigned int scif1_clk_b_pins[] = {
2044         /* SCK */
2045         RCAR_GP_PIN(3, 17),
2046 };
2047 static const unsigned int scif1_clk_b_mux[] = {
2048         SCK1_B_MARK,
2049 };
2050 static const unsigned int scif1_ctrl_b_pins[] = {
2051         /* RTS, CTS */
2052         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2053 };
2054 static const unsigned int scif1_ctrl_b_mux[] = {
2055         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
2056 };
2057 static const unsigned int scif1_data_c_pins[] = {
2058         /* RXD, TXD */
2059         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2060 };
2061 static const unsigned int scif1_data_c_mux[] = {
2062         RX1_C_MARK, TX1_C_MARK,
2063 };
2064 static const unsigned int scif1_clk_c_pins[] = {
2065         /* SCK */
2066         RCAR_GP_PIN(2, 22),
2067 };
2068 static const unsigned int scif1_clk_c_mux[] = {
2069         SCK1_C_MARK,
2070 };
2071 static const unsigned int scif1_ctrl_c_pins[] = {
2072         /* RTS, CTS */
2073         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2074 };
2075 static const unsigned int scif1_ctrl_c_mux[] = {
2076         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
2077 };
2078 /* - SCIF2 ------------------------------------------------------------------ */
2079 static const unsigned int scif2_data_pins[] = {
2080         /* RXD, TXD */
2081         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2082 };
2083 static const unsigned int scif2_data_mux[] = {
2084         RX2_MARK, TX2_MARK,
2085 };
2086 static const unsigned int scif2_clk_pins[] = {
2087         /* SCK */
2088         RCAR_GP_PIN(3, 11),
2089 };
2090 static const unsigned int scif2_clk_mux[] = {
2091         SCK2_MARK,
2092 };
2093 static const unsigned int scif2_data_b_pins[] = {
2094         /* RXD, TXD */
2095         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2096 };
2097 static const unsigned int scif2_data_b_mux[] = {
2098         RX2_B_MARK, TX2_B_MARK,
2099 };
2100 static const unsigned int scif2_clk_b_pins[] = {
2101         /* SCK */
2102         RCAR_GP_PIN(3, 22),
2103 };
2104 static const unsigned int scif2_clk_b_mux[] = {
2105         SCK2_B_MARK,
2106 };
2107 static const unsigned int scif2_data_c_pins[] = {
2108         /* RXD, TXD */
2109         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2110 };
2111 static const unsigned int scif2_data_c_mux[] = {
2112         RX2_C_MARK, TX2_C_MARK,
2113 };
2114 static const unsigned int scif2_clk_c_pins[] = {
2115         /* SCK */
2116         RCAR_GP_PIN(1, 0),
2117 };
2118 static const unsigned int scif2_clk_c_mux[] = {
2119         SCK2_C_MARK,
2120 };
2121 static const unsigned int scif2_data_d_pins[] = {
2122         /* RXD, TXD */
2123         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2124 };
2125 static const unsigned int scif2_data_d_mux[] = {
2126         RX2_D_MARK, TX2_D_MARK,
2127 };
2128 static const unsigned int scif2_clk_d_pins[] = {
2129         /* SCK */
2130         RCAR_GP_PIN(1, 31),
2131 };
2132 static const unsigned int scif2_clk_d_mux[] = {
2133         SCK2_D_MARK,
2134 };
2135 static const unsigned int scif2_data_e_pins[] = {
2136         /* RXD, TXD */
2137         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2138 };
2139 static const unsigned int scif2_data_e_mux[] = {
2140         RX2_E_MARK, TX2_E_MARK,
2141 };
2142 /* - SCIF3 ------------------------------------------------------------------ */
2143 static const unsigned int scif3_data_pins[] = {
2144         /* RXD, TXD */
2145         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2146 };
2147 static const unsigned int scif3_data_mux[] = {
2148         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2149 };
2150 static const unsigned int scif3_clk_pins[] = {
2151         /* SCK */
2152         RCAR_GP_PIN(4, 7),
2153 };
2154 static const unsigned int scif3_clk_mux[] = {
2155         SCK3_MARK,
2156 };
2157
2158 static const unsigned int scif3_data_b_pins[] = {
2159         /* RXD, TXD */
2160         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2161 };
2162 static const unsigned int scif3_data_b_mux[] = {
2163         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2164 };
2165 static const unsigned int scif3_data_c_pins[] = {
2166         /* RXD, TXD */
2167         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2168 };
2169 static const unsigned int scif3_data_c_mux[] = {
2170         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2171 };
2172 static const unsigned int scif3_data_d_pins[] = {
2173         /* RXD, TXD */
2174         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2175 };
2176 static const unsigned int scif3_data_d_mux[] = {
2177         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2178 };
2179 static const unsigned int scif3_data_e_pins[] = {
2180         /* RXD, TXD */
2181         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2182 };
2183 static const unsigned int scif3_data_e_mux[] = {
2184         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2185 };
2186 static const unsigned int scif3_clk_e_pins[] = {
2187         /* SCK */
2188         RCAR_GP_PIN(1, 10),
2189 };
2190 static const unsigned int scif3_clk_e_mux[] = {
2191         SCK3_E_MARK,
2192 };
2193 /* - SCIF4 ------------------------------------------------------------------ */
2194 static const unsigned int scif4_data_pins[] = {
2195         /* RXD, TXD */
2196         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2197 };
2198 static const unsigned int scif4_data_mux[] = {
2199         RX4_MARK, TX4_MARK,
2200 };
2201 static const unsigned int scif4_clk_pins[] = {
2202         /* SCK */
2203         RCAR_GP_PIN(3, 25),
2204 };
2205 static const unsigned int scif4_clk_mux[] = {
2206         SCK4_MARK,
2207 };
2208 static const unsigned int scif4_data_b_pins[] = {
2209         /* RXD, TXD */
2210         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2211 };
2212 static const unsigned int scif4_data_b_mux[] = {
2213         RX4_B_MARK, TX4_B_MARK,
2214 };
2215 static const unsigned int scif4_clk_b_pins[] = {
2216         /* SCK */
2217         RCAR_GP_PIN(3, 16),
2218 };
2219 static const unsigned int scif4_clk_b_mux[] = {
2220         SCK4_B_MARK,
2221 };
2222 static const unsigned int scif4_data_c_pins[] = {
2223         /* RXD, TXD */
2224         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2225 };
2226 static const unsigned int scif4_data_c_mux[] = {
2227         RX4_C_MARK, TX4_C_MARK,
2228 };
2229 static const unsigned int scif4_data_d_pins[] = {
2230         /* RXD, TXD */
2231         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2232 };
2233 static const unsigned int scif4_data_d_mux[] = {
2234         RX4_D_MARK, TX4_D_MARK,
2235 };
2236 /* - SCIF5 ------------------------------------------------------------------ */
2237 static const unsigned int scif5_data_pins[] = {
2238         /* RXD, TXD */
2239         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2240 };
2241 static const unsigned int scif5_data_mux[] = {
2242         RX5_MARK, TX5_MARK,
2243 };
2244 static const unsigned int scif5_clk_pins[] = {
2245         /* SCK */
2246         RCAR_GP_PIN(1, 11),
2247 };
2248 static const unsigned int scif5_clk_mux[] = {
2249         SCK5_MARK,
2250 };
2251 static const unsigned int scif5_data_b_pins[] = {
2252         /* RXD, TXD */
2253         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2254 };
2255 static const unsigned int scif5_data_b_mux[] = {
2256         RX5_B_MARK, TX5_B_MARK,
2257 };
2258 static const unsigned int scif5_clk_b_pins[] = {
2259         /* SCK */
2260         RCAR_GP_PIN(0, 19),
2261 };
2262 static const unsigned int scif5_clk_b_mux[] = {
2263         SCK5_B_MARK,
2264 };
2265 static const unsigned int scif5_data_c_pins[] = {
2266         /* RXD, TXD */
2267         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2268 };
2269 static const unsigned int scif5_data_c_mux[] = {
2270         RX5_C_MARK, TX5_C_MARK,
2271 };
2272 static const unsigned int scif5_clk_c_pins[] = {
2273         /* SCK */
2274         RCAR_GP_PIN(0, 28),
2275 };
2276 static const unsigned int scif5_clk_c_mux[] = {
2277         SCK5_C_MARK,
2278 };
2279 static const unsigned int scif5_data_d_pins[] = {
2280         /* RXD, TXD */
2281         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2282 };
2283 static const unsigned int scif5_data_d_mux[] = {
2284         RX5_D_MARK, TX5_D_MARK,
2285 };
2286 static const unsigned int scif5_clk_d_pins[] = {
2287         /* SCK */
2288         RCAR_GP_PIN(0, 7),
2289 };
2290 static const unsigned int scif5_clk_d_mux[] = {
2291         SCK5_D_MARK,
2292 };
2293 /* - SDHI0 ------------------------------------------------------------------ */
2294 static const unsigned int sdhi0_data1_pins[] = {
2295         /* D0 */
2296         RCAR_GP_PIN(3, 21),
2297 };
2298 static const unsigned int sdhi0_data1_mux[] = {
2299         SD0_DAT0_MARK,
2300 };
2301 static const unsigned int sdhi0_data4_pins[] = {
2302         /* D[0:3] */
2303         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2304         RCAR_GP_PIN(3, 24),
2305 };
2306 static const unsigned int sdhi0_data4_mux[] = {
2307         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2308 };
2309 static const unsigned int sdhi0_ctrl_pins[] = {
2310         /* CMD, CLK */
2311         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2312 };
2313 static const unsigned int sdhi0_ctrl_mux[] = {
2314         SD0_CMD_MARK, SD0_CLK_MARK,
2315 };
2316 static const unsigned int sdhi0_cd_pins[] = {
2317         /* CD */
2318         RCAR_GP_PIN(3, 19),
2319 };
2320 static const unsigned int sdhi0_cd_mux[] = {
2321         SD0_CD_MARK,
2322 };
2323 static const unsigned int sdhi0_wp_pins[] = {
2324         /* WP */
2325         RCAR_GP_PIN(3, 20),
2326 };
2327 static const unsigned int sdhi0_wp_mux[] = {
2328         SD0_WP_MARK,
2329 };
2330 /* - SDHI1 ------------------------------------------------------------------ */
2331 static const unsigned int sdhi1_data1_pins[] = {
2332         /* D0 */
2333         RCAR_GP_PIN(0, 19),
2334 };
2335 static const unsigned int sdhi1_data1_mux[] = {
2336         SD1_DAT0_MARK,
2337 };
2338 static const unsigned int sdhi1_data4_pins[] = {
2339         /* D[0:3] */
2340         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2341         RCAR_GP_PIN(0, 2),
2342 };
2343 static const unsigned int sdhi1_data4_mux[] = {
2344         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2345 };
2346 static const unsigned int sdhi1_ctrl_pins[] = {
2347         /* CMD, CLK */
2348         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2349 };
2350 static const unsigned int sdhi1_ctrl_mux[] = {
2351         SD1_CMD_MARK, SD1_CLK_MARK,
2352 };
2353 static const unsigned int sdhi1_cd_pins[] = {
2354         /* CD */
2355         RCAR_GP_PIN(0, 10),
2356 };
2357 static const unsigned int sdhi1_cd_mux[] = {
2358         SD1_CD_MARK,
2359 };
2360 static const unsigned int sdhi1_wp_pins[] = {
2361         /* WP */
2362         RCAR_GP_PIN(0, 11),
2363 };
2364 static const unsigned int sdhi1_wp_mux[] = {
2365         SD1_WP_MARK,
2366 };
2367 /* - SDHI2 ------------------------------------------------------------------ */
2368 static const unsigned int sdhi2_data1_pins[] = {
2369         /* D0 */
2370         RCAR_GP_PIN(3, 1),
2371 };
2372 static const unsigned int sdhi2_data1_mux[] = {
2373         SD2_DAT0_MARK,
2374 };
2375 static const unsigned int sdhi2_data4_pins[] = {
2376         /* D[0:3] */
2377         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2378         RCAR_GP_PIN(3, 4),
2379 };
2380 static const unsigned int sdhi2_data4_mux[] = {
2381         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2382 };
2383 static const unsigned int sdhi2_ctrl_pins[] = {
2384         /* CMD, CLK */
2385         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2386 };
2387 static const unsigned int sdhi2_ctrl_mux[] = {
2388         SD2_CMD_MARK, SD2_CLK_MARK,
2389 };
2390 static const unsigned int sdhi2_cd_pins[] = {
2391         /* CD */
2392         RCAR_GP_PIN(3, 7),
2393 };
2394 static const unsigned int sdhi2_cd_mux[] = {
2395         SD2_CD_MARK,
2396 };
2397 static const unsigned int sdhi2_wp_pins[] = {
2398         /* WP */
2399         RCAR_GP_PIN(3, 8),
2400 };
2401 static const unsigned int sdhi2_wp_mux[] = {
2402         SD2_WP_MARK,
2403 };
2404 /* - SDHI3 ------------------------------------------------------------------ */
2405 static const unsigned int sdhi3_data1_pins[] = {
2406         /* D0 */
2407         RCAR_GP_PIN(1, 18),
2408 };
2409 static const unsigned int sdhi3_data1_mux[] = {
2410         SD3_DAT0_MARK,
2411 };
2412 static const unsigned int sdhi3_data4_pins[] = {
2413         /* D[0:3] */
2414         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2415         RCAR_GP_PIN(1, 21),
2416 };
2417 static const unsigned int sdhi3_data4_mux[] = {
2418         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2419 };
2420 static const unsigned int sdhi3_ctrl_pins[] = {
2421         /* CMD, CLK */
2422         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2423 };
2424 static const unsigned int sdhi3_ctrl_mux[] = {
2425         SD3_CMD_MARK, SD3_CLK_MARK,
2426 };
2427 static const unsigned int sdhi3_cd_pins[] = {
2428         /* CD */
2429         RCAR_GP_PIN(1, 30),
2430 };
2431 static const unsigned int sdhi3_cd_mux[] = {
2432         SD3_CD_MARK,
2433 };
2434 static const unsigned int sdhi3_wp_pins[] = {
2435         /* WP */
2436         RCAR_GP_PIN(2, 0),
2437 };
2438 static const unsigned int sdhi3_wp_mux[] = {
2439         SD3_WP_MARK,
2440 };
2441 /* - USB0 ------------------------------------------------------------------- */
2442 static const unsigned int usb0_pins[] = {
2443         /* PENC */
2444         RCAR_GP_PIN(4, 26),
2445 };
2446 static const unsigned int usb0_mux[] = {
2447         USB_PENC0_MARK,
2448 };
2449 static const unsigned int usb0_ovc_pins[] = {
2450         /* USB_OVC */
2451         RCAR_GP_PIN(4, 22),
2452 };
2453 static const unsigned int usb0_ovc_mux[] = {
2454         USB_OVC0_MARK,
2455 };
2456 /* - USB1 ------------------------------------------------------------------- */
2457 static const unsigned int usb1_pins[] = {
2458         /* PENC */
2459         RCAR_GP_PIN(4, 27),
2460 };
2461 static const unsigned int usb1_mux[] = {
2462         USB_PENC1_MARK,
2463 };
2464 static const unsigned int usb1_ovc_pins[] = {
2465         /* USB_OVC */
2466         RCAR_GP_PIN(4, 24),
2467 };
2468 static const unsigned int usb1_ovc_mux[] = {
2469         USB_OVC1_MARK,
2470 };
2471 /* - USB2 ------------------------------------------------------------------- */
2472 static const unsigned int usb2_pins[] = {
2473         /* PENC */
2474         RCAR_GP_PIN(4, 28),
2475 };
2476 static const unsigned int usb2_mux[] = {
2477         USB_PENC2_MARK,
2478 };
2479 static const unsigned int usb2_ovc_pins[] = {
2480         /* USB_OVC */
2481         RCAR_GP_PIN(3, 29),
2482 };
2483 static const unsigned int usb2_ovc_mux[] = {
2484         USB_OVC2_MARK,
2485 };
2486 /* - VIN0 ------------------------------------------------------------------- */
2487 static const unsigned int vin0_data8_pins[] = {
2488         /* D[0:7] */
2489         RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
2490         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2491         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2492 };
2493 static const unsigned int vin0_data8_mux[] = {
2494         VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2495         VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2496         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2497 };
2498 static const unsigned int vin0_clk_pins[] = {
2499         /* CLK */
2500         RCAR_GP_PIN(2, 1),
2501 };
2502 static const unsigned int vin0_clk_mux[] = {
2503         VI0_CLK_MARK,
2504 };
2505 static const unsigned int vin0_sync_pins[] = {
2506         /* HSYNC, VSYNC */
2507         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2508 };
2509 static const unsigned int vin0_sync_mux[] = {
2510         VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2511 };
2512 /* - VIN1 ------------------------------------------------------------------- */
2513 static const unsigned int vin1_data8_pins[] = {
2514         /* D[0:7] */
2515         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2516         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2517         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2518 };
2519 static const unsigned int vin1_data8_mux[] = {
2520         VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2521         VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2522         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2523 };
2524 static const unsigned int vin1_clk_pins[] = {
2525         /* CLK */
2526         RCAR_GP_PIN(2, 30),
2527 };
2528 static const unsigned int vin1_clk_mux[] = {
2529         VI1_CLK_MARK,
2530 };
2531 static const unsigned int vin1_sync_pins[] = {
2532         /* HSYNC, VSYNC */
2533         RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2534 };
2535 static const unsigned int vin1_sync_mux[] = {
2536         VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2537 };
2538 /* - VIN2 ------------------------------------------------------------------- */
2539 static const unsigned int vin2_data8_pins[] = {
2540         /* D[0:7] */
2541         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
2542         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2543         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2544 };
2545 static const unsigned int vin2_data8_mux[] = {
2546         VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2547         VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2548         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2549 };
2550 static const unsigned int vin2_clk_pins[] = {
2551         /* CLK */
2552         RCAR_GP_PIN(1, 30),
2553 };
2554 static const unsigned int vin2_clk_mux[] = {
2555         VI2_CLK_MARK,
2556 };
2557 static const unsigned int vin2_sync_pins[] = {
2558         /* HSYNC, VSYNC */
2559         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2560 };
2561 static const unsigned int vin2_sync_mux[] = {
2562         VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2563 };
2564 /* - VIN3 ------------------------------------------------------------------- */
2565 static const unsigned int vin3_data8_pins[] = {
2566         /* D[0:7] */
2567         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2568         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2569         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2570 };
2571 static const unsigned int vin3_data8_mux[] = {
2572         VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2573         VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2574         VI3_DATA6_MARK, VI3_DATA7_MARK,
2575 };
2576 static const unsigned int vin3_clk_pins[] = {
2577         /* CLK */
2578         RCAR_GP_PIN(2, 31),
2579 };
2580 static const unsigned int vin3_clk_mux[] = {
2581         VI3_CLK_MARK,
2582 };
2583 static const unsigned int vin3_sync_pins[] = {
2584         /* HSYNC, VSYNC */
2585         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2586 };
2587 static const unsigned int vin3_sync_mux[] = {
2588         VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2589 };
2590
2591 static const struct sh_pfc_pin_group pinmux_groups[] = {
2592         SH_PFC_PIN_GROUP(du0_rgb666),
2593         SH_PFC_PIN_GROUP(du0_rgb888),
2594         SH_PFC_PIN_GROUP(du0_clk_in),
2595         SH_PFC_PIN_GROUP(du0_clk_out_0),
2596         SH_PFC_PIN_GROUP(du0_clk_out_1),
2597         SH_PFC_PIN_GROUP(du0_sync_0),
2598         SH_PFC_PIN_GROUP(du0_sync_1),
2599         SH_PFC_PIN_GROUP(du0_oddf),
2600         SH_PFC_PIN_GROUP(du0_cde),
2601         SH_PFC_PIN_GROUP(du1_rgb666),
2602         SH_PFC_PIN_GROUP(du1_rgb888),
2603         SH_PFC_PIN_GROUP(du1_clk_in),
2604         SH_PFC_PIN_GROUP(du1_clk_out),
2605         SH_PFC_PIN_GROUP(du1_sync_0),
2606         SH_PFC_PIN_GROUP(du1_sync_1),
2607         SH_PFC_PIN_GROUP(du1_oddf),
2608         SH_PFC_PIN_GROUP(du1_cde),
2609         SH_PFC_PIN_GROUP(ether_rmii),
2610         SH_PFC_PIN_GROUP(ether_link),
2611         SH_PFC_PIN_GROUP(ether_magic),
2612         SH_PFC_PIN_GROUP(hspi0),
2613         SH_PFC_PIN_GROUP(hspi1),
2614         SH_PFC_PIN_GROUP(hspi1_b),
2615         SH_PFC_PIN_GROUP(hspi1_c),
2616         SH_PFC_PIN_GROUP(hspi1_d),
2617         SH_PFC_PIN_GROUP(hspi2),
2618         SH_PFC_PIN_GROUP(hspi2_b),
2619         SH_PFC_PIN_GROUP(i2c1),
2620         SH_PFC_PIN_GROUP(i2c1_b),
2621         SH_PFC_PIN_GROUP(i2c1_c),
2622         SH_PFC_PIN_GROUP(i2c1_d),
2623         SH_PFC_PIN_GROUP(i2c2),
2624         SH_PFC_PIN_GROUP(i2c2_b),
2625         SH_PFC_PIN_GROUP(i2c2_c),
2626         SH_PFC_PIN_GROUP(i2c2_d),
2627         SH_PFC_PIN_GROUP(i2c3),
2628         SH_PFC_PIN_GROUP(i2c3_b),
2629         SH_PFC_PIN_GROUP(intc_irq0),
2630         SH_PFC_PIN_GROUP(intc_irq0_b),
2631         SH_PFC_PIN_GROUP(intc_irq1),
2632         SH_PFC_PIN_GROUP(intc_irq1_b),
2633         SH_PFC_PIN_GROUP(intc_irq2),
2634         SH_PFC_PIN_GROUP(intc_irq2_b),
2635         SH_PFC_PIN_GROUP(intc_irq3),
2636         SH_PFC_PIN_GROUP(intc_irq3_b),
2637         SH_PFC_PIN_GROUP(lbsc_cs0),
2638         SH_PFC_PIN_GROUP(lbsc_cs1),
2639         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2640         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2641         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2642         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2643         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2644         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2645         SH_PFC_PIN_GROUP(mmc0_data1),
2646         SH_PFC_PIN_GROUP(mmc0_data4),
2647         SH_PFC_PIN_GROUP(mmc0_data8),
2648         SH_PFC_PIN_GROUP(mmc0_ctrl),
2649         SH_PFC_PIN_GROUP(mmc1_data1),
2650         SH_PFC_PIN_GROUP(mmc1_data4),
2651         SH_PFC_PIN_GROUP(mmc1_data8),
2652         SH_PFC_PIN_GROUP(mmc1_ctrl),
2653         SH_PFC_PIN_GROUP(scif0_data),
2654         SH_PFC_PIN_GROUP(scif0_clk),
2655         SH_PFC_PIN_GROUP(scif0_ctrl),
2656         SH_PFC_PIN_GROUP(scif0_data_b),
2657         SH_PFC_PIN_GROUP(scif0_clk_b),
2658         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2659         SH_PFC_PIN_GROUP(scif0_data_c),
2660         SH_PFC_PIN_GROUP(scif0_clk_c),
2661         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2662         SH_PFC_PIN_GROUP(scif0_data_d),
2663         SH_PFC_PIN_GROUP(scif0_clk_d),
2664         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2665         SH_PFC_PIN_GROUP(scif1_data),
2666         SH_PFC_PIN_GROUP(scif1_clk),
2667         SH_PFC_PIN_GROUP(scif1_ctrl),
2668         SH_PFC_PIN_GROUP(scif1_data_b),
2669         SH_PFC_PIN_GROUP(scif1_clk_b),
2670         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2671         SH_PFC_PIN_GROUP(scif1_data_c),
2672         SH_PFC_PIN_GROUP(scif1_clk_c),
2673         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2674         SH_PFC_PIN_GROUP(scif2_data),
2675         SH_PFC_PIN_GROUP(scif2_clk),
2676         SH_PFC_PIN_GROUP(scif2_data_b),
2677         SH_PFC_PIN_GROUP(scif2_clk_b),
2678         SH_PFC_PIN_GROUP(scif2_data_c),
2679         SH_PFC_PIN_GROUP(scif2_clk_c),
2680         SH_PFC_PIN_GROUP(scif2_data_d),
2681         SH_PFC_PIN_GROUP(scif2_clk_d),
2682         SH_PFC_PIN_GROUP(scif2_data_e),
2683         SH_PFC_PIN_GROUP(scif3_data),
2684         SH_PFC_PIN_GROUP(scif3_clk),
2685         SH_PFC_PIN_GROUP(scif3_data_b),
2686         SH_PFC_PIN_GROUP(scif3_data_c),
2687         SH_PFC_PIN_GROUP(scif3_data_d),
2688         SH_PFC_PIN_GROUP(scif3_data_e),
2689         SH_PFC_PIN_GROUP(scif3_clk_e),
2690         SH_PFC_PIN_GROUP(scif4_data),
2691         SH_PFC_PIN_GROUP(scif4_clk),
2692         SH_PFC_PIN_GROUP(scif4_data_b),
2693         SH_PFC_PIN_GROUP(scif4_clk_b),
2694         SH_PFC_PIN_GROUP(scif4_data_c),
2695         SH_PFC_PIN_GROUP(scif4_data_d),
2696         SH_PFC_PIN_GROUP(scif5_data),
2697         SH_PFC_PIN_GROUP(scif5_clk),
2698         SH_PFC_PIN_GROUP(scif5_data_b),
2699         SH_PFC_PIN_GROUP(scif5_clk_b),
2700         SH_PFC_PIN_GROUP(scif5_data_c),
2701         SH_PFC_PIN_GROUP(scif5_clk_c),
2702         SH_PFC_PIN_GROUP(scif5_data_d),
2703         SH_PFC_PIN_GROUP(scif5_clk_d),
2704         SH_PFC_PIN_GROUP(sdhi0_data1),
2705         SH_PFC_PIN_GROUP(sdhi0_data4),
2706         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2707         SH_PFC_PIN_GROUP(sdhi0_cd),
2708         SH_PFC_PIN_GROUP(sdhi0_wp),
2709         SH_PFC_PIN_GROUP(sdhi1_data1),
2710         SH_PFC_PIN_GROUP(sdhi1_data4),
2711         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2712         SH_PFC_PIN_GROUP(sdhi1_cd),
2713         SH_PFC_PIN_GROUP(sdhi1_wp),
2714         SH_PFC_PIN_GROUP(sdhi2_data1),
2715         SH_PFC_PIN_GROUP(sdhi2_data4),
2716         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2717         SH_PFC_PIN_GROUP(sdhi2_cd),
2718         SH_PFC_PIN_GROUP(sdhi2_wp),
2719         SH_PFC_PIN_GROUP(sdhi3_data1),
2720         SH_PFC_PIN_GROUP(sdhi3_data4),
2721         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2722         SH_PFC_PIN_GROUP(sdhi3_cd),
2723         SH_PFC_PIN_GROUP(sdhi3_wp),
2724         SH_PFC_PIN_GROUP(usb0),
2725         SH_PFC_PIN_GROUP(usb0_ovc),
2726         SH_PFC_PIN_GROUP(usb1),
2727         SH_PFC_PIN_GROUP(usb1_ovc),
2728         SH_PFC_PIN_GROUP(usb2),
2729         SH_PFC_PIN_GROUP(usb2_ovc),
2730         SH_PFC_PIN_GROUP(vin0_data8),
2731         SH_PFC_PIN_GROUP(vin0_clk),
2732         SH_PFC_PIN_GROUP(vin0_sync),
2733         SH_PFC_PIN_GROUP(vin1_data8),
2734         SH_PFC_PIN_GROUP(vin1_clk),
2735         SH_PFC_PIN_GROUP(vin1_sync),
2736         SH_PFC_PIN_GROUP(vin2_data8),
2737         SH_PFC_PIN_GROUP(vin2_clk),
2738         SH_PFC_PIN_GROUP(vin2_sync),
2739         SH_PFC_PIN_GROUP(vin3_data8),
2740         SH_PFC_PIN_GROUP(vin3_clk),
2741         SH_PFC_PIN_GROUP(vin3_sync),
2742 };
2743
2744 static const char * const du0_groups[] = {
2745         "du0_rgb666",
2746         "du0_rgb888",
2747         "du0_clk_in",
2748         "du0_clk_out_0",
2749         "du0_clk_out_1",
2750         "du0_sync_0",
2751         "du0_sync_1",
2752         "du0_oddf",
2753         "du0_cde",
2754 };
2755
2756 static const char * const du1_groups[] = {
2757         "du1_rgb666",
2758         "du1_rgb888",
2759         "du1_clk_in",
2760         "du1_clk_out",
2761         "du1_sync_0",
2762         "du1_sync_1",
2763         "du1_oddf",
2764         "du1_cde",
2765 };
2766
2767 static const char * const ether_groups[] = {
2768         "ether_rmii",
2769         "ether_link",
2770         "ether_magic",
2771 };
2772
2773 static const char * const hspi0_groups[] = {
2774         "hspi0",
2775 };
2776
2777 static const char * const hspi1_groups[] = {
2778         "hspi1",
2779         "hspi1_b",
2780         "hspi1_c",
2781         "hspi1_d",
2782 };
2783
2784 static const char * const hspi2_groups[] = {
2785         "hspi2",
2786         "hspi2_b",
2787 };
2788
2789 static const char * const i2c1_groups[] = {
2790         "i2c1",
2791         "i2c1_b",
2792         "i2c1_c",
2793         "i2c1_d",
2794 };
2795
2796 static const char * const i2c2_groups[] = {
2797         "i2c2",
2798         "i2c2_b",
2799         "i2c2_c",
2800         "i2c2_d",
2801 };
2802
2803 static const char * const i2c3_groups[] = {
2804         "i2c3",
2805         "i2c3_b",
2806 };
2807
2808 static const char * const intc_groups[] = {
2809         "intc_irq0",
2810         "intc_irq0_b",
2811         "intc_irq1",
2812         "intc_irq1_b",
2813         "intc_irq2",
2814         "intc_irq2_b",
2815         "intc_irq3",
2816         "intc_irq3_b",
2817 };
2818
2819 static const char * const lbsc_groups[] = {
2820         "lbsc_cs0",
2821         "lbsc_cs1",
2822         "lbsc_ex_cs0",
2823         "lbsc_ex_cs1",
2824         "lbsc_ex_cs2",
2825         "lbsc_ex_cs3",
2826         "lbsc_ex_cs4",
2827         "lbsc_ex_cs5",
2828 };
2829
2830 static const char * const mmc0_groups[] = {
2831         "mmc0_data1",
2832         "mmc0_data4",
2833         "mmc0_data8",
2834         "mmc0_ctrl",
2835 };
2836
2837 static const char * const mmc1_groups[] = {
2838         "mmc1_data1",
2839         "mmc1_data4",
2840         "mmc1_data8",
2841         "mmc1_ctrl",
2842 };
2843
2844 static const char * const scif0_groups[] = {
2845         "scif0_data",
2846         "scif0_clk",
2847         "scif0_ctrl",
2848         "scif0_data_b",
2849         "scif0_clk_b",
2850         "scif0_ctrl_b",
2851         "scif0_data_c",
2852         "scif0_clk_c",
2853         "scif0_ctrl_c",
2854         "scif0_data_d",
2855         "scif0_clk_d",
2856         "scif0_ctrl_d",
2857 };
2858
2859 static const char * const scif1_groups[] = {
2860         "scif1_data",
2861         "scif1_clk",
2862         "scif1_ctrl",
2863         "scif1_data_b",
2864         "scif1_clk_b",
2865         "scif1_ctrl_b",
2866         "scif1_data_c",
2867         "scif1_clk_c",
2868         "scif1_ctrl_c",
2869 };
2870
2871 static const char * const scif2_groups[] = {
2872         "scif2_data",
2873         "scif2_clk",
2874         "scif2_data_b",
2875         "scif2_clk_b",
2876         "scif2_data_c",
2877         "scif2_clk_c",
2878         "scif2_data_d",
2879         "scif2_clk_d",
2880         "scif2_data_e",
2881 };
2882
2883 static const char * const scif3_groups[] = {
2884         "scif3_data",
2885         "scif3_clk",
2886         "scif3_data_b",
2887         "scif3_data_c",
2888         "scif3_data_d",
2889         "scif3_data_e",
2890         "scif3_clk_e",
2891 };
2892
2893 static const char * const scif4_groups[] = {
2894         "scif4_data",
2895         "scif4_clk",
2896         "scif4_data_b",
2897         "scif4_clk_b",
2898         "scif4_data_c",
2899         "scif4_data_d",
2900 };
2901
2902 static const char * const scif5_groups[] = {
2903         "scif5_data",
2904         "scif5_clk",
2905         "scif5_data_b",
2906         "scif5_clk_b",
2907         "scif5_data_c",
2908         "scif5_clk_c",
2909         "scif5_data_d",
2910         "scif5_clk_d",
2911 };
2912
2913 static const char * const sdhi0_groups[] = {
2914         "sdhi0_data1",
2915         "sdhi0_data4",
2916         "sdhi0_ctrl",
2917         "sdhi0_cd",
2918         "sdhi0_wp",
2919 };
2920
2921 static const char * const sdhi1_groups[] = {
2922         "sdhi1_data1",
2923         "sdhi1_data4",
2924         "sdhi1_ctrl",
2925         "sdhi1_cd",
2926         "sdhi1_wp",
2927 };
2928
2929 static const char * const sdhi2_groups[] = {
2930         "sdhi2_data1",
2931         "sdhi2_data4",
2932         "sdhi2_ctrl",
2933         "sdhi2_cd",
2934         "sdhi2_wp",
2935 };
2936
2937 static const char * const sdhi3_groups[] = {
2938         "sdhi3_data1",
2939         "sdhi3_data4",
2940         "sdhi3_ctrl",
2941         "sdhi3_cd",
2942         "sdhi3_wp",
2943 };
2944
2945 static const char * const usb0_groups[] = {
2946         "usb0",
2947         "usb0_ovc",
2948 };
2949
2950 static const char * const usb1_groups[] = {
2951         "usb1",
2952         "usb1_ovc",
2953 };
2954
2955 static const char * const usb2_groups[] = {
2956         "usb2",
2957         "usb2_ovc",
2958 };
2959
2960 static const char * const vin0_groups[] = {
2961         "vin0_data8",
2962         "vin0_clk",
2963         "vin0_sync",
2964 };
2965
2966 static const char * const vin1_groups[] = {
2967         "vin1_data8",
2968         "vin1_clk",
2969         "vin1_sync",
2970 };
2971
2972 static const char * const vin2_groups[] = {
2973         "vin2_data8",
2974         "vin2_clk",
2975         "vin2_sync",
2976 };
2977
2978 static const char * const vin3_groups[] = {
2979         "vin3_data8",
2980         "vin3_clk",
2981         "vin3_sync",
2982 };
2983
2984 static const struct sh_pfc_function pinmux_functions[] = {
2985         SH_PFC_FUNCTION(du0),
2986         SH_PFC_FUNCTION(du1),
2987         SH_PFC_FUNCTION(ether),
2988         SH_PFC_FUNCTION(hspi0),
2989         SH_PFC_FUNCTION(hspi1),
2990         SH_PFC_FUNCTION(hspi2),
2991         SH_PFC_FUNCTION(i2c1),
2992         SH_PFC_FUNCTION(i2c2),
2993         SH_PFC_FUNCTION(i2c3),
2994         SH_PFC_FUNCTION(intc),
2995         SH_PFC_FUNCTION(lbsc),
2996         SH_PFC_FUNCTION(mmc0),
2997         SH_PFC_FUNCTION(mmc1),
2998         SH_PFC_FUNCTION(sdhi0),
2999         SH_PFC_FUNCTION(sdhi1),
3000         SH_PFC_FUNCTION(sdhi2),
3001         SH_PFC_FUNCTION(sdhi3),
3002         SH_PFC_FUNCTION(scif0),
3003         SH_PFC_FUNCTION(scif1),
3004         SH_PFC_FUNCTION(scif2),
3005         SH_PFC_FUNCTION(scif3),
3006         SH_PFC_FUNCTION(scif4),
3007         SH_PFC_FUNCTION(scif5),
3008         SH_PFC_FUNCTION(usb0),
3009         SH_PFC_FUNCTION(usb1),
3010         SH_PFC_FUNCTION(usb2),
3011         SH_PFC_FUNCTION(vin0),
3012         SH_PFC_FUNCTION(vin1),
3013         SH_PFC_FUNCTION(vin2),
3014         SH_PFC_FUNCTION(vin3),
3015 };
3016
3017 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3018         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
3019                 GP_0_31_FN, FN_IP3_31_29,
3020                 GP_0_30_FN, FN_IP3_26_24,
3021                 GP_0_29_FN, FN_IP3_22_21,
3022                 GP_0_28_FN, FN_IP3_14_12,
3023                 GP_0_27_FN, FN_IP3_11_9,
3024                 GP_0_26_FN, FN_IP3_2_0,
3025                 GP_0_25_FN, FN_IP2_30_28,
3026                 GP_0_24_FN, FN_IP2_21_19,
3027                 GP_0_23_FN, FN_IP2_18_16,
3028                 GP_0_22_FN, FN_IP0_30_28,
3029                 GP_0_21_FN, FN_IP0_5_3,
3030                 GP_0_20_FN, FN_IP1_18_15,
3031                 GP_0_19_FN, FN_IP1_14_11,
3032                 GP_0_18_FN, FN_IP1_10_7,
3033                 GP_0_17_FN, FN_IP1_6_4,
3034                 GP_0_16_FN, FN_IP1_3_2,
3035                 GP_0_15_FN, FN_IP1_1_0,
3036                 GP_0_14_FN, FN_IP0_27_26,
3037                 GP_0_13_FN, FN_IP0_25,
3038                 GP_0_12_FN, FN_IP0_24_23,
3039                 GP_0_11_FN, FN_IP0_22_19,
3040                 GP_0_10_FN, FN_IP0_18_16,
3041                 GP_0_9_FN, FN_IP0_15_14,
3042                 GP_0_8_FN, FN_IP0_13_12,
3043                 GP_0_7_FN, FN_IP0_11_10,
3044                 GP_0_6_FN, FN_IP0_9_8,
3045                 GP_0_5_FN, FN_A19,
3046                 GP_0_4_FN, FN_A18,
3047                 GP_0_3_FN, FN_A17,
3048                 GP_0_2_FN, FN_IP0_7_6,
3049                 GP_0_1_FN, FN_AVS2,
3050                 GP_0_0_FN, FN_AVS1 }
3051         },
3052         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
3053                 GP_1_31_FN, FN_IP5_23_21,
3054                 GP_1_30_FN, FN_IP5_20_17,
3055                 GP_1_29_FN, FN_IP5_16_15,
3056                 GP_1_28_FN, FN_IP5_14_13,
3057                 GP_1_27_FN, FN_IP5_12_11,
3058                 GP_1_26_FN, FN_IP5_10_9,
3059                 GP_1_25_FN, FN_IP5_8,
3060                 GP_1_24_FN, FN_IP5_7,
3061                 GP_1_23_FN, FN_IP5_6,
3062                 GP_1_22_FN, FN_IP5_5,
3063                 GP_1_21_FN, FN_IP5_4,
3064                 GP_1_20_FN, FN_IP5_3,
3065                 GP_1_19_FN, FN_IP5_2_0,
3066                 GP_1_18_FN, FN_IP4_31_29,
3067                 GP_1_17_FN, FN_IP4_28,
3068                 GP_1_16_FN, FN_IP4_27,
3069                 GP_1_15_FN, FN_IP4_26,
3070                 GP_1_14_FN, FN_IP4_25,
3071                 GP_1_13_FN, FN_IP4_24,
3072                 GP_1_12_FN, FN_IP4_23,
3073                 GP_1_11_FN, FN_IP4_22_20,
3074                 GP_1_10_FN, FN_IP4_19_17,
3075                 GP_1_9_FN, FN_IP4_16,
3076                 GP_1_8_FN, FN_IP4_15,
3077                 GP_1_7_FN, FN_IP4_14,
3078                 GP_1_6_FN, FN_IP4_13,
3079                 GP_1_5_FN, FN_IP4_12,
3080                 GP_1_4_FN, FN_IP4_11,
3081                 GP_1_3_FN, FN_IP4_10_8,
3082                 GP_1_2_FN, FN_IP4_7_5,
3083                 GP_1_1_FN, FN_IP4_4_2,
3084                 GP_1_0_FN, FN_IP4_1_0 }
3085         },
3086         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
3087                 GP_2_31_FN, FN_IP10_28_26,
3088                 GP_2_30_FN, FN_IP10_25_24,
3089                 GP_2_29_FN, FN_IP10_23_21,
3090                 GP_2_28_FN, FN_IP10_20_18,
3091                 GP_2_27_FN, FN_IP10_17_15,
3092                 GP_2_26_FN, FN_IP10_14_12,
3093                 GP_2_25_FN, FN_IP10_11_9,
3094                 GP_2_24_FN, FN_IP10_8_6,
3095                 GP_2_23_FN, FN_IP10_5_3,
3096                 GP_2_22_FN, FN_IP10_2_0,
3097                 GP_2_21_FN, FN_IP9_29_28,
3098                 GP_2_20_FN, FN_IP9_27_26,
3099                 GP_2_19_FN, FN_IP9_25_24,
3100                 GP_2_18_FN, FN_IP9_23_22,
3101                 GP_2_17_FN, FN_IP9_21_19,
3102                 GP_2_16_FN, FN_IP9_18_16,
3103                 GP_2_15_FN, FN_IP9_15_14,
3104                 GP_2_14_FN, FN_IP9_13_12,
3105                 GP_2_13_FN, FN_IP9_11_10,
3106                 GP_2_12_FN, FN_IP9_9_8,
3107                 GP_2_11_FN, FN_IP9_7,
3108                 GP_2_10_FN, FN_IP9_6,
3109                 GP_2_9_FN, FN_IP9_5,
3110                 GP_2_8_FN, FN_IP9_4,
3111                 GP_2_7_FN, FN_IP9_3_2,
3112                 GP_2_6_FN, FN_IP9_1_0,
3113                 GP_2_5_FN, FN_IP8_30_28,
3114                 GP_2_4_FN, FN_IP8_27_25,
3115                 GP_2_3_FN, FN_IP8_24_23,
3116                 GP_2_2_FN, FN_IP8_22_21,
3117                 GP_2_1_FN, FN_IP8_20,
3118                 GP_2_0_FN, FN_IP5_27_24 }
3119         },
3120         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
3121                 GP_3_31_FN, FN_IP6_3_2,
3122                 GP_3_30_FN, FN_IP6_1_0,
3123                 GP_3_29_FN, FN_IP5_30_29,
3124                 GP_3_28_FN, FN_IP5_28,
3125                 GP_3_27_FN, FN_IP1_24_23,
3126                 GP_3_26_FN, FN_IP1_22_21,
3127                 GP_3_25_FN, FN_IP1_20_19,
3128                 GP_3_24_FN, FN_IP7_26_25,
3129                 GP_3_23_FN, FN_IP7_24_23,
3130                 GP_3_22_FN, FN_IP7_22_21,
3131                 GP_3_21_FN, FN_IP7_20_19,
3132                 GP_3_20_FN, FN_IP7_30_29,
3133                 GP_3_19_FN, FN_IP7_28_27,
3134                 GP_3_18_FN, FN_IP7_18_17,
3135                 GP_3_17_FN, FN_IP7_16_15,
3136                 GP_3_16_FN, FN_IP12_17_15,
3137                 GP_3_15_FN, FN_IP12_14_12,
3138                 GP_3_14_FN, FN_IP12_11_9,
3139                 GP_3_13_FN, FN_IP12_8_6,
3140                 GP_3_12_FN, FN_IP12_5_3,
3141                 GP_3_11_FN, FN_IP12_2_0,
3142                 GP_3_10_FN, FN_IP11_29_27,
3143                 GP_3_9_FN, FN_IP11_26_24,
3144                 GP_3_8_FN, FN_IP11_23_21,
3145                 GP_3_7_FN, FN_IP11_20_18,
3146                 GP_3_6_FN, FN_IP11_17_15,
3147                 GP_3_5_FN, FN_IP11_14_12,
3148                 GP_3_4_FN, FN_IP11_11_9,
3149                 GP_3_3_FN, FN_IP11_8_6,
3150                 GP_3_2_FN, FN_IP11_5_3,
3151                 GP_3_1_FN, FN_IP11_2_0,
3152                 GP_3_0_FN, FN_IP10_31_29 }
3153         },
3154         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
3155                 GP_4_31_FN, FN_IP8_19,
3156                 GP_4_30_FN, FN_IP8_18,
3157                 GP_4_29_FN, FN_IP8_17_16,
3158                 GP_4_28_FN, FN_IP0_2_0,
3159                 GP_4_27_FN, FN_USB_PENC1,
3160                 GP_4_26_FN, FN_USB_PENC0,
3161                 GP_4_25_FN, FN_IP8_15_12,
3162                 GP_4_24_FN, FN_IP8_11_8,
3163                 GP_4_23_FN, FN_IP8_7_4,
3164                 GP_4_22_FN, FN_IP8_3_0,
3165                 GP_4_21_FN, FN_IP2_3_0,
3166                 GP_4_20_FN, FN_IP1_28_25,
3167                 GP_4_19_FN, FN_IP2_15_12,
3168                 GP_4_18_FN, FN_IP2_11_8,
3169                 GP_4_17_FN, FN_IP2_7_4,
3170                 GP_4_16_FN, FN_IP7_14_13,
3171                 GP_4_15_FN, FN_IP7_12_10,
3172                 GP_4_14_FN, FN_IP7_9_7,
3173                 GP_4_13_FN, FN_IP7_6_4,
3174                 GP_4_12_FN, FN_IP7_3_2,
3175                 GP_4_11_FN, FN_IP7_1_0,
3176                 GP_4_10_FN, FN_IP6_30_29,
3177                 GP_4_9_FN, FN_IP6_26_25,
3178                 GP_4_8_FN, FN_IP6_24_23,
3179                 GP_4_7_FN, FN_IP6_22_20,
3180                 GP_4_6_FN, FN_IP6_19_18,
3181                 GP_4_5_FN, FN_IP6_17_15,
3182                 GP_4_4_FN, FN_IP6_14_12,
3183                 GP_4_3_FN, FN_IP6_11_9,
3184                 GP_4_2_FN, FN_IP6_8,
3185                 GP_4_1_FN, FN_IP6_7_6,
3186                 GP_4_0_FN, FN_IP6_5_4 }
3187         },
3188         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
3189                 GP_5_31_FN, FN_IP3_5,
3190                 GP_5_30_FN, FN_IP3_4,
3191                 GP_5_29_FN, FN_IP3_3,
3192                 GP_5_28_FN, FN_IP2_27,
3193                 GP_5_27_FN, FN_IP2_26,
3194                 GP_5_26_FN, FN_IP2_25,
3195                 GP_5_25_FN, FN_IP2_24,
3196                 GP_5_24_FN, FN_IP2_23,
3197                 GP_5_23_FN, FN_IP2_22,
3198                 GP_5_22_FN, FN_IP3_28,
3199                 GP_5_21_FN, FN_IP3_27,
3200                 GP_5_20_FN, FN_IP3_23,
3201                 GP_5_19_FN, FN_EX_WAIT0,
3202                 GP_5_18_FN, FN_WE1,
3203                 GP_5_17_FN, FN_WE0,
3204                 GP_5_16_FN, FN_RD,
3205                 GP_5_15_FN, FN_A16,
3206                 GP_5_14_FN, FN_A15,
3207                 GP_5_13_FN, FN_A14,
3208                 GP_5_12_FN, FN_A13,
3209                 GP_5_11_FN, FN_A12,
3210                 GP_5_10_FN, FN_A11,
3211                 GP_5_9_FN, FN_A10,
3212                 GP_5_8_FN, FN_A9,
3213                 GP_5_7_FN, FN_A8,
3214                 GP_5_6_FN, FN_A7,
3215                 GP_5_5_FN, FN_A6,
3216                 GP_5_4_FN, FN_A5,
3217                 GP_5_3_FN, FN_A4,
3218                 GP_5_2_FN, FN_A3,
3219                 GP_5_1_FN, FN_A2,
3220                 GP_5_0_FN, FN_A1 }
3221         },
3222         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
3223                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3224                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3225                 0, 0, 0, 0, 0, 0, 0, 0,
3226                 0, 0,
3227                 0, 0,
3228                 0, 0,
3229                 GP_6_8_FN, FN_IP3_20,
3230                 GP_6_7_FN, FN_IP3_19,
3231                 GP_6_6_FN, FN_IP3_18,
3232                 GP_6_5_FN, FN_IP3_17,
3233                 GP_6_4_FN, FN_IP3_16,
3234                 GP_6_3_FN, FN_IP3_15,
3235                 GP_6_2_FN, FN_IP3_8,
3236                 GP_6_1_FN, FN_IP3_7,
3237                 GP_6_0_FN, FN_IP3_6 }
3238         },
3239
3240         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3241                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
3242                 /* IP0_31 [1] */
3243                 0, 0,
3244                 /* IP0_30_28 [3] */
3245                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
3246                 FN_HRTS1, FN_RX4_C, 0, 0,
3247                 /* IP0_27_26 [2] */
3248                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
3249                 /* IP0_25 [1] */
3250                 FN_CS0, FN_HSPI_CS2_B,
3251                 /* IP0_24_23 [2] */
3252                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
3253                 /* IP0_22_19 [4] */
3254                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
3255                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
3256                 FN_CTS0_B, 0, 0, 0,
3257                 0, 0, 0, 0,
3258                 /* IP0_18_16 [3] */
3259                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
3260                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
3261                 /* IP0_15_14 [2] */
3262                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
3263                 /* IP0_13_12 [2] */
3264                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
3265                 /* IP0_11_10 [2] */
3266                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
3267                 /* IP0_9_8 [2] */
3268                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3269                 /* IP0_7_6 [2] */
3270                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3271                 /* IP0_5_3 [3] */
3272                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3273                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3274                 /* IP0_2_0 [3] */
3275                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3276                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3277         },
3278         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3279                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3280                 /* IP1_31_29 [3] */
3281                 0, 0, 0, 0, 0, 0, 0, 0,
3282                 /* IP1_28_25 [4] */
3283                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3284                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3285                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3286                 0, 0, 0, 0,
3287                 /* IP1_24_23 [2] */
3288                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3289                 /* IP1_22_21 [2] */
3290                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3291                 /* IP1_20_19 [2] */
3292                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3293                 /* IP1_18_15 [4] */
3294                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3295                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3296                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3297                 0, 0, 0, 0,
3298                 /* IP1_14_11 [4] */
3299                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3300                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3301                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3302                 0, 0, 0, 0,
3303                 /* IP1_10_7 [4] */
3304                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3305                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3306                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3307                 0, 0, 0, 0,
3308                 /* IP1_6_4 [3] */
3309                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3310                 FN_ATACS00, 0, 0, 0,
3311                 /* IP1_3_2 [2] */
3312                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3313                 /* IP1_1_0 [2] */
3314                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3315         },
3316         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3317                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3318                 /* IP2_31 [1] */
3319                 0, 0,
3320                 /* IP2_30_28 [3] */
3321                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3322                 FN_AUDATA2, 0, 0, 0,
3323                 /* IP2_27 [1] */
3324                 FN_DU0_DR7, FN_LCDOUT7,
3325                 /* IP2_26 [1] */
3326                 FN_DU0_DR6, FN_LCDOUT6,
3327                 /* IP2_25 [1] */
3328                 FN_DU0_DR5, FN_LCDOUT5,
3329                 /* IP2_24 [1] */
3330                 FN_DU0_DR4, FN_LCDOUT4,
3331                 /* IP2_23 [1] */
3332                 FN_DU0_DR3, FN_LCDOUT3,
3333                 /* IP2_22 [1] */
3334                 FN_DU0_DR2, FN_LCDOUT2,
3335                 /* IP2_21_19 [3] */
3336                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3337                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3338                 /* IP2_18_16 [3] */
3339                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3340                 FN_AUDATA0, FN_TX5_C, 0, 0,
3341                 /* IP2_15_12 [4] */
3342                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3343                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3344                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3345                 0, 0, 0, 0,
3346                 /* IP2_11_8 [4] */
3347                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3348                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3349                 FN_CC5_OSCOUT, 0, 0, 0,
3350                 0, 0, 0, 0,
3351                 /* IP2_7_4 [4] */
3352                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3353                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3354                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3355                 0, 0, 0, 0,
3356                 /* IP2_3_0 [4] */
3357                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3358                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3359                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3360                 0, 0, 0, 0 }
3361         },
3362         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3363                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3364                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3365             /* IP3_31_29 [3] */
3366             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3367             FN_SCL2_C, FN_REMOCON, 0, 0,
3368             /* IP3_28 [1] */
3369             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3370             /* IP3_27 [1] */
3371             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3372             /* IP3_26_24 [3] */
3373             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3374             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3375             /* IP3_23 [1] */
3376             FN_DU0_DOTCLKOUT0, FN_QCLK,
3377             /* IP3_22_21 [2] */
3378             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3379             /* IP3_20 [1] */
3380             FN_DU0_DB7, FN_LCDOUT23,
3381             /* IP3_19 [1] */
3382             FN_DU0_DB6, FN_LCDOUT22,
3383             /* IP3_18 [1] */
3384             FN_DU0_DB5, FN_LCDOUT21,
3385             /* IP3_17 [1] */
3386             FN_DU0_DB4, FN_LCDOUT20,
3387             /* IP3_16 [1] */
3388             FN_DU0_DB3, FN_LCDOUT19,
3389             /* IP3_15 [1] */
3390             FN_DU0_DB2, FN_LCDOUT18,
3391             /* IP3_14_12 [3] */
3392             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3393             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3394             /* IP3_11_9 [3] */
3395             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3396             FN_TCLK1, FN_AUDATA4, 0, 0,
3397             /* IP3_8 [1] */
3398             FN_DU0_DG7, FN_LCDOUT15,
3399             /* IP3_7 [1] */
3400             FN_DU0_DG6, FN_LCDOUT14,
3401             /* IP3_6 [1] */
3402             FN_DU0_DG5, FN_LCDOUT13,
3403             /* IP3_5 [1] */
3404             FN_DU0_DG4, FN_LCDOUT12,
3405             /* IP3_4 [1] */
3406             FN_DU0_DG3, FN_LCDOUT11,
3407             /* IP3_3 [1] */
3408             FN_DU0_DG2, FN_LCDOUT10,
3409             /* IP3_2_0 [3] */
3410             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3411             FN_AUDATA3, 0, 0, 0 }
3412         },
3413         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3414                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3415                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3416             /* IP4_31_29 [3] */
3417             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3418             FN_TX5, FN_SCK0_D, 0, 0,
3419             /* IP4_28 [1] */
3420             FN_DU1_DG7, FN_VI2_R3,
3421             /* IP4_27 [1] */
3422             FN_DU1_DG6, FN_VI2_R2,
3423             /* IP4_26 [1] */
3424             FN_DU1_DG5, FN_VI2_R1,
3425             /* IP4_25 [1] */
3426             FN_DU1_DG4, FN_VI2_R0,
3427             /* IP4_24 [1] */
3428             FN_DU1_DG3, FN_VI2_G7,
3429             /* IP4_23 [1] */
3430             FN_DU1_DG2, FN_VI2_G6,
3431             /* IP4_22_20 [3] */
3432             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3433             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3434             /* IP4_19_17 [3] */
3435             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3436             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3437             /* IP4_16 [1] */
3438             FN_DU1_DR7, FN_VI2_G5,
3439             /* IP4_15 [1] */
3440             FN_DU1_DR6, FN_VI2_G4,
3441             /* IP4_14 [1] */
3442             FN_DU1_DR5, FN_VI2_G3,
3443             /* IP4_13 [1] */
3444             FN_DU1_DR4, FN_VI2_G2,
3445             /* IP4_12 [1] */
3446             FN_DU1_DR3, FN_VI2_G1,
3447             /* IP4_11 [1] */
3448             FN_DU1_DR2, FN_VI2_G0,
3449             /* IP4_10_8 [3] */
3450             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3451             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3452             /* IP4_7_5 [3] */
3453             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3454             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3455             /* IP4_4_2 [3] */
3456             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3457             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3458             /* IP4_1_0 [2] */
3459             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3460         },
3461         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3462                              1, 2, 1, 4, 3, 4, 2, 2,
3463                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3464             /* IP5_31 [1] */
3465             0, 0,
3466             /* IP5_30_29 [2] */
3467             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3468             /* IP5_28 [1] */
3469             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3470             /* IP5_27_24 [4] */
3471             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3472             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3473             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3474             0, 0, 0, 0,
3475             /* IP5_23_21 [3] */
3476             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3477             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3478             /* IP5_20_17 [4] */
3479             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3480             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3481             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3482             0, 0, 0, 0,
3483             /* IP5_16_15 [2] */
3484             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3485             /* IP5_14_13 [2] */
3486             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3487             /* IP5_12_11 [2] */
3488             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3489             /* IP5_10_9 [2] */
3490             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3491             /* IP5_8 [1] */
3492             FN_DU1_DB7, FN_SDA2_D,
3493             /* IP5_7 [1] */
3494             FN_DU1_DB6, FN_SCL2_D,
3495             /* IP5_6 [1] */
3496             FN_DU1_DB5, FN_VI2_R7,
3497             /* IP5_5 [1] */
3498             FN_DU1_DB4, FN_VI2_R6,
3499             /* IP5_4 [1] */
3500             FN_DU1_DB3, FN_VI2_R5,
3501             /* IP5_3 [1] */
3502             FN_DU1_DB2, FN_VI2_R4,
3503             /* IP5_2_0 [3] */
3504             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3505             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3506         },
3507         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3508                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3509             /* IP6_31 [1] */
3510             0, 0,
3511             /* IP6_30_29 [2] */
3512             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3513             /* IP_28_27 [2] */
3514             0, 0, 0, 0,
3515             /* IP6_26_25 [2] */
3516             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3517             /* IP6_24_23 [2] */
3518             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3519             /* IP6_22_20 [3] */
3520             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3521             FN_TCLK0_D, 0, 0, 0,
3522             /* IP6_19_18 [2] */
3523             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3524             /* IP6_17_15 [3] */
3525             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3526             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3527             /* IP6_14_12 [3] */
3528             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3529             FN_SSI_WS9_C, 0, 0, 0,
3530             /* IP6_11_9 [3] */
3531             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3532             FN_SSI_SCK9_C, 0, 0, 0,
3533             /* IP6_8 [1] */
3534             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3535             /* IP6_7_6 [2] */
3536             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3537             /* IP6_5_4 [2] */
3538             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3539             /* IP6_3_2 [2] */
3540             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3541             /* IP6_1_0 [2] */
3542             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3543         },
3544         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3545                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3546             /* IP7_31 [1] */
3547             0, 0,
3548             /* IP7_30_29 [2] */
3549             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3550             /* IP7_28_27 [2] */
3551             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3552             /* IP7_26_25 [2] */
3553             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3554             /* IP7_24_23 [2] */
3555             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3556             /* IP7_22_21 [2] */
3557             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3558             /* IP7_20_19 [2] */
3559             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3560             /* IP7_18_17 [2] */
3561             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3562             /* IP7_16_15 [2] */
3563             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3564             /* IP7_14_13 [2] */
3565             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3566             /* IP7_12_10 [3] */
3567             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3568             FN_HSPI_TX1_C, 0, 0, 0,
3569             /* IP7_9_7 [3] */
3570             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3571             FN_HSPI_CS1_C, 0, 0, 0,
3572             /* IP7_6_4 [3] */
3573             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3574             FN_HSPI_CLK1_C, 0, 0, 0,
3575             /* IP7_3_2 [2] */
3576             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3577             /* IP7_1_0 [2] */
3578             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3579         },
3580         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3581                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3582             /* IP8_31 [1] */
3583             0, 0,
3584             /* IP8_30_28 [3] */
3585             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3586             FN_PWMFSW0_C, 0, 0, 0,
3587             /* IP8_27_25 [3] */
3588             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3589             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3590             /* IP8_24_23 [2] */
3591             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3592             /* IP8_22_21 [2] */
3593             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3594             /* IP8_20 [1] */
3595             FN_VI0_CLK, FN_MMC1_CLK,
3596             /* IP8_19 [1] */
3597             FN_FMIN, FN_RDS_DATA,
3598             /* IP8_18 [1] */
3599             FN_BPFCLK, FN_PCMWE,
3600             /* IP8_17_16 [2] */
3601             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3602             /* IP8_15_12 [4] */
3603             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3604             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3605             FN_CC5_STATE39, 0, 0, 0,
3606             0, 0, 0, 0,
3607             /* IP8_11_8 [4] */
3608             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3609             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3610             FN_CC5_STATE38, 0, 0, 0,
3611             0, 0, 0, 0,
3612             /* IP8_7_4 [4] */
3613             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3614             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3615             FN_CC5_STATE37, 0, 0, 0,
3616             0, 0, 0, 0,
3617             /* IP8_3_0 [4] */
3618             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3619             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3620             FN_CC5_STATE36, 0, 0, 0,
3621             0, 0, 0, 0 }
3622         },
3623         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3624                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3625                              2, 2, 1, 1, 1, 1, 2, 2) {
3626             /* IP9_31_30 [2] */
3627             0, 0, 0, 0,
3628             /* IP9_29_28 [2] */
3629             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3630             /* IP9_27_26 [2] */
3631             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3632             /* IP9_25_24 [2] */
3633             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3634             /* IP9_23_22 [2] */
3635             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3636             /* IP9_21_19 [3] */
3637             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3638             FN_TS_SDAT0, 0, 0, 0,
3639             /* IP9_18_16 [3] */
3640             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3641             FN_TS_SPSYNC0, 0, 0, 0,
3642             /* IP9_15_14 [2] */
3643             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3644             /* IP9_13_12 [2] */
3645             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3646             /* IP9_11_10 [2] */
3647             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3648             /* IP9_9_8 [2] */
3649             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3650             /* IP9_7 [1] */
3651             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3652             /* IP9_6 [1] */
3653             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3654             /* IP9_5 [1] */
3655             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3656             /* IP9_4 [1] */
3657             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3658             /* IP9_3_2 [2] */
3659             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3660             /* IP9_1_0 [2] */
3661             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3662         },
3663         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3664                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3665             /* IP10_31_29 [3] */
3666             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3667             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3668             /* IP10_28_26 [3] */
3669             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3670             FN_PWMFSW0_E, 0, 0, 0,
3671             /* IP10_25_24 [2] */
3672             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3673             /* IP10_23_21 [3] */
3674             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3675             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3676             /* IP10_20_18 [3] */
3677             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3678             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3679             /* IP10_17_15 [3] */
3680             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3681             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3682             /* IP10_14_12 [3] */
3683             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3684             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3685             /* IP10_11_9 [3] */
3686             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3687             FN_ARM_TRACEDATA_13, 0, 0, 0,
3688             /* IP10_8_6 [3] */
3689             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3690             FN_ARM_TRACEDATA_12, 0, 0, 0,
3691             /* IP10_5_3 [3] */
3692             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3693             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3694             /* IP10_2_0 [3] */
3695             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3696             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3697         },
3698         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3699                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3700             /* IP11_31_30 [2] */
3701             0, 0, 0, 0,
3702             /* IP11_29_27 [3] */
3703             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3704             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3705             /* IP11_26_24 [3] */
3706             FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3707             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3708             /* IP11_23_21 [3] */
3709             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3710             FN_HSPI_RX1_D, 0, 0, 0,
3711             /* IP11_20_18 [3] */
3712             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3713             FN_HSPI_TX1_D, 0, 0, 0,
3714             /* IP11_17_15 [3] */
3715             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3716             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3717             /* IP11_14_12 [3] */
3718             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3719             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3720             /* IP11_11_9 [3] */
3721             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3722             FN_ADICHS0_B, 0, 0, 0,
3723             /* IP11_8_6 [3] */
3724             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3725             FN_ADIDATA_B, 0, 0, 0,
3726             /* IP11_5_3 [3] */
3727             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3728             FN_ADICS_B_SAMP_B, 0, 0, 0,
3729             /* IP11_2_0 [3] */
3730             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3731             FN_ADICLK_B, 0, 0, 0 }
3732         },
3733         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3734                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3735             /* IP12_31_28 [4] */
3736             0, 0, 0, 0, 0, 0, 0, 0,
3737             0, 0, 0, 0, 0, 0, 0, 0,
3738             /* IP12_27_24 [4] */
3739             0, 0, 0, 0, 0, 0, 0, 0,
3740             0, 0, 0, 0, 0, 0, 0, 0,
3741             /* IP12_23_20 [4] */
3742             0, 0, 0, 0, 0, 0, 0, 0,
3743             0, 0, 0, 0, 0, 0, 0, 0,
3744             /* IP12_19_18 [2] */
3745             0, 0, 0, 0,
3746             /* IP12_17_15 [3] */
3747             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3748             FN_SCK4_B, 0, 0, 0,
3749             /* IP12_14_12 [3] */
3750             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3751             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3752             /* IP12_11_9 [3] */
3753             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3754             FN_TX4_B, FN_SIM_D_B, 0, 0,
3755             /* IP12_8_6 [3] */
3756             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3757             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3758             /* IP12_5_3 [3] */
3759             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3760             FN_SCL1_C, FN_HTX0_B, 0, 0,
3761             /* IP12_2_0 [3] */
3762             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3763             FN_SCK2, FN_HSCK0_B, 0, 0 }
3764         },
3765         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3766                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3767                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3768             /* SEL_SCIF5 [2] */
3769             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3770             /* SEL_SCIF4 [2] */
3771             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3772             /* SEL_SCIF3 [3] */
3773             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3774             FN_SEL_SCIF3_4, 0, 0, 0,
3775             /* SEL_SCIF2 [3] */
3776             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3777             FN_SEL_SCIF2_4, 0, 0, 0,
3778             /* SEL_SCIF1 [2] */
3779             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3780             /* SEL_SCIF0 [2] */
3781             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3782             /* SEL_SSI9 [2] */
3783             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3784             /* SEL_SSI8 [2] */
3785             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3786             /* SEL_SSI7 [2] */
3787             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3788             /* SEL_VI0 [1] */
3789             FN_SEL_VI0_0, FN_SEL_VI0_1,
3790             /* SEL_SD2 [1] */
3791             FN_SEL_SD2_0, FN_SEL_SD2_1,
3792             /* SEL_INT3 [1] */
3793             FN_SEL_INT3_0, FN_SEL_INT3_1,
3794             /* SEL_INT2 [1] */
3795             FN_SEL_INT2_0, FN_SEL_INT2_1,
3796             /* SEL_INT1 [1] */
3797             FN_SEL_INT1_0, FN_SEL_INT1_1,
3798             /* SEL_INT0 [1] */
3799             FN_SEL_INT0_0, FN_SEL_INT0_1,
3800             /* SEL_IE [1] */
3801             FN_SEL_IE_0, FN_SEL_IE_1,
3802             /* SEL_EXBUS2 [2] */
3803             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3804             /* SEL_EXBUS1 [1] */
3805             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3806             /* SEL_EXBUS0 [2] */
3807             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3808         },
3809         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3810                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3811                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3812             /* SEL_TMU1 [2] */
3813             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3814             /* SEL_TMU0 [2] */
3815             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3816             /* SEL_SCIF [2] */
3817             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3818             /* SEL_CANCLK [2] */
3819             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3820             /* SEL_CAN0 [1] */
3821             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3822             /* SEL_HSCIF1 [1] */
3823             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3824             /* SEL_HSCIF0 [1] */
3825             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3826             /* SEL_PWMFSW [3] */
3827             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3828             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3829             /* SEL_ADI [1] */
3830             FN_SEL_ADI_0, FN_SEL_ADI_1,
3831             /* [2] */
3832             0, 0, 0, 0,
3833             /* [2] */
3834             0, 0, 0, 0,
3835             /* [2] */
3836             0, 0, 0, 0,
3837             /* SEL_GPS [2] */
3838             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3839             /* SEL_SIM [1] */
3840             FN_SEL_SIM_0, FN_SEL_SIM_1,
3841             /* SEL_HSPI2 [1] */
3842             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3843             /* SEL_HSPI1 [2] */
3844             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3845             /* SEL_I2C3 [1] */
3846             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3847             /* SEL_I2C2 [2] */
3848             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3849             /* SEL_I2C1 [2] */
3850             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3851         },
3852         { },
3853 };
3854
3855 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3856         .name = "r8a7779_pfc",
3857
3858         .unlock_reg = 0xfffc0000, /* PMMR */
3859
3860         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3861
3862         .pins = pinmux_pins,
3863         .nr_pins = ARRAY_SIZE(pinmux_pins),
3864         .groups = pinmux_groups,
3865         .nr_groups = ARRAY_SIZE(pinmux_groups),
3866         .functions = pinmux_functions,
3867         .nr_functions = ARRAY_SIZE(pinmux_functions),
3868
3869         .cfg_regs = pinmux_config_regs,
3870
3871         .gpio_data = pinmux_data,
3872         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3873 };