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Linux 4.1.16
[linux/fpc-iii.git] / drivers / rtc / rtc-ab-b5ze-s3.c
blobb5cbc1bf5a3e5fb50efd2dabc897598cef5365e6
1 /*
2 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
3 * I2C RTC / Alarm chip
4 *
5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
6 *
7 * Detailed datasheet of the chip is available here:
8 *
9 * http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
10 *
11 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/rtc.h>
27 #include <linux/i2c.h>
28 #include <linux/bcd.h>
29 #include <linux/of.h>
30 #include <linux/regmap.h>
31 #include <linux/interrupt.h>
32
33 #define DRV_NAME "rtc-ab-b5ze-s3"
34
35 /* Control section */
36 #define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
37 #define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
38 #define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
39 #define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
40 #define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
41 #define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
42 #define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
43 #define ABB5ZES3_REG_CTRL1_CAP BIT(7)
44
45 #define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
46 #define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
47 #define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
48 #define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
49 #define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
50 #define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
51 #define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
52 #define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
53 #define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
54
55 #define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
56 #define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
57 #define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
58 #define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
59 #define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
60 #define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
61 #define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
62 #define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
63
64 #define ABB5ZES3_CTRL_SEC_LEN 3
65
66 /* RTC section */
67 #define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
68 #define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
69 #define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
70 #define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
71 #define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
72 #define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
73 #define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
74 #define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
75 #define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
76
77 #define ABB5ZES3_RTC_SEC_LEN 7
78
79 /* Alarm section (enable bits are all active low) */
80 #define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
81 #define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
82 #define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
83 #define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
84 #define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
85 #define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
86 #define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
87 #define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
88
89 #define ABB5ZES3_ALRM_SEC_LEN 4
90
91 /* Frequency offset section */
92 #define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
93 #define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
94
95 /* CLOCKOUT section */
96 #define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
97 #define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
98 #define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
99 #define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
100 #define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
101 #define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
102 #define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
103 #define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
104 #define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
105
106 /* Timer A Section */
107 #define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
108 #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
109 #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
110 #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
111 #define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
112
113 #define ABB5ZES3_TIMA_SEC_LEN 2
114
115 /* Timer B Section */
116 #define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
117 #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
118 #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
119 #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
120 #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
121 #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
122 #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
123 #define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
124 #define ABB5ZES3_TIMB_SEC_LEN 2
125
126 #define ABB5ZES3_MEM_MAP_LEN 0x14
127
128 struct abb5zes3_rtc_data {
129 struct rtc_device *rtc;
130 struct regmap *regmap;
131 struct mutex lock;
132
133 int irq;
134
135 bool battery_low;
136 bool timer_alarm; /* current alarm is via timer A */
137 };
138
139 /*
140 * Try and match register bits w/ fixed null values to see whether we
141 * are dealing with an ABB5ZES3. Note: this function is called early
142 * during init and hence does need mutex protection.
143 */
144 static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
145 {
146 u8 regs[ABB5ZES3_MEM_MAP_LEN];
147 static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
148 0x80, 0xc0, 0xc0, 0xf8,
149 0xe0, 0x00, 0x00, 0x40,
150 0x40, 0x78, 0x00, 0x00,
151 0xf8, 0x00, 0x88, 0x00 };
152 int ret, i;
153
154 ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
155 if (ret)
156 return ret;
157
158 for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
159 if (regs[i] & mask[i]) /* check if bits are cleared */
160 return -ENODEV;
161 }
162
163 return 0;
164 }
165
166 /* Clear alarm status bit. */
167 static int _abb5zes3_rtc_clear_alarm(struct device *dev)
168 {
169 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
170 int ret;
171
172 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
173 ABB5ZES3_REG_CTRL2_AF, 0);
174 if (ret)
175 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
176
177 return ret;
178 }
179
180 /* Enable or disable alarm (i.e. alarm interrupt generation) */
181 static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
182 {
183 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
184 int ret;
185
186 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
187 ABB5ZES3_REG_CTRL1_AIE,
188 enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
189 if (ret)
190 dev_err(dev, "%s: writing alarm INT failed (%d)\n",
191 __func__, ret);
192
193 return ret;
194 }
195
196 /* Enable or disable timer (watchdog timer A interrupt generation) */
197 static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
198 {
199 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
200 int ret;
201
202 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
203 ABB5ZES3_REG_CTRL2_WTAIE,
204 enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
205 if (ret)
206 dev_err(dev, "%s: writing timer INT failed (%d)\n",
207 __func__, ret);
208
209 return ret;
210 }
211
212 /*
213 * Note: we only read, so regmap inner lock protection is sufficient, i.e.
214 * we do not need driver's main lock protection.
215 */
216 static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
217 {
218 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
219 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
220 int ret;
221
222 /*
223 * As we need to read CTRL1 register anyway to access 24/12h
224 * mode bit, we do a single bulk read of both control and RTC
225 * sections (they are consecutive). This also ease indexing
226 * of register values after bulk read.
227 */
228 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
229 sizeof(regs));
230 if (ret) {
231 dev_err(dev, "%s: reading RTC time failed (%d)\n",
232 __func__, ret);
233 goto err;
234 }
235
236 /* If clock integrity is not guaranteed, do not return a time value */
237 if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC) {
238 ret = -ENODATA;
239 goto err;
240 }
241
242 tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
243 tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
244
245 if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
246 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
247 if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
248 tm->tm_hour += 12;
249 } else { /* 24hr mode */
250 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
251 }
252
253 tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
254 tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
255 tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
256 tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
257
258 ret = rtc_valid_tm(tm);
259
260 err:
261 return ret;
262 }
263
264 static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
265 {
266 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
267 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
268 int ret;
269
270 /*
271 * Year register is 8-bit wide and bcd-coded, i.e records values
272 * between 0 and 99. tm_year is an offset from 1900 and we are
273 * interested in the 2000-2099 range, so any value less than 100
274 * is invalid.
275 */
276 if (tm->tm_year < 100)
277 return -EINVAL;
278
279 regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
280 regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
281 regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
282 regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
283 regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
284 regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
285 regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
286
287 mutex_lock(&data->lock);
288 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
289 regs + ABB5ZES3_REG_RTC_SC,
290 ABB5ZES3_RTC_SEC_LEN);
291 mutex_unlock(&data->lock);
292
293
294 return ret;
295 }
296
297 /*
298 * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
299 * given number of seconds.
300 */
301 static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
302 {
303 *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
304 *timer_a = secs;
305 }
306
307 /*
308 * Return current number of seconds in Timer A. As we only use
309 * timer A with a 1Hz freq, this is what we expect to have.
310 */
311 static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
312 {
313 if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
314 return -EINVAL;
315
316 *secs = timer_a;
317
318 return 0;
319 }
320
321 /*
322 * Read alarm currently configured via a watchdog timer using timer A. This
323 * is done by reading current RTC time and adding remaining timer time.
324 */
325 static int _abb5zes3_rtc_read_timer(struct device *dev,
326 struct rtc_wkalrm *alarm)
327 {
328 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
329 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
330 u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
331 unsigned long rtc_secs;
332 unsigned int reg;
333 u8 timer_secs;
334 int ret;
335
336 /*
337 * Instead of doing two separate calls, because they are consecutive,
338 * we grab both clockout register and Timer A section. The latter is
339 * used to decide if timer A is enabled (as a watchdog timer).
340 */
341 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
342 ABB5ZES3_TIMA_SEC_LEN + 1);
343 if (ret) {
344 dev_err(dev, "%s: reading Timer A section failed (%d)\n",
345 __func__, ret);
346 goto err;
347 }
348
349 /* get current time ... */
350 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
351 if (ret)
352 goto err;
353
354 /* ... convert to seconds ... */
355 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
356 if (ret)
357 goto err;
358
359 /* ... add remaining timer A time ... */
360 ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
361 if (ret)
362 goto err;
363
364 /* ... and convert back. */
365 rtc_time_to_tm(rtc_secs + timer_secs, alarm_tm);
366
367 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
368 if (ret) {
369 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
370 __func__, ret);
371 goto err;
372 }
373
374 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
375
376 err:
377 return ret;
378 }
379
380 /* Read alarm currently configured via a RTC alarm registers. */
381 static int _abb5zes3_rtc_read_alarm(struct device *dev,
382 struct rtc_wkalrm *alarm)
383 {
384 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
385 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
386 unsigned long rtc_secs, alarm_secs;
387 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
388 unsigned int reg;
389 int ret;
390
391 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
392 ABB5ZES3_ALRM_SEC_LEN);
393 if (ret) {
394 dev_err(dev, "%s: reading alarm section failed (%d)\n",
395 __func__, ret);
396 goto err;
397 }
398
399 alarm_tm->tm_sec = 0;
400 alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
401 alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
402 alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
403 alarm_tm->tm_wday = -1;
404
405 /*
406 * The alarm section does not store year/month. We use the ones in rtc
407 * section as a basis and increment month and then year if needed to get
408 * alarm after current time.
409 */
410 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
411 if (ret)
412 goto err;
413
414 alarm_tm->tm_year = rtc_tm.tm_year;
415 alarm_tm->tm_mon = rtc_tm.tm_mon;
416
417 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
418 if (ret)
419 goto err;
420
421 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
422 if (ret)
423 goto err;
424
425 if (alarm_secs < rtc_secs) {
426 if (alarm_tm->tm_mon == 11) {
427 alarm_tm->tm_mon = 0;
428 alarm_tm->tm_year += 1;
429 } else {
430 alarm_tm->tm_mon += 1;
431 }
432 }
433
434 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
435 if (ret) {
436 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
437 __func__, ret);
438 goto err;
439 }
440
441 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
442
443 err:
444 return ret;
445 }
446
447 /*
448 * As the Alarm mechanism supported by the chip is only accurate to the
449 * minute, we use the watchdog timer mechanism provided by timer A
450 * (up to 256 seconds w/ a second accuracy) for low alarm values (below
451 * 4 minutes). Otherwise, we use the common alarm mechanism provided
452 * by the chip. In order for that to work, we keep track of currently
453 * configured timer type via 'timer_alarm' flag in our private data
454 * structure.
455 */
456 static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
457 {
458 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
459 int ret;
460
461 mutex_lock(&data->lock);
462 if (data->timer_alarm)
463 ret = _abb5zes3_rtc_read_timer(dev, alarm);
464 else
465 ret = _abb5zes3_rtc_read_alarm(dev, alarm);
466 mutex_unlock(&data->lock);
467
468 return ret;
469 }
470
471 /*
472 * Set alarm using chip alarm mechanism. It is only accurate to the
473 * minute (not the second). The function expects alarm interrupt to
474 * be disabled.
475 */
476 static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
477 {
478 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
479 struct rtc_time *alarm_tm = &alarm->time;
480 unsigned long rtc_secs, alarm_secs;
481 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
482 struct rtc_time rtc_tm;
483 int ret, enable = 1;
484
485 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
486 if (ret)
487 goto err;
488
489 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
490 if (ret)
491 goto err;
492
493 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
494 if (ret)
495 goto err;
496
497 /* If alarm time is before current time, disable the alarm */
498 if (!alarm->enabled || alarm_secs <= rtc_secs) {
499 enable = 0;
500 } else {
501 /*
502 * Chip only support alarms up to one month in the future. Let's
503 * return an error if we get something after that limit.
504 * Comparison is done by incrementing rtc_tm month field by one
505 * and checking alarm value is still below.
506 */
507 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
508 rtc_tm.tm_mon = 0;
509 rtc_tm.tm_year += 1;
510 } else {
511 rtc_tm.tm_mon += 1;
512 }
513
514 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
515 if (ret)
516 goto err;
517
518 if (alarm_secs > rtc_secs) {
519 dev_err(dev, "%s: alarm maximum is one month in the "
520 "future (%d)\n", __func__, ret);
521 ret = -EINVAL;
522 goto err;
523 }
524 }
525
526 /*
527 * Program all alarm registers but DW one. For each register, setting
528 * MSB to 0 enables associated alarm.
529 */
530 regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
531 regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
532 regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
533 regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
534
535 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
536 ABB5ZES3_ALRM_SEC_LEN);
537 if (ret < 0) {
538 dev_err(dev, "%s: writing ALARM section failed (%d)\n",
539 __func__, ret);
540 goto err;
541 }
542
543 /* Record currently configured alarm is not a timer */
544 data->timer_alarm = 0;
545
546 /* Enable or disable alarm interrupt generation */
547 ret = _abb5zes3_rtc_update_alarm(dev, enable);
548
549 err:
550 return ret;
551 }
552
553 /*
554 * Set alarm using timer watchdog (via timer A) mechanism. The function expects
555 * timer A interrupt to be disabled.
556 */
557 static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
558 u8 secs)
559 {
560 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
561 u8 regs[ABB5ZES3_TIMA_SEC_LEN];
562 u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
563 int ret = 0;
564
565 /* Program given number of seconds to Timer A registers */
566 sec_to_timer_a(secs, &regs[0], &regs[1]);
567 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
568 ABB5ZES3_TIMA_SEC_LEN);
569 if (ret < 0) {
570 dev_err(dev, "%s: writing timer section failed\n", __func__);
571 goto err;
572 }
573
574 /* Configure Timer A as a watchdog timer */
575 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
576 mask, ABB5ZES3_REG_TIM_CLK_TAC1);
577 if (ret)
578 dev_err(dev, "%s: failed to update timer\n", __func__);
579
580 /* Record currently configured alarm is a timer */
581 data->timer_alarm = 1;
582
583 /* Enable or disable timer interrupt generation */
584 ret = _abb5zes3_rtc_update_timer(dev, alarm->enabled);
585
586 err:
587 return ret;
588 }
589
590 /*
591 * The chip has an alarm which is only accurate to the minute. In order to
592 * handle alarms below that limit, we use the watchdog timer function of
593 * timer A. More precisely, the timer method is used for alarms below 240
594 * seconds.
595 */
596 static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
597 {
598 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
599 struct rtc_time *alarm_tm = &alarm->time;
600 unsigned long rtc_secs, alarm_secs;
601 struct rtc_time rtc_tm;
602 int ret;
603
604 mutex_lock(&data->lock);
605 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
606 if (ret)
607 goto err;
608
609 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
610 if (ret)
611 goto err;
612
613 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
614 if (ret)
615 goto err;
616
617 /* Let's first disable both the alarm and the timer interrupts */
618 ret = _abb5zes3_rtc_update_alarm(dev, false);
619 if (ret < 0) {
620 dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
621 ret);
622 goto err;
623 }
624 ret = _abb5zes3_rtc_update_timer(dev, false);
625 if (ret < 0) {
626 dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
627 ret);
628 goto err;
629 }
630
631 data->timer_alarm = 0;
632
633 /*
634 * Let's now configure the alarm; if we are expected to ring in
635 * more than 240s, then we setup an alarm. Otherwise, a timer.
636 */
637 if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
638 ret = _abb5zes3_rtc_set_timer(dev, alarm,
639 alarm_secs - rtc_secs);
640 else
641 ret = _abb5zes3_rtc_set_alarm(dev, alarm);
642
643 err:
644 mutex_unlock(&data->lock);
645
646 if (ret)
647 dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
648 ret);
649
650 return ret;
651 }
652
653 /* Enable or disable battery low irq generation */
654 static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
655 bool enable)
656 {
657 return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
658 ABB5ZES3_REG_CTRL3_BLIE,
659 enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
660 }
661
662 /*
663 * Check current RTC status and enable/disable what needs to be. Return 0 if
664 * everything went ok and a negative value upon error. Note: this function
665 * is called early during init and hence does need mutex protection.
666 */
667 static int abb5zes3_rtc_check_setup(struct device *dev)
668 {
669 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
670 struct regmap *regmap = data->regmap;
671 unsigned int reg;
672 int ret;
673 u8 mask;
674
675 /*
676 * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
677 * is disabled here to prevent polluting the interrupt line and
678 * uselessly triggering the IRQ handler we install for alarm and battery
679 * low events. Note: this is done before clearing int. status below
680 * in this function.
681 * We also disable all timers and set timer interrupt to permanent (not
682 * pulsed).
683 */
684 mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
685 ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
686 ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
687 ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
688 ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
689 ABB5ZES3_REG_TIM_CLK_COF0 | ABB5ZES3_REG_TIM_CLK_COF1 |
690 ABB5ZES3_REG_TIM_CLK_COF2);
691 if (ret < 0) {
692 dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
693 __func__, ret);
694 return ret;
695 }
696
697 /*
698 * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
699 * individually by clearing/setting MSB of each associated register. So,
700 * we set all alarm enable bits to disable current alarm setting.
701 */
702 mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
703 ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
704 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
705 if (ret < 0) {
706 dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
707 __func__, ret);
708 return ret;
709 }
710
711 /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
712 mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
713 ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
714 ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
715 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
716 if (ret < 0) {
717 dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
718 __func__, ret);
719 return ret;
720 }
721
722 /*
723 * Set Control 2 register (timer int. disabled, alarm status cleared).
724 * WTAF is read-only and cleared automatically by reading the register.
725 */
726 mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
727 ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
728 ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
729 ABB5ZES3_REG_CTRL2_CTAF);
730 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
731 if (ret < 0) {
732 dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
733 __func__, ret);
734 return ret;
735 }
736
737 /*
738 * Enable battery low detection function and battery switchover function
739 * (standard mode). Disable associated interrupts. Clear battery
740 * switchover flag but not battery low flag. The latter is checked
741 * later below.
742 */
743 mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
744 ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
745 ABB5ZES3_REG_CTRL3_BSIE| ABB5ZES3_REG_CTRL3_BSF);
746 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
747 if (ret < 0) {
748 dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
749 __func__, ret);
750 return ret;
751 }
752
753 /* Check oscillator integrity flag */
754 ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
755 if (ret < 0) {
756 dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
757 __func__, ret);
758 return ret;
759 }
760
761 if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
762 dev_err(dev, "clock integrity not guaranteed. Osc. has stopped "
763 "or has been interrupted.\n");
764 dev_err(dev, "change battery (if not already done) and "
765 "then set time to reset osc. failure flag.\n");
766 }
767
768 /*
769 * Check battery low flag at startup: this allows reporting battery
770 * is low at startup when IRQ line is not connected. Note: we record
771 * current status to avoid reenabling this interrupt later in probe
772 * function if battery is low.
773 */
774 ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
775 if (ret < 0) {
776 dev_err(dev, "%s: unable to read battery low flag (%d)\n",
777 __func__, ret);
778 return ret;
779 }
780
781 data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
782 if (data->battery_low) {
783 dev_err(dev, "RTC battery is low; please, consider "
784 "changing it!\n");
785
786 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
787 if (ret)
788 dev_err(dev, "%s: disabling battery low interrupt "
789 "generation failed (%d)\n", __func__, ret);
790 }
791
792 return ret;
793 }
794
795 static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
796 unsigned int enable)
797 {
798 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
799 int ret = 0;
800
801 if (rtc_data->irq) {
802 mutex_lock(&rtc_data->lock);
803 if (rtc_data->timer_alarm)
804 ret = _abb5zes3_rtc_update_timer(dev, enable);
805 else
806 ret = _abb5zes3_rtc_update_alarm(dev, enable);
807 mutex_unlock(&rtc_data->lock);
808 }
809
810 return ret;
811 }
812
813 static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
814 {
815 struct i2c_client *client = data;
816 struct device *dev = &client->dev;
817 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
818 struct rtc_device *rtc = rtc_data->rtc;
819 u8 regs[ABB5ZES3_CTRL_SEC_LEN];
820 int ret, handled = IRQ_NONE;
821
822 ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
823 ABB5ZES3_CTRL_SEC_LEN);
824 if (ret) {
825 dev_err(dev, "%s: unable to read control section (%d)!\n",
826 __func__, ret);
827 return handled;
828 }
829
830 /*
831 * Check battery low detection flag and disable battery low interrupt
832 * generation if flag is set (interrupt can only be cleared when
833 * battery is replaced).
834 */
835 if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
836 dev_err(dev, "RTC battery is low; please change it!\n");
837
838 _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
839
840 handled = IRQ_HANDLED;
841 }
842
843 /* Check alarm flag */
844 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
845 dev_dbg(dev, "RTC alarm!\n");
846
847 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
848
849 /* Acknowledge and disable the alarm */
850 _abb5zes3_rtc_clear_alarm(dev);
851 _abb5zes3_rtc_update_alarm(dev, 0);
852
853 handled = IRQ_HANDLED;
854 }
855
856 /* Check watchdog Timer A flag */
857 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
858 dev_dbg(dev, "RTC timer!\n");
859
860 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
861
862 /*
863 * Acknowledge and disable the alarm. Note: WTAF
864 * flag had been cleared when reading CTRL2
865 */
866 _abb5zes3_rtc_update_timer(dev, 0);
867
868 rtc_data->timer_alarm = 0;
869
870 handled = IRQ_HANDLED;
871 }
872
873 return handled;
874 }
875
876 static const struct rtc_class_ops rtc_ops = {
877 .read_time = _abb5zes3_rtc_read_time,
878 .set_time = abb5zes3_rtc_set_time,
879 .read_alarm = abb5zes3_rtc_read_alarm,
880 .set_alarm = abb5zes3_rtc_set_alarm,
881 .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
882 };
883
884 static const struct regmap_config abb5zes3_rtc_regmap_config = {
885 .reg_bits = 8,
886 .val_bits = 8,
887 };
888
889 static int abb5zes3_probe(struct i2c_client *client,
890 const struct i2c_device_id *id)
891 {
892 struct abb5zes3_rtc_data *data = NULL;
893 struct device *dev = &client->dev;
894 struct regmap *regmap;
895 int ret;
896
897 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
898 I2C_FUNC_SMBUS_BYTE_DATA |
899 I2C_FUNC_SMBUS_I2C_BLOCK)) {
900 ret = -ENODEV;
901 goto err;
902 }
903
904 regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
905 if (IS_ERR(regmap)) {
906 ret = PTR_ERR(regmap);
907 dev_err(dev, "%s: regmap allocation failed: %d\n",
908 __func__, ret);
909 goto err;
910 }
911
912 ret = abb5zes3_i2c_validate_chip(regmap);
913 if (ret)
914 goto err;
915
916 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
917 if (!data) {
918 ret = -ENOMEM;
919 goto err;
920 }
921
922 mutex_init(&data->lock);
923 data->regmap = regmap;
924 dev_set_drvdata(dev, data);
925
926 ret = abb5zes3_rtc_check_setup(dev);
927 if (ret)
928 goto err;
929
930 if (client->irq > 0) {
931 ret = devm_request_threaded_irq(dev, client->irq, NULL,
932 _abb5zes3_rtc_interrupt,
933 IRQF_SHARED|IRQF_ONESHOT,
934 DRV_NAME, client);
935 if (!ret) {
936 device_init_wakeup(dev, true);
937 data->irq = client->irq;
938 dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
939 client->irq);
940 } else {
941 dev_err(dev, "%s: irq %d unavailable (%d)\n",
942 __func__, client->irq, ret);
943 goto err;
944 }
945 }
946
947 data->rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops,
948 THIS_MODULE);
949 ret = PTR_ERR_OR_ZERO(data->rtc);
950 if (ret) {
951 dev_err(dev, "%s: unable to register RTC device (%d)\n",
952 __func__, ret);
953 goto err;
954 }
955
956 /* Enable battery low detection interrupt if battery not already low */
957 if (!data->battery_low && data->irq) {
958 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
959 if (ret) {
960 dev_err(dev, "%s: enabling battery low interrupt "
961 "generation failed (%d)\n", __func__, ret);
962 goto err;
963 }
964 }
965
966 err:
967 if (ret && data && data->irq)
968 device_init_wakeup(dev, false);
969 return ret;
970 }
971
972 static int abb5zes3_remove(struct i2c_client *client)
973 {
974 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(&client->dev);
975
976 if (rtc_data->irq > 0)
977 device_init_wakeup(&client->dev, false);
978
979 return 0;
980 }
981
982 #ifdef CONFIG_PM_SLEEP
983 static int abb5zes3_rtc_suspend(struct device *dev)
984 {
985 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
986
987 if (device_may_wakeup(dev))
988 return enable_irq_wake(rtc_data->irq);
989
990 return 0;
991 }
992
993 static int abb5zes3_rtc_resume(struct device *dev)
994 {
995 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
996
997 if (device_may_wakeup(dev))
998 return disable_irq_wake(rtc_data->irq);
999
1000 return 0;
1001 }
1002 #endif
1003
1004 static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
1005 abb5zes3_rtc_resume);
1006
1007 #ifdef CONFIG_OF
1008 static const struct of_device_id abb5zes3_dt_match[] = {
1009 { .compatible = "abracon,abb5zes3" },
1010 { },
1011 };
1012 #endif
1013
1014 static const struct i2c_device_id abb5zes3_id[] = {
1015 { "abb5zes3", 0 },
1016 { }
1017 };
1018 MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
1019
1020 static struct i2c_driver abb5zes3_driver = {
1021 .driver = {
1022 .name = DRV_NAME,
1023 .owner = THIS_MODULE,
1024 .pm = &abb5zes3_rtc_pm_ops,
1025 .of_match_table = of_match_ptr(abb5zes3_dt_match),
1026 },
1027 .probe = abb5zes3_probe,
1028 .remove = abb5zes3_remove,
1029 .id_table = abb5zes3_id,
1030 };
1031 module_i2c_driver(abb5zes3_driver);
1032
1033 MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
1034 MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
1035 MODULE_LICENSE("GPL");
Linux with added FPC-III support