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Linux 4.1.16
[linux/fpc-iii.git] / drivers / rtc / rtc-sirfsoc.c
blobedc3b43282d4033c531d21b55e14679a6f577aa0
1 /*
2 * SiRFSoC Real Time Clock interface for Linux
3 *
4 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9 #include <linux/module.h>
10 #include <linux/err.h>
11 #include <linux/rtc.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/rtc/sirfsoc_rtciobrg.h>
17
18
19 #define RTC_CN 0x00
20 #define RTC_ALARM0 0x04
21 #define RTC_ALARM1 0x18
22 #define RTC_STATUS 0x08
23 #define RTC_SW_VALUE 0x40
24 #define SIRFSOC_RTC_AL1E (1<<6)
25 #define SIRFSOC_RTC_AL1 (1<<4)
26 #define SIRFSOC_RTC_HZE (1<<3)
27 #define SIRFSOC_RTC_AL0E (1<<2)
28 #define SIRFSOC_RTC_HZ (1<<1)
29 #define SIRFSOC_RTC_AL0 (1<<0)
30 #define RTC_DIV 0x0c
31 #define RTC_DEEP_CTRL 0x14
32 #define RTC_CLOCK_SWITCH 0x1c
33 #define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
34
35 /* Refer to RTC DIV switch */
36 #define RTC_HZ 16
37
38 /* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
39 #define RTC_SHIFT 4
40
41 #define INTR_SYSRTC_CN 0x48
42
43 struct sirfsoc_rtc_drv {
44 struct rtc_device *rtc;
45 u32 rtc_base;
46 u32 irq;
47 unsigned irq_wake;
48 /* Overflow for every 8 years extra time */
49 u32 overflow_rtc;
50 spinlock_t lock;
51 #ifdef CONFIG_PM
52 u32 saved_counter;
53 u32 saved_overflow_rtc;
54 #endif
55 };
56
57 static int sirfsoc_rtc_read_alarm(struct device *dev,
58 struct rtc_wkalrm *alrm)
59 {
60 unsigned long rtc_alarm, rtc_count;
61 struct sirfsoc_rtc_drv *rtcdrv;
62
63 rtcdrv = dev_get_drvdata(dev);
64
65 spin_lock_irq(&rtcdrv->lock);
66
67 rtc_count = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
68
69 rtc_alarm = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_ALARM0);
70 memset(alrm, 0, sizeof(struct rtc_wkalrm));
71
72 /*
73 * assume alarm interval not beyond one round counter overflow_rtc:
74 * 0->0xffffffff
75 */
76 /* if alarm is in next overflow cycle */
77 if (rtc_count > rtc_alarm)
78 rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
79 << (BITS_PER_LONG - RTC_SHIFT)
80 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
81 else
82 rtc_time_to_tm(rtcdrv->overflow_rtc
83 << (BITS_PER_LONG - RTC_SHIFT)
84 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
85 if (sirfsoc_rtc_iobrg_readl(
86 rtcdrv->rtc_base + RTC_STATUS) & SIRFSOC_RTC_AL0E)
87 alrm->enabled = 1;
88
89 spin_unlock_irq(&rtcdrv->lock);
90
91 return 0;
92 }
93
94 static int sirfsoc_rtc_set_alarm(struct device *dev,
95 struct rtc_wkalrm *alrm)
96 {
97 unsigned long rtc_status_reg, rtc_alarm;
98 struct sirfsoc_rtc_drv *rtcdrv;
99 rtcdrv = dev_get_drvdata(dev);
100
101 if (alrm->enabled) {
102 rtc_tm_to_time(&(alrm->time), &rtc_alarm);
103
104 spin_lock_irq(&rtcdrv->lock);
105
106 rtc_status_reg = sirfsoc_rtc_iobrg_readl(
107 rtcdrv->rtc_base + RTC_STATUS);
108 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
109 /*
110 * An ongoing alarm in progress - ingore it and not
111 * to return EBUSY
112 */
113 dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
114 }
115
116 sirfsoc_rtc_iobrg_writel(
117 rtc_alarm << RTC_SHIFT, rtcdrv->rtc_base + RTC_ALARM0);
118 rtc_status_reg &= ~0x07; /* mask out the lower status bits */
119 /*
120 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
121 * Writing 1 into this bit will clear it
122 */
123 rtc_status_reg |= SIRFSOC_RTC_AL0;
124 /* enable the RTC alarm interrupt */
125 rtc_status_reg |= SIRFSOC_RTC_AL0E;
126 sirfsoc_rtc_iobrg_writel(
127 rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
128
129 spin_unlock_irq(&rtcdrv->lock);
130 } else {
131 /*
132 * if this function was called with enabled=0
133 * then it could mean that the application is
134 * trying to cancel an ongoing alarm
135 */
136 spin_lock_irq(&rtcdrv->lock);
137
138 rtc_status_reg = sirfsoc_rtc_iobrg_readl(
139 rtcdrv->rtc_base + RTC_STATUS);
140 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
141 /* clear the RTC status register's alarm bit */
142 rtc_status_reg &= ~0x07;
143 /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
144 rtc_status_reg |= (SIRFSOC_RTC_AL0);
145 /* Clear the Alarm enable bit */
146 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
147
148 sirfsoc_rtc_iobrg_writel(rtc_status_reg,
149 rtcdrv->rtc_base + RTC_STATUS);
150 }
151
152 spin_unlock_irq(&rtcdrv->lock);
153 }
154
155 return 0;
156 }
157
158 static int sirfsoc_rtc_read_time(struct device *dev,
159 struct rtc_time *tm)
160 {
161 unsigned long tmp_rtc = 0;
162 struct sirfsoc_rtc_drv *rtcdrv;
163 rtcdrv = dev_get_drvdata(dev);
164 /*
165 * This patch is taken from WinCE - Need to validate this for
166 * correctness. To work around sirfsoc RTC counter double sync logic
167 * fail, read several times to make sure get stable value.
168 */
169 do {
170 tmp_rtc = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
171 cpu_relax();
172 } while (tmp_rtc != sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN));
173
174 rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
175 tmp_rtc >> RTC_SHIFT, tm);
176 return 0;
177 }
178
179 static int sirfsoc_rtc_set_time(struct device *dev,
180 struct rtc_time *tm)
181 {
182 unsigned long rtc_time;
183 struct sirfsoc_rtc_drv *rtcdrv;
184 rtcdrv = dev_get_drvdata(dev);
185
186 rtc_tm_to_time(tm, &rtc_time);
187
188 rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
189
190 sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
191 rtcdrv->rtc_base + RTC_SW_VALUE);
192 sirfsoc_rtc_iobrg_writel(
193 rtc_time << RTC_SHIFT, rtcdrv->rtc_base + RTC_CN);
194
195 return 0;
196 }
197
198 static int sirfsoc_rtc_ioctl(struct device *dev, unsigned int cmd,
199 unsigned long arg)
200 {
201 switch (cmd) {
202 case RTC_PIE_ON:
203 case RTC_PIE_OFF:
204 case RTC_UIE_ON:
205 case RTC_UIE_OFF:
206 case RTC_AIE_ON:
207 case RTC_AIE_OFF:
208 return 0;
209
210 default:
211 return -ENOIOCTLCMD;
212 }
213 }
214
215 static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
216 unsigned int enabled)
217 {
218 unsigned long rtc_status_reg = 0x0;
219 struct sirfsoc_rtc_drv *rtcdrv;
220
221 rtcdrv = dev_get_drvdata(dev);
222
223 spin_lock_irq(&rtcdrv->lock);
224
225 rtc_status_reg = sirfsoc_rtc_iobrg_readl(
226 rtcdrv->rtc_base + RTC_STATUS);
227 if (enabled)
228 rtc_status_reg |= SIRFSOC_RTC_AL0E;
229 else
230 rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
231
232 sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
233
234 spin_unlock_irq(&rtcdrv->lock);
235
236 return 0;
237
238 }
239
240 static const struct rtc_class_ops sirfsoc_rtc_ops = {
241 .read_time = sirfsoc_rtc_read_time,
242 .set_time = sirfsoc_rtc_set_time,
243 .read_alarm = sirfsoc_rtc_read_alarm,
244 .set_alarm = sirfsoc_rtc_set_alarm,
245 .ioctl = sirfsoc_rtc_ioctl,
246 .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
247 };
248
249 static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
250 {
251 struct sirfsoc_rtc_drv *rtcdrv = pdata;
252 unsigned long rtc_status_reg = 0x0;
253 unsigned long events = 0x0;
254
255 spin_lock(&rtcdrv->lock);
256
257 rtc_status_reg = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_STATUS);
258 /* this bit will be set ONLY if an alarm was active
259 * and it expired NOW
260 * So this is being used as an ASSERT
261 */
262 if (rtc_status_reg & SIRFSOC_RTC_AL0) {
263 /*
264 * clear the RTC status register's alarm bit
265 * mask out the lower status bits
266 */
267 rtc_status_reg &= ~0x07;
268 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
269 rtc_status_reg |= (SIRFSOC_RTC_AL0);
270 /* Clear the Alarm enable bit */
271 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
272 }
273 sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
274
275 spin_unlock(&rtcdrv->lock);
276
277 /* this should wake up any apps polling/waiting on the read
278 * after setting the alarm
279 */
280 events |= RTC_IRQF | RTC_AF;
281 rtc_update_irq(rtcdrv->rtc, 1, events);
282
283 return IRQ_HANDLED;
284 }
285
286 static const struct of_device_id sirfsoc_rtc_of_match[] = {
287 { .compatible = "sirf,prima2-sysrtc"},
288 {},
289 };
290 MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
291
292 static int sirfsoc_rtc_probe(struct platform_device *pdev)
293 {
294 int err;
295 unsigned long rtc_div;
296 struct sirfsoc_rtc_drv *rtcdrv;
297 struct device_node *np = pdev->dev.of_node;
298
299 rtcdrv = devm_kzalloc(&pdev->dev,
300 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
301 if (rtcdrv == NULL)
302 return -ENOMEM;
303
304 spin_lock_init(&rtcdrv->lock);
305
306 err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
307 if (err) {
308 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
309 return err;
310 }
311
312 platform_set_drvdata(pdev, rtcdrv);
313
314 /* Register rtc alarm as a wakeup source */
315 device_init_wakeup(&pdev->dev, 1);
316
317 /*
318 * Set SYS_RTC counter in RTC_HZ HZ Units
319 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
320 * If 16HZ, therefore RTC_DIV = 1023;
321 */
322 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
323 sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
324
325 /* 0x3 -> RTC_CLK */
326 sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
327 rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
328
329 /* reset SYS RTC ALARM0 */
330 sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
331
332 /* reset SYS RTC ALARM1 */
333 sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
334
335 /* Restore RTC Overflow From Register After Command Reboot */
336 rtcdrv->overflow_rtc =
337 sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
338
339 rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
340 &sirfsoc_rtc_ops, THIS_MODULE);
341 if (IS_ERR(rtcdrv->rtc)) {
342 err = PTR_ERR(rtcdrv->rtc);
343 dev_err(&pdev->dev, "can't register RTC device\n");
344 return err;
345 }
346
347 rtcdrv->irq = platform_get_irq(pdev, 0);
348 err = devm_request_irq(
349 &pdev->dev,
350 rtcdrv->irq,
351 sirfsoc_rtc_irq_handler,
352 IRQF_SHARED,
353 pdev->name,
354 rtcdrv);
355 if (err) {
356 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
357 return err;
358 }
359
360 return 0;
361 }
362
363 static int sirfsoc_rtc_remove(struct platform_device *pdev)
364 {
365 device_init_wakeup(&pdev->dev, 0);
366
367 return 0;
368 }
369
370 #ifdef CONFIG_PM_SLEEP
371 static int sirfsoc_rtc_suspend(struct device *dev)
372 {
373 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
374 rtcdrv->overflow_rtc =
375 sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
376
377 rtcdrv->saved_counter =
378 sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
379 rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
380 if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
381 rtcdrv->irq_wake = 1;
382
383 return 0;
384 }
385
386 static int sirfsoc_rtc_resume(struct device *dev)
387 {
388 u32 tmp;
389 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
390
391 /*
392 * if resume from snapshot and the rtc power is lost,
393 * restroe the rtc settings
394 */
395 if (SIRFSOC_RTC_CLK != sirfsoc_rtc_iobrg_readl(
396 rtcdrv->rtc_base + RTC_CLOCK_SWITCH)) {
397 u32 rtc_div;
398 /* 0x3 -> RTC_CLK */
399 sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
400 rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
401 /*
402 * Set SYS_RTC counter in RTC_HZ HZ Units
403 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
404 * If 16HZ, therefore RTC_DIV = 1023;
405 */
406 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
407
408 sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
409
410 /* reset SYS RTC ALARM0 */
411 sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
412
413 /* reset SYS RTC ALARM1 */
414 sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
415 }
416 rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
417
418 /*
419 * if current counter is small than previous,
420 * it means overflow in sleep
421 */
422 tmp = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
423 if (tmp <= rtcdrv->saved_counter)
424 rtcdrv->overflow_rtc++;
425 /*
426 *PWRC Value Be Changed When Suspend, Restore Overflow
427 * In Memory To Register
428 */
429 sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
430 rtcdrv->rtc_base + RTC_SW_VALUE);
431
432 if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
433 disable_irq_wake(rtcdrv->irq);
434 rtcdrv->irq_wake = 0;
435 }
436
437 return 0;
438 }
439 #endif
440
441 static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
442 sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
443
444 static struct platform_driver sirfsoc_rtc_driver = {
445 .driver = {
446 .name = "sirfsoc-rtc",
447 .pm = &sirfsoc_rtc_pm_ops,
448 .of_match_table = sirfsoc_rtc_of_match,
449 },
450 .probe = sirfsoc_rtc_probe,
451 .remove = sirfsoc_rtc_remove,
452 };
453 module_platform_driver(sirfsoc_rtc_driver);
454
455 MODULE_DESCRIPTION("SiRF SoC rtc driver");
456 MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
457 MODULE_LICENSE("GPL v2");
458 MODULE_ALIAS("platform:sirfsoc-rtc");
Linux with added FPC-III support