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Linux 4.1.16
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blob1e0d9b8c48c9391b666d041c0338398836d64e1f
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/io.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
49 #include <linux/of.h>
50
51 #include <asm/irq.h>
52
53 #include "samsung.h"
54
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 defined(CONFIG_DEBUG_LL) && \
57 !defined(MODULE)
58
59 extern void printascii(const char *);
60
61 __printf(1, 2)
62 static void dbg(const char *fmt, ...)
63 {
64 va_list va;
65 char buff[256];
66
67 va_start(va, fmt);
68 vscnprintf(buff, sizeof(buff), fmt, va);
69 va_end(va);
70
71 printascii(buff);
72 }
73
74 #else
75 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
76 #endif
77
78 /* UART name and device definitions */
79
80 #define S3C24XX_SERIAL_NAME "ttySAC"
81 #define S3C24XX_SERIAL_MAJOR 204
82 #define S3C24XX_SERIAL_MINOR 64
83
84 #define S3C24XX_TX_PIO 1
85 #define S3C24XX_TX_DMA 2
86 #define S3C24XX_RX_PIO 1
87 #define S3C24XX_RX_DMA 2
88 /* macros to change one thing to another */
89
90 #define tx_enabled(port) ((port)->unused[0])
91 #define rx_enabled(port) ((port)->unused[1])
92
93 /* flag to ignore all characters coming in */
94 #define RXSTAT_DUMMY_READ (0x10000000)
95
96 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
97 {
98 return container_of(port, struct s3c24xx_uart_port, port);
99 }
100
101 /* translate a port to the device name */
102
103 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
104 {
105 return to_platform_device(port->dev)->name;
106 }
107
108 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
109 {
110 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
111 }
112
113 /*
114 * s3c64xx and later SoC's include the interrupt mask and status registers in
115 * the controller itself, unlike the s3c24xx SoC's which have these registers
116 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 */
118 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
119 {
120 return to_ourport(port)->info->type == PORT_S3C6400;
121 }
122
123 static void s3c24xx_serial_rx_enable(struct uart_port *port)
124 {
125 unsigned long flags;
126 unsigned int ucon, ufcon;
127 int count = 10000;
128
129 spin_lock_irqsave(&port->lock, flags);
130
131 while (--count && !s3c24xx_serial_txempty_nofifo(port))
132 udelay(100);
133
134 ufcon = rd_regl(port, S3C2410_UFCON);
135 ufcon |= S3C2410_UFCON_RESETRX;
136 wr_regl(port, S3C2410_UFCON, ufcon);
137
138 ucon = rd_regl(port, S3C2410_UCON);
139 ucon |= S3C2410_UCON_RXIRQMODE;
140 wr_regl(port, S3C2410_UCON, ucon);
141
142 rx_enabled(port) = 1;
143 spin_unlock_irqrestore(&port->lock, flags);
144 }
145
146 static void s3c24xx_serial_rx_disable(struct uart_port *port)
147 {
148 unsigned long flags;
149 unsigned int ucon;
150
151 spin_lock_irqsave(&port->lock, flags);
152
153 ucon = rd_regl(port, S3C2410_UCON);
154 ucon &= ~S3C2410_UCON_RXIRQMODE;
155 wr_regl(port, S3C2410_UCON, ucon);
156
157 rx_enabled(port) = 0;
158 spin_unlock_irqrestore(&port->lock, flags);
159 }
160
161 static void s3c24xx_serial_stop_tx(struct uart_port *port)
162 {
163 struct s3c24xx_uart_port *ourport = to_ourport(port);
164 struct s3c24xx_uart_dma *dma = ourport->dma;
165 struct circ_buf *xmit = &port->state->xmit;
166 struct dma_tx_state state;
167 int count;
168
169 if (!tx_enabled(port))
170 return;
171
172 if (s3c24xx_serial_has_interrupt_mask(port))
173 __set_bit(S3C64XX_UINTM_TXD,
174 portaddrl(port, S3C64XX_UINTM));
175 else
176 disable_irq_nosync(ourport->tx_irq);
177
178 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
179 dmaengine_pause(dma->tx_chan);
180 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
181 dmaengine_terminate_all(dma->tx_chan);
182 dma_sync_single_for_cpu(ourport->port.dev,
183 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
184 async_tx_ack(dma->tx_desc);
185 count = dma->tx_bytes_requested - state.residue;
186 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
187 port->icount.tx += count;
188 }
189
190 tx_enabled(port) = 0;
191 ourport->tx_in_progress = 0;
192
193 if (port->flags & UPF_CONS_FLOW)
194 s3c24xx_serial_rx_enable(port);
195
196 ourport->tx_mode = 0;
197 }
198
199 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
200
201 static void s3c24xx_serial_tx_dma_complete(void *args)
202 {
203 struct s3c24xx_uart_port *ourport = args;
204 struct uart_port *port = &ourport->port;
205 struct circ_buf *xmit = &port->state->xmit;
206 struct s3c24xx_uart_dma *dma = ourport->dma;
207 struct dma_tx_state state;
208 unsigned long flags;
209 int count;
210
211
212 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
213 count = dma->tx_bytes_requested - state.residue;
214 async_tx_ack(dma->tx_desc);
215
216 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
217 dma->tx_size, DMA_TO_DEVICE);
218
219 spin_lock_irqsave(&port->lock, flags);
220
221 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
222 port->icount.tx += count;
223 ourport->tx_in_progress = 0;
224
225 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
227
228 s3c24xx_serial_start_next_tx(ourport);
229 spin_unlock_irqrestore(&port->lock, flags);
230 }
231
232 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
233 {
234 struct uart_port *port = &ourport->port;
235 u32 ucon;
236
237 /* Mask Tx interrupt */
238 if (s3c24xx_serial_has_interrupt_mask(port))
239 __set_bit(S3C64XX_UINTM_TXD,
240 portaddrl(port, S3C64XX_UINTM));
241 else
242 disable_irq_nosync(ourport->tx_irq);
243
244 /* Enable tx dma mode */
245 ucon = rd_regl(port, S3C2410_UCON);
246 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
247 ucon |= (dma_get_cache_alignment() >= 16) ?
248 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
249 ucon |= S3C64XX_UCON_TXMODE_DMA;
250 wr_regl(port, S3C2410_UCON, ucon);
251
252 ourport->tx_mode = S3C24XX_TX_DMA;
253 }
254
255 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
256 {
257 struct uart_port *port = &ourport->port;
258 u32 ucon, ufcon;
259
260 /* Set ufcon txtrig */
261 ourport->tx_in_progress = S3C24XX_TX_PIO;
262 ufcon = rd_regl(port, S3C2410_UFCON);
263 wr_regl(port, S3C2410_UFCON, ufcon);
264
265 /* Enable tx pio mode */
266 ucon = rd_regl(port, S3C2410_UCON);
267 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
268 ucon |= S3C64XX_UCON_TXMODE_CPU;
269 wr_regl(port, S3C2410_UCON, ucon);
270
271 /* Unmask Tx interrupt */
272 if (s3c24xx_serial_has_interrupt_mask(port))
273 __clear_bit(S3C64XX_UINTM_TXD,
274 portaddrl(port, S3C64XX_UINTM));
275 else
276 enable_irq(ourport->tx_irq);
277
278 ourport->tx_mode = S3C24XX_TX_PIO;
279 }
280
281 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
282 {
283 if (ourport->tx_mode != S3C24XX_TX_PIO)
284 enable_tx_pio(ourport);
285 }
286
287 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
288 unsigned int count)
289 {
290 struct uart_port *port = &ourport->port;
291 struct circ_buf *xmit = &port->state->xmit;
292 struct s3c24xx_uart_dma *dma = ourport->dma;
293
294
295 if (ourport->tx_mode != S3C24XX_TX_DMA)
296 enable_tx_dma(ourport);
297
298 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
299 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
300
301 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
302 dma->tx_size, DMA_TO_DEVICE);
303
304 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
305 dma->tx_transfer_addr, dma->tx_size,
306 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
307 if (!dma->tx_desc) {
308 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
309 return -EIO;
310 }
311
312 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
313 dma->tx_desc->callback_param = ourport;
314 dma->tx_bytes_requested = dma->tx_size;
315
316 ourport->tx_in_progress = S3C24XX_TX_DMA;
317 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
318 dma_async_issue_pending(dma->tx_chan);
319 return 0;
320 }
321
322 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
323 {
324 struct uart_port *port = &ourport->port;
325 struct circ_buf *xmit = &port->state->xmit;
326 unsigned long count;
327
328 /* Get data size up to the end of buffer */
329 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
330
331 if (!count) {
332 s3c24xx_serial_stop_tx(port);
333 return;
334 }
335
336 if (!ourport->dma || !ourport->dma->tx_chan ||
337 count < ourport->min_dma_size ||
338 xmit->tail & (dma_get_cache_alignment() - 1))
339 s3c24xx_serial_start_tx_pio(ourport);
340 else
341 s3c24xx_serial_start_tx_dma(ourport, count);
342 }
343
344 void s3c24xx_serial_start_tx(struct uart_port *port)
345 {
346 struct s3c24xx_uart_port *ourport = to_ourport(port);
347 struct circ_buf *xmit = &port->state->xmit;
348
349 if (!tx_enabled(port)) {
350 if (port->flags & UPF_CONS_FLOW)
351 s3c24xx_serial_rx_disable(port);
352
353 tx_enabled(port) = 1;
354 if (!ourport->dma || !ourport->dma->tx_chan)
355 s3c24xx_serial_start_tx_pio(ourport);
356 }
357
358 if (ourport->dma && ourport->dma->tx_chan) {
359 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
360 s3c24xx_serial_start_next_tx(ourport);
361 }
362 }
363
364 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
365 struct tty_port *tty, int count)
366 {
367 struct s3c24xx_uart_dma *dma = ourport->dma;
368 int copied;
369
370 if (!count)
371 return;
372
373 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
374 dma->rx_size, DMA_FROM_DEVICE);
375
376 ourport->port.icount.rx += count;
377 if (!tty) {
378 dev_err(ourport->port.dev, "No tty port\n");
379 return;
380 }
381 copied = tty_insert_flip_string(tty,
382 ((unsigned char *)(ourport->dma->rx_buf)), count);
383 if (copied != count) {
384 WARN_ON(1);
385 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
386 }
387 }
388
389 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
390 unsigned long ufstat);
391
392 static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
393 {
394 struct uart_port *port = &ourport->port;
395 struct tty_port *tty = &port->state->port;
396 unsigned int ch, ufstat;
397 unsigned int count;
398
399 ufstat = rd_regl(port, S3C2410_UFSTAT);
400 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
401
402 if (!count)
403 return;
404
405 while (count-- > 0) {
406 ch = rd_regb(port, S3C2410_URXH);
407
408 ourport->port.icount.rx++;
409 tty_insert_flip_char(tty, ch, TTY_NORMAL);
410 }
411
412 tty_flip_buffer_push(tty);
413 }
414
415 static void s3c24xx_serial_stop_rx(struct uart_port *port)
416 {
417 struct s3c24xx_uart_port *ourport = to_ourport(port);
418 struct s3c24xx_uart_dma *dma = ourport->dma;
419 struct tty_port *t = &port->state->port;
420 struct dma_tx_state state;
421 enum dma_status dma_status;
422 unsigned int received;
423
424 if (rx_enabled(port)) {
425 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
426 if (s3c24xx_serial_has_interrupt_mask(port))
427 __set_bit(S3C64XX_UINTM_RXD,
428 portaddrl(port, S3C64XX_UINTM));
429 else
430 disable_irq_nosync(ourport->rx_irq);
431 rx_enabled(port) = 0;
432 }
433 if (dma && dma->rx_chan) {
434 dmaengine_pause(dma->tx_chan);
435 dma_status = dmaengine_tx_status(dma->rx_chan,
436 dma->rx_cookie, &state);
437 if (dma_status == DMA_IN_PROGRESS ||
438 dma_status == DMA_PAUSED) {
439 received = dma->rx_bytes_requested - state.residue;
440 dmaengine_terminate_all(dma->rx_chan);
441 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
442 }
443 }
444 }
445
446 static inline struct s3c24xx_uart_info
447 *s3c24xx_port_to_info(struct uart_port *port)
448 {
449 return to_ourport(port)->info;
450 }
451
452 static inline struct s3c2410_uartcfg
453 *s3c24xx_port_to_cfg(struct uart_port *port)
454 {
455 struct s3c24xx_uart_port *ourport;
456
457 if (port->dev == NULL)
458 return NULL;
459
460 ourport = container_of(port, struct s3c24xx_uart_port, port);
461 return ourport->cfg;
462 }
463
464 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
465 unsigned long ufstat)
466 {
467 struct s3c24xx_uart_info *info = ourport->info;
468
469 if (ufstat & info->rx_fifofull)
470 return ourport->port.fifosize;
471
472 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
473 }
474
475 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
476 static void s3c24xx_serial_rx_dma_complete(void *args)
477 {
478 struct s3c24xx_uart_port *ourport = args;
479 struct uart_port *port = &ourport->port;
480
481 struct s3c24xx_uart_dma *dma = ourport->dma;
482 struct tty_port *t = &port->state->port;
483 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
484
485 struct dma_tx_state state;
486 unsigned long flags;
487 int received;
488
489 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
490 received = dma->rx_bytes_requested - state.residue;
491 async_tx_ack(dma->rx_desc);
492
493 spin_lock_irqsave(&port->lock, flags);
494
495 if (received)
496 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
497
498 if (tty) {
499 tty_flip_buffer_push(t);
500 tty_kref_put(tty);
501 }
502
503 s3c64xx_start_rx_dma(ourport);
504
505 spin_unlock_irqrestore(&port->lock, flags);
506 }
507
508 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
509 {
510 struct s3c24xx_uart_dma *dma = ourport->dma;
511
512 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
513 dma->rx_size, DMA_FROM_DEVICE);
514
515 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
516 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
517 DMA_PREP_INTERRUPT);
518 if (!dma->rx_desc) {
519 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
520 return;
521 }
522
523 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
524 dma->rx_desc->callback_param = ourport;
525 dma->rx_bytes_requested = dma->rx_size;
526
527 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
528 dma_async_issue_pending(dma->rx_chan);
529 }
530
531 /* ? - where has parity gone?? */
532 #define S3C2410_UERSTAT_PARITY (0x1000)
533
534 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
535 {
536 struct uart_port *port = &ourport->port;
537 unsigned int ucon;
538
539 /* set Rx mode to DMA mode */
540 ucon = rd_regl(port, S3C2410_UCON);
541 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
542 S3C64XX_UCON_TIMEOUT_MASK |
543 S3C64XX_UCON_EMPTYINT_EN |
544 S3C64XX_UCON_DMASUS_EN |
545 S3C64XX_UCON_TIMEOUT_EN |
546 S3C64XX_UCON_RXMODE_MASK);
547 ucon |= S3C64XX_UCON_RXBURST_16 |
548 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
549 S3C64XX_UCON_EMPTYINT_EN |
550 S3C64XX_UCON_TIMEOUT_EN |
551 S3C64XX_UCON_RXMODE_DMA;
552 wr_regl(port, S3C2410_UCON, ucon);
553
554 ourport->rx_mode = S3C24XX_RX_DMA;
555 }
556
557 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
558 {
559 struct uart_port *port = &ourport->port;
560 unsigned int ucon;
561
562 /* set Rx mode to DMA mode */
563 ucon = rd_regl(port, S3C2410_UCON);
564 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
565 S3C64XX_UCON_EMPTYINT_EN |
566 S3C64XX_UCON_DMASUS_EN |
567 S3C64XX_UCON_TIMEOUT_EN |
568 S3C64XX_UCON_RXMODE_MASK);
569 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
570 S3C64XX_UCON_TIMEOUT_EN |
571 S3C64XX_UCON_RXMODE_CPU;
572 wr_regl(port, S3C2410_UCON, ucon);
573
574 ourport->rx_mode = S3C24XX_RX_PIO;
575 }
576
577 static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
578 {
579 unsigned int utrstat, ufstat, received;
580 struct s3c24xx_uart_port *ourport = dev_id;
581 struct uart_port *port = &ourport->port;
582 struct s3c24xx_uart_dma *dma = ourport->dma;
583 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
584 struct tty_port *t = &port->state->port;
585 unsigned long flags;
586 struct dma_tx_state state;
587
588 utrstat = rd_regl(port, S3C2410_UTRSTAT);
589 ufstat = rd_regl(port, S3C2410_UFSTAT);
590
591 spin_lock_irqsave(&port->lock, flags);
592
593 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
594 s3c64xx_start_rx_dma(ourport);
595 if (ourport->rx_mode == S3C24XX_RX_PIO)
596 enable_rx_dma(ourport);
597 goto finish;
598 }
599
600 if (ourport->rx_mode == S3C24XX_RX_DMA) {
601 dmaengine_pause(dma->rx_chan);
602 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
603 dmaengine_terminate_all(dma->rx_chan);
604 received = dma->rx_bytes_requested - state.residue;
605 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
606
607 enable_rx_pio(ourport);
608 }
609
610 uart_rx_drain_fifo(ourport);
611
612 if (tty) {
613 tty_flip_buffer_push(t);
614 tty_kref_put(tty);
615 }
616
617 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
618
619 finish:
620 spin_unlock_irqrestore(&port->lock, flags);
621
622 return IRQ_HANDLED;
623 }
624
625 static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
626 {
627 struct s3c24xx_uart_port *ourport = dev_id;
628 struct uart_port *port = &ourport->port;
629 unsigned int ufcon, ch, flag, ufstat, uerstat;
630 unsigned long flags;
631 int max_count = port->fifosize;
632
633 spin_lock_irqsave(&port->lock, flags);
634
635 while (max_count-- > 0) {
636 ufcon = rd_regl(port, S3C2410_UFCON);
637 ufstat = rd_regl(port, S3C2410_UFSTAT);
638
639 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
640 break;
641
642 uerstat = rd_regl(port, S3C2410_UERSTAT);
643 ch = rd_regb(port, S3C2410_URXH);
644
645 if (port->flags & UPF_CONS_FLOW) {
646 int txe = s3c24xx_serial_txempty_nofifo(port);
647
648 if (rx_enabled(port)) {
649 if (!txe) {
650 rx_enabled(port) = 0;
651 continue;
652 }
653 } else {
654 if (txe) {
655 ufcon |= S3C2410_UFCON_RESETRX;
656 wr_regl(port, S3C2410_UFCON, ufcon);
657 rx_enabled(port) = 1;
658 spin_unlock_irqrestore(&port->lock,
659 flags);
660 goto out;
661 }
662 continue;
663 }
664 }
665
666 /* insert the character into the buffer */
667
668 flag = TTY_NORMAL;
669 port->icount.rx++;
670
671 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
672 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
673 ch, uerstat);
674
675 /* check for break */
676 if (uerstat & S3C2410_UERSTAT_BREAK) {
677 dbg("break!\n");
678 port->icount.brk++;
679 if (uart_handle_break(port))
680 goto ignore_char;
681 }
682
683 if (uerstat & S3C2410_UERSTAT_FRAME)
684 port->icount.frame++;
685 if (uerstat & S3C2410_UERSTAT_OVERRUN)
686 port->icount.overrun++;
687
688 uerstat &= port->read_status_mask;
689
690 if (uerstat & S3C2410_UERSTAT_BREAK)
691 flag = TTY_BREAK;
692 else if (uerstat & S3C2410_UERSTAT_PARITY)
693 flag = TTY_PARITY;
694 else if (uerstat & (S3C2410_UERSTAT_FRAME |
695 S3C2410_UERSTAT_OVERRUN))
696 flag = TTY_FRAME;
697 }
698
699 if (uart_handle_sysrq_char(port, ch))
700 goto ignore_char;
701
702 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
703 ch, flag);
704
705 ignore_char:
706 continue;
707 }
708
709 spin_unlock_irqrestore(&port->lock, flags);
710 tty_flip_buffer_push(&port->state->port);
711
712 out:
713 return IRQ_HANDLED;
714 }
715
716
717 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
718 {
719 struct s3c24xx_uart_port *ourport = dev_id;
720
721 if (ourport->dma && ourport->dma->rx_chan)
722 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
723 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
724 }
725
726 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
727 {
728 struct s3c24xx_uart_port *ourport = id;
729 struct uart_port *port = &ourport->port;
730 struct circ_buf *xmit = &port->state->xmit;
731 unsigned long flags;
732 int count, dma_count = 0;
733
734 spin_lock_irqsave(&port->lock, flags);
735
736 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
737
738 if (ourport->dma && ourport->dma->tx_chan &&
739 count >= ourport->min_dma_size) {
740 int align = dma_get_cache_alignment() -
741 (xmit->tail & (dma_get_cache_alignment() - 1));
742 if (count-align >= ourport->min_dma_size) {
743 dma_count = count-align;
744 count = align;
745 }
746 }
747
748 if (port->x_char) {
749 wr_regb(port, S3C2410_UTXH, port->x_char);
750 port->icount.tx++;
751 port->x_char = 0;
752 goto out;
753 }
754
755 /* if there isn't anything more to transmit, or the uart is now
756 * stopped, disable the uart and exit
757 */
758
759 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
760 s3c24xx_serial_stop_tx(port);
761 goto out;
762 }
763
764 /* try and drain the buffer... */
765
766 if (count > port->fifosize) {
767 count = port->fifosize;
768 dma_count = 0;
769 }
770
771 while (!uart_circ_empty(xmit) && count > 0) {
772 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
773 break;
774
775 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
776 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
777 port->icount.tx++;
778 count--;
779 }
780
781 if (!count && dma_count) {
782 s3c24xx_serial_start_tx_dma(ourport, dma_count);
783 goto out;
784 }
785
786 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
787 spin_unlock(&port->lock);
788 uart_write_wakeup(port);
789 spin_lock(&port->lock);
790 }
791
792 if (uart_circ_empty(xmit))
793 s3c24xx_serial_stop_tx(port);
794
795 out:
796 spin_unlock_irqrestore(&port->lock, flags);
797 return IRQ_HANDLED;
798 }
799
800 /* interrupt handler for s3c64xx and later SoC's.*/
801 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
802 {
803 struct s3c24xx_uart_port *ourport = id;
804 struct uart_port *port = &ourport->port;
805 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
806 irqreturn_t ret = IRQ_HANDLED;
807
808 if (pend & S3C64XX_UINTM_RXD_MSK) {
809 ret = s3c24xx_serial_rx_chars(irq, id);
810 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
811 }
812 if (pend & S3C64XX_UINTM_TXD_MSK) {
813 ret = s3c24xx_serial_tx_chars(irq, id);
814 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
815 }
816 return ret;
817 }
818
819 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
820 {
821 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
822 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
823 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
824
825 if (ufcon & S3C2410_UFCON_FIFOMODE) {
826 if ((ufstat & info->tx_fifomask) != 0 ||
827 (ufstat & info->tx_fifofull))
828 return 0;
829
830 return 1;
831 }
832
833 return s3c24xx_serial_txempty_nofifo(port);
834 }
835
836 /* no modem control lines */
837 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
838 {
839 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
840
841 if (umstat & S3C2410_UMSTAT_CTS)
842 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
843 else
844 return TIOCM_CAR | TIOCM_DSR;
845 }
846
847 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
848 {
849 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
850
851 if (mctrl & TIOCM_RTS)
852 umcon |= S3C2410_UMCOM_RTS_LOW;
853 else
854 umcon &= ~S3C2410_UMCOM_RTS_LOW;
855
856 wr_regl(port, S3C2410_UMCON, umcon);
857 }
858
859 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
860 {
861 unsigned long flags;
862 unsigned int ucon;
863
864 spin_lock_irqsave(&port->lock, flags);
865
866 ucon = rd_regl(port, S3C2410_UCON);
867
868 if (break_state)
869 ucon |= S3C2410_UCON_SBREAK;
870 else
871 ucon &= ~S3C2410_UCON_SBREAK;
872
873 wr_regl(port, S3C2410_UCON, ucon);
874
875 spin_unlock_irqrestore(&port->lock, flags);
876 }
877
878 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
879 {
880 struct s3c24xx_uart_dma *dma = p->dma;
881 dma_cap_mask_t mask;
882 unsigned long flags;
883
884 /* Default slave configuration parameters */
885 dma->rx_conf.direction = DMA_DEV_TO_MEM;
886 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
887 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
888 dma->rx_conf.src_maxburst = 16;
889
890 dma->tx_conf.direction = DMA_MEM_TO_DEV;
891 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
892 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
893 if (dma_get_cache_alignment() >= 16)
894 dma->tx_conf.dst_maxburst = 16;
895 else
896 dma->tx_conf.dst_maxburst = 1;
897
898 dma_cap_zero(mask);
899 dma_cap_set(DMA_SLAVE, mask);
900
901 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
902 dma->rx_param, p->port.dev, "rx");
903 if (!dma->rx_chan)
904 return -ENODEV;
905
906 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
907
908 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
909 dma->tx_param, p->port.dev, "tx");
910 if (!dma->tx_chan) {
911 dma_release_channel(dma->rx_chan);
912 return -ENODEV;
913 }
914
915 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
916
917 /* RX buffer */
918 dma->rx_size = PAGE_SIZE;
919
920 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
921
922 if (!dma->rx_buf) {
923 dma_release_channel(dma->rx_chan);
924 dma_release_channel(dma->tx_chan);
925 return -ENOMEM;
926 }
927
928 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
929 dma->rx_size, DMA_FROM_DEVICE);
930
931 spin_lock_irqsave(&p->port.lock, flags);
932
933 /* TX buffer */
934 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
935 p->port.state->xmit.buf,
936 UART_XMIT_SIZE, DMA_TO_DEVICE);
937
938 spin_unlock_irqrestore(&p->port.lock, flags);
939
940 return 0;
941 }
942
943 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
944 {
945 struct s3c24xx_uart_dma *dma = p->dma;
946
947 if (dma->rx_chan) {
948 dmaengine_terminate_all(dma->rx_chan);
949 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
950 dma->rx_size, DMA_FROM_DEVICE);
951 kfree(dma->rx_buf);
952 dma_release_channel(dma->rx_chan);
953 dma->rx_chan = NULL;
954 }
955
956 if (dma->tx_chan) {
957 dmaengine_terminate_all(dma->tx_chan);
958 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
959 UART_XMIT_SIZE, DMA_TO_DEVICE);
960 dma_release_channel(dma->tx_chan);
961 dma->tx_chan = NULL;
962 }
963 }
964
965 static void s3c24xx_serial_shutdown(struct uart_port *port)
966 {
967 struct s3c24xx_uart_port *ourport = to_ourport(port);
968
969 if (ourport->tx_claimed) {
970 if (!s3c24xx_serial_has_interrupt_mask(port))
971 free_irq(ourport->tx_irq, ourport);
972 tx_enabled(port) = 0;
973 ourport->tx_claimed = 0;
974 ourport->tx_mode = 0;
975 }
976
977 if (ourport->rx_claimed) {
978 if (!s3c24xx_serial_has_interrupt_mask(port))
979 free_irq(ourport->rx_irq, ourport);
980 ourport->rx_claimed = 0;
981 rx_enabled(port) = 0;
982 }
983
984 /* Clear pending interrupts and mask all interrupts */
985 if (s3c24xx_serial_has_interrupt_mask(port)) {
986 free_irq(port->irq, ourport);
987
988 wr_regl(port, S3C64XX_UINTP, 0xf);
989 wr_regl(port, S3C64XX_UINTM, 0xf);
990 }
991
992 if (ourport->dma)
993 s3c24xx_serial_release_dma(ourport);
994
995 ourport->tx_in_progress = 0;
996 }
997
998 static int s3c24xx_serial_startup(struct uart_port *port)
999 {
1000 struct s3c24xx_uart_port *ourport = to_ourport(port);
1001 int ret;
1002
1003 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1004 port, (unsigned long long)port->mapbase, port->membase);
1005
1006 rx_enabled(port) = 1;
1007
1008 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1009 s3c24xx_serial_portname(port), ourport);
1010
1011 if (ret != 0) {
1012 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1013 return ret;
1014 }
1015
1016 ourport->rx_claimed = 1;
1017
1018 dbg("requesting tx irq...\n");
1019
1020 tx_enabled(port) = 1;
1021
1022 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1023 s3c24xx_serial_portname(port), ourport);
1024
1025 if (ret) {
1026 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1027 goto err;
1028 }
1029
1030 ourport->tx_claimed = 1;
1031
1032 dbg("s3c24xx_serial_startup ok\n");
1033
1034 /* the port reset code should have done the correct
1035 * register setup for the port controls */
1036
1037 return ret;
1038
1039 err:
1040 s3c24xx_serial_shutdown(port);
1041 return ret;
1042 }
1043
1044 static int s3c64xx_serial_startup(struct uart_port *port)
1045 {
1046 struct s3c24xx_uart_port *ourport = to_ourport(port);
1047 unsigned long flags;
1048 unsigned int ufcon;
1049 int ret;
1050
1051 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1052 port, (unsigned long long)port->mapbase, port->membase);
1053
1054 wr_regl(port, S3C64XX_UINTM, 0xf);
1055 if (ourport->dma) {
1056 ret = s3c24xx_serial_request_dma(ourport);
1057 if (ret < 0) {
1058 dev_warn(port->dev, "DMA request failed\n");
1059 return ret;
1060 }
1061 }
1062
1063 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1064 s3c24xx_serial_portname(port), ourport);
1065 if (ret) {
1066 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1067 return ret;
1068 }
1069
1070 /* For compatibility with s3c24xx Soc's */
1071 rx_enabled(port) = 1;
1072 ourport->rx_claimed = 1;
1073 tx_enabled(port) = 0;
1074 ourport->tx_claimed = 1;
1075
1076 spin_lock_irqsave(&port->lock, flags);
1077
1078 ufcon = rd_regl(port, S3C2410_UFCON);
1079 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1080 if (!uart_console(port))
1081 ufcon |= S3C2410_UFCON_RESETTX;
1082 wr_regl(port, S3C2410_UFCON, ufcon);
1083
1084 enable_rx_pio(ourport);
1085
1086 spin_unlock_irqrestore(&port->lock, flags);
1087
1088 /* Enable Rx Interrupt */
1089 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1090
1091 dbg("s3c64xx_serial_startup ok\n");
1092 return ret;
1093 }
1094
1095 /* power power management control */
1096
1097 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1098 unsigned int old)
1099 {
1100 struct s3c24xx_uart_port *ourport = to_ourport(port);
1101 int timeout = 10000;
1102
1103 ourport->pm_level = level;
1104
1105 switch (level) {
1106 case 3:
1107 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1108 udelay(100);
1109
1110 if (!IS_ERR(ourport->baudclk))
1111 clk_disable_unprepare(ourport->baudclk);
1112
1113 clk_disable_unprepare(ourport->clk);
1114 break;
1115
1116 case 0:
1117 clk_prepare_enable(ourport->clk);
1118
1119 if (!IS_ERR(ourport->baudclk))
1120 clk_prepare_enable(ourport->baudclk);
1121
1122 break;
1123 default:
1124 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1125 }
1126 }
1127
1128 /* baud rate calculation
1129 *
1130 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1131 * of different sources, including the peripheral clock ("pclk") and an
1132 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1133 * with a programmable extra divisor.
1134 *
1135 * The following code goes through the clock sources, and calculates the
1136 * baud clocks (and the resultant actual baud rates) and then tries to
1137 * pick the closest one and select that.
1138 *
1139 */
1140
1141 #define MAX_CLK_NAME_LENGTH 15
1142
1143 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1144 {
1145 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1146 unsigned int ucon;
1147
1148 if (info->num_clks == 1)
1149 return 0;
1150
1151 ucon = rd_regl(port, S3C2410_UCON);
1152 ucon &= info->clksel_mask;
1153 return ucon >> info->clksel_shift;
1154 }
1155
1156 static void s3c24xx_serial_setsource(struct uart_port *port,
1157 unsigned int clk_sel)
1158 {
1159 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1160 unsigned int ucon;
1161
1162 if (info->num_clks == 1)
1163 return;
1164
1165 ucon = rd_regl(port, S3C2410_UCON);
1166 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1167 return;
1168
1169 ucon &= ~info->clksel_mask;
1170 ucon |= clk_sel << info->clksel_shift;
1171 wr_regl(port, S3C2410_UCON, ucon);
1172 }
1173
1174 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1175 unsigned int req_baud, struct clk **best_clk,
1176 unsigned int *clk_num)
1177 {
1178 struct s3c24xx_uart_info *info = ourport->info;
1179 struct clk *clk;
1180 unsigned long rate;
1181 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1182 char clkname[MAX_CLK_NAME_LENGTH];
1183 int calc_deviation, deviation = (1 << 30) - 1;
1184
1185 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1186 ourport->info->def_clk_sel;
1187 for (cnt = 0; cnt < info->num_clks; cnt++) {
1188 if (!(clk_sel & (1 << cnt)))
1189 continue;
1190
1191 sprintf(clkname, "clk_uart_baud%d", cnt);
1192 clk = clk_get(ourport->port.dev, clkname);
1193 if (IS_ERR(clk))
1194 continue;
1195
1196 rate = clk_get_rate(clk);
1197 if (!rate)
1198 continue;
1199
1200 if (ourport->info->has_divslot) {
1201 unsigned long div = rate / req_baud;
1202
1203 /* The UDIVSLOT register on the newer UARTs allows us to
1204 * get a divisor adjustment of 1/16th on the baud clock.
1205 *
1206 * We don't keep the UDIVSLOT value (the 16ths we
1207 * calculated by not multiplying the baud by 16) as it
1208 * is easy enough to recalculate.
1209 */
1210
1211 quot = div / 16;
1212 baud = rate / div;
1213 } else {
1214 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1215 baud = rate / (quot * 16);
1216 }
1217 quot--;
1218
1219 calc_deviation = req_baud - baud;
1220 if (calc_deviation < 0)
1221 calc_deviation = -calc_deviation;
1222
1223 if (calc_deviation < deviation) {
1224 *best_clk = clk;
1225 best_quot = quot;
1226 *clk_num = cnt;
1227 deviation = calc_deviation;
1228 }
1229 }
1230
1231 return best_quot;
1232 }
1233
1234 /* udivslot_table[]
1235 *
1236 * This table takes the fractional value of the baud divisor and gives
1237 * the recommended setting for the UDIVSLOT register.
1238 */
1239 static u16 udivslot_table[16] = {
1240 [0] = 0x0000,
1241 [1] = 0x0080,
1242 [2] = 0x0808,
1243 [3] = 0x0888,
1244 [4] = 0x2222,
1245 [5] = 0x4924,
1246 [6] = 0x4A52,
1247 [7] = 0x54AA,
1248 [8] = 0x5555,
1249 [9] = 0xD555,
1250 [10] = 0xD5D5,
1251 [11] = 0xDDD5,
1252 [12] = 0xDDDD,
1253 [13] = 0xDFDD,
1254 [14] = 0xDFDF,
1255 [15] = 0xFFDF,
1256 };
1257
1258 static void s3c24xx_serial_set_termios(struct uart_port *port,
1259 struct ktermios *termios,
1260 struct ktermios *old)
1261 {
1262 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1263 struct s3c24xx_uart_port *ourport = to_ourport(port);
1264 struct clk *clk = ERR_PTR(-EINVAL);
1265 unsigned long flags;
1266 unsigned int baud, quot, clk_sel = 0;
1267 unsigned int ulcon;
1268 unsigned int umcon;
1269 unsigned int udivslot = 0;
1270
1271 /*
1272 * We don't support modem control lines.
1273 */
1274 termios->c_cflag &= ~(HUPCL | CMSPAR);
1275 termios->c_cflag |= CLOCAL;
1276
1277 /*
1278 * Ask the core to calculate the divisor for us.
1279 */
1280
1281 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1282 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1283 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1284 quot = port->custom_divisor;
1285 if (IS_ERR(clk))
1286 return;
1287
1288 /* check to see if we need to change clock source */
1289
1290 if (ourport->baudclk != clk) {
1291 s3c24xx_serial_setsource(port, clk_sel);
1292
1293 if (!IS_ERR(ourport->baudclk)) {
1294 clk_disable_unprepare(ourport->baudclk);
1295 ourport->baudclk = ERR_PTR(-EINVAL);
1296 }
1297
1298 clk_prepare_enable(clk);
1299
1300 ourport->baudclk = clk;
1301 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1302 }
1303
1304 if (ourport->info->has_divslot) {
1305 unsigned int div = ourport->baudclk_rate / baud;
1306
1307 if (cfg->has_fracval) {
1308 udivslot = (div & 15);
1309 dbg("fracval = %04x\n", udivslot);
1310 } else {
1311 udivslot = udivslot_table[div & 15];
1312 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1313 }
1314 }
1315
1316 switch (termios->c_cflag & CSIZE) {
1317 case CS5:
1318 dbg("config: 5bits/char\n");
1319 ulcon = S3C2410_LCON_CS5;
1320 break;
1321 case CS6:
1322 dbg("config: 6bits/char\n");
1323 ulcon = S3C2410_LCON_CS6;
1324 break;
1325 case CS7:
1326 dbg("config: 7bits/char\n");
1327 ulcon = S3C2410_LCON_CS7;
1328 break;
1329 case CS8:
1330 default:
1331 dbg("config: 8bits/char\n");
1332 ulcon = S3C2410_LCON_CS8;
1333 break;
1334 }
1335
1336 /* preserve original lcon IR settings */
1337 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1338
1339 if (termios->c_cflag & CSTOPB)
1340 ulcon |= S3C2410_LCON_STOPB;
1341
1342 if (termios->c_cflag & PARENB) {
1343 if (termios->c_cflag & PARODD)
1344 ulcon |= S3C2410_LCON_PODD;
1345 else
1346 ulcon |= S3C2410_LCON_PEVEN;
1347 } else {
1348 ulcon |= S3C2410_LCON_PNONE;
1349 }
1350
1351 spin_lock_irqsave(&port->lock, flags);
1352
1353 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1354 ulcon, quot, udivslot);
1355
1356 wr_regl(port, S3C2410_ULCON, ulcon);
1357 wr_regl(port, S3C2410_UBRDIV, quot);
1358
1359 umcon = rd_regl(port, S3C2410_UMCON);
1360 if (termios->c_cflag & CRTSCTS) {
1361 umcon |= S3C2410_UMCOM_AFC;
1362 /* Disable RTS when RX FIFO contains 63 bytes */
1363 umcon &= ~S3C2412_UMCON_AFC_8;
1364 } else {
1365 umcon &= ~S3C2410_UMCOM_AFC;
1366 }
1367 wr_regl(port, S3C2410_UMCON, umcon);
1368
1369 if (ourport->info->has_divslot)
1370 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1371
1372 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1373 rd_regl(port, S3C2410_ULCON),
1374 rd_regl(port, S3C2410_UCON),
1375 rd_regl(port, S3C2410_UFCON));
1376
1377 /*
1378 * Update the per-port timeout.
1379 */
1380 uart_update_timeout(port, termios->c_cflag, baud);
1381
1382 /*
1383 * Which character status flags are we interested in?
1384 */
1385 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1386 if (termios->c_iflag & INPCK)
1387 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1388 S3C2410_UERSTAT_PARITY;
1389 /*
1390 * Which character status flags should we ignore?
1391 */
1392 port->ignore_status_mask = 0;
1393 if (termios->c_iflag & IGNPAR)
1394 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1395 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1396 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1397
1398 /*
1399 * Ignore all characters if CREAD is not set.
1400 */
1401 if ((termios->c_cflag & CREAD) == 0)
1402 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1403
1404 spin_unlock_irqrestore(&port->lock, flags);
1405 }
1406
1407 static const char *s3c24xx_serial_type(struct uart_port *port)
1408 {
1409 switch (port->type) {
1410 case PORT_S3C2410:
1411 return "S3C2410";
1412 case PORT_S3C2440:
1413 return "S3C2440";
1414 case PORT_S3C2412:
1415 return "S3C2412";
1416 case PORT_S3C6400:
1417 return "S3C6400/10";
1418 default:
1419 return NULL;
1420 }
1421 }
1422
1423 #define MAP_SIZE (0x100)
1424
1425 static void s3c24xx_serial_release_port(struct uart_port *port)
1426 {
1427 release_mem_region(port->mapbase, MAP_SIZE);
1428 }
1429
1430 static int s3c24xx_serial_request_port(struct uart_port *port)
1431 {
1432 const char *name = s3c24xx_serial_portname(port);
1433 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1434 }
1435
1436 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1437 {
1438 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1439
1440 if (flags & UART_CONFIG_TYPE &&
1441 s3c24xx_serial_request_port(port) == 0)
1442 port->type = info->type;
1443 }
1444
1445 /*
1446 * verify the new serial_struct (for TIOCSSERIAL).
1447 */
1448 static int
1449 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1450 {
1451 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1452
1453 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1454 return -EINVAL;
1455
1456 return 0;
1457 }
1458
1459
1460 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1461
1462 static struct console s3c24xx_serial_console;
1463
1464 static int __init s3c24xx_serial_console_init(void)
1465 {
1466 register_console(&s3c24xx_serial_console);
1467 return 0;
1468 }
1469 console_initcall(s3c24xx_serial_console_init);
1470
1471 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1472 #else
1473 #define S3C24XX_SERIAL_CONSOLE NULL
1474 #endif
1475
1476 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1477 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1478 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1479 unsigned char c);
1480 #endif
1481
1482 static struct uart_ops s3c24xx_serial_ops = {
1483 .pm = s3c24xx_serial_pm,
1484 .tx_empty = s3c24xx_serial_tx_empty,
1485 .get_mctrl = s3c24xx_serial_get_mctrl,
1486 .set_mctrl = s3c24xx_serial_set_mctrl,
1487 .stop_tx = s3c24xx_serial_stop_tx,
1488 .start_tx = s3c24xx_serial_start_tx,
1489 .stop_rx = s3c24xx_serial_stop_rx,
1490 .break_ctl = s3c24xx_serial_break_ctl,
1491 .startup = s3c24xx_serial_startup,
1492 .shutdown = s3c24xx_serial_shutdown,
1493 .set_termios = s3c24xx_serial_set_termios,
1494 .type = s3c24xx_serial_type,
1495 .release_port = s3c24xx_serial_release_port,
1496 .request_port = s3c24xx_serial_request_port,
1497 .config_port = s3c24xx_serial_config_port,
1498 .verify_port = s3c24xx_serial_verify_port,
1499 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1500 .poll_get_char = s3c24xx_serial_get_poll_char,
1501 .poll_put_char = s3c24xx_serial_put_poll_char,
1502 #endif
1503 };
1504
1505 static struct uart_driver s3c24xx_uart_drv = {
1506 .owner = THIS_MODULE,
1507 .driver_name = "s3c2410_serial",
1508 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1509 .cons = S3C24XX_SERIAL_CONSOLE,
1510 .dev_name = S3C24XX_SERIAL_NAME,
1511 .major = S3C24XX_SERIAL_MAJOR,
1512 .minor = S3C24XX_SERIAL_MINOR,
1513 };
1514
1515 #define __PORT_LOCK_UNLOCKED(i) \
1516 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1517 static struct s3c24xx_uart_port
1518 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1519 [0] = {
1520 .port = {
1521 .lock = __PORT_LOCK_UNLOCKED(0),
1522 .iotype = UPIO_MEM,
1523 .uartclk = 0,
1524 .fifosize = 16,
1525 .ops = &s3c24xx_serial_ops,
1526 .flags = UPF_BOOT_AUTOCONF,
1527 .line = 0,
1528 }
1529 },
1530 [1] = {
1531 .port = {
1532 .lock = __PORT_LOCK_UNLOCKED(1),
1533 .iotype = UPIO_MEM,
1534 .uartclk = 0,
1535 .fifosize = 16,
1536 .ops = &s3c24xx_serial_ops,
1537 .flags = UPF_BOOT_AUTOCONF,
1538 .line = 1,
1539 }
1540 },
1541 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1542
1543 [2] = {
1544 .port = {
1545 .lock = __PORT_LOCK_UNLOCKED(2),
1546 .iotype = UPIO_MEM,
1547 .uartclk = 0,
1548 .fifosize = 16,
1549 .ops = &s3c24xx_serial_ops,
1550 .flags = UPF_BOOT_AUTOCONF,
1551 .line = 2,
1552 }
1553 },
1554 #endif
1555 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1556 [3] = {
1557 .port = {
1558 .lock = __PORT_LOCK_UNLOCKED(3),
1559 .iotype = UPIO_MEM,
1560 .uartclk = 0,
1561 .fifosize = 16,
1562 .ops = &s3c24xx_serial_ops,
1563 .flags = UPF_BOOT_AUTOCONF,
1564 .line = 3,
1565 }
1566 }
1567 #endif
1568 };
1569 #undef __PORT_LOCK_UNLOCKED
1570
1571 /* s3c24xx_serial_resetport
1572 *
1573 * reset the fifos and other the settings.
1574 */
1575
1576 static void s3c24xx_serial_resetport(struct uart_port *port,
1577 struct s3c2410_uartcfg *cfg)
1578 {
1579 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1580 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1581 unsigned int ucon_mask;
1582
1583 ucon_mask = info->clksel_mask;
1584 if (info->type == PORT_S3C2440)
1585 ucon_mask |= S3C2440_UCON0_DIVMASK;
1586
1587 ucon &= ucon_mask;
1588 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1589
1590 /* reset both fifos */
1591 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1592 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1593
1594 /* some delay is required after fifo reset */
1595 udelay(1);
1596 }
1597
1598
1599 #ifdef CONFIG_CPU_FREQ
1600
1601 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1602 unsigned long val, void *data)
1603 {
1604 struct s3c24xx_uart_port *port;
1605 struct uart_port *uport;
1606
1607 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1608 uport = &port->port;
1609
1610 /* check to see if port is enabled */
1611
1612 if (port->pm_level != 0)
1613 return 0;
1614
1615 /* try and work out if the baudrate is changing, we can detect
1616 * a change in rate, but we do not have support for detecting
1617 * a disturbance in the clock-rate over the change.
1618 */
1619
1620 if (IS_ERR(port->baudclk))
1621 goto exit;
1622
1623 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1624 goto exit;
1625
1626 if (val == CPUFREQ_PRECHANGE) {
1627 /* we should really shut the port down whilst the
1628 * frequency change is in progress. */
1629
1630 } else if (val == CPUFREQ_POSTCHANGE) {
1631 struct ktermios *termios;
1632 struct tty_struct *tty;
1633
1634 if (uport->state == NULL)
1635 goto exit;
1636
1637 tty = uport->state->port.tty;
1638
1639 if (tty == NULL)
1640 goto exit;
1641
1642 termios = &tty->termios;
1643
1644 if (termios == NULL) {
1645 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1646 goto exit;
1647 }
1648
1649 s3c24xx_serial_set_termios(uport, termios, NULL);
1650 }
1651
1652 exit:
1653 return 0;
1654 }
1655
1656 static inline int
1657 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1658 {
1659 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1660
1661 return cpufreq_register_notifier(&port->freq_transition,
1662 CPUFREQ_TRANSITION_NOTIFIER);
1663 }
1664
1665 static inline void
1666 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1667 {
1668 cpufreq_unregister_notifier(&port->freq_transition,
1669 CPUFREQ_TRANSITION_NOTIFIER);
1670 }
1671
1672 #else
1673 static inline int
1674 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1675 {
1676 return 0;
1677 }
1678
1679 static inline void
1680 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1681 {
1682 }
1683 #endif
1684
1685 /* s3c24xx_serial_init_port
1686 *
1687 * initialise a single serial port from the platform device given
1688 */
1689
1690 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1691 struct platform_device *platdev)
1692 {
1693 struct uart_port *port = &ourport->port;
1694 struct s3c2410_uartcfg *cfg = ourport->cfg;
1695 struct resource *res;
1696 int ret;
1697
1698 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1699
1700 if (platdev == NULL)
1701 return -ENODEV;
1702
1703 if (port->mapbase != 0)
1704 return 0;
1705
1706 /* setup info for port */
1707 port->dev = &platdev->dev;
1708
1709 /* Startup sequence is different for s3c64xx and higher SoC's */
1710 if (s3c24xx_serial_has_interrupt_mask(port))
1711 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1712
1713 port->uartclk = 1;
1714
1715 if (cfg->uart_flags & UPF_CONS_FLOW) {
1716 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1717 port->flags |= UPF_CONS_FLOW;
1718 }
1719
1720 /* sort our the physical and virtual addresses for each UART */
1721
1722 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1723 if (res == NULL) {
1724 dev_err(port->dev, "failed to find memory resource for uart\n");
1725 return -EINVAL;
1726 }
1727
1728 dbg("resource %pR)\n", res);
1729
1730 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1731 if (!port->membase) {
1732 dev_err(port->dev, "failed to remap controller address\n");
1733 return -EBUSY;
1734 }
1735
1736 port->mapbase = res->start;
1737 ret = platform_get_irq(platdev, 0);
1738 if (ret < 0)
1739 port->irq = 0;
1740 else {
1741 port->irq = ret;
1742 ourport->rx_irq = ret;
1743 ourport->tx_irq = ret + 1;
1744 }
1745
1746 ret = platform_get_irq(platdev, 1);
1747 if (ret > 0)
1748 ourport->tx_irq = ret;
1749 /*
1750 * DMA is currently supported only on DT platforms, if DMA properties
1751 * are specified.
1752 */
1753 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1754 "dmas", NULL)) {
1755 ourport->dma = devm_kzalloc(port->dev,
1756 sizeof(*ourport->dma),
1757 GFP_KERNEL);
1758 if (!ourport->dma)
1759 return -ENOMEM;
1760 }
1761
1762 ourport->clk = clk_get(&platdev->dev, "uart");
1763 if (IS_ERR(ourport->clk)) {
1764 pr_err("%s: Controller clock not found\n",
1765 dev_name(&platdev->dev));
1766 return PTR_ERR(ourport->clk);
1767 }
1768
1769 ret = clk_prepare_enable(ourport->clk);
1770 if (ret) {
1771 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1772 clk_put(ourport->clk);
1773 return ret;
1774 }
1775
1776 /* Keep all interrupts masked and cleared */
1777 if (s3c24xx_serial_has_interrupt_mask(port)) {
1778 wr_regl(port, S3C64XX_UINTM, 0xf);
1779 wr_regl(port, S3C64XX_UINTP, 0xf);
1780 wr_regl(port, S3C64XX_UINTSP, 0xf);
1781 }
1782
1783 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1784 &port->mapbase, port->membase, port->irq,
1785 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1786
1787 /* reset the fifos (and setup the uart) */
1788 s3c24xx_serial_resetport(port, cfg);
1789 return 0;
1790 }
1791
1792 /* Device driver serial port probe */
1793
1794 static const struct of_device_id s3c24xx_uart_dt_match[];
1795 static int probe_index;
1796
1797 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1798 struct platform_device *pdev)
1799 {
1800 #ifdef CONFIG_OF
1801 if (pdev->dev.of_node) {
1802 const struct of_device_id *match;
1803 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1804 return (struct s3c24xx_serial_drv_data *)match->data;
1805 }
1806 #endif
1807 return (struct s3c24xx_serial_drv_data *)
1808 platform_get_device_id(pdev)->driver_data;
1809 }
1810
1811 static int s3c24xx_serial_probe(struct platform_device *pdev)
1812 {
1813 struct device_node *np = pdev->dev.of_node;
1814 struct s3c24xx_uart_port *ourport;
1815 int index = probe_index;
1816 int ret;
1817
1818 if (np) {
1819 ret = of_alias_get_id(np, "serial");
1820 if (ret >= 0)
1821 index = ret;
1822 }
1823
1824 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1825
1826 ourport = &s3c24xx_serial_ports[index];
1827
1828 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1829 if (!ourport->drv_data) {
1830 dev_err(&pdev->dev, "could not find driver data\n");
1831 return -ENODEV;
1832 }
1833
1834 ourport->baudclk = ERR_PTR(-EINVAL);
1835 ourport->info = ourport->drv_data->info;
1836 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1837 dev_get_platdata(&pdev->dev) :
1838 ourport->drv_data->def_cfg;
1839
1840 if (np)
1841 of_property_read_u32(np,
1842 "samsung,uart-fifosize", &ourport->port.fifosize);
1843
1844 if (ourport->drv_data->fifosize[index])
1845 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1846 else if (ourport->info->fifosize)
1847 ourport->port.fifosize = ourport->info->fifosize;
1848
1849 /*
1850 * DMA transfers must be aligned at least to cache line size,
1851 * so find minimal transfer size suitable for DMA mode
1852 */
1853 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1854 dma_get_cache_alignment());
1855
1856 probe_index++;
1857
1858 dbg("%s: initialising port %p...\n", __func__, ourport);
1859
1860 ret = s3c24xx_serial_init_port(ourport, pdev);
1861 if (ret < 0)
1862 return ret;
1863
1864 if (!s3c24xx_uart_drv.state) {
1865 ret = uart_register_driver(&s3c24xx_uart_drv);
1866 if (ret < 0) {
1867 pr_err("Failed to register Samsung UART driver\n");
1868 return ret;
1869 }
1870 }
1871
1872 dbg("%s: adding port\n", __func__);
1873 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1874 platform_set_drvdata(pdev, &ourport->port);
1875
1876 /*
1877 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1878 * so that a potential re-enablement through the pm-callback overlaps
1879 * and keeps the clock enabled in this case.
1880 */
1881 clk_disable_unprepare(ourport->clk);
1882
1883 ret = s3c24xx_serial_cpufreq_register(ourport);
1884 if (ret < 0)
1885 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1886
1887 return 0;
1888 }
1889
1890 static int s3c24xx_serial_remove(struct platform_device *dev)
1891 {
1892 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1893
1894 if (port) {
1895 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1896 uart_remove_one_port(&s3c24xx_uart_drv, port);
1897 }
1898
1899 uart_unregister_driver(&s3c24xx_uart_drv);
1900
1901 return 0;
1902 }
1903
1904 /* UART power management code */
1905 #ifdef CONFIG_PM_SLEEP
1906 static int s3c24xx_serial_suspend(struct device *dev)
1907 {
1908 struct uart_port *port = s3c24xx_dev_to_port(dev);
1909
1910 if (port)
1911 uart_suspend_port(&s3c24xx_uart_drv, port);
1912
1913 return 0;
1914 }
1915
1916 static int s3c24xx_serial_resume(struct device *dev)
1917 {
1918 struct uart_port *port = s3c24xx_dev_to_port(dev);
1919 struct s3c24xx_uart_port *ourport = to_ourport(port);
1920
1921 if (port) {
1922 clk_prepare_enable(ourport->clk);
1923 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1924 clk_disable_unprepare(ourport->clk);
1925
1926 uart_resume_port(&s3c24xx_uart_drv, port);
1927 }
1928
1929 return 0;
1930 }
1931
1932 static int s3c24xx_serial_resume_noirq(struct device *dev)
1933 {
1934 struct uart_port *port = s3c24xx_dev_to_port(dev);
1935
1936 if (port) {
1937 /* restore IRQ mask */
1938 if (s3c24xx_serial_has_interrupt_mask(port)) {
1939 unsigned int uintm = 0xf;
1940 if (tx_enabled(port))
1941 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1942 if (rx_enabled(port))
1943 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1944 wr_regl(port, S3C64XX_UINTM, uintm);
1945 }
1946 }
1947
1948 return 0;
1949 }
1950
1951 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1952 .suspend = s3c24xx_serial_suspend,
1953 .resume = s3c24xx_serial_resume,
1954 .resume_noirq = s3c24xx_serial_resume_noirq,
1955 };
1956 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1957
1958 #else /* !CONFIG_PM_SLEEP */
1959
1960 #define SERIAL_SAMSUNG_PM_OPS NULL
1961 #endif /* CONFIG_PM_SLEEP */
1962
1963 /* Console code */
1964
1965 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1966
1967 static struct uart_port *cons_uart;
1968
1969 static int
1970 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1971 {
1972 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1973 unsigned long ufstat, utrstat;
1974
1975 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1976 /* fifo mode - check amount of data in fifo registers... */
1977
1978 ufstat = rd_regl(port, S3C2410_UFSTAT);
1979 return (ufstat & info->tx_fifofull) ? 0 : 1;
1980 }
1981
1982 /* in non-fifo mode, we go and use the tx buffer empty */
1983
1984 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1985 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1986 }
1987
1988 static bool
1989 s3c24xx_port_configured(unsigned int ucon)
1990 {
1991 /* consider the serial port configured if the tx/rx mode set */
1992 return (ucon & 0xf) != 0;
1993 }
1994
1995 #ifdef CONFIG_CONSOLE_POLL
1996 /*
1997 * Console polling routines for writing and reading from the uart while
1998 * in an interrupt or debug context.
1999 */
2000
2001 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2002 {
2003 struct s3c24xx_uart_port *ourport = to_ourport(port);
2004 unsigned int ufstat;
2005
2006 ufstat = rd_regl(port, S3C2410_UFSTAT);
2007 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2008 return NO_POLL_CHAR;
2009
2010 return rd_regb(port, S3C2410_URXH);
2011 }
2012
2013 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2014 unsigned char c)
2015 {
2016 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2017 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2018
2019 /* not possible to xmit on unconfigured port */
2020 if (!s3c24xx_port_configured(ucon))
2021 return;
2022
2023 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2024 cpu_relax();
2025 wr_regb(port, S3C2410_UTXH, c);
2026 }
2027
2028 #endif /* CONFIG_CONSOLE_POLL */
2029
2030 static void
2031 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2032 {
2033 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2034
2035 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2036 cpu_relax();
2037 wr_regb(port, S3C2410_UTXH, ch);
2038 }
2039
2040 static void
2041 s3c24xx_serial_console_write(struct console *co, const char *s,
2042 unsigned int count)
2043 {
2044 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2045
2046 /* not possible to xmit on unconfigured port */
2047 if (!s3c24xx_port_configured(ucon))
2048 return;
2049
2050 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2051 }
2052
2053 static void __init
2054 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2055 int *parity, int *bits)
2056 {
2057 struct clk *clk;
2058 unsigned int ulcon;
2059 unsigned int ucon;
2060 unsigned int ubrdiv;
2061 unsigned long rate;
2062 unsigned int clk_sel;
2063 char clk_name[MAX_CLK_NAME_LENGTH];
2064
2065 ulcon = rd_regl(port, S3C2410_ULCON);
2066 ucon = rd_regl(port, S3C2410_UCON);
2067 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2068
2069 dbg("s3c24xx_serial_get_options: port=%p\n"
2070 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2071 port, ulcon, ucon, ubrdiv);
2072
2073 if (s3c24xx_port_configured(ucon)) {
2074 switch (ulcon & S3C2410_LCON_CSMASK) {
2075 case S3C2410_LCON_CS5:
2076 *bits = 5;
2077 break;
2078 case S3C2410_LCON_CS6:
2079 *bits = 6;
2080 break;
2081 case S3C2410_LCON_CS7:
2082 *bits = 7;
2083 break;
2084 case S3C2410_LCON_CS8:
2085 default:
2086 *bits = 8;
2087 break;
2088 }
2089
2090 switch (ulcon & S3C2410_LCON_PMASK) {
2091 case S3C2410_LCON_PEVEN:
2092 *parity = 'e';
2093 break;
2094
2095 case S3C2410_LCON_PODD:
2096 *parity = 'o';
2097 break;
2098
2099 case S3C2410_LCON_PNONE:
2100 default:
2101 *parity = 'n';
2102 }
2103
2104 /* now calculate the baud rate */
2105
2106 clk_sel = s3c24xx_serial_getsource(port);
2107 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2108
2109 clk = clk_get(port->dev, clk_name);
2110 if (!IS_ERR(clk))
2111 rate = clk_get_rate(clk);
2112 else
2113 rate = 1;
2114
2115 *baud = rate / (16 * (ubrdiv + 1));
2116 dbg("calculated baud %d\n", *baud);
2117 }
2118
2119 }
2120
2121 static int __init
2122 s3c24xx_serial_console_setup(struct console *co, char *options)
2123 {
2124 struct uart_port *port;
2125 int baud = 9600;
2126 int bits = 8;
2127 int parity = 'n';
2128 int flow = 'n';
2129
2130 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2131 co, co->index, options);
2132
2133 /* is this a valid port */
2134
2135 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2136 co->index = 0;
2137
2138 port = &s3c24xx_serial_ports[co->index].port;
2139
2140 /* is the port configured? */
2141
2142 if (port->mapbase == 0x0)
2143 return -ENODEV;
2144
2145 cons_uart = port;
2146
2147 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2148
2149 /*
2150 * Check whether an invalid uart number has been specified, and
2151 * if so, search for the first available port that does have
2152 * console support.
2153 */
2154 if (options)
2155 uart_parse_options(options, &baud, &parity, &bits, &flow);
2156 else
2157 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2158
2159 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2160
2161 return uart_set_options(port, co, baud, parity, bits, flow);
2162 }
2163
2164 static struct console s3c24xx_serial_console = {
2165 .name = S3C24XX_SERIAL_NAME,
2166 .device = uart_console_device,
2167 .flags = CON_PRINTBUFFER,
2168 .index = -1,
2169 .write = s3c24xx_serial_console_write,
2170 .setup = s3c24xx_serial_console_setup,
2171 .data = &s3c24xx_uart_drv,
2172 };
2173 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2174
2175 #ifdef CONFIG_CPU_S3C2410
2176 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2177 .info = &(struct s3c24xx_uart_info) {
2178 .name = "Samsung S3C2410 UART",
2179 .type = PORT_S3C2410,
2180 .fifosize = 16,
2181 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2182 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2183 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2184 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2185 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2186 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2187 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2188 .num_clks = 2,
2189 .clksel_mask = S3C2410_UCON_CLKMASK,
2190 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2191 },
2192 .def_cfg = &(struct s3c2410_uartcfg) {
2193 .ucon = S3C2410_UCON_DEFAULT,
2194 .ufcon = S3C2410_UFCON_DEFAULT,
2195 },
2196 };
2197 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2198 #else
2199 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2200 #endif
2201
2202 #ifdef CONFIG_CPU_S3C2412
2203 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2204 .info = &(struct s3c24xx_uart_info) {
2205 .name = "Samsung S3C2412 UART",
2206 .type = PORT_S3C2412,
2207 .fifosize = 64,
2208 .has_divslot = 1,
2209 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2210 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2211 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2212 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2213 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2214 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2215 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2216 .num_clks = 4,
2217 .clksel_mask = S3C2412_UCON_CLKMASK,
2218 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2219 },
2220 .def_cfg = &(struct s3c2410_uartcfg) {
2221 .ucon = S3C2410_UCON_DEFAULT,
2222 .ufcon = S3C2410_UFCON_DEFAULT,
2223 },
2224 };
2225 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2226 #else
2227 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2228 #endif
2229
2230 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2231 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2232 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2233 .info = &(struct s3c24xx_uart_info) {
2234 .name = "Samsung S3C2440 UART",
2235 .type = PORT_S3C2440,
2236 .fifosize = 64,
2237 .has_divslot = 1,
2238 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2239 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2240 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2241 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2242 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2243 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2244 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2245 .num_clks = 4,
2246 .clksel_mask = S3C2412_UCON_CLKMASK,
2247 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2248 },
2249 .def_cfg = &(struct s3c2410_uartcfg) {
2250 .ucon = S3C2410_UCON_DEFAULT,
2251 .ufcon = S3C2410_UFCON_DEFAULT,
2252 },
2253 };
2254 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2255 #else
2256 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2257 #endif
2258
2259 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2260 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2261 .info = &(struct s3c24xx_uart_info) {
2262 .name = "Samsung S3C6400 UART",
2263 .type = PORT_S3C6400,
2264 .fifosize = 64,
2265 .has_divslot = 1,
2266 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2267 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2268 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2269 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2270 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2271 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2272 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2273 .num_clks = 4,
2274 .clksel_mask = S3C6400_UCON_CLKMASK,
2275 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2276 },
2277 .def_cfg = &(struct s3c2410_uartcfg) {
2278 .ucon = S3C2410_UCON_DEFAULT,
2279 .ufcon = S3C2410_UFCON_DEFAULT,
2280 },
2281 };
2282 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2283 #else
2284 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2285 #endif
2286
2287 #ifdef CONFIG_CPU_S5PV210
2288 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2289 .info = &(struct s3c24xx_uart_info) {
2290 .name = "Samsung S5PV210 UART",
2291 .type = PORT_S3C6400,
2292 .has_divslot = 1,
2293 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2294 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2295 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2296 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2297 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2298 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2299 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2300 .num_clks = 2,
2301 .clksel_mask = S5PV210_UCON_CLKMASK,
2302 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2303 },
2304 .def_cfg = &(struct s3c2410_uartcfg) {
2305 .ucon = S5PV210_UCON_DEFAULT,
2306 .ufcon = S5PV210_UFCON_DEFAULT,
2307 },
2308 .fifosize = { 256, 64, 16, 16 },
2309 };
2310 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2311 #else
2312 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2313 #endif
2314
2315 #if defined(CONFIG_ARCH_EXYNOS)
2316 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2317 .info = &(struct s3c24xx_uart_info) { \
2318 .name = "Samsung Exynos UART", \
2319 .type = PORT_S3C6400, \
2320 .has_divslot = 1, \
2321 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2322 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2323 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2324 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2325 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2326 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2327 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2328 .num_clks = 1, \
2329 .clksel_mask = 0, \
2330 .clksel_shift = 0, \
2331 }, \
2332 .def_cfg = &(struct s3c2410_uartcfg) { \
2333 .ucon = S5PV210_UCON_DEFAULT, \
2334 .ufcon = S5PV210_UFCON_DEFAULT, \
2335 .has_fracval = 1, \
2336 } \
2337
2338 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2339 EXYNOS_COMMON_SERIAL_DRV_DATA,
2340 .fifosize = { 256, 64, 16, 16 },
2341 };
2342
2343 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2344 EXYNOS_COMMON_SERIAL_DRV_DATA,
2345 .fifosize = { 64, 256, 16, 256 },
2346 };
2347
2348 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2349 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2350 #else
2351 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2352 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2353 #endif
2354
2355 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
2356 {
2357 .name = "s3c2410-uart",
2358 .driver_data = S3C2410_SERIAL_DRV_DATA,
2359 }, {
2360 .name = "s3c2412-uart",
2361 .driver_data = S3C2412_SERIAL_DRV_DATA,
2362 }, {
2363 .name = "s3c2440-uart",
2364 .driver_data = S3C2440_SERIAL_DRV_DATA,
2365 }, {
2366 .name = "s3c6400-uart",
2367 .driver_data = S3C6400_SERIAL_DRV_DATA,
2368 }, {
2369 .name = "s5pv210-uart",
2370 .driver_data = S5PV210_SERIAL_DRV_DATA,
2371 }, {
2372 .name = "exynos4210-uart",
2373 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2374 }, {
2375 .name = "exynos5433-uart",
2376 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2377 },
2378 { },
2379 };
2380 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2381
2382 #ifdef CONFIG_OF
2383 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2384 { .compatible = "samsung,s3c2410-uart",
2385 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2386 { .compatible = "samsung,s3c2412-uart",
2387 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2388 { .compatible = "samsung,s3c2440-uart",
2389 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2390 { .compatible = "samsung,s3c6400-uart",
2391 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2392 { .compatible = "samsung,s5pv210-uart",
2393 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2394 { .compatible = "samsung,exynos4210-uart",
2395 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2396 { .compatible = "samsung,exynos5433-uart",
2397 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2398 {},
2399 };
2400 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2401 #endif
2402
2403 static struct platform_driver samsung_serial_driver = {
2404 .probe = s3c24xx_serial_probe,
2405 .remove = s3c24xx_serial_remove,
2406 .id_table = s3c24xx_serial_driver_ids,
2407 .driver = {
2408 .name = "samsung-uart",
2409 .pm = SERIAL_SAMSUNG_PM_OPS,
2410 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2411 },
2412 };
2413
2414 module_platform_driver(samsung_serial_driver);
2415
2416 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2417 /*
2418 * Early console.
2419 */
2420
2421 struct samsung_early_console_data {
2422 u32 txfull_mask;
2423 };
2424
2425 static void samsung_early_busyuart(struct uart_port *port)
2426 {
2427 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2428 ;
2429 }
2430
2431 static void samsung_early_busyuart_fifo(struct uart_port *port)
2432 {
2433 struct samsung_early_console_data *data = port->private_data;
2434
2435 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2436 ;
2437 }
2438
2439 static void samsung_early_putc(struct uart_port *port, int c)
2440 {
2441 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2442 samsung_early_busyuart_fifo(port);
2443 else
2444 samsung_early_busyuart(port);
2445
2446 writeb(c, port->membase + S3C2410_UTXH);
2447 }
2448
2449 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2450 {
2451 struct earlycon_device *dev = con->data;
2452
2453 uart_console_write(&dev->port, s, n, samsung_early_putc);
2454 }
2455
2456 static int __init samsung_early_console_setup(struct earlycon_device *device,
2457 const char *opt)
2458 {
2459 if (!device->port.membase)
2460 return -ENODEV;
2461
2462 device->con->write = samsung_early_write;
2463 return 0;
2464 }
2465
2466 /* S3C2410 */
2467 static struct samsung_early_console_data s3c2410_early_console_data = {
2468 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2469 };
2470
2471 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2472 const char *opt)
2473 {
2474 device->port.private_data = &s3c2410_early_console_data;
2475 return samsung_early_console_setup(device, opt);
2476 }
2477 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2478 s3c2410_early_console_setup);
2479 EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2480
2481 /* S3C2412, S3C2440, S3C64xx */
2482 static struct samsung_early_console_data s3c2440_early_console_data = {
2483 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2484 };
2485
2486 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2487 const char *opt)
2488 {
2489 device->port.private_data = &s3c2440_early_console_data;
2490 return samsung_early_console_setup(device, opt);
2491 }
2492 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2493 s3c2440_early_console_setup);
2494 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2495 s3c2440_early_console_setup);
2496 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2497 s3c2440_early_console_setup);
2498 EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2499 EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2500 EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2501
2502 /* S5PV210, EXYNOS */
2503 static struct samsung_early_console_data s5pv210_early_console_data = {
2504 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2505 };
2506
2507 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2508 const char *opt)
2509 {
2510 device->port.private_data = &s5pv210_early_console_data;
2511 return samsung_early_console_setup(device, opt);
2512 }
2513 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2514 s5pv210_early_console_setup);
2515 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2516 s5pv210_early_console_setup);
2517 EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2518 EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2519 #endif
2520
2521 MODULE_ALIAS("platform:samsung-uart");
2522 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2523 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2524 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support