2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/regmap.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/uaccess.h>
30 #define SC16IS7XX_NAME "sc16is7xx"
32 /* SC16IS7XX register definitions */
33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67 /* Enhanced Register set: Only if (LCR == 0xBF) */
68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74 /* IER register bits */
75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
83 /* IER register bits - write only if (EFR[4] == 1) */
84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89 /* FCR register bits */
90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96 /* FCR register bits - write only if (EFR[4] == 1) */
97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100 /* IIR register bits */
101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
118 /* LCR register bits */
119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 * Word length bits table:
128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 * STOP length bit table:
132 * 1 -> 1-1.5 stop bits if
134 * 2 stop bits otherwise
136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
150 /* MCR register bits */
151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 /* LSR register bits */
171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181 /* MSR register bits */
182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
195 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
196 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
199 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
202 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237 /* IOControl register bits (Only 750/760) */
238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242 /* EFCR register bits */
243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
252 * 1 = rate upto 1.152 Mbit/s
256 /* EFR register bits */
257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
270 * 01 -> transmitter generates
272 * 10 -> transmitter generates
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
284 * 01 -> receiver compares
286 * 10 -> receiver compares
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
293 /* Misc definitions */
294 #define SC16IS7XX_FIFO_SIZE (64)
295 #define SC16IS7XX_REG_SHIFT 2
297 struct sc16is7xx_devtype
{
303 struct sc16is7xx_one
{
304 struct uart_port port
;
305 struct work_struct tx_work
;
306 struct work_struct md_work
;
309 struct sc16is7xx_port
{
310 struct uart_driver uart
;
311 struct sc16is7xx_devtype
*devtype
;
312 struct regmap
*regmap
;
315 #ifdef CONFIG_GPIOLIB
316 struct gpio_chip gpio
;
318 unsigned char buf
[SC16IS7XX_FIFO_SIZE
];
319 struct sc16is7xx_one p
[0];
322 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
324 static u8
sc16is7xx_port_read(struct uart_port
*port
, u8 reg
)
326 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
327 unsigned int val
= 0;
329 regmap_read(s
->regmap
,
330 (reg
<< SC16IS7XX_REG_SHIFT
) | port
->line
, &val
);
335 static void sc16is7xx_port_write(struct uart_port
*port
, u8 reg
, u8 val
)
337 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
339 regmap_write(s
->regmap
,
340 (reg
<< SC16IS7XX_REG_SHIFT
) | port
->line
, val
);
343 static void sc16is7xx_port_update(struct uart_port
*port
, u8 reg
,
346 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
348 regmap_update_bits(s
->regmap
,
349 (reg
<< SC16IS7XX_REG_SHIFT
) | port
->line
,
354 static void sc16is7xx_power(struct uart_port
*port
, int on
)
356 sc16is7xx_port_update(port
, SC16IS7XX_IER_REG
,
357 SC16IS7XX_IER_SLEEP_BIT
,
358 on
? 0 : SC16IS7XX_IER_SLEEP_BIT
);
361 static const struct sc16is7xx_devtype sc16is74x_devtype
= {
367 static const struct sc16is7xx_devtype sc16is750_devtype
= {
373 static const struct sc16is7xx_devtype sc16is752_devtype
= {
379 static const struct sc16is7xx_devtype sc16is760_devtype
= {
385 static const struct sc16is7xx_devtype sc16is762_devtype
= {
391 static bool sc16is7xx_regmap_volatile(struct device
*dev
, unsigned int reg
)
393 switch (reg
>> SC16IS7XX_REG_SHIFT
) {
394 case SC16IS7XX_RHR_REG
:
395 case SC16IS7XX_IIR_REG
:
396 case SC16IS7XX_LSR_REG
:
397 case SC16IS7XX_MSR_REG
:
398 case SC16IS7XX_TXLVL_REG
:
399 case SC16IS7XX_RXLVL_REG
:
400 case SC16IS7XX_IOSTATE_REG
:
409 static bool sc16is7xx_regmap_precious(struct device
*dev
, unsigned int reg
)
411 switch (reg
>> SC16IS7XX_REG_SHIFT
) {
412 case SC16IS7XX_RHR_REG
:
421 static int sc16is7xx_set_baud(struct uart_port
*port
, int baud
)
423 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
426 unsigned long clk
= port
->uartclk
, div
= clk
/ 16 / baud
;
429 prescaler
= SC16IS7XX_MCR_CLKSEL_BIT
;
433 lcr
= sc16is7xx_port_read(port
, SC16IS7XX_LCR_REG
);
435 /* Open the LCR divisors for configuration */
436 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
437 SC16IS7XX_LCR_CONF_MODE_B
);
439 /* Enable enhanced features */
440 regcache_cache_bypass(s
->regmap
, true);
441 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
,
442 SC16IS7XX_EFR_ENABLE_BIT
);
443 regcache_cache_bypass(s
->regmap
, false);
445 /* Put LCR back to the normal mode */
446 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
448 sc16is7xx_port_update(port
, SC16IS7XX_MCR_REG
,
449 SC16IS7XX_MCR_CLKSEL_BIT
,
452 /* Open the LCR divisors for configuration */
453 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
454 SC16IS7XX_LCR_CONF_MODE_A
);
456 /* Write the new divisor */
457 regcache_cache_bypass(s
->regmap
, true);
458 sc16is7xx_port_write(port
, SC16IS7XX_DLH_REG
, div
/ 256);
459 sc16is7xx_port_write(port
, SC16IS7XX_DLL_REG
, div
% 256);
460 regcache_cache_bypass(s
->regmap
, false);
462 /* Put LCR back to the normal mode */
463 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
465 return DIV_ROUND_CLOSEST(clk
/ 16, div
);
468 static void sc16is7xx_handle_rx(struct uart_port
*port
, unsigned int rxlen
,
471 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
472 unsigned int lsr
= 0, ch
, flag
, bytes_read
, i
;
473 bool read_lsr
= (iir
== SC16IS7XX_IIR_RLSE_SRC
) ? true : false;
475 if (unlikely(rxlen
>= sizeof(s
->buf
))) {
476 dev_warn_ratelimited(port
->dev
,
477 "Port %i: Possible RX FIFO overrun: %d\n",
479 port
->icount
.buf_overrun
++;
480 /* Ensure sanity of RX level */
481 rxlen
= sizeof(s
->buf
);
485 /* Only read lsr if there are possible errors in FIFO */
487 lsr
= sc16is7xx_port_read(port
, SC16IS7XX_LSR_REG
);
488 if (!(lsr
& SC16IS7XX_LSR_FIFOE_BIT
))
489 read_lsr
= false; /* No errors left in FIFO */
494 s
->buf
[0] = sc16is7xx_port_read(port
, SC16IS7XX_RHR_REG
);
497 regcache_cache_bypass(s
->regmap
, true);
498 regmap_raw_read(s
->regmap
, SC16IS7XX_RHR_REG
,
500 regcache_cache_bypass(s
->regmap
, false);
504 lsr
&= SC16IS7XX_LSR_BRK_ERROR_MASK
;
510 if (lsr
& SC16IS7XX_LSR_BI_BIT
) {
512 if (uart_handle_break(port
))
514 } else if (lsr
& SC16IS7XX_LSR_PE_BIT
)
515 port
->icount
.parity
++;
516 else if (lsr
& SC16IS7XX_LSR_FE_BIT
)
517 port
->icount
.frame
++;
518 else if (lsr
& SC16IS7XX_LSR_OE_BIT
)
519 port
->icount
.overrun
++;
521 lsr
&= port
->read_status_mask
;
522 if (lsr
& SC16IS7XX_LSR_BI_BIT
)
524 else if (lsr
& SC16IS7XX_LSR_PE_BIT
)
526 else if (lsr
& SC16IS7XX_LSR_FE_BIT
)
528 else if (lsr
& SC16IS7XX_LSR_OE_BIT
)
532 for (i
= 0; i
< bytes_read
; ++i
) {
534 if (uart_handle_sysrq_char(port
, ch
))
537 if (lsr
& port
->ignore_status_mask
)
540 uart_insert_char(port
, lsr
, SC16IS7XX_LSR_OE_BIT
, ch
,
546 tty_flip_buffer_push(&port
->state
->port
);
549 static void sc16is7xx_handle_tx(struct uart_port
*port
)
551 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
552 struct circ_buf
*xmit
= &port
->state
->xmit
;
553 unsigned int txlen
, to_send
, i
;
555 if (unlikely(port
->x_char
)) {
556 sc16is7xx_port_write(port
, SC16IS7XX_THR_REG
, port
->x_char
);
562 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
))
565 /* Get length of data pending in circular buffer */
566 to_send
= uart_circ_chars_pending(xmit
);
567 if (likely(to_send
)) {
568 /* Limit to size of TX FIFO */
569 txlen
= sc16is7xx_port_read(port
, SC16IS7XX_TXLVL_REG
);
570 to_send
= (to_send
> txlen
) ? txlen
: to_send
;
572 /* Add data to send */
573 port
->icount
.tx
+= to_send
;
575 /* Convert to linear buffer */
576 for (i
= 0; i
< to_send
; ++i
) {
577 s
->buf
[i
] = xmit
->buf
[xmit
->tail
];
578 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
580 regcache_cache_bypass(s
->regmap
, true);
581 regmap_raw_write(s
->regmap
, SC16IS7XX_THR_REG
, s
->buf
, to_send
);
582 regcache_cache_bypass(s
->regmap
, false);
585 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
586 uart_write_wakeup(port
);
589 static void sc16is7xx_port_irq(struct sc16is7xx_port
*s
, int portno
)
591 struct uart_port
*port
= &s
->p
[portno
].port
;
594 unsigned int iir
, msr
, rxlen
;
596 iir
= sc16is7xx_port_read(port
, SC16IS7XX_IIR_REG
);
597 if (iir
& SC16IS7XX_IIR_NO_INT_BIT
)
600 iir
&= SC16IS7XX_IIR_ID_MASK
;
603 case SC16IS7XX_IIR_RDI_SRC
:
604 case SC16IS7XX_IIR_RLSE_SRC
:
605 case SC16IS7XX_IIR_RTOI_SRC
:
606 case SC16IS7XX_IIR_XOFFI_SRC
:
607 rxlen
= sc16is7xx_port_read(port
, SC16IS7XX_RXLVL_REG
);
609 sc16is7xx_handle_rx(port
, rxlen
, iir
);
612 case SC16IS7XX_IIR_CTSRTS_SRC
:
613 msr
= sc16is7xx_port_read(port
, SC16IS7XX_MSR_REG
);
614 uart_handle_cts_change(port
,
615 !!(msr
& SC16IS7XX_MSR_CTS_BIT
));
617 case SC16IS7XX_IIR_THRI_SRC
:
618 mutex_lock(&s
->mutex
);
619 sc16is7xx_handle_tx(port
);
620 mutex_unlock(&s
->mutex
);
623 dev_err_ratelimited(port
->dev
,
624 "Port %i: Unexpected interrupt: %x",
631 static irqreturn_t
sc16is7xx_ist(int irq
, void *dev_id
)
633 struct sc16is7xx_port
*s
= (struct sc16is7xx_port
*)dev_id
;
636 for (i
= 0; i
< s
->uart
.nr
; ++i
)
637 sc16is7xx_port_irq(s
, i
);
642 static void sc16is7xx_wq_proc(struct work_struct
*ws
)
644 struct sc16is7xx_one
*one
= to_sc16is7xx_one(ws
, tx_work
);
645 struct sc16is7xx_port
*s
= dev_get_drvdata(one
->port
.dev
);
647 mutex_lock(&s
->mutex
);
648 sc16is7xx_handle_tx(&one
->port
);
649 mutex_unlock(&s
->mutex
);
652 static void sc16is7xx_stop_tx(struct uart_port
* port
)
654 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
655 struct circ_buf
*xmit
= &one
->port
.state
->xmit
;
658 if (port
->rs485
.flags
& SER_RS485_ENABLED
) {
659 /* do nothing if current tx not yet completed */
660 int lsr
= sc16is7xx_port_read(port
, SC16IS7XX_LSR_REG
);
661 if (!(lsr
& SC16IS7XX_LSR_TEMT_BIT
))
664 if (uart_circ_empty(xmit
) &&
665 (port
->rs485
.delay_rts_after_send
> 0))
666 mdelay(port
->rs485
.delay_rts_after_send
);
669 sc16is7xx_port_update(port
, SC16IS7XX_IER_REG
,
670 SC16IS7XX_IER_THRI_BIT
,
674 static void sc16is7xx_stop_rx(struct uart_port
* port
)
676 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
678 one
->port
.read_status_mask
&= ~SC16IS7XX_LSR_DR_BIT
;
679 sc16is7xx_port_update(port
, SC16IS7XX_IER_REG
,
680 SC16IS7XX_LSR_DR_BIT
,
684 static void sc16is7xx_start_tx(struct uart_port
*port
)
686 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
689 if ((port
->rs485
.flags
& SER_RS485_ENABLED
) &&
690 (port
->rs485
.delay_rts_before_send
> 0)) {
691 mdelay(port
->rs485
.delay_rts_before_send
);
694 if (!work_pending(&one
->tx_work
))
695 schedule_work(&one
->tx_work
);
698 static unsigned int sc16is7xx_tx_empty(struct uart_port
*port
)
700 unsigned int lvl
, lsr
;
702 lvl
= sc16is7xx_port_read(port
, SC16IS7XX_TXLVL_REG
);
703 lsr
= sc16is7xx_port_read(port
, SC16IS7XX_LSR_REG
);
705 return ((lsr
& SC16IS7XX_LSR_THRE_BIT
) && !lvl
) ? TIOCSER_TEMT
: 0;
708 static unsigned int sc16is7xx_get_mctrl(struct uart_port
*port
)
710 /* DCD and DSR are not wired and CTS/RTS is handled automatically
711 * so just indicate DSR and CAR asserted
713 return TIOCM_DSR
| TIOCM_CAR
;
716 static void sc16is7xx_md_proc(struct work_struct
*ws
)
718 struct sc16is7xx_one
*one
= to_sc16is7xx_one(ws
, md_work
);
720 sc16is7xx_port_update(&one
->port
, SC16IS7XX_MCR_REG
,
721 SC16IS7XX_MCR_LOOP_BIT
,
722 (one
->port
.mctrl
& TIOCM_LOOP
) ?
723 SC16IS7XX_MCR_LOOP_BIT
: 0);
726 static void sc16is7xx_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
728 struct sc16is7xx_one
*one
= to_sc16is7xx_one(port
, port
);
730 schedule_work(&one
->md_work
);
733 static void sc16is7xx_break_ctl(struct uart_port
*port
, int break_state
)
735 sc16is7xx_port_update(port
, SC16IS7XX_LCR_REG
,
736 SC16IS7XX_LCR_TXBREAK_BIT
,
737 break_state
? SC16IS7XX_LCR_TXBREAK_BIT
: 0);
740 static void sc16is7xx_set_termios(struct uart_port
*port
,
741 struct ktermios
*termios
,
742 struct ktermios
*old
)
744 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
745 unsigned int lcr
, flow
= 0;
748 /* Mask termios capabilities we don't support */
749 termios
->c_cflag
&= ~CMSPAR
;
752 switch (termios
->c_cflag
& CSIZE
) {
754 lcr
= SC16IS7XX_LCR_WORD_LEN_5
;
757 lcr
= SC16IS7XX_LCR_WORD_LEN_6
;
760 lcr
= SC16IS7XX_LCR_WORD_LEN_7
;
763 lcr
= SC16IS7XX_LCR_WORD_LEN_8
;
766 lcr
= SC16IS7XX_LCR_WORD_LEN_8
;
767 termios
->c_cflag
&= ~CSIZE
;
768 termios
->c_cflag
|= CS8
;
773 if (termios
->c_cflag
& PARENB
) {
774 lcr
|= SC16IS7XX_LCR_PARITY_BIT
;
775 if (!(termios
->c_cflag
& PARODD
))
776 lcr
|= SC16IS7XX_LCR_EVENPARITY_BIT
;
780 if (termios
->c_cflag
& CSTOPB
)
781 lcr
|= SC16IS7XX_LCR_STOPLEN_BIT
; /* 2 stops */
783 /* Set read status mask */
784 port
->read_status_mask
= SC16IS7XX_LSR_OE_BIT
;
785 if (termios
->c_iflag
& INPCK
)
786 port
->read_status_mask
|= SC16IS7XX_LSR_PE_BIT
|
787 SC16IS7XX_LSR_FE_BIT
;
788 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
789 port
->read_status_mask
|= SC16IS7XX_LSR_BI_BIT
;
791 /* Set status ignore mask */
792 port
->ignore_status_mask
= 0;
793 if (termios
->c_iflag
& IGNBRK
)
794 port
->ignore_status_mask
|= SC16IS7XX_LSR_BI_BIT
;
795 if (!(termios
->c_cflag
& CREAD
))
796 port
->ignore_status_mask
|= SC16IS7XX_LSR_BRK_ERROR_MASK
;
798 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
799 SC16IS7XX_LCR_CONF_MODE_B
);
801 /* Configure flow control */
802 regcache_cache_bypass(s
->regmap
, true);
803 sc16is7xx_port_write(port
, SC16IS7XX_XON1_REG
, termios
->c_cc
[VSTART
]);
804 sc16is7xx_port_write(port
, SC16IS7XX_XOFF1_REG
, termios
->c_cc
[VSTOP
]);
805 if (termios
->c_cflag
& CRTSCTS
)
806 flow
|= SC16IS7XX_EFR_AUTOCTS_BIT
|
807 SC16IS7XX_EFR_AUTORTS_BIT
;
808 if (termios
->c_iflag
& IXON
)
809 flow
|= SC16IS7XX_EFR_SWFLOW3_BIT
;
810 if (termios
->c_iflag
& IXOFF
)
811 flow
|= SC16IS7XX_EFR_SWFLOW1_BIT
;
813 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
, flow
);
814 regcache_cache_bypass(s
->regmap
, false);
816 /* Update LCR register */
817 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, lcr
);
819 /* Get baud rate generator configuration */
820 baud
= uart_get_baud_rate(port
, termios
, old
,
821 port
->uartclk
/ 16 / 4 / 0xffff,
824 /* Setup baudrate generator */
825 baud
= sc16is7xx_set_baud(port
, baud
);
827 /* Update timeout according to new baud rate */
828 uart_update_timeout(port
, termios
->c_cflag
, baud
);
831 static int sc16is7xx_config_rs485(struct uart_port
*port
,
832 struct serial_rs485
*rs485
)
834 const u32 mask
= SC16IS7XX_EFCR_AUTO_RS485_BIT
|
835 SC16IS7XX_EFCR_RTS_INVERT_BIT
;
838 if (rs485
->flags
& SER_RS485_ENABLED
) {
839 bool rts_during_rx
, rts_during_tx
;
841 rts_during_rx
= rs485
->flags
& SER_RS485_RTS_AFTER_SEND
;
842 rts_during_tx
= rs485
->flags
& SER_RS485_RTS_ON_SEND
;
844 efcr
|= SC16IS7XX_EFCR_AUTO_RS485_BIT
;
846 if (!rts_during_rx
&& rts_during_tx
)
848 else if (rts_during_rx
&& !rts_during_tx
)
849 efcr
|= SC16IS7XX_EFCR_RTS_INVERT_BIT
;
852 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
853 rts_during_tx
, rts_during_rx
);
856 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
, mask
, efcr
);
858 port
->rs485
= *rs485
;
863 static int sc16is7xx_startup(struct uart_port
*port
)
865 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
868 sc16is7xx_power(port
, 1);
871 val
= SC16IS7XX_FCR_RXRESET_BIT
| SC16IS7XX_FCR_TXRESET_BIT
;
872 sc16is7xx_port_write(port
, SC16IS7XX_FCR_REG
, val
);
874 sc16is7xx_port_write(port
, SC16IS7XX_FCR_REG
,
875 SC16IS7XX_FCR_FIFO_BIT
);
878 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
,
879 SC16IS7XX_LCR_CONF_MODE_B
);
881 regcache_cache_bypass(s
->regmap
, true);
883 /* Enable write access to enhanced features and internal clock div */
884 sc16is7xx_port_write(port
, SC16IS7XX_EFR_REG
,
885 SC16IS7XX_EFR_ENABLE_BIT
);
888 sc16is7xx_port_update(port
, SC16IS7XX_MCR_REG
,
889 SC16IS7XX_MCR_TCRTLR_BIT
,
890 SC16IS7XX_MCR_TCRTLR_BIT
);
892 /* Configure flow control levels */
893 /* Flow control halt level 48, resume level 24 */
894 sc16is7xx_port_write(port
, SC16IS7XX_TCR_REG
,
895 SC16IS7XX_TCR_RX_RESUME(24) |
896 SC16IS7XX_TCR_RX_HALT(48));
898 regcache_cache_bypass(s
->regmap
, false);
900 /* Now, initialize the UART */
901 sc16is7xx_port_write(port
, SC16IS7XX_LCR_REG
, SC16IS7XX_LCR_WORD_LEN_8
);
903 /* Enable the Rx and Tx FIFO */
904 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
,
905 SC16IS7XX_EFCR_RXDISABLE_BIT
|
906 SC16IS7XX_EFCR_TXDISABLE_BIT
,
909 /* Enable RX, TX, CTS change interrupts */
910 val
= SC16IS7XX_IER_RDI_BIT
| SC16IS7XX_IER_THRI_BIT
|
911 SC16IS7XX_IER_CTSI_BIT
;
912 sc16is7xx_port_write(port
, SC16IS7XX_IER_REG
, val
);
917 static void sc16is7xx_shutdown(struct uart_port
*port
)
919 /* Disable all interrupts */
920 sc16is7xx_port_write(port
, SC16IS7XX_IER_REG
, 0);
922 sc16is7xx_port_update(port
, SC16IS7XX_EFCR_REG
,
923 SC16IS7XX_EFCR_RXDISABLE_BIT
|
924 SC16IS7XX_EFCR_TXDISABLE_BIT
,
925 SC16IS7XX_EFCR_RXDISABLE_BIT
|
926 SC16IS7XX_EFCR_TXDISABLE_BIT
);
928 sc16is7xx_power(port
, 0);
931 static const char *sc16is7xx_type(struct uart_port
*port
)
933 struct sc16is7xx_port
*s
= dev_get_drvdata(port
->dev
);
935 return (port
->type
== PORT_SC16IS7XX
) ? s
->devtype
->name
: NULL
;
938 static int sc16is7xx_request_port(struct uart_port
*port
)
944 static void sc16is7xx_config_port(struct uart_port
*port
, int flags
)
946 if (flags
& UART_CONFIG_TYPE
)
947 port
->type
= PORT_SC16IS7XX
;
950 static int sc16is7xx_verify_port(struct uart_port
*port
,
951 struct serial_struct
*s
)
953 if ((s
->type
!= PORT_UNKNOWN
) && (s
->type
!= PORT_SC16IS7XX
))
955 if (s
->irq
!= port
->irq
)
961 static void sc16is7xx_pm(struct uart_port
*port
, unsigned int state
,
962 unsigned int oldstate
)
964 sc16is7xx_power(port
, (state
== UART_PM_STATE_ON
) ? 1 : 0);
967 static void sc16is7xx_null_void(struct uart_port
*port
)
972 static const struct uart_ops sc16is7xx_ops
= {
973 .tx_empty
= sc16is7xx_tx_empty
,
974 .set_mctrl
= sc16is7xx_set_mctrl
,
975 .get_mctrl
= sc16is7xx_get_mctrl
,
976 .stop_tx
= sc16is7xx_stop_tx
,
977 .start_tx
= sc16is7xx_start_tx
,
978 .stop_rx
= sc16is7xx_stop_rx
,
979 .break_ctl
= sc16is7xx_break_ctl
,
980 .startup
= sc16is7xx_startup
,
981 .shutdown
= sc16is7xx_shutdown
,
982 .set_termios
= sc16is7xx_set_termios
,
983 .type
= sc16is7xx_type
,
984 .request_port
= sc16is7xx_request_port
,
985 .release_port
= sc16is7xx_null_void
,
986 .config_port
= sc16is7xx_config_port
,
987 .verify_port
= sc16is7xx_verify_port
,
991 #ifdef CONFIG_GPIOLIB
992 static int sc16is7xx_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
995 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
997 struct uart_port
*port
= &s
->p
[0].port
;
999 val
= sc16is7xx_port_read(port
, SC16IS7XX_IOSTATE_REG
);
1001 return !!(val
& BIT(offset
));
1004 static void sc16is7xx_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
1006 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1008 struct uart_port
*port
= &s
->p
[0].port
;
1010 sc16is7xx_port_update(port
, SC16IS7XX_IOSTATE_REG
, BIT(offset
),
1011 val
? BIT(offset
) : 0);
1014 static int sc16is7xx_gpio_direction_input(struct gpio_chip
*chip
,
1017 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1019 struct uart_port
*port
= &s
->p
[0].port
;
1021 sc16is7xx_port_update(port
, SC16IS7XX_IODIR_REG
, BIT(offset
), 0);
1026 static int sc16is7xx_gpio_direction_output(struct gpio_chip
*chip
,
1027 unsigned offset
, int val
)
1029 struct sc16is7xx_port
*s
= container_of(chip
, struct sc16is7xx_port
,
1031 struct uart_port
*port
= &s
->p
[0].port
;
1033 sc16is7xx_port_update(port
, SC16IS7XX_IOSTATE_REG
, BIT(offset
),
1034 val
? BIT(offset
) : 0);
1035 sc16is7xx_port_update(port
, SC16IS7XX_IODIR_REG
, BIT(offset
),
1042 static int sc16is7xx_probe(struct device
*dev
,
1043 struct sc16is7xx_devtype
*devtype
,
1044 struct regmap
*regmap
, int irq
, unsigned long flags
)
1046 unsigned long freq
, *pfreq
= dev_get_platdata(dev
);
1048 struct sc16is7xx_port
*s
;
1051 return PTR_ERR(regmap
);
1053 /* Alloc port structure */
1054 s
= devm_kzalloc(dev
, sizeof(*s
) +
1055 sizeof(struct sc16is7xx_one
) * devtype
->nr_uart
,
1058 dev_err(dev
, "Error allocating port structure\n");
1062 s
->clk
= devm_clk_get(dev
, NULL
);
1063 if (IS_ERR(s
->clk
)) {
1067 return PTR_ERR(s
->clk
);
1069 clk_prepare_enable(s
->clk
);
1070 freq
= clk_get_rate(s
->clk
);
1074 s
->devtype
= devtype
;
1075 dev_set_drvdata(dev
, s
);
1077 /* Register UART driver */
1078 s
->uart
.owner
= THIS_MODULE
;
1079 s
->uart
.dev_name
= "ttySC";
1080 s
->uart
.nr
= devtype
->nr_uart
;
1081 ret
= uart_register_driver(&s
->uart
);
1083 dev_err(dev
, "Registering UART driver failed\n");
1087 #ifdef CONFIG_GPIOLIB
1088 if (devtype
->nr_gpio
) {
1089 /* Setup GPIO cotroller */
1090 s
->gpio
.owner
= THIS_MODULE
;
1092 s
->gpio
.label
= dev_name(dev
);
1093 s
->gpio
.direction_input
= sc16is7xx_gpio_direction_input
;
1094 s
->gpio
.get
= sc16is7xx_gpio_get
;
1095 s
->gpio
.direction_output
= sc16is7xx_gpio_direction_output
;
1096 s
->gpio
.set
= sc16is7xx_gpio_set
;
1098 s
->gpio
.ngpio
= devtype
->nr_gpio
;
1099 s
->gpio
.can_sleep
= 1;
1100 ret
= gpiochip_add(&s
->gpio
);
1106 mutex_init(&s
->mutex
);
1108 for (i
= 0; i
< devtype
->nr_uart
; ++i
) {
1109 /* Initialize port data */
1110 s
->p
[i
].port
.line
= i
;
1111 s
->p
[i
].port
.dev
= dev
;
1112 s
->p
[i
].port
.irq
= irq
;
1113 s
->p
[i
].port
.type
= PORT_SC16IS7XX
;
1114 s
->p
[i
].port
.fifosize
= SC16IS7XX_FIFO_SIZE
;
1115 s
->p
[i
].port
.flags
= UPF_FIXED_TYPE
| UPF_LOW_LATENCY
;
1116 s
->p
[i
].port
.iotype
= UPIO_PORT
;
1117 s
->p
[i
].port
.uartclk
= freq
;
1118 s
->p
[i
].port
.rs485_config
= sc16is7xx_config_rs485
;
1119 s
->p
[i
].port
.ops
= &sc16is7xx_ops
;
1120 /* Disable all interrupts */
1121 sc16is7xx_port_write(&s
->p
[i
].port
, SC16IS7XX_IER_REG
, 0);
1123 sc16is7xx_port_write(&s
->p
[i
].port
, SC16IS7XX_EFCR_REG
,
1124 SC16IS7XX_EFCR_RXDISABLE_BIT
|
1125 SC16IS7XX_EFCR_TXDISABLE_BIT
);
1126 /* Initialize queue for start TX */
1127 INIT_WORK(&s
->p
[i
].tx_work
, sc16is7xx_wq_proc
);
1128 /* Initialize queue for changing mode */
1129 INIT_WORK(&s
->p
[i
].md_work
, sc16is7xx_md_proc
);
1131 uart_add_one_port(&s
->uart
, &s
->p
[i
].port
);
1132 /* Go to suspend mode */
1133 sc16is7xx_power(&s
->p
[i
].port
, 0);
1136 /* Setup interrupt */
1137 ret
= devm_request_threaded_irq(dev
, irq
, NULL
, sc16is7xx_ist
,
1138 IRQF_ONESHOT
| flags
, dev_name(dev
), s
);
1142 for (i
= 0; i
< s
->uart
.nr
; i
++)
1143 uart_remove_one_port(&s
->uart
, &s
->p
[i
].port
);
1145 mutex_destroy(&s
->mutex
);
1147 #ifdef CONFIG_GPIOLIB
1148 if (devtype
->nr_gpio
)
1149 gpiochip_remove(&s
->gpio
);
1153 uart_unregister_driver(&s
->uart
);
1156 if (!IS_ERR(s
->clk
))
1157 clk_disable_unprepare(s
->clk
);
1162 static int sc16is7xx_remove(struct device
*dev
)
1164 struct sc16is7xx_port
*s
= dev_get_drvdata(dev
);
1167 #ifdef CONFIG_GPIOLIB
1168 if (s
->devtype
->nr_gpio
)
1169 gpiochip_remove(&s
->gpio
);
1172 for (i
= 0; i
< s
->uart
.nr
; i
++) {
1173 cancel_work_sync(&s
->p
[i
].tx_work
);
1174 cancel_work_sync(&s
->p
[i
].md_work
);
1175 uart_remove_one_port(&s
->uart
, &s
->p
[i
].port
);
1176 sc16is7xx_power(&s
->p
[i
].port
, 0);
1179 mutex_destroy(&s
->mutex
);
1180 uart_unregister_driver(&s
->uart
);
1181 if (!IS_ERR(s
->clk
))
1182 clk_disable_unprepare(s
->clk
);
1187 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids
[] = {
1188 { .compatible
= "nxp,sc16is740", .data
= &sc16is74x_devtype
, },
1189 { .compatible
= "nxp,sc16is741", .data
= &sc16is74x_devtype
, },
1190 { .compatible
= "nxp,sc16is750", .data
= &sc16is750_devtype
, },
1191 { .compatible
= "nxp,sc16is752", .data
= &sc16is752_devtype
, },
1192 { .compatible
= "nxp,sc16is760", .data
= &sc16is760_devtype
, },
1193 { .compatible
= "nxp,sc16is762", .data
= &sc16is762_devtype
, },
1196 MODULE_DEVICE_TABLE(of
, sc16is7xx_dt_ids
);
1198 static struct regmap_config regcfg
= {
1202 .cache_type
= REGCACHE_RBTREE
,
1203 .volatile_reg
= sc16is7xx_regmap_volatile
,
1204 .precious_reg
= sc16is7xx_regmap_precious
,
1207 static int sc16is7xx_i2c_probe(struct i2c_client
*i2c
,
1208 const struct i2c_device_id
*id
)
1210 struct sc16is7xx_devtype
*devtype
;
1211 unsigned long flags
= 0;
1212 struct regmap
*regmap
;
1214 if (i2c
->dev
.of_node
) {
1215 const struct of_device_id
*of_id
=
1216 of_match_device(sc16is7xx_dt_ids
, &i2c
->dev
);
1218 devtype
= (struct sc16is7xx_devtype
*)of_id
->data
;
1220 devtype
= (struct sc16is7xx_devtype
*)id
->driver_data
;
1221 flags
= IRQF_TRIGGER_FALLING
;
1224 regcfg
.max_register
= (0xf << SC16IS7XX_REG_SHIFT
) |
1225 (devtype
->nr_uart
- 1);
1226 regmap
= devm_regmap_init_i2c(i2c
, ®cfg
);
1228 return sc16is7xx_probe(&i2c
->dev
, devtype
, regmap
, i2c
->irq
, flags
);
1231 static int sc16is7xx_i2c_remove(struct i2c_client
*client
)
1233 return sc16is7xx_remove(&client
->dev
);
1236 static const struct i2c_device_id sc16is7xx_i2c_id_table
[] = {
1237 { "sc16is74x", (kernel_ulong_t
)&sc16is74x_devtype
, },
1238 { "sc16is750", (kernel_ulong_t
)&sc16is750_devtype
, },
1239 { "sc16is752", (kernel_ulong_t
)&sc16is752_devtype
, },
1240 { "sc16is760", (kernel_ulong_t
)&sc16is760_devtype
, },
1241 { "sc16is762", (kernel_ulong_t
)&sc16is762_devtype
, },
1244 MODULE_DEVICE_TABLE(i2c
, sc16is7xx_i2c_id_table
);
1246 static struct i2c_driver sc16is7xx_i2c_uart_driver
= {
1248 .name
= SC16IS7XX_NAME
,
1249 .owner
= THIS_MODULE
,
1250 .of_match_table
= of_match_ptr(sc16is7xx_dt_ids
),
1252 .probe
= sc16is7xx_i2c_probe
,
1253 .remove
= sc16is7xx_i2c_remove
,
1254 .id_table
= sc16is7xx_i2c_id_table
,
1256 module_i2c_driver(sc16is7xx_i2c_uart_driver
);
1257 MODULE_ALIAS("i2c:sc16is7xx");
1259 MODULE_LICENSE("GPL");
1260 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1261 MODULE_DESCRIPTION("SC16IS7XX serial driver");